2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
9 sys_clk : in std_logic;
10 sys_res_n : in std_logic;
16 do_calc : in std_logic;
17 calc_done : out std_logic;
18 calc_error : out std_logic
22 architecture beh of alu is
23 type ALU_STATE is (SIDLE, SADD, SSUB, SMUL, SDIV, SDIV_CALC, SDONE, SERROR);
24 signal state_int, state_next : ALU_STATE;
25 signal done_intern, error_intern : std_logic;
26 signal div_go_calc_int : std_logic;
27 signal op3_int, op3_next, opM_int, opM_next : csigned;
28 signal calc_done_int, calc_done_next : std_logic;
29 signal calc_error_int, calc_error_next : std_logic;
30 -- signale fuer division
31 signal dividend_msb_int, dividend_msb_next, laengediv_int, laengediv_next : divinteger;
32 signal quo_int, quo_next, aktdiv_int, aktdiv_int_next, op1_int, op1_next, op2_int, op2_next : csigned;
33 signal sign_int, sign_next : std_logic;
37 calc_done <= calc_done_int;
38 calc_error <= calc_error_int;
41 process(sys_clk, sys_res_n)
43 if sys_res_n = '0' then
45 op3_int <= (others => '0');
46 opM_int <= (others => '0');
48 calc_error_int <= '0';
50 dividend_msb_int <= (others => '0');
51 laengediv_int <= (others => '0');
52 quo_int <= (others => '0');
53 aktdiv_int <= (others => '0');
54 op1_int <= (others => '0');
55 op2_int <= (others => '0');
57 elsif rising_edge(sys_clk) then
58 state_int <= state_next;
61 calc_done_int <= calc_done_next;
62 calc_error_int <= calc_error_next;
64 dividend_msb_int <= dividend_msb_next;
65 laengediv_int <= laengediv_next;
67 aktdiv_int <= aktdiv_int_next;
70 sign_int <= sign_next;
75 process(state_int, opcode, done_intern, error_intern, do_calc, div_go_calc_int)
77 -- set a default value for next state
78 state_next <= state_int;
79 -- next state berechnen
84 when ALU_ADD => state_next <= SADD;
85 when ALU_SUB => state_next <= SSUB;
86 when ALU_MUL => state_next <= SMUL;
87 when ALU_DIV => state_next <= SDIV;
88 when others => state_next <= SIDLE;
91 when SADD | SSUB | SMUL | SDIV | SDIV_CALC =>
94 if div_go_calc_int = '1' then
95 state_next <= SDIV_CALC;
99 if done_intern = '1' then
102 if error_intern = '1' then
103 state_next <= SERROR;
105 when SDONE | SERROR =>
106 if do_calc = '0' then
113 process(state_int, op1, op2, dividend_msb_int, laengediv_int, quo_int,
114 aktdiv_int, sign_int, op1_int, op2_int, op3_int, opM_int)
115 variable multmp, multmp2 : signed(((2*CBITS)-1) downto 0);
116 variable mulsign : std_logic;
117 variable tmp : csigned;
119 variable laengediv_var, dividend_msb_var, divtmp : divinteger;
120 variable aktdiv_int_var, quo_var, op1_var, op2_var : csigned;
122 calc_done_next <= '0';
123 calc_error_next <= '0';
124 div_go_calc_int <= '0';
128 dividend_msb_next <= (others => '0');
129 laengediv_next <= (others => '0');
130 quo_next <= (others => '0');
131 aktdiv_int_next <= aktdiv_int;
132 op1_next <= (others => '0');
133 op2_next <= (others => '0');
140 opM_next <= (others => '0');
141 aktdiv_int_next <= (others => '0');
146 -- over- bzw. underflow?
147 if (op1(CBITS-1) = op2(CBITS-1)) and (op1(CBITS-1) /= tmp(CBITS -1)) then
156 -- over- bzw. underflow?
157 if (op1(CBITS-1) /= op2(CBITS-1)) and (op1(CBITS-1) /= tmp(CBITS -1)) then
163 mulsign := op1(CBITS-1) xor op2(CBITS-1);
165 op3_next((CBITS-2) downto 0) <= multmp((CBITS-2) downto 0);
166 op3_next(CBITS-1) <= mulsign;
168 if mulsign = '1' then
169 multmp2 := (not multmp) + 1;
174 if(multmp2((2*CBITS)-2 downto (CBITS-1)) > 0) then
181 -- division implementiert nach ~hwmod/doc/division.pdf
182 if ((op1 = x"80000000" and op2 = to_signed(-1, CBITS)) or op2 = to_signed(0, CBITS)) then
188 if op1(CBITS-1) = '1' then
189 op1_var := (not op1_var) + 1;
191 if op2(CBITS-1) = '1' then
192 op2_var := (not op2_var) + 1;
195 dividend_msb_var := divinteger(find_msb(std_logic_vector(op1_var)))-1;
196 laengediv_var := divinteger(find_msb(std_logic_vector(op2_var)))-1;
198 aktdiv_int_next <= op1_var srl to_integer(dividend_msb_var - laengediv_var + 1);
200 -- anmerkung: xst (xilinx) kann folgende zeile nicht uebersetzen
201 -- > if op1 = to_signed(-2147483648, CBITS) then
202 -- darum folgende schreibweise ->
203 if op1 = x"80000000" then
204 -- so ziemlich das boeseste was passieren kann
206 op3_next <= to_signed(-214748364,CBITS);
207 opM_next <= to_signed(8,CBITS);
208 elsif (op1_var < op2_var) then
210 op3_next <= to_signed(0,CBITS);
213 div_go_calc_int <= '1';
214 dividend_msb_next <= dividend_msb_var;
215 laengediv_next <= laengediv_var;
216 quo_next <= (others => '0');
219 sign_next <= op1(CBITS-1) xor op2(CBITS-1);
223 divtmp := dividend_msb_int - laengediv_int + 1;
226 aktdiv_int_var := aktdiv_int sll 1;
227 aktdiv_int_var(0) := op1_int(to_integer(divtmp) - 1);
229 quo_var := quo_int sll 1;
230 if aktdiv_int_var >= op2_int then
232 aktdiv_int_var := aktdiv_int_var - op2_int;
236 aktdiv_int_next <= aktdiv_int_var;
237 dividend_msb_next <= dividend_msb_int;
238 laengediv_next <= laengediv_int + 1;
241 sign_next <= sign_int;
243 if sign_int = '1' then
244 op3_next <= (not quo_int) + 1;
248 opM_next <= aktdiv_int;
251 when SDONE | SERROR =>
252 calc_done_next <= '1';
253 if (state_int = SERROR) then
254 calc_error_next <= '1';
258 end architecture beh;