quartus/project_gen.tcl

   1 package require ::quartus::project
   2
   3 set need_to_close_project 0
   4 set make_assignments 1
   5
   6 # Check that the right project is open
   7 if {[is_project_open]} {
   8         if {[string compare $quartus(project) "calc"]} {
   9                 puts "Project calc is not open"
  10                 set make_assignments 0
  11         }
  12 } else {
  13         # Only open if not already open
  14         if {[project_exists calc]} {
  15                 project_open -revision calc calc
  16         } else {
  17                 project_new -revision calc calc
  18         }
  19         set need_to_close_project 1
  20 }
  21
  22 # Make assignments
  23 if {$make_assignments} {
  24         set_global_assignment -name FAMILY Stratix
  25         set_global_assignment -name DEVICE %DEVICE%
  26         set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
  27         set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
  28         set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
  29         set_global_assignment -name MISC_FILE "calc.dpf"
  30         set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
  31         set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
  32         set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
  33
  34         #set_global_assignment -name TOP_LEVEL_ENTITY scanner
  35         #set_global_assignment -name VHDL_FILE ../../src/gen_pkg.vhd
  36         #set_global_assignment -name VHDL_FILE ../../src/alu.vhd
  37         #set_global_assignment -name VHDL_FILE ../../src/parser.vhd
  38         #set_global_assignment -name VHDL_FILE ../../src/scanner.vhd
  39
  40
  41         #include source files
  42         set_global_assignment -name TOP_LEVEL_ENTITY calc
  43         set_global_assignment -name VHDL_FILE ../../src/gen_pkg.vhd
  44         set_global_assignment -name VHDL_FILE ../../src/alu.vhd
  45         set_global_assignment -name VHDL_FILE ../../src/parser.vhd
  46         set_global_assignment -name VHDL_FILE ../../src/scanner.vhd
  47         set_global_assignment -name VHDL_FILE ../../src/display.vhd
  48         set_global_assignment -name VHDL_FILE ../../src/sp_ram.vhd
  49         set_global_assignment -name VHDL_FILE ../../src/history.vhd
  50         set_global_assignment -name VHDL_FILE ../../src/calc.vhd
  51         set_global_assignment -name VHDL_FILE ../../src/vpll.vhd
  52
  53         #vga ip-core
  54         set_global_assignment -name VHDL_FILE ../../src/textmode_vga/console_sm.vhd
  55         set_global_assignment -name VHDL_FILE ../../src/textmode_vga/console_sm_beh.vhd
  56         set_global_assignment -name VHDL_FILE ../../src/textmode_vga/console_sm_sync.vhd
  57         set_global_assignment -name VHDL_FILE ../../src/textmode_vga/console_sm_sync_beh.vhd
  58         set_global_assignment -name VHDL_FILE ../../src/textmode_vga/font_pkg.vhd
  59         set_global_assignment -name VHDL_FILE ../../src/textmode_vga/font_rom.vhd
  60         set_global_assignment -name VHDL_FILE ../../src/textmode_vga/font_rom_beh.vhd
  61         set_global_assignment -name VHDL_FILE ../../src/textmode_vga/interval.vhd
  62         set_global_assignment -name VHDL_FILE ../../src/textmode_vga/interval_beh.vhd
  63         set_global_assignment -name VHDL_FILE ../../src/textmode_vga/textmode_vga.vhd
  64         set_global_assignment -name VHDL_FILE ../../src/textmode_vga/textmode_vga_component_pkg.vhd
  65         set_global_assignment -name VHDL_FILE ../../src/textmode_vga/textmode_vga_h_sm.vhd
  66         set_global_assignment -name VHDL_FILE ../../src/textmode_vga/textmode_vga_h_sm_beh.vhd
  67         set_global_assignment -name VHDL_FILE ../../src/textmode_vga/textmode_vga_pkg.vhd
  68         set_global_assignment -name VHDL_FILE ../../src/textmode_vga/textmode_vga_struct.vhd
  69         set_global_assignment -name VHDL_FILE ../../src/textmode_vga/textmode_vga_v_sm.vhd
  70         set_global_assignment -name VHDL_FILE ../../src/textmode_vga/textmode_vga_v_sm_beh.vhd
  71         set_global_assignment -name VHDL_FILE ../../src/textmode_vga/video_memory.vhd
  72         set_global_assignment -name VHDL_FILE ../../src/textmode_vga/video_memory_beh.vhd
  73         set_global_assignment -name VHDL_FILE ../../src/textmode_vga/mjl_stratix/textmode_vga_platform_dependent_pkg.vhd
  74
  75         #ps/2 ip-core
  76         set_global_assignment -name VHDL_FILE ../../src/ps2/ps2_keyboard_controller.vhd
  77         set_global_assignment -name VHDL_FILE ../../src/ps2/ps2_keyboard_controller_beh.vhd
  78         set_global_assignment -name VHDL_FILE ../../src/ps2/ps2_keyboard_controller_pkg.vhd
  79         set_global_assignment -name VHDL_FILE ../../src/ps2/ps2_transceiver.vhd
  80         set_global_assignment -name VHDL_FILE ../../src/ps2/ps2_transceiver_beh.vhd
  81         set_global_assignment -name VHDL_FILE ../../src/ps2/ps2_transceiver_pkg.vhd
  82
  83         #gen ip-core
  84         set_global_assignment -name VHDL_FILE ../../src/math_pkg.vhd
  85
  86
  87         #pin mapping/system
  88         set_location_assignment PIN_N3 -to sys_clk
  89         set_location_assignment PIN_AF17 -to sys_res_n
  90
  91         #vga
  92         set_location_assignment PIN_F1 -to hsync_n
  93         set_location_assignment PIN_F2 -to vsync_n
  94         set_location_assignment PIN_E22 -to r[0]
  95         set_location_assignment PIN_T4 -to r[1]
  96         set_location_assignment PIN_T7 -to r[2]
  97         set_location_assignment PIN_E23 -to g[0]
  98         set_location_assignment PIN_T5 -to g[1]
  99         set_location_assignment PIN_T24 -to g[2]
 100         set_location_assignment PIN_E24 -to b[0]
 101         set_location_assignment PIN_T6 -to b[1]
 102
 103         #ps/2
 104         set_location_assignment PIN_Y26 -to ps2_clk
 105         set_location_assignment PIN_E21 -to ps2_data
 106
 107         set_global_assignment -name FMAX_REQUIREMENT "33.33 MHz" -section_id sys_clk
 108         set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk
 109         #warning fix fuer pll
 110         set_global_assignment -name ENABLE_CLOCK_LATENCY ON
 111
 112         set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
 113         set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
 114         set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 115         set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 116         set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 117
 118         # Commit assignments
 119         export_assignments
 120
 121         # Close project
 122         if {$need_to_close_project} {
 123                 project_close
 124         }
 125 }