2 * Copyright (c) 2004 Hewlett-Packard Development Company, L.P.
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * Most of this code originally comes from Hans-Peter Nilsson. It is included
23 * here with his permission.
25 * This version has not been tested. It was coped here from a GC
26 * patch so that we wouldn't lose the code in the upgrade to gc7.
29 #include "../all_atomic_load_store.h"
31 #include "../ordered.h" /* There are no multiprocessor implementations. */
33 #include "../test_and_set_t_is_ao_t.h"
36 * The architecture apparently supports an "f" flag which is
37 * set on preemption. This essentially gives us load-locked,
38 * store-conditional primitives, though I'm not quite sure how
39 * this would work on a hypothetical multiprocessor. -HB
42 * http://developer.axis.com/doc/hardware/etrax100lx/prog_man/
43 * 1_architectural_description.pdf
45 * Presumably many other primitives (notably CAS, including the double-
46 * width versions) could be implemented in this manner, if someone got
51 AO_test_and_set_full(volatile AO_TS_t *addr) {
52 /* Ripped from linuxthreads/sysdeps/cris/pt-machine.h */
53 register unsigned long int ret;
55 /* Note the use of a dummy output of *addr to expose the write. The
56 memory barrier is to stop *other* writes being moved past this code. */
57 __asm__ __volatile__("clearf\n"
64 : "=&r" (ret), "=m" (*addr)
65 : "r" (addr), "r" ((int) 1), "m" (*addr)
69 #define AO_HAVE_test_and_set_full