bsp4/Designflow/syn/rev_1/vga.vqm

   1 //
   2 // Written by Synplify
   3 // Product Version "C-2009.06"
   4 // Program "Synplify Pro", Mapper "map450rc, Build 029R"
   5 // Tue Nov  3 17:21:45 2009
   6 //
   7 // Source file index table:
   8 // Object locations will have the form <file>:<line>
   9 // file 0 "noname"
  10 // file 1 "\/opt/synplify/fpga_c200906/lib/vhd/std.vhd "
  11 // file 2 "\/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_pak.vhd "
  12 // file 3 "\/opt/synplify/fpga_c200906/lib/vhd/std1164.vhd "
  13 // file 4 "\/opt/synplify/fpga_c200906/lib/vhd/unsigned.vhd "
  14 // file 5 "\/opt/synplify/fpga_c200906/lib/vhd/arith.vhd "
  15 // file 6 "\/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_ent.vhd "
  16 // file 7 "\/homes/burban/didelu/dide_16/bsp4/Designflow/src/board_driver_ent.vhd "
  17 // file 8 "\/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_control_ent.vhd "
  18 // file 9 "\/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_driver_ent.vhd "
  19 // file 10 "\/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_arc.vhd "
  20 // file 11 "\/homes/burban/didelu/dide_16/bsp4/Designflow/src/board_driver_arc.vhd "
  21 // file 12 "\/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_control_arc.vhd "
  22 // file 13 "\/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_driver_arc.vhd "
  23
  24 // VQM4.1+
  25 module vga_driver (
  26   line_counter_sig_0,
  27   line_counter_sig_1,
  28   line_counter_sig_2,
  29   line_counter_sig_3,
  30   line_counter_sig_4,
  31   line_counter_sig_5,
  32   line_counter_sig_6,
  33   line_counter_sig_7,
  34   line_counter_sig_8,
  35   dly_counter_1,
  36   dly_counter_0,
  37   vsync_state_2,
  38   vsync_state_5,
  39   vsync_state_3,
  40   vsync_state_6,
  41   vsync_state_4,
  42   vsync_state_1,
  43   vsync_state_0,
  44   hsync_state_2,
  45   hsync_state_4,
  46   hsync_state_0,
  47   hsync_state_5,
  48   hsync_state_1,
  49   hsync_state_3,
  50   hsync_state_6,
  51   column_counter_sig_0,
  52   column_counter_sig_1,
  53   column_counter_sig_2,
  54   column_counter_sig_3,
  55   column_counter_sig_4,
  56   column_counter_sig_5,
  57   column_counter_sig_6,
  58   column_counter_sig_7,
  59   column_counter_sig_8,
  60   column_counter_sig_9,
  61   vsync_counter_9,
  62   vsync_counter_8,
  63   vsync_counter_7,
  64   vsync_counter_6,
  65   vsync_counter_5,
  66   vsync_counter_4,
  67   vsync_counter_3,
  68   vsync_counter_2,
  69   vsync_counter_1,
  70   vsync_counter_0,
  71   hsync_counter_9,
  72   hsync_counter_8,
  73   hsync_counter_7,
  74   hsync_counter_6,
  75   hsync_counter_5,
  76   hsync_counter_4,
  77   hsync_counter_3,
  78   hsync_counter_2,
  79   hsync_counter_1,
  80   hsync_counter_0,
  81   d_set_vsync_counter,
  82   un10_column_counter_siglt6_1,
  83   v_sync,
  84   h_sync,
  85   h_enable_sig,
  86   v_enable_sig,
  87   reset_pin_c,
  88   un6_dly_counter_0_x,
  89   d_set_hsync_counter,
  90   clk_pin_c
  91 )
  92 ;
  93 output line_counter_sig_0 ;
  94 output line_counter_sig_1 ;
  95 output line_counter_sig_2 ;
  96 output line_counter_sig_3 ;
  97 output line_counter_sig_4 ;
  98 output line_counter_sig_5 ;
  99 output line_counter_sig_6 ;
 100 output line_counter_sig_7 ;
 101 output line_counter_sig_8 ;
 102 input dly_counter_1 ;
 103 input dly_counter_0 ;
 104 output vsync_state_2 ;
 105 output vsync_state_5 ;
 106 output vsync_state_3 ;
 107 output vsync_state_6 ;
 108 output vsync_state_4 ;
 109 output vsync_state_1 ;
 110 output vsync_state_0 ;
 111 output hsync_state_2 ;
 112 output hsync_state_4 ;
 113 output hsync_state_0 ;
 114 output hsync_state_5 ;
 115 output hsync_state_1 ;
 116 output hsync_state_3 ;
 117 output hsync_state_6 ;
 118 output column_counter_sig_0 ;
 119 output column_counter_sig_1 ;
 120 output column_counter_sig_2 ;
 121 output column_counter_sig_3 ;
 122 output column_counter_sig_4 ;
 123 output column_counter_sig_5 ;
 124 output column_counter_sig_6 ;
 125 output column_counter_sig_7 ;
 126 output column_counter_sig_8 ;
 127 output column_counter_sig_9 ;
 128 output vsync_counter_9 ;
 129 output vsync_counter_8 ;
 130 output vsync_counter_7 ;
 131 output vsync_counter_6 ;
 132 output vsync_counter_5 ;
 133 output vsync_counter_4 ;
 134 output vsync_counter_3 ;
 135 output vsync_counter_2 ;
 136 output vsync_counter_1 ;
 137 output vsync_counter_0 ;
 138 output hsync_counter_9 ;
 139 output hsync_counter_8 ;
 140 output hsync_counter_7 ;
 141 output hsync_counter_6 ;
 142 output hsync_counter_5 ;
 143 output hsync_counter_4 ;
 144 output hsync_counter_3 ;
 145 output hsync_counter_2 ;
 146 output hsync_counter_1 ;
 147 output hsync_counter_0 ;
 148 output d_set_vsync_counter ;
 149 output un10_column_counter_siglt6_1 ;
 150 output v_sync ;
 151 output h_sync ;
 152 output h_enable_sig ;
 153 output v_enable_sig ;
 154 input reset_pin_c ;
 155 output un6_dly_counter_0_x ;
 156 output d_set_hsync_counter ;
 157 input clk_pin_c ;
 158 wire line_counter_sig_0 ;
 159 wire line_counter_sig_1 ;
 160 wire line_counter_sig_2 ;
 161 wire line_counter_sig_3 ;
 162 wire line_counter_sig_4 ;
 163 wire line_counter_sig_5 ;
 164 wire line_counter_sig_6 ;
 165 wire line_counter_sig_7 ;
 166 wire line_counter_sig_8 ;
 167 wire dly_counter_1 ;
 168 wire dly_counter_0 ;
 169 wire vsync_state_2 ;
 170 wire vsync_state_5 ;
 171 wire vsync_state_3 ;
 172 wire vsync_state_6 ;
 173 wire vsync_state_4 ;
 174 wire vsync_state_1 ;
 175 wire vsync_state_0 ;
 176 wire hsync_state_2 ;
 177 wire hsync_state_4 ;
 178 wire hsync_state_0 ;
 179 wire hsync_state_5 ;
 180 wire hsync_state_1 ;
 181 wire hsync_state_3 ;
 182 wire hsync_state_6 ;
 183 wire column_counter_sig_0 ;
 184 wire column_counter_sig_1 ;
 185 wire column_counter_sig_2 ;
 186 wire column_counter_sig_3 ;
 187 wire column_counter_sig_4 ;
 188 wire column_counter_sig_5 ;
 189 wire column_counter_sig_6 ;
 190 wire column_counter_sig_7 ;
 191 wire column_counter_sig_8 ;
 192 wire column_counter_sig_9 ;
 193 wire vsync_counter_9 ;
 194 wire vsync_counter_8 ;
 195 wire vsync_counter_7 ;
 196 wire vsync_counter_6 ;
 197 wire vsync_counter_5 ;
 198 wire vsync_counter_4 ;
 199 wire vsync_counter_3 ;
 200 wire vsync_counter_2 ;
 201 wire vsync_counter_1 ;
 202 wire vsync_counter_0 ;
 203 wire hsync_counter_9 ;
 204 wire hsync_counter_8 ;
 205 wire hsync_counter_7 ;
 206 wire hsync_counter_6 ;
 207 wire hsync_counter_5 ;
 208 wire hsync_counter_4 ;
 209 wire hsync_counter_3 ;
 210 wire hsync_counter_2 ;
 211 wire hsync_counter_1 ;
 212 wire hsync_counter_0 ;
 213 wire d_set_vsync_counter ;
 214 wire un10_column_counter_siglt6_1 ;
 215 wire v_sync ;
 216 wire h_sync ;
 217 wire h_enable_sig ;
 218 wire v_enable_sig ;
 219 wire reset_pin_c ;
 220 wire un6_dly_counter_0_x ;
 221 wire d_set_hsync_counter ;
 222 wire clk_pin_c ;
 223 wire [8:0] hsync_counter_cout;
 224 wire [8:0] vsync_counter_cout;
 225 wire [9:1] un2_column_counter_next_combout;
 226 wire [9:1] un1_line_counter_sig_combout;
 227 wire [7:1] un1_line_counter_sig_cout;
 228 wire [1:1] un1_line_counter_sig_a_cout;
 229 wire [7:0] un2_column_counter_next_cout;
 230 wire hsync_counter_next_1_sqmuxa ;
 231 wire G_2_i ;
 232 wire un9_hsync_counterlt9 ;
 233 wire vsync_counter_next_1_sqmuxa ;
 234 wire G_16_i ;
 235 wire un9_vsync_counterlt9 ;
 236 wire un10_column_counter_siglto9 ;
 237 wire column_counter_next_0_sqmuxa_1_1 ;
 238 wire vsync_state_3_iv_0_0__g0_0_a3_0 ;
 239 wire vsync_state_next_2_sqmuxa ;
 240 wire un12_vsync_counter_7 ;
 241 wire un13_vsync_counter_4 ;
 242 wire un10_line_counter_siglto8 ;
 243 wire line_counter_next_0_sqmuxa_1_1 ;
 244 wire v_enable_sig_1_0_0_0_g0_i_o4 ;
 245 wire h_enable_sig_1_0_0_0_g0_i_o4 ;
 246 wire h_sync_1_0_0_0_g1 ;
 247 wire v_sync_1_0_0_0_g1 ;
 248 wire un14_vsync_counter_8 ;
 249 wire hsync_state_3_0_0_0__g0_0 ;
 250 wire un10_hsync_counter_3 ;
 251 wire un10_hsync_counter_1 ;
 252 wire un10_hsync_counter_4 ;
 253 wire un12_hsync_counter ;
 254 wire un11_hsync_counter_2 ;
 255 wire un11_hsync_counter_3 ;
 256 wire un13_hsync_counter ;
 257 wire vsync_state_next_1_sqmuxa_1 ;
 258 wire vsync_state_next_1_sqmuxa_3 ;
 259 wire un1_vsync_state_next_1_sqmuxa_0 ;
 260 wire hsync_state_next_1_sqmuxa_1 ;
 261 wire hsync_state_next_1_sqmuxa_2 ;
 262 wire un1_hsync_state_next_1_sqmuxa_0 ;
 263 wire un12_vsync_counter_6 ;
 264 wire un15_vsync_counter_4 ;
 265 wire vsync_state_next_1_sqmuxa_2 ;
 266 wire un10_line_counter_siglto5 ;
 267 wire un10_column_counter_siglt6 ;
 268 wire un12_hsync_counter_3 ;
 269 wire un12_hsync_counter_4 ;
 270 wire un13_hsync_counter_2 ;
 271 wire un13_hsync_counter_7 ;
 272 wire un9_hsync_counterlt9_3 ;
 273 wire un9_vsync_counterlt9_5 ;
 274 wire un9_vsync_counterlt9_6 ;
 275 wire un10_line_counter_siglt4_2 ;
 276 wire un13_vsync_counter_3 ;
 277 wire un15_vsync_counter_3 ;
 278 wire un10_column_counter_siglt6_2 ;
 279 wire un1_hsync_state_3_0 ;
 280 wire un1_vsync_state_2_0 ;
 281 wire VCC ;
 282 wire GND ;
 283 wire line_counter_next_0_sqmuxa_1_1_i ;
 284 wire column_counter_next_0_sqmuxa_1_1_i ;
 285 wire un9_vsync_counterlt9_i ;
 286 wire G_16_i_i ;
 287 wire un9_hsync_counterlt9_i ;
 288 wire G_2_i_i ;
 289 //@1:1
 290   assign VCC = 1'b1;
 291   assign GND = 1'b0;
 292 // @13:158
 293   stratix_lcell hsync_counter_0_ (
 294         .regout(hsync_counter_0),
 295         .cout(hsync_counter_cout[0]),
 296         .clk(clk_pin_c),
 297         .dataa(hsync_counter_0),
 298         .datab(VCC),
 299         .datac(hsync_counter_next_1_sqmuxa),
 300         .datad(VCC),
 301         .aclr(GND),
 302         .sclr(G_2_i_i),
 303         .sload(un9_hsync_counterlt9_i),
 304         .ena(VCC),
 305         .inverta(GND),
 306         .aload(GND),
 307         .regcascin(GND)
 308 );
 309 defparam hsync_counter_0_.operation_mode="arithmetic";
 310 defparam hsync_counter_0_.output_mode="reg_only";
 311 defparam hsync_counter_0_.lut_mask="55aa";
 312 defparam hsync_counter_0_.synch_mode="on";
 313 defparam hsync_counter_0_.sum_lutc_input="datac";
 314 // @13:158
 315   stratix_lcell hsync_counter_1_ (
 316         .regout(hsync_counter_1),
 317         .cout(hsync_counter_cout[1]),
 318         .clk(clk_pin_c),
 319         .dataa(hsync_counter_1),
 320         .datab(VCC),
 321         .datac(hsync_counter_next_1_sqmuxa),
 322         .datad(VCC),
 323         .aclr(GND),
 324         .sclr(G_2_i_i),
 325         .sload(un9_hsync_counterlt9_i),
 326         .ena(VCC),
 327         .cin(hsync_counter_cout[0]),
 328         .inverta(GND),
 329         .aload(GND),
 330         .regcascin(GND)
 331 );
 332 defparam hsync_counter_1_.cin_used="true";
 333 defparam hsync_counter_1_.operation_mode="arithmetic";
 334 defparam hsync_counter_1_.output_mode="reg_only";
 335 defparam hsync_counter_1_.lut_mask="5aa0";
 336 defparam hsync_counter_1_.synch_mode="on";
 337 defparam hsync_counter_1_.sum_lutc_input="cin";
 338 // @13:158
 339   stratix_lcell hsync_counter_2_ (
 340         .regout(hsync_counter_2),
 341         .cout(hsync_counter_cout[2]),
 342         .clk(clk_pin_c),
 343         .dataa(hsync_counter_2),
 344         .datab(VCC),
 345         .datac(hsync_counter_next_1_sqmuxa),
 346         .datad(VCC),
 347         .aclr(GND),
 348         .sclr(G_2_i_i),
 349         .sload(un9_hsync_counterlt9_i),
 350         .ena(VCC),
 351         .cin(hsync_counter_cout[1]),
 352         .inverta(GND),
 353         .aload(GND),
 354         .regcascin(GND)
 355 );
 356 defparam hsync_counter_2_.cin_used="true";
 357 defparam hsync_counter_2_.operation_mode="arithmetic";
 358 defparam hsync_counter_2_.output_mode="reg_only";
 359 defparam hsync_counter_2_.lut_mask="5aa0";
 360 defparam hsync_counter_2_.synch_mode="on";
 361 defparam hsync_counter_2_.sum_lutc_input="cin";
 362 // @13:158
 363   stratix_lcell hsync_counter_3_ (
 364         .regout(hsync_counter_3),
 365         .cout(hsync_counter_cout[3]),
 366         .clk(clk_pin_c),
 367         .dataa(hsync_counter_3),
 368         .datab(VCC),
 369         .datac(hsync_counter_next_1_sqmuxa),
 370         .datad(VCC),
 371         .aclr(GND),
 372         .sclr(G_2_i_i),
 373         .sload(un9_hsync_counterlt9_i),
 374         .ena(VCC),
 375         .cin(hsync_counter_cout[2]),
 376         .inverta(GND),
 377         .aload(GND),
 378         .regcascin(GND)
 379 );
 380 defparam hsync_counter_3_.cin_used="true";
 381 defparam hsync_counter_3_.operation_mode="arithmetic";
 382 defparam hsync_counter_3_.output_mode="reg_only";
 383 defparam hsync_counter_3_.lut_mask="5aa0";
 384 defparam hsync_counter_3_.synch_mode="on";
 385 defparam hsync_counter_3_.sum_lutc_input="cin";
 386 // @13:158
 387   stratix_lcell hsync_counter_4_ (
 388         .regout(hsync_counter_4),
 389         .cout(hsync_counter_cout[4]),
 390         .clk(clk_pin_c),
 391         .dataa(hsync_counter_4),
 392         .datab(VCC),
 393         .datac(hsync_counter_next_1_sqmuxa),
 394         .datad(VCC),
 395         .aclr(GND),
 396         .sclr(G_2_i_i),
 397         .sload(un9_hsync_counterlt9_i),
 398         .ena(VCC),
 399         .cin(hsync_counter_cout[3]),
 400         .inverta(GND),
 401         .aload(GND),
 402         .regcascin(GND)
 403 );
 404 defparam hsync_counter_4_.cin_used="true";
 405 defparam hsync_counter_4_.operation_mode="arithmetic";
 406 defparam hsync_counter_4_.output_mode="reg_only";
 407 defparam hsync_counter_4_.lut_mask="5aa0";
 408 defparam hsync_counter_4_.synch_mode="on";
 409 defparam hsync_counter_4_.sum_lutc_input="cin";
 410 // @13:158
 411   stratix_lcell hsync_counter_5_ (
 412         .regout(hsync_counter_5),
 413         .cout(hsync_counter_cout[5]),
 414         .clk(clk_pin_c),
 415         .dataa(hsync_counter_5),
 416         .datab(VCC),
 417         .datac(hsync_counter_next_1_sqmuxa),
 418         .datad(VCC),
 419         .aclr(GND),
 420         .sclr(G_2_i_i),
 421         .sload(un9_hsync_counterlt9_i),
 422         .ena(VCC),
 423         .cin(hsync_counter_cout[4]),
 424         .inverta(GND),
 425         .aload(GND),
 426         .regcascin(GND)
 427 );
 428 defparam hsync_counter_5_.cin_used="true";
 429 defparam hsync_counter_5_.operation_mode="arithmetic";
 430 defparam hsync_counter_5_.output_mode="reg_only";
 431 defparam hsync_counter_5_.lut_mask="5aa0";
 432 defparam hsync_counter_5_.synch_mode="on";
 433 defparam hsync_counter_5_.sum_lutc_input="cin";
 434 // @13:158
 435   stratix_lcell hsync_counter_6_ (
 436         .regout(hsync_counter_6),
 437         .cout(hsync_counter_cout[6]),
 438         .clk(clk_pin_c),
 439         .dataa(hsync_counter_6),
 440         .datab(VCC),
 441         .datac(hsync_counter_next_1_sqmuxa),
 442         .datad(VCC),
 443         .aclr(GND),
 444         .sclr(G_2_i_i),
 445         .sload(un9_hsync_counterlt9_i),
 446         .ena(VCC),
 447         .cin(hsync_counter_cout[5]),
 448         .inverta(GND),
 449         .aload(GND),
 450         .regcascin(GND)
 451 );
 452 defparam hsync_counter_6_.cin_used="true";
 453 defparam hsync_counter_6_.operation_mode="arithmetic";
 454 defparam hsync_counter_6_.output_mode="reg_only";
 455 defparam hsync_counter_6_.lut_mask="5aa0";
 456 defparam hsync_counter_6_.synch_mode="on";
 457 defparam hsync_counter_6_.sum_lutc_input="cin";
 458 // @13:158
 459   stratix_lcell hsync_counter_7_ (
 460         .regout(hsync_counter_7),
 461         .cout(hsync_counter_cout[7]),
 462         .clk(clk_pin_c),
 463         .dataa(hsync_counter_7),
 464         .datab(VCC),
 465         .datac(hsync_counter_next_1_sqmuxa),
 466         .datad(VCC),
 467         .aclr(GND),
 468         .sclr(G_2_i_i),
 469         .sload(un9_hsync_counterlt9_i),
 470         .ena(VCC),
 471         .cin(hsync_counter_cout[6]),
 472         .inverta(GND),
 473         .aload(GND),
 474         .regcascin(GND)
 475 );
 476 defparam hsync_counter_7_.cin_used="true";
 477 defparam hsync_counter_7_.operation_mode="arithmetic";
 478 defparam hsync_counter_7_.output_mode="reg_only";
 479 defparam hsync_counter_7_.lut_mask="5aa0";
 480 defparam hsync_counter_7_.synch_mode="on";
 481 defparam hsync_counter_7_.sum_lutc_input="cin";
 482 // @13:158
 483   stratix_lcell hsync_counter_8_ (
 484         .regout(hsync_counter_8),
 485         .cout(hsync_counter_cout[8]),
 486         .clk(clk_pin_c),
 487         .dataa(hsync_counter_8),
 488         .datab(VCC),
 489         .datac(hsync_counter_next_1_sqmuxa),
 490         .datad(VCC),
 491         .aclr(GND),
 492         .sclr(G_2_i_i),
 493         .sload(un9_hsync_counterlt9_i),
 494         .ena(VCC),
 495         .cin(hsync_counter_cout[7]),
 496         .inverta(GND),
 497         .aload(GND),
 498         .regcascin(GND)
 499 );
 500 defparam hsync_counter_8_.cin_used="true";
 501 defparam hsync_counter_8_.operation_mode="arithmetic";
 502 defparam hsync_counter_8_.output_mode="reg_only";
 503 defparam hsync_counter_8_.lut_mask="5aa0";
 504 defparam hsync_counter_8_.synch_mode="on";
 505 defparam hsync_counter_8_.sum_lutc_input="cin";
 506 // @13:158
 507   stratix_lcell hsync_counter_9_ (
 508         .regout(hsync_counter_9),
 509         .clk(clk_pin_c),
 510         .dataa(hsync_counter_9),
 511         .datab(VCC),
 512         .datac(hsync_counter_next_1_sqmuxa),
 513         .datad(VCC),
 514         .aclr(GND),
 515         .sclr(G_2_i_i),
 516         .sload(un9_hsync_counterlt9_i),
 517         .ena(VCC),
 518         .cin(hsync_counter_cout[8]),
 519         .inverta(GND),
 520         .aload(GND),
 521         .regcascin(GND)
 522 );
 523 defparam hsync_counter_9_.cin_used="true";
 524 defparam hsync_counter_9_.operation_mode="normal";
 525 defparam hsync_counter_9_.output_mode="reg_only";
 526 defparam hsync_counter_9_.lut_mask="5a5a";
 527 defparam hsync_counter_9_.synch_mode="on";
 528 defparam hsync_counter_9_.sum_lutc_input="cin";
 529 // @13:267
 530   stratix_lcell vsync_counter_0_ (
 531         .regout(vsync_counter_0),
 532         .cout(vsync_counter_cout[0]),
 533         .clk(clk_pin_c),
 534         .dataa(vsync_counter_0),
 535         .datab(d_set_hsync_counter),
 536         .datac(vsync_counter_next_1_sqmuxa),
 537         .datad(VCC),
 538         .aclr(GND),
 539         .sclr(G_16_i_i),
 540         .sload(un9_vsync_counterlt9_i),
 541         .ena(VCC),
 542         .inverta(GND),
 543         .aload(GND),
 544         .regcascin(GND)
 545 );
 546 defparam vsync_counter_0_.operation_mode="arithmetic";
 547 defparam vsync_counter_0_.output_mode="reg_only";
 548 defparam vsync_counter_0_.lut_mask="6688";
 549 defparam vsync_counter_0_.synch_mode="on";
 550 defparam vsync_counter_0_.sum_lutc_input="datac";
 551 // @13:267
 552   stratix_lcell vsync_counter_1_ (
 553         .regout(vsync_counter_1),
 554         .cout(vsync_counter_cout[1]),
 555         .clk(clk_pin_c),
 556         .dataa(vsync_counter_1),
 557         .datab(VCC),
 558         .datac(vsync_counter_next_1_sqmuxa),
 559         .datad(VCC),
 560         .aclr(GND),
 561         .sclr(G_16_i_i),
 562         .sload(un9_vsync_counterlt9_i),
 563         .ena(VCC),
 564         .cin(vsync_counter_cout[0]),
 565         .inverta(GND),
 566         .aload(GND),
 567         .regcascin(GND)
 568 );
 569 defparam vsync_counter_1_.cin_used="true";
 570 defparam vsync_counter_1_.operation_mode="arithmetic";
 571 defparam vsync_counter_1_.output_mode="reg_only";
 572 defparam vsync_counter_1_.lut_mask="5aa0";
 573 defparam vsync_counter_1_.synch_mode="on";
 574 defparam vsync_counter_1_.sum_lutc_input="cin";
 575 // @13:267
 576   stratix_lcell vsync_counter_2_ (
 577         .regout(vsync_counter_2),
 578         .cout(vsync_counter_cout[2]),
 579         .clk(clk_pin_c),
 580         .dataa(vsync_counter_2),
 581         .datab(VCC),
 582         .datac(vsync_counter_next_1_sqmuxa),
 583         .datad(VCC),
 584         .aclr(GND),
 585         .sclr(G_16_i_i),
 586         .sload(un9_vsync_counterlt9_i),
 587         .ena(VCC),
 588         .cin(vsync_counter_cout[1]),
 589         .inverta(GND),
 590         .aload(GND),
 591         .regcascin(GND)
 592 );
 593 defparam vsync_counter_2_.cin_used="true";
 594 defparam vsync_counter_2_.operation_mode="arithmetic";
 595 defparam vsync_counter_2_.output_mode="reg_only";
 596 defparam vsync_counter_2_.lut_mask="5aa0";
 597 defparam vsync_counter_2_.synch_mode="on";
 598 defparam vsync_counter_2_.sum_lutc_input="cin";
 599 // @13:267
 600   stratix_lcell vsync_counter_3_ (
 601         .regout(vsync_counter_3),
 602         .cout(vsync_counter_cout[3]),
 603         .clk(clk_pin_c),
 604         .dataa(vsync_counter_3),
 605         .datab(VCC),
 606         .datac(vsync_counter_next_1_sqmuxa),
 607         .datad(VCC),
 608         .aclr(GND),
 609         .sclr(G_16_i_i),
 610         .sload(un9_vsync_counterlt9_i),
 611         .ena(VCC),
 612         .cin(vsync_counter_cout[2]),
 613         .inverta(GND),
 614         .aload(GND),
 615         .regcascin(GND)
 616 );
 617 defparam vsync_counter_3_.cin_used="true";
 618 defparam vsync_counter_3_.operation_mode="arithmetic";
 619 defparam vsync_counter_3_.output_mode="reg_only";
 620 defparam vsync_counter_3_.lut_mask="5aa0";
 621 defparam vsync_counter_3_.synch_mode="on";
 622 defparam vsync_counter_3_.sum_lutc_input="cin";
 623 // @13:267
 624   stratix_lcell vsync_counter_4_ (
 625         .regout(vsync_counter_4),
 626         .cout(vsync_counter_cout[4]),
 627         .clk(clk_pin_c),
 628         .dataa(vsync_counter_4),
 629         .datab(VCC),
 630         .datac(vsync_counter_next_1_sqmuxa),
 631         .datad(VCC),
 632         .aclr(GND),
 633         .sclr(G_16_i_i),
 634         .sload(un9_vsync_counterlt9_i),
 635         .ena(VCC),
 636         .cin(vsync_counter_cout[3]),
 637         .inverta(GND),
 638         .aload(GND),
 639         .regcascin(GND)
 640 );
 641 defparam vsync_counter_4_.cin_used="true";
 642 defparam vsync_counter_4_.operation_mode="arithmetic";
 643 defparam vsync_counter_4_.output_mode="reg_only";
 644 defparam vsync_counter_4_.lut_mask="5aa0";
 645 defparam vsync_counter_4_.synch_mode="on";
 646 defparam vsync_counter_4_.sum_lutc_input="cin";
 647 // @13:267
 648   stratix_lcell vsync_counter_5_ (
 649         .regout(vsync_counter_5),
 650         .cout(vsync_counter_cout[5]),
 651         .clk(clk_pin_c),
 652         .dataa(vsync_counter_5),
 653         .datab(VCC),
 654         .datac(vsync_counter_next_1_sqmuxa),
 655         .datad(VCC),
 656         .aclr(GND),
 657         .sclr(G_16_i_i),
 658         .sload(un9_vsync_counterlt9_i),
 659         .ena(VCC),
 660         .cin(vsync_counter_cout[4]),
 661         .inverta(GND),
 662         .aload(GND),
 663         .regcascin(GND)
 664 );
 665 defparam vsync_counter_5_.cin_used="true";
 666 defparam vsync_counter_5_.operation_mode="arithmetic";
 667 defparam vsync_counter_5_.output_mode="reg_only";
 668 defparam vsync_counter_5_.lut_mask="5aa0";
 669 defparam vsync_counter_5_.synch_mode="on";
 670 defparam vsync_counter_5_.sum_lutc_input="cin";
 671 // @13:267
 672   stratix_lcell vsync_counter_6_ (
 673         .regout(vsync_counter_6),
 674         .cout(vsync_counter_cout[6]),
 675         .clk(clk_pin_c),
 676         .dataa(vsync_counter_6),
 677         .datab(VCC),
 678         .datac(vsync_counter_next_1_sqmuxa),
 679         .datad(VCC),
 680         .aclr(GND),
 681         .sclr(G_16_i_i),
 682         .sload(un9_vsync_counterlt9_i),
 683         .ena(VCC),
 684         .cin(vsync_counter_cout[5]),
 685         .inverta(GND),
 686         .aload(GND),
 687         .regcascin(GND)
 688 );
 689 defparam vsync_counter_6_.cin_used="true";
 690 defparam vsync_counter_6_.operation_mode="arithmetic";
 691 defparam vsync_counter_6_.output_mode="reg_only";
 692 defparam vsync_counter_6_.lut_mask="5aa0";
 693 defparam vsync_counter_6_.synch_mode="on";
 694 defparam vsync_counter_6_.sum_lutc_input="cin";
 695 // @13:267
 696   stratix_lcell vsync_counter_7_ (
 697         .regout(vsync_counter_7),
 698         .cout(vsync_counter_cout[7]),
 699         .clk(clk_pin_c),
 700         .dataa(vsync_counter_7),
 701         .datab(VCC),
 702         .datac(vsync_counter_next_1_sqmuxa),
 703         .datad(VCC),
 704         .aclr(GND),
 705         .sclr(G_16_i_i),
 706         .sload(un9_vsync_counterlt9_i),
 707         .ena(VCC),
 708         .cin(vsync_counter_cout[6]),
 709         .inverta(GND),
 710         .aload(GND),
 711         .regcascin(GND)
 712 );
 713 defparam vsync_counter_7_.cin_used="true";
 714 defparam vsync_counter_7_.operation_mode="arithmetic";
 715 defparam vsync_counter_7_.output_mode="reg_only";
 716 defparam vsync_counter_7_.lut_mask="5aa0";
 717 defparam vsync_counter_7_.synch_mode="on";
 718 defparam vsync_counter_7_.sum_lutc_input="cin";
 719 // @13:267
 720   stratix_lcell vsync_counter_8_ (
 721         .regout(vsync_counter_8),
 722         .cout(vsync_counter_cout[8]),
 723         .clk(clk_pin_c),
 724         .dataa(vsync_counter_8),
 725         .datab(VCC),
 726         .datac(vsync_counter_next_1_sqmuxa),
 727         .datad(VCC),
 728         .aclr(GND),
 729         .sclr(G_16_i_i),
 730         .sload(un9_vsync_counterlt9_i),
 731         .ena(VCC),
 732         .cin(vsync_counter_cout[7]),
 733         .inverta(GND),
 734         .aload(GND),
 735         .regcascin(GND)
 736 );
 737 defparam vsync_counter_8_.cin_used="true";
 738 defparam vsync_counter_8_.operation_mode="arithmetic";
 739 defparam vsync_counter_8_.output_mode="reg_only";
 740 defparam vsync_counter_8_.lut_mask="5aa0";
 741 defparam vsync_counter_8_.synch_mode="on";
 742 defparam vsync_counter_8_.sum_lutc_input="cin";
 743 // @13:267
 744   stratix_lcell vsync_counter_9_ (
 745         .regout(vsync_counter_9),
 746         .clk(clk_pin_c),
 747         .dataa(vsync_counter_9),
 748         .datab(VCC),
 749         .datac(vsync_counter_next_1_sqmuxa),
 750         .datad(VCC),
 751         .aclr(GND),
 752         .sclr(G_16_i_i),
 753         .sload(un9_vsync_counterlt9_i),
 754         .ena(VCC),
 755         .cin(vsync_counter_cout[8]),
 756         .inverta(GND),
 757         .aload(GND),
 758         .regcascin(GND)
 759 );
 760 defparam vsync_counter_9_.cin_used="true";
 761 defparam vsync_counter_9_.operation_mode="normal";
 762 defparam vsync_counter_9_.output_mode="reg_only";
 763 defparam vsync_counter_9_.lut_mask="5a5a";
 764 defparam vsync_counter_9_.synch_mode="on";
 765 defparam vsync_counter_9_.sum_lutc_input="cin";
 766 // @13:97
 767   stratix_lcell column_counter_sig_9_ (
 768         .regout(column_counter_sig_9),
 769         .clk(clk_pin_c),
 770         .dataa(un2_column_counter_next_combout[9]),
 771         .datab(un10_column_counter_siglto9),
 772         .datac(VCC),
 773         .datad(VCC),
 774         .aclr(GND),
 775         .sclr(column_counter_next_0_sqmuxa_1_1_i),
 776         .sload(GND),
 777         .ena(VCC),
 778         .inverta(GND),
 779         .aload(GND),
 780         .regcascin(GND)
 781 );
 782 defparam column_counter_sig_9_.operation_mode="normal";
 783 defparam column_counter_sig_9_.output_mode="reg_only";
 784 defparam column_counter_sig_9_.lut_mask="bbbb";
 785 defparam column_counter_sig_9_.synch_mode="on";
 786 defparam column_counter_sig_9_.sum_lutc_input="datac";
 787 // @13:97
 788   stratix_lcell column_counter_sig_8_ (
 789         .regout(column_counter_sig_8),
 790         .clk(clk_pin_c),
 791         .dataa(un2_column_counter_next_combout[8]),
 792         .datab(un10_column_counter_siglto9),
 793         .datac(column_counter_next_0_sqmuxa_1_1),
 794         .datad(VCC),
 795         .aclr(GND),
 796         .sclr(GND),
 797         .sload(GND),
 798         .ena(VCC),
 799         .inverta(GND),
 800         .aload(GND),
 801         .regcascin(GND)
 802 );
 803 defparam column_counter_sig_8_.operation_mode="normal";
 804 defparam column_counter_sig_8_.output_mode="reg_only";
 805 defparam column_counter_sig_8_.lut_mask="8080";
 806 defparam column_counter_sig_8_.synch_mode="off";
 807 defparam column_counter_sig_8_.sum_lutc_input="datac";
 808 // @13:97
 809   stratix_lcell column_counter_sig_7_ (
 810         .regout(column_counter_sig_7),
 811         .clk(clk_pin_c),
 812         .dataa(un2_column_counter_next_combout[7]),
 813         .datab(un10_column_counter_siglto9),
 814         .datac(column_counter_next_0_sqmuxa_1_1),
 815         .datad(VCC),
 816         .aclr(GND),
 817         .sclr(GND),
 818         .sload(GND),
 819         .ena(VCC),
 820         .inverta(GND),
 821         .aload(GND),
 822         .regcascin(GND)
 823 );
 824 defparam column_counter_sig_7_.operation_mode="normal";
 825 defparam column_counter_sig_7_.output_mode="reg_only";
 826 defparam column_counter_sig_7_.lut_mask="8080";
 827 defparam column_counter_sig_7_.synch_mode="off";
 828 defparam column_counter_sig_7_.sum_lutc_input="datac";
 829 // @13:97
 830   stratix_lcell column_counter_sig_6_ (
 831         .regout(column_counter_sig_6),
 832         .clk(clk_pin_c),
 833         .dataa(un2_column_counter_next_combout[6]),
 834         .datab(un10_column_counter_siglto9),
 835         .datac(VCC),
 836         .datad(VCC),
 837         .aclr(GND),
 838         .sclr(column_counter_next_0_sqmuxa_1_1_i),
 839         .sload(GND),
 840         .ena(VCC),
 841         .inverta(GND),
 842         .aload(GND),
 843         .regcascin(GND)
 844 );
 845 defparam column_counter_sig_6_.operation_mode="normal";
 846 defparam column_counter_sig_6_.output_mode="reg_only";
 847 defparam column_counter_sig_6_.lut_mask="bbbb";
 848 defparam column_counter_sig_6_.synch_mode="on";
 849 defparam column_counter_sig_6_.sum_lutc_input="datac";
 850 // @13:97
 851   stratix_lcell column_counter_sig_5_ (
 852         .regout(column_counter_sig_5),
 853         .clk(clk_pin_c),
 854         .dataa(un2_column_counter_next_combout[5]),
 855         .datab(un10_column_counter_siglto9),
 856         .datac(VCC),
 857         .datad(VCC),
 858         .aclr(GND),
 859         .sclr(column_counter_next_0_sqmuxa_1_1_i),
 860         .sload(GND),
 861         .ena(VCC),
 862         .inverta(GND),
 863         .aload(GND),
 864         .regcascin(GND)
 865 );
 866 defparam column_counter_sig_5_.operation_mode="normal";
 867 defparam column_counter_sig_5_.output_mode="reg_only";
 868 defparam column_counter_sig_5_.lut_mask="bbbb";
 869 defparam column_counter_sig_5_.synch_mode="on";
 870 defparam column_counter_sig_5_.sum_lutc_input="datac";
 871 // @13:97
 872   stratix_lcell column_counter_sig_4_ (
 873         .regout(column_counter_sig_4),
 874         .clk(clk_pin_c),
 875         .dataa(un2_column_counter_next_combout[4]),
 876         .datab(un10_column_counter_siglto9),
 877         .datac(VCC),
 878         .datad(VCC),
 879         .aclr(GND),
 880         .sclr(column_counter_next_0_sqmuxa_1_1_i),
 881         .sload(GND),
 882         .ena(VCC),
 883         .inverta(GND),
 884         .aload(GND),
 885         .regcascin(GND)
 886 );
 887 defparam column_counter_sig_4_.operation_mode="normal";
 888 defparam column_counter_sig_4_.output_mode="reg_only";
 889 defparam column_counter_sig_4_.lut_mask="bbbb";
 890 defparam column_counter_sig_4_.synch_mode="on";
 891 defparam column_counter_sig_4_.sum_lutc_input="datac";
 892 // @13:97
 893   stratix_lcell column_counter_sig_3_ (
 894         .regout(column_counter_sig_3),
 895         .clk(clk_pin_c),
 896         .dataa(un2_column_counter_next_combout[3]),
 897         .datab(un10_column_counter_siglto9),
 898         .datac(VCC),
 899         .datad(VCC),
 900         .aclr(GND),
 901         .sclr(column_counter_next_0_sqmuxa_1_1_i),
 902         .sload(GND),
 903         .ena(VCC),
 904         .inverta(GND),
 905         .aload(GND),
 906         .regcascin(GND)
 907 );
 908 defparam column_counter_sig_3_.operation_mode="normal";
 909 defparam column_counter_sig_3_.output_mode="reg_only";
 910 defparam column_counter_sig_3_.lut_mask="bbbb";
 911 defparam column_counter_sig_3_.synch_mode="on";
 912 defparam column_counter_sig_3_.sum_lutc_input="datac";
 913 // @13:97
 914   stratix_lcell column_counter_sig_2_ (
 915         .regout(column_counter_sig_2),
 916         .clk(clk_pin_c),
 917         .dataa(un2_column_counter_next_combout[2]),
 918         .datab(un10_column_counter_siglto9),
 919         .datac(VCC),
 920         .datad(VCC),
 921         .aclr(GND),
 922         .sclr(column_counter_next_0_sqmuxa_1_1_i),
 923         .sload(GND),
 924         .ena(VCC),
 925         .inverta(GND),
 926         .aload(GND),
 927         .regcascin(GND)
 928 );
 929 defparam column_counter_sig_2_.operation_mode="normal";
 930 defparam column_counter_sig_2_.output_mode="reg_only";
 931 defparam column_counter_sig_2_.lut_mask="bbbb";
 932 defparam column_counter_sig_2_.synch_mode="on";
 933 defparam column_counter_sig_2_.sum_lutc_input="datac";
 934 // @13:97
 935   stratix_lcell column_counter_sig_1_ (
 936         .regout(column_counter_sig_1),
 937         .clk(clk_pin_c),
 938         .dataa(un2_column_counter_next_combout[1]),
 939         .datab(un10_column_counter_siglto9),
 940         .datac(VCC),
 941         .datad(VCC),
 942         .aclr(GND),
 943         .sclr(column_counter_next_0_sqmuxa_1_1_i),
 944         .sload(GND),
 945         .ena(VCC),
 946         .inverta(GND),
 947         .aload(GND),
 948         .regcascin(GND)
 949 );
 950 defparam column_counter_sig_1_.operation_mode="normal";
 951 defparam column_counter_sig_1_.output_mode="reg_only";
 952 defparam column_counter_sig_1_.lut_mask="bbbb";
 953 defparam column_counter_sig_1_.synch_mode="on";
 954 defparam column_counter_sig_1_.sum_lutc_input="datac";
 955 // @13:97
 956   stratix_lcell column_counter_sig_0_ (
 957         .regout(column_counter_sig_0),
 958         .clk(clk_pin_c),
 959         .dataa(column_counter_sig_0),
 960         .datab(un10_column_counter_siglto9),
 961         .datac(VCC),
 962         .datad(VCC),
 963         .aclr(GND),
 964         .sclr(column_counter_next_0_sqmuxa_1_1_i),
 965         .sload(GND),
 966         .ena(VCC),
 967         .inverta(GND),
 968         .aload(GND),
 969         .regcascin(GND)
 970 );
 971 defparam column_counter_sig_0_.operation_mode="normal";
 972 defparam column_counter_sig_0_.output_mode="reg_only";
 973 defparam column_counter_sig_0_.lut_mask="7777";
 974 defparam column_counter_sig_0_.synch_mode="on";
 975 defparam column_counter_sig_0_.sum_lutc_input="datac";
 976 // @13:187
 977   stratix_lcell hsync_state_6_ (
 978         .regout(hsync_state_6),
 979         .clk(clk_pin_c),
 980         .dataa(VCC),
 981         .datab(VCC),
 982         .datac(VCC),
 983         .datad(un6_dly_counter_0_x),
 984         .aclr(GND),
 985         .sclr(GND),
 986         .sload(GND),
 987         .ena(VCC),
 988         .inverta(GND),
 989         .aload(GND),
 990         .regcascin(GND)
 991 );
 992 defparam hsync_state_6_.operation_mode="normal";
 993 defparam hsync_state_6_.output_mode="reg_only";
 994 defparam hsync_state_6_.lut_mask="ff00";
 995 defparam hsync_state_6_.synch_mode="off";
 996 defparam hsync_state_6_.sum_lutc_input="datac";
 997 // @13:300
 998   stratix_lcell vsync_state_0_ (
 999         .regout(vsync_state_0),
1000         .clk(clk_pin_c),
1001         .dataa(vsync_state_0),
1002         .datab(vsync_state_3_iv_0_0__g0_0_a3_0),
1003         .datac(un6_dly_counter_0_x),
1004         .datad(vsync_state_next_2_sqmuxa),
1005         .aclr(GND),
1006         .sclr(GND),
1007         .sload(GND),
1008         .ena(VCC),
1009         .inverta(GND),
1010         .aload(GND),
1011         .regcascin(GND)
1012 );
1013 defparam vsync_state_0_.operation_mode="normal";
1014 defparam vsync_state_0_.output_mode="reg_only";
1015 defparam vsync_state_0_.lut_mask="0cae";
1016 defparam vsync_state_0_.synch_mode="off";
1017 defparam vsync_state_0_.sum_lutc_input="datac";
1018 // @13:300
1019   stratix_lcell vsync_state_1_ (
1020         .regout(vsync_state_1),
1021         .clk(clk_pin_c),
1022         .dataa(vsync_state_4),
1023         .datab(un12_vsync_counter_7),
1024         .datac(un13_vsync_counter_4),
1025         .datad(un6_dly_counter_0_x),
1026         .aclr(GND),
1027         .sclr(GND),
1028         .sload(GND),
1029         .ena(VCC),
1030         .inverta(GND),
1031         .aload(GND),
1032         .regcascin(GND)
1033 );
1034 defparam vsync_state_1_.operation_mode="normal";
1035 defparam vsync_state_1_.output_mode="reg_only";
1036 defparam vsync_state_1_.lut_mask="0080";
1037 defparam vsync_state_1_.synch_mode="off";
1038 defparam vsync_state_1_.sum_lutc_input="datac";
1039 // @13:300
1040   stratix_lcell vsync_state_6_ (
1041         .combout(un6_dly_counter_0_x),
1042         .regout(vsync_state_6),
1043         .clk(clk_pin_c),
1044         .dataa(reset_pin_c),
1045         .datab(dly_counter_0),
1046         .datac(dly_counter_1),
1047         .datad(VCC),
1048         .aclr(GND),
1049         .sclr(GND),
1050         .sload(GND),
1051         .ena(VCC),
1052         .inverta(GND),
1053         .aload(GND),
1054         .regcascin(GND)
1055 );
1056 defparam vsync_state_6_.operation_mode="normal";
1057 defparam vsync_state_6_.output_mode="reg_and_comb";
1058 defparam vsync_state_6_.lut_mask="7f7f";
1059 defparam vsync_state_6_.synch_mode="off";
1060 defparam vsync_state_6_.sum_lutc_input="datac";
1061 // @13:125
1062   stratix_lcell line_counter_sig_8_ (
1063         .regout(line_counter_sig_8),
1064         .clk(clk_pin_c),
1065         .dataa(un10_line_counter_siglto8),
1066         .datab(un1_line_counter_sig_combout[9]),
1067         .datac(VCC),
1068         .datad(VCC),
1069         .aclr(GND),
1070         .sclr(line_counter_next_0_sqmuxa_1_1_i),
1071         .sload(GND),
1072         .ena(VCC),
1073         .inverta(GND),
1074         .aload(GND),
1075         .regcascin(GND)
1076 );
1077 defparam line_counter_sig_8_.operation_mode="normal";
1078 defparam line_counter_sig_8_.output_mode="reg_only";
1079 defparam line_counter_sig_8_.lut_mask="dddd";
1080 defparam line_counter_sig_8_.synch_mode="on";
1081 defparam line_counter_sig_8_.sum_lutc_input="datac";
1082 // @13:125
1083   stratix_lcell line_counter_sig_7_ (
1084         .regout(line_counter_sig_7),
1085         .clk(clk_pin_c),
1086         .dataa(un10_line_counter_siglto8),
1087         .datab(un1_line_counter_sig_combout[8]),
1088         .datac(VCC),
1089         .datad(VCC),
1090         .aclr(GND),
1091         .sclr(line_counter_next_0_sqmuxa_1_1_i),
1092         .sload(GND),
1093         .ena(VCC),
1094         .inverta(GND),
1095         .aload(GND),
1096         .regcascin(GND)
1097 );
1098 defparam line_counter_sig_7_.operation_mode="normal";
1099 defparam line_counter_sig_7_.output_mode="reg_only";
1100 defparam line_counter_sig_7_.lut_mask="dddd";
1101 defparam line_counter_sig_7_.synch_mode="on";
1102 defparam line_counter_sig_7_.sum_lutc_input="datac";
1103 // @13:125
1104   stratix_lcell line_counter_sig_6_ (
1105         .regout(line_counter_sig_6),
1106         .clk(clk_pin_c),
1107         .dataa(un10_line_counter_siglto8),
1108         .datab(un1_line_counter_sig_combout[7]),
1109         .datac(VCC),
1110         .datad(VCC),
1111         .aclr(GND),
1112         .sclr(line_counter_next_0_sqmuxa_1_1_i),
1113         .sload(GND),
1114         .ena(VCC),
1115         .inverta(GND),
1116         .aload(GND),
1117         .regcascin(GND)
1118 );
1119 defparam line_counter_sig_6_.operation_mode="normal";
1120 defparam line_counter_sig_6_.output_mode="reg_only";
1121 defparam line_counter_sig_6_.lut_mask="dddd";
1122 defparam line_counter_sig_6_.synch_mode="on";
1123 defparam line_counter_sig_6_.sum_lutc_input="datac";
1124 // @13:125
1125   stratix_lcell line_counter_sig_5_ (
1126         .regout(line_counter_sig_5),
1127         .clk(clk_pin_c),
1128         .dataa(un10_line_counter_siglto8),
1129         .datab(un1_line_counter_sig_combout[6]),
1130         .datac(line_counter_next_0_sqmuxa_1_1),
1131         .datad(VCC),
1132         .aclr(GND),
1133         .sclr(GND),
1134         .sload(GND),
1135         .ena(VCC),
1136         .inverta(GND),
1137         .aload(GND),
1138         .regcascin(GND)
1139 );
1140 defparam line_counter_sig_5_.operation_mode="normal";
1141 defparam line_counter_sig_5_.output_mode="reg_only";
1142 defparam line_counter_sig_5_.lut_mask="8080";
1143 defparam line_counter_sig_5_.synch_mode="off";
1144 defparam line_counter_sig_5_.sum_lutc_input="datac";
1145 // @13:125
1146   stratix_lcell line_counter_sig_4_ (
1147         .regout(line_counter_sig_4),
1148         .clk(clk_pin_c),
1149         .dataa(un10_line_counter_siglto8),
1150         .datab(un1_line_counter_sig_combout[5]),
1151         .datac(VCC),
1152         .datad(VCC),
1153         .aclr(GND),
1154         .sclr(line_counter_next_0_sqmuxa_1_1_i),
1155         .sload(GND),
1156         .ena(VCC),
1157         .inverta(GND),
1158         .aload(GND),
1159         .regcascin(GND)
1160 );
1161 defparam line_counter_sig_4_.operation_mode="normal";
1162 defparam line_counter_sig_4_.output_mode="reg_only";
1163 defparam line_counter_sig_4_.lut_mask="dddd";
1164 defparam line_counter_sig_4_.synch_mode="on";
1165 defparam line_counter_sig_4_.sum_lutc_input="datac";
1166 // @13:125
1167   stratix_lcell line_counter_sig_3_ (
1168         .regout(line_counter_sig_3),
1169         .clk(clk_pin_c),
1170         .dataa(un10_line_counter_siglto8),
1171         .datab(un1_line_counter_sig_combout[4]),
1172         .datac(VCC),
1173         .datad(VCC),
1174         .aclr(GND),
1175         .sclr(line_counter_next_0_sqmuxa_1_1_i),
1176         .sload(GND),
1177         .ena(VCC),
1178         .inverta(GND),
1179         .aload(GND),
1180         .regcascin(GND)
1181 );
1182 defparam line_counter_sig_3_.operation_mode="normal";
1183 defparam line_counter_sig_3_.output_mode="reg_only";
1184 defparam line_counter_sig_3_.lut_mask="dddd";
1185 defparam line_counter_sig_3_.synch_mode="on";
1186 defparam line_counter_sig_3_.sum_lutc_input="datac";
1187 // @13:125
1188   stratix_lcell line_counter_sig_2_ (
1189         .regout(line_counter_sig_2),
1190         .clk(clk_pin_c),
1191         .dataa(un10_line_counter_siglto8),
1192         .datab(un1_line_counter_sig_combout[3]),
1193         .datac(VCC),
1194         .datad(VCC),
1195         .aclr(GND),
1196         .sclr(line_counter_next_0_sqmuxa_1_1_i),
1197         .sload(GND),
1198         .ena(VCC),
1199         .inverta(GND),
1200         .aload(GND),
1201         .regcascin(GND)
1202 );
1203 defparam line_counter_sig_2_.operation_mode="normal";
1204 defparam line_counter_sig_2_.output_mode="reg_only";
1205 defparam line_counter_sig_2_.lut_mask="dddd";
1206 defparam line_counter_sig_2_.synch_mode="on";
1207 defparam line_counter_sig_2_.sum_lutc_input="datac";
1208 // @13:125
1209   stratix_lcell line_counter_sig_1_ (
1210         .regout(line_counter_sig_1),
1211         .clk(clk_pin_c),
1212         .dataa(un10_line_counter_siglto8),
1213         .datab(un1_line_counter_sig_combout[2]),
1214         .datac(VCC),
1215         .datad(VCC),
1216         .aclr(GND),
1217         .sclr(line_counter_next_0_sqmuxa_1_1_i),
1218         .sload(GND),
1219         .ena(VCC),
1220         .inverta(GND),
1221         .aload(GND),
1222         .regcascin(GND)
1223 );
1224 defparam line_counter_sig_1_.operation_mode="normal";
1225 defparam line_counter_sig_1_.output_mode="reg_only";
1226 defparam line_counter_sig_1_.lut_mask="dddd";
1227 defparam line_counter_sig_1_.synch_mode="on";
1228 defparam line_counter_sig_1_.sum_lutc_input="datac";
1229 // @13:125
1230   stratix_lcell line_counter_sig_0_ (
1231         .regout(line_counter_sig_0),
1232         .clk(clk_pin_c),
1233         .dataa(un1_line_counter_sig_combout[1]),
1234         .datab(un10_line_counter_siglto8),
1235         .datac(VCC),
1236         .datad(VCC),
1237         .aclr(GND),
1238         .sclr(line_counter_next_0_sqmuxa_1_1_i),
1239         .sload(GND),
1240         .ena(VCC),
1241         .inverta(GND),
1242         .aload(GND),
1243         .regcascin(GND)
1244 );
1245 defparam line_counter_sig_0_.operation_mode="normal";
1246 defparam line_counter_sig_0_.output_mode="reg_only";
1247 defparam line_counter_sig_0_.lut_mask="bbbb";
1248 defparam line_counter_sig_0_.synch_mode="on";
1249 defparam line_counter_sig_0_.sum_lutc_input="datac";
1250 // @13:187
1251   stratix_lcell v_enable_sig_Z (
1252         .regout(v_enable_sig),
1253         .clk(clk_pin_c),
1254         .dataa(hsync_state_3),
1255         .datab(hsync_state_1),
1256         .datac(VCC),
1257         .datad(VCC),
1258         .aclr(GND),
1259         .sclr(un6_dly_counter_0_x),
1260         .sload(GND),
1261         .ena(v_enable_sig_1_0_0_0_g0_i_o4),
1262         .inverta(GND),
1263         .aload(GND),
1264         .regcascin(GND)
1265 );
1266 defparam v_enable_sig_Z.operation_mode="normal";
1267 defparam v_enable_sig_Z.output_mode="reg_only";
1268 defparam v_enable_sig_Z.lut_mask="eeee";
1269 defparam v_enable_sig_Z.synch_mode="on";
1270 defparam v_enable_sig_Z.sum_lutc_input="datac";
1271 // @13:300
1272   stratix_lcell h_enable_sig_Z (
1273         .regout(h_enable_sig),
1274         .clk(clk_pin_c),
1275         .dataa(vsync_state_3),
1276         .datab(vsync_state_1),
1277         .datac(VCC),
1278         .datad(VCC),
1279         .aclr(GND),
1280         .sclr(un6_dly_counter_0_x),
1281         .sload(GND),
1282         .ena(h_enable_sig_1_0_0_0_g0_i_o4),
1283         .inverta(GND),
1284         .aload(GND),
1285         .regcascin(GND)
1286 );
1287 defparam h_enable_sig_Z.operation_mode="normal";
1288 defparam h_enable_sig_Z.output_mode="reg_only";
1289 defparam h_enable_sig_Z.lut_mask="eeee";
1290 defparam h_enable_sig_Z.synch_mode="on";
1291 defparam h_enable_sig_Z.sum_lutc_input="datac";
1292 // @13:187
1293   stratix_lcell h_sync_Z (
1294         .regout(h_sync),
1295         .clk(clk_pin_c),
1296         .dataa(reset_pin_c),
1297         .datab(dly_counter_0),
1298         .datac(dly_counter_1),
1299         .datad(h_sync_1_0_0_0_g1),
1300         .aclr(GND),
1301         .sclr(GND),
1302         .sload(GND),
1303         .ena(VCC),
1304         .inverta(GND),
1305         .aload(GND),
1306         .regcascin(GND)
1307 );
1308 defparam h_sync_Z.operation_mode="normal";
1309 defparam h_sync_Z.output_mode="reg_only";
1310 defparam h_sync_Z.lut_mask="ff7f";
1311 defparam h_sync_Z.synch_mode="off";
1312 defparam h_sync_Z.sum_lutc_input="datac";
1313 // @13:300
1314   stratix_lcell v_sync_Z (
1315         .regout(v_sync),
1316         .clk(clk_pin_c),
1317         .dataa(reset_pin_c),
1318         .datab(dly_counter_0),
1319         .datac(dly_counter_1),
1320         .datad(v_sync_1_0_0_0_g1),
1321         .aclr(GND),
1322         .sclr(GND),
1323         .sload(GND),
1324         .ena(VCC),
1325         .inverta(GND),
1326         .aload(GND),
1327         .regcascin(GND)
1328 );
1329 defparam v_sync_Z.operation_mode="normal";
1330 defparam v_sync_Z.output_mode="reg_only";
1331 defparam v_sync_Z.lut_mask="ff7f";
1332 defparam v_sync_Z.synch_mode="off";
1333 defparam v_sync_Z.sum_lutc_input="datac";
1334 // @13:300
1335   stratix_lcell vsync_state_5_ (
1336         .regout(vsync_state_5),
1337         .clk(clk_pin_c),
1338         .dataa(vsync_state_6),
1339         .datab(vsync_state_0),
1340         .datac(VCC),
1341         .datad(VCC),
1342         .aclr(GND),
1343         .sclr(un6_dly_counter_0_x),
1344         .sload(GND),
1345         .ena(vsync_state_next_2_sqmuxa),
1346         .inverta(GND),
1347         .aload(GND),
1348         .regcascin(GND)
1349 );
1350 defparam vsync_state_5_.operation_mode="normal";
1351 defparam vsync_state_5_.output_mode="reg_only";
1352 defparam vsync_state_5_.lut_mask="eeee";
1353 defparam vsync_state_5_.synch_mode="on";
1354 defparam vsync_state_5_.sum_lutc_input="datac";
1355 // @13:300
1356   stratix_lcell vsync_state_4_ (
1357         .regout(vsync_state_4),
1358         .clk(clk_pin_c),
1359         .dataa(vsync_counter_0),
1360         .datab(vsync_counter_9),
1361         .datac(vsync_state_5),
1362         .datad(un14_vsync_counter_8),
1363         .aclr(GND),
1364         .sclr(un6_dly_counter_0_x),
1365         .sload(GND),
1366         .ena(vsync_state_next_2_sqmuxa),
1367         .inverta(GND),
1368         .aload(GND),
1369         .regcascin(GND)
1370 );
1371 defparam vsync_state_4_.operation_mode="normal";
1372 defparam vsync_state_4_.output_mode="reg_only";
1373 defparam vsync_state_4_.lut_mask="2000";
1374 defparam vsync_state_4_.synch_mode="on";
1375 defparam vsync_state_4_.sum_lutc_input="datac";
1376 // @13:300
1377   stratix_lcell vsync_state_3_ (
1378         .regout(vsync_state_3),
1379         .clk(clk_pin_c),
1380         .dataa(vsync_state_1),
1381         .datab(VCC),
1382         .datac(VCC),
1383         .datad(VCC),
1384         .aclr(GND),
1385         .sclr(un6_dly_counter_0_x),
1386         .sload(GND),
1387         .ena(vsync_state_next_2_sqmuxa),
1388         .inverta(GND),
1389         .aload(GND),
1390         .regcascin(GND)
1391 );
1392 defparam vsync_state_3_.operation_mode="normal";
1393 defparam vsync_state_3_.output_mode="reg_only";
1394 defparam vsync_state_3_.lut_mask="aaaa";
1395 defparam vsync_state_3_.synch_mode="on";
1396 defparam vsync_state_3_.sum_lutc_input="datac";
1397 // @13:300
1398   stratix_lcell vsync_state_2_ (
1399         .regout(vsync_state_2),
1400         .clk(clk_pin_c),
1401         .dataa(vsync_counter_0),
1402         .datab(vsync_counter_9),
1403         .datac(vsync_state_3),
1404         .datad(un14_vsync_counter_8),
1405         .aclr(GND),
1406         .sclr(un6_dly_counter_0_x),
1407         .sload(GND),
1408         .ena(vsync_state_next_2_sqmuxa),
1409         .inverta(GND),
1410         .aload(GND),
1411         .regcascin(GND)
1412 );
1413 defparam vsync_state_2_.operation_mode="normal";
1414 defparam vsync_state_2_.output_mode="reg_only";
1415 defparam vsync_state_2_.lut_mask="8000";
1416 defparam vsync_state_2_.synch_mode="on";
1417 defparam vsync_state_2_.sum_lutc_input="datac";
1418 // @13:187
1419   stratix_lcell hsync_state_5_ (
1420         .regout(hsync_state_5),
1421         .clk(clk_pin_c),
1422         .dataa(hsync_state_6),
1423         .datab(hsync_state_0),
1424         .datac(VCC),
1425         .datad(VCC),
1426         .aclr(GND),
1427         .sclr(un6_dly_counter_0_x),
1428         .sload(GND),
1429         .ena(hsync_state_3_0_0_0__g0_0),
1430         .inverta(GND),
1431         .aload(GND),
1432         .regcascin(GND)
1433 );
1434 defparam hsync_state_5_.operation_mode="normal";
1435 defparam hsync_state_5_.output_mode="reg_only";
1436 defparam hsync_state_5_.lut_mask="eeee";
1437 defparam hsync_state_5_.synch_mode="on";
1438 defparam hsync_state_5_.sum_lutc_input="datac";
1439 // @13:187
1440   stratix_lcell hsync_state_4_ (
1441         .regout(hsync_state_4),
1442         .clk(clk_pin_c),
1443         .dataa(hsync_state_5),
1444         .datab(un10_hsync_counter_3),
1445         .datac(un10_hsync_counter_1),
1446         .datad(un10_hsync_counter_4),
1447         .aclr(GND),
1448         .sclr(un6_dly_counter_0_x),
1449         .sload(GND),
1450         .ena(hsync_state_3_0_0_0__g0_0),
1451         .inverta(GND),
1452         .aload(GND),
1453         .regcascin(GND)
1454 );
1455 defparam hsync_state_4_.operation_mode="normal";
1456 defparam hsync_state_4_.output_mode="reg_only";
1457 defparam hsync_state_4_.lut_mask="8000";
1458 defparam hsync_state_4_.synch_mode="on";
1459 defparam hsync_state_4_.sum_lutc_input="datac";
1460 // @13:187
1461   stratix_lcell hsync_state_3_ (
1462         .regout(hsync_state_3),
1463         .clk(clk_pin_c),
1464         .dataa(hsync_state_1),
1465         .datab(VCC),
1466         .datac(VCC),
1467         .datad(VCC),
1468         .aclr(GND),
1469         .sclr(un6_dly_counter_0_x),
1470         .sload(GND),
1471         .ena(hsync_state_3_0_0_0__g0_0),
1472         .inverta(GND),
1473         .aload(GND),
1474         .regcascin(GND)
1475 );
1476 defparam hsync_state_3_.operation_mode="normal";
1477 defparam hsync_state_3_.output_mode="reg_only";
1478 defparam hsync_state_3_.lut_mask="aaaa";
1479 defparam hsync_state_3_.synch_mode="on";
1480 defparam hsync_state_3_.sum_lutc_input="datac";
1481 // @13:187
1482   stratix_lcell hsync_state_2_ (
1483         .regout(hsync_state_2),
1484         .clk(clk_pin_c),
1485         .dataa(hsync_state_3),
1486         .datab(un12_hsync_counter),
1487         .datac(VCC),
1488         .datad(VCC),
1489         .aclr(GND),
1490         .sclr(un6_dly_counter_0_x),
1491         .sload(GND),
1492         .ena(hsync_state_3_0_0_0__g0_0),
1493         .inverta(GND),
1494         .aload(GND),
1495         .regcascin(GND)
1496 );
1497 defparam hsync_state_2_.operation_mode="normal";
1498 defparam hsync_state_2_.output_mode="reg_only";
1499 defparam hsync_state_2_.lut_mask="8888";
1500 defparam hsync_state_2_.synch_mode="on";
1501 defparam hsync_state_2_.sum_lutc_input="datac";
1502 // @13:187
1503   stratix_lcell hsync_state_1_ (
1504         .regout(hsync_state_1),
1505         .clk(clk_pin_c),
1506         .dataa(hsync_state_4),
1507         .datab(un11_hsync_counter_2),
1508         .datac(un10_hsync_counter_1),
1509         .datad(un11_hsync_counter_3),
1510         .aclr(GND),
1511         .sclr(un6_dly_counter_0_x),
1512         .sload(GND),
1513         .ena(hsync_state_3_0_0_0__g0_0),
1514         .inverta(GND),
1515         .aload(GND),
1516         .regcascin(GND)
1517 );
1518 defparam hsync_state_1_.operation_mode="normal";
1519 defparam hsync_state_1_.output_mode="reg_only";
1520 defparam hsync_state_1_.lut_mask="8000";
1521 defparam hsync_state_1_.synch_mode="on";
1522 defparam hsync_state_1_.sum_lutc_input="datac";
1523 // @13:187
1524   stratix_lcell hsync_state_0_ (
1525         .regout(hsync_state_0),
1526         .clk(clk_pin_c),
1527         .dataa(hsync_state_2),
1528         .datab(un13_hsync_counter),
1529         .datac(VCC),
1530         .datad(VCC),
1531         .aclr(GND),
1532         .sclr(un6_dly_counter_0_x),
1533         .sload(GND),
1534         .ena(hsync_state_3_0_0_0__g0_0),
1535         .inverta(GND),
1536         .aload(GND),
1537         .regcascin(GND)
1538 );
1539 defparam hsync_state_0_.operation_mode="normal";
1540 defparam hsync_state_0_.output_mode="reg_only";
1541 defparam hsync_state_0_.lut_mask="8888";
1542 defparam hsync_state_0_.synch_mode="on";
1543 defparam hsync_state_0_.sum_lutc_input="datac";
1544 // @13:97
1545   stratix_lcell vsync_state_next_2_sqmuxa_cZ (
1546         .combout(vsync_state_next_2_sqmuxa),
1547         .clk(GND),
1548         .dataa(un6_dly_counter_0_x),
1549         .datab(vsync_state_next_1_sqmuxa_1),
1550         .datac(vsync_state_next_1_sqmuxa_3),
1551         .datad(un1_vsync_state_next_1_sqmuxa_0),
1552         .aclr(GND),
1553         .sclr(GND),
1554         .sload(GND),
1555         .ena(VCC),
1556         .inverta(GND),
1557         .aload(GND),
1558         .regcascin(GND)
1559 );
1560 defparam vsync_state_next_2_sqmuxa_cZ.operation_mode="normal";
1561 defparam vsync_state_next_2_sqmuxa_cZ.output_mode="comb_only";
1562 defparam vsync_state_next_2_sqmuxa_cZ.lut_mask="aaab";
1563 defparam vsync_state_next_2_sqmuxa_cZ.synch_mode="off";
1564 defparam vsync_state_next_2_sqmuxa_cZ.sum_lutc_input="datac";
1565   stratix_lcell hsync_state_3_0_0_0__g0_0_cZ (
1566         .combout(hsync_state_3_0_0_0__g0_0),
1567         .clk(GND),
1568         .dataa(hsync_state_next_1_sqmuxa_1),
1569         .datab(hsync_state_next_1_sqmuxa_2),
1570         .datac(un6_dly_counter_0_x),
1571         .datad(un1_hsync_state_next_1_sqmuxa_0),
1572         .aclr(GND),
1573         .sclr(GND),
1574         .sload(GND),
1575         .ena(VCC),
1576         .inverta(GND),
1577         .aload(GND),
1578         .regcascin(GND)
1579 );
1580 defparam hsync_state_3_0_0_0__g0_0_cZ.operation_mode="normal";
1581 defparam hsync_state_3_0_0_0__g0_0_cZ.output_mode="comb_only";
1582 defparam hsync_state_3_0_0_0__g0_0_cZ.lut_mask="f0f1";
1583 defparam hsync_state_3_0_0_0__g0_0_cZ.synch_mode="off";
1584 defparam hsync_state_3_0_0_0__g0_0_cZ.sum_lutc_input="datac";
1585 // @13:206
1586   stratix_lcell un1_hsync_state_next_1_sqmuxa_0_cZ (
1587         .combout(un1_hsync_state_next_1_sqmuxa_0),
1588         .clk(GND),
1589         .dataa(hsync_state_2),
1590         .datab(hsync_state_3),
1591         .datac(un13_hsync_counter),
1592         .datad(un12_hsync_counter),
1593         .aclr(GND),
1594         .sclr(GND),
1595         .sload(GND),
1596         .ena(VCC),
1597         .inverta(GND),
1598         .aload(GND),
1599         .regcascin(GND)
1600 );
1601 defparam un1_hsync_state_next_1_sqmuxa_0_cZ.operation_mode="normal";
1602 defparam un1_hsync_state_next_1_sqmuxa_0_cZ.output_mode="comb_only";
1603 defparam un1_hsync_state_next_1_sqmuxa_0_cZ.lut_mask="0ace";
1604 defparam un1_hsync_state_next_1_sqmuxa_0_cZ.synch_mode="off";
1605 defparam un1_hsync_state_next_1_sqmuxa_0_cZ.sum_lutc_input="datac";
1606 // @13:319
1607   stratix_lcell un1_vsync_state_next_1_sqmuxa_0_cZ (
1608         .combout(un1_vsync_state_next_1_sqmuxa_0),
1609         .clk(GND),
1610         .dataa(vsync_state_2),
1611         .datab(un12_vsync_counter_6),
1612         .datac(un15_vsync_counter_4),
1613         .datad(vsync_state_next_1_sqmuxa_2),
1614         .aclr(GND),
1615         .sclr(GND),
1616         .sload(GND),
1617         .ena(VCC),
1618         .inverta(GND),
1619         .aload(GND),
1620         .regcascin(GND)
1621 );
1622 defparam un1_vsync_state_next_1_sqmuxa_0_cZ.operation_mode="normal";
1623 defparam un1_vsync_state_next_1_sqmuxa_0_cZ.output_mode="comb_only";
1624 defparam un1_vsync_state_next_1_sqmuxa_0_cZ.lut_mask="ff2a";
1625 defparam un1_vsync_state_next_1_sqmuxa_0_cZ.synch_mode="off";
1626 defparam un1_vsync_state_next_1_sqmuxa_0_cZ.sum_lutc_input="datac";
1627   stratix_lcell vsync_state_3_iv_0_0__g0_0_a3_0_cZ (
1628         .combout(vsync_state_3_iv_0_0__g0_0_a3_0),
1629         .clk(GND),
1630         .dataa(vsync_state_2),
1631         .datab(un12_vsync_counter_6),
1632         .datac(un15_vsync_counter_4),
1633         .datad(VCC),
1634         .aclr(GND),
1635         .sclr(GND),
1636         .sload(GND),
1637         .ena(VCC),
1638         .inverta(GND),
1639         .aload(GND),
1640         .regcascin(GND)
1641 );
1642 defparam vsync_state_3_iv_0_0__g0_0_a3_0_cZ.operation_mode="normal";
1643 defparam vsync_state_3_iv_0_0__g0_0_a3_0_cZ.output_mode="comb_only";
1644 defparam vsync_state_3_iv_0_0__g0_0_a3_0_cZ.lut_mask="8080";
1645 defparam vsync_state_3_iv_0_0__g0_0_a3_0_cZ.synch_mode="off";
1646 defparam vsync_state_3_iv_0_0__g0_0_a3_0_cZ.sum_lutc_input="datac";
1647 // @13:139
1648   stratix_lcell LINE_COUNT_next_un10_line_counter_siglto8 (
1649         .combout(un10_line_counter_siglto8),
1650         .clk(GND),
1651         .dataa(line_counter_sig_7),
1652         .datab(line_counter_sig_8),
1653         .datac(line_counter_sig_6),
1654         .datad(un10_line_counter_siglto5),
1655         .aclr(GND),
1656         .sclr(GND),
1657         .sload(GND),
1658         .ena(VCC),
1659         .inverta(GND),
1660         .aload(GND),
1661         .regcascin(GND)
1662 );
1663 defparam LINE_COUNT_next_un10_line_counter_siglto8.operation_mode="normal";
1664 defparam LINE_COUNT_next_un10_line_counter_siglto8.output_mode="comb_only";
1665 defparam LINE_COUNT_next_un10_line_counter_siglto8.lut_mask="ff7f";
1666 defparam LINE_COUNT_next_un10_line_counter_siglto8.synch_mode="off";
1667 defparam LINE_COUNT_next_un10_line_counter_siglto8.sum_lutc_input="datac";
1668 // @10:161
1669   stratix_lcell G_2 (
1670         .combout(G_2_i),
1671         .clk(GND),
1672         .dataa(hsync_state_0),
1673         .datab(hsync_state_6),
1674         .datac(un9_hsync_counterlt9),
1675         .datad(un6_dly_counter_0_x),
1676         .aclr(GND),
1677         .sclr(GND),
1678         .sload(GND),
1679         .ena(VCC),
1680         .inverta(GND),
1681         .aload(GND),
1682         .regcascin(GND)
1683 );
1684 defparam G_2.operation_mode="normal";
1685 defparam G_2.output_mode="comb_only";
1686 defparam G_2.lut_mask="0f1f";
1687 defparam G_2.synch_mode="off";
1688 defparam G_2.sum_lutc_input="datac";
1689 // @13:326
1690   stratix_lcell vsync_state_next_1_sqmuxa_1_cZ (
1691         .combout(vsync_state_next_1_sqmuxa_1),
1692         .clk(GND),
1693         .dataa(vsync_counter_0),
1694         .datab(vsync_counter_9),
1695         .datac(vsync_state_5),
1696         .datad(un14_vsync_counter_8),
1697         .aclr(GND),
1698         .sclr(GND),
1699         .sload(GND),
1700         .ena(VCC),
1701         .inverta(GND),
1702         .aload(GND),
1703         .regcascin(GND)
1704 );
1705 defparam vsync_state_next_1_sqmuxa_1_cZ.operation_mode="normal";
1706 defparam vsync_state_next_1_sqmuxa_1_cZ.output_mode="comb_only";
1707 defparam vsync_state_next_1_sqmuxa_1_cZ.lut_mask="d0f0";
1708 defparam vsync_state_next_1_sqmuxa_1_cZ.synch_mode="off";
1709 defparam vsync_state_next_1_sqmuxa_1_cZ.sum_lutc_input="datac";
1710 // @13:331
1711   stratix_lcell vsync_state_next_1_sqmuxa_2_cZ (
1712         .combout(vsync_state_next_1_sqmuxa_2),
1713         .clk(GND),
1714         .dataa(vsync_state_4),
1715         .datab(un12_vsync_counter_7),
1716         .datac(un13_vsync_counter_4),
1717         .datad(VCC),
1718         .aclr(GND),
1719         .sclr(GND),
1720         .sload(GND),
1721         .ena(VCC),
1722         .inverta(GND),
1723         .aload(GND),
1724         .regcascin(GND)
1725 );
1726 defparam vsync_state_next_1_sqmuxa_2_cZ.operation_mode="normal";
1727 defparam vsync_state_next_1_sqmuxa_2_cZ.output_mode="comb_only";
1728 defparam vsync_state_next_1_sqmuxa_2_cZ.lut_mask="2a2a";
1729 defparam vsync_state_next_1_sqmuxa_2_cZ.synch_mode="off";
1730 defparam vsync_state_next_1_sqmuxa_2_cZ.sum_lutc_input="datac";
1731 // @13:339
1732   stratix_lcell vsync_state_next_1_sqmuxa_3_cZ (
1733         .combout(vsync_state_next_1_sqmuxa_3),
1734         .clk(GND),
1735         .dataa(vsync_counter_0),
1736         .datab(vsync_counter_9),
1737         .datac(vsync_state_3),
1738         .datad(un14_vsync_counter_8),
1739         .aclr(GND),
1740         .sclr(GND),
1741         .sload(GND),
1742         .ena(VCC),
1743         .inverta(GND),
1744         .aload(GND),
1745         .regcascin(GND)
1746 );
1747 defparam vsync_state_next_1_sqmuxa_3_cZ.operation_mode="normal";
1748 defparam vsync_state_next_1_sqmuxa_3_cZ.output_mode="comb_only";
1749 defparam vsync_state_next_1_sqmuxa_3_cZ.lut_mask="70f0";
1750 defparam vsync_state_next_1_sqmuxa_3_cZ.synch_mode="off";
1751 defparam vsync_state_next_1_sqmuxa_3_cZ.sum_lutc_input="datac";
1752 // @10:161
1753   stratix_lcell G_16 (
1754         .combout(G_16_i),
1755         .clk(GND),
1756         .dataa(vsync_state_0),
1757         .datab(vsync_state_6),
1758         .datac(un9_vsync_counterlt9),
1759         .datad(un6_dly_counter_0_x),
1760         .aclr(GND),
1761         .sclr(GND),
1762         .sload(GND),
1763         .ena(VCC),
1764         .inverta(GND),
1765         .aload(GND),
1766         .regcascin(GND)
1767 );
1768 defparam G_16.operation_mode="normal";
1769 defparam G_16.output_mode="comb_only";
1770 defparam G_16.lut_mask="0f1f";
1771 defparam G_16.synch_mode="off";
1772 defparam G_16.sum_lutc_input="datac";
1773 // @13:218
1774   stratix_lcell hsync_state_next_1_sqmuxa_2_cZ (
1775         .combout(hsync_state_next_1_sqmuxa_2),
1776         .clk(GND),
1777         .dataa(hsync_state_4),
1778         .datab(un11_hsync_counter_2),
1779         .datac(un10_hsync_counter_1),
1780         .datad(un11_hsync_counter_3),
1781         .aclr(GND),
1782         .sclr(GND),
1783         .sload(GND),
1784         .ena(VCC),
1785         .inverta(GND),
1786         .aload(GND),
1787         .regcascin(GND)
1788 );
1789 defparam hsync_state_next_1_sqmuxa_2_cZ.operation_mode="normal";
1790 defparam hsync_state_next_1_sqmuxa_2_cZ.output_mode="comb_only";
1791 defparam hsync_state_next_1_sqmuxa_2_cZ.lut_mask="2aaa";
1792 defparam hsync_state_next_1_sqmuxa_2_cZ.synch_mode="off";
1793 defparam hsync_state_next_1_sqmuxa_2_cZ.sum_lutc_input="datac";
1794 // @13:213
1795   stratix_lcell hsync_state_next_1_sqmuxa_1_cZ (
1796         .combout(hsync_state_next_1_sqmuxa_1),
1797         .clk(GND),
1798         .dataa(hsync_state_5),
1799         .datab(un10_hsync_counter_3),
1800         .datac(un10_hsync_counter_1),
1801         .datad(un10_hsync_counter_4),
1802         .aclr(GND),
1803         .sclr(GND),
1804         .sload(GND),
1805         .ena(VCC),
1806         .inverta(GND),
1807         .aload(GND),
1808         .regcascin(GND)
1809 );
1810 defparam hsync_state_next_1_sqmuxa_1_cZ.operation_mode="normal";
1811 defparam hsync_state_next_1_sqmuxa_1_cZ.output_mode="comb_only";
1812 defparam hsync_state_next_1_sqmuxa_1_cZ.lut_mask="2aaa";
1813 defparam hsync_state_next_1_sqmuxa_1_cZ.synch_mode="off";
1814 defparam hsync_state_next_1_sqmuxa_1_cZ.sum_lutc_input="datac";
1815 // @13:111
1816   stratix_lcell COLUMN_COUNT_next_un10_column_counter_siglto9 (
1817         .combout(un10_column_counter_siglto9),
1818         .clk(GND),
1819         .dataa(column_counter_sig_7),
1820         .datab(column_counter_sig_8),
1821         .datac(column_counter_sig_9),
1822         .datad(un10_column_counter_siglt6),
1823         .aclr(GND),
1824         .sclr(GND),
1825         .sload(GND),
1826         .ena(VCC),
1827         .inverta(GND),
1828         .aload(GND),
1829         .regcascin(GND)
1830 );
1831 defparam COLUMN_COUNT_next_un10_column_counter_siglto9.operation_mode="normal";
1832 defparam COLUMN_COUNT_next_un10_column_counter_siglto9.output_mode="comb_only";
1833 defparam COLUMN_COUNT_next_un10_column_counter_siglto9.lut_mask="1f0f";
1834 defparam COLUMN_COUNT_next_un10_column_counter_siglto9.synch_mode="off";
1835 defparam COLUMN_COUNT_next_un10_column_counter_siglto9.sum_lutc_input="datac";
1836 // @13:226
1837   stratix_lcell HSYNC_FSM_next_un12_hsync_counter (
1838         .combout(un12_hsync_counter),
1839         .clk(GND),
1840         .dataa(hsync_counter_0),
1841         .datab(hsync_counter_1),
1842         .datac(un12_hsync_counter_3),
1843         .datad(un12_hsync_counter_4),
1844         .aclr(GND),
1845         .sclr(GND),
1846         .sload(GND),
1847         .ena(VCC),
1848         .inverta(GND),
1849         .aload(GND),
1850         .regcascin(GND)
1851 );
1852 defparam HSYNC_FSM_next_un12_hsync_counter.operation_mode="normal";
1853 defparam HSYNC_FSM_next_un12_hsync_counter.output_mode="comb_only";
1854 defparam HSYNC_FSM_next_un12_hsync_counter.lut_mask="8000";
1855 defparam HSYNC_FSM_next_un12_hsync_counter.synch_mode="off";
1856 defparam HSYNC_FSM_next_un12_hsync_counter.sum_lutc_input="datac";
1857 // @13:231
1858   stratix_lcell HSYNC_FSM_next_un13_hsync_counter (
1859         .combout(un13_hsync_counter),
1860         .clk(GND),
1861         .dataa(hsync_counter_6),
1862         .datab(hsync_counter_7),
1863         .datac(un13_hsync_counter_2),
1864         .datad(un13_hsync_counter_7),
1865         .aclr(GND),
1866         .sclr(GND),
1867         .sload(GND),
1868         .ena(VCC),
1869         .inverta(GND),
1870         .aload(GND),
1871         .regcascin(GND)
1872 );
1873 defparam HSYNC_FSM_next_un13_hsync_counter.operation_mode="normal";
1874 defparam HSYNC_FSM_next_un13_hsync_counter.output_mode="comb_only";
1875 defparam HSYNC_FSM_next_un13_hsync_counter.lut_mask="1000";
1876 defparam HSYNC_FSM_next_un13_hsync_counter.synch_mode="off";
1877 defparam HSYNC_FSM_next_un13_hsync_counter.sum_lutc_input="datac";
1878 // @13:172
1879   stratix_lcell HSYNC_COUNT_next_un9_hsync_counterlt9 (
1880         .combout(un9_hsync_counterlt9),
1881         .clk(GND),
1882         .dataa(hsync_counter_8),
1883         .datab(hsync_counter_9),
1884         .datac(un9_hsync_counterlt9_3),
1885         .datad(un13_hsync_counter_7),
1886         .aclr(GND),
1887         .sclr(GND),
1888         .sload(GND),
1889         .ena(VCC),
1890         .inverta(GND),
1891         .aload(GND),
1892         .regcascin(GND)
1893 );
1894 defparam HSYNC_COUNT_next_un9_hsync_counterlt9.operation_mode="normal";
1895 defparam HSYNC_COUNT_next_un9_hsync_counterlt9.output_mode="comb_only";
1896 defparam HSYNC_COUNT_next_un9_hsync_counterlt9.lut_mask="f7ff";
1897 defparam HSYNC_COUNT_next_un9_hsync_counterlt9.synch_mode="off";
1898 defparam HSYNC_COUNT_next_un9_hsync_counterlt9.sum_lutc_input="datac";
1899 // @13:281
1900   stratix_lcell VSYNC_COUNT_next_un9_vsync_counterlt9 (
1901         .combout(un9_vsync_counterlt9),
1902         .clk(GND),
1903         .dataa(vsync_counter_4),
1904         .datab(vsync_counter_5),
1905         .datac(un9_vsync_counterlt9_5),
1906         .datad(un9_vsync_counterlt9_6),
1907         .aclr(GND),
1908         .sclr(GND),
1909         .sload(GND),
1910         .ena(VCC),
1911         .inverta(GND),
1912         .aload(GND),
1913         .regcascin(GND)
1914 );
1915 defparam VSYNC_COUNT_next_un9_vsync_counterlt9.operation_mode="normal";
1916 defparam VSYNC_COUNT_next_un9_vsync_counterlt9.output_mode="comb_only";
1917 defparam VSYNC_COUNT_next_un9_vsync_counterlt9.lut_mask="fff7";
1918 defparam VSYNC_COUNT_next_un9_vsync_counterlt9.synch_mode="off";
1919 defparam VSYNC_COUNT_next_un9_vsync_counterlt9.sum_lutc_input="datac";
1920 // @13:139
1921   stratix_lcell LINE_COUNT_next_un10_line_counter_siglto5 (
1922         .combout(un10_line_counter_siglto5),
1923         .clk(GND),
1924         .dataa(line_counter_sig_1),
1925         .datab(line_counter_sig_2),
1926         .datac(line_counter_sig_5),
1927         .datad(un10_line_counter_siglt4_2),
1928         .aclr(GND),
1929         .sclr(GND),
1930         .sload(GND),
1931         .ena(VCC),
1932         .inverta(GND),
1933         .aload(GND),
1934         .regcascin(GND)
1935 );
1936 defparam LINE_COUNT_next_un10_line_counter_siglto5.operation_mode="normal";
1937 defparam LINE_COUNT_next_un10_line_counter_siglto5.output_mode="comb_only";
1938 defparam LINE_COUNT_next_un10_line_counter_siglto5.lut_mask="0f07";
1939 defparam LINE_COUNT_next_un10_line_counter_siglto5.synch_mode="off";
1940 defparam LINE_COUNT_next_un10_line_counter_siglto5.sum_lutc_input="datac";
1941 // @13:331
1942   stratix_lcell VSYNC_FSM_next_un13_vsync_counter_4 (
1943         .combout(un13_vsync_counter_4),
1944         .clk(GND),
1945         .dataa(vsync_counter_0),
1946         .datab(vsync_counter_5),
1947         .datac(un13_vsync_counter_3),
1948         .datad(VCC),
1949         .aclr(GND),
1950         .sclr(GND),
1951         .sload(GND),
1952         .ena(VCC),
1953         .inverta(GND),
1954         .aload(GND),
1955         .regcascin(GND)
1956 );
1957 defparam VSYNC_FSM_next_un13_vsync_counter_4.operation_mode="normal";
1958 defparam VSYNC_FSM_next_un13_vsync_counter_4.output_mode="comb_only";
1959 defparam VSYNC_FSM_next_un13_vsync_counter_4.lut_mask="8080";
1960 defparam VSYNC_FSM_next_un13_vsync_counter_4.synch_mode="off";
1961 defparam VSYNC_FSM_next_un13_vsync_counter_4.sum_lutc_input="datac";
1962 // @13:344
1963   stratix_lcell VSYNC_FSM_next_un15_vsync_counter_4 (
1964         .combout(un15_vsync_counter_4),
1965         .clk(GND),
1966         .dataa(vsync_counter_1),
1967         .datab(vsync_counter_4),
1968         .datac(un15_vsync_counter_3),
1969         .datad(VCC),
1970         .aclr(GND),
1971         .sclr(GND),
1972         .sload(GND),
1973         .ena(VCC),
1974         .inverta(GND),
1975         .aload(GND),
1976         .regcascin(GND)
1977 );
1978 defparam VSYNC_FSM_next_un15_vsync_counter_4.operation_mode="normal";
1979 defparam VSYNC_FSM_next_un15_vsync_counter_4.output_mode="comb_only";
1980 defparam VSYNC_FSM_next_un15_vsync_counter_4.lut_mask="1010";
1981 defparam VSYNC_FSM_next_un15_vsync_counter_4.synch_mode="off";
1982 defparam VSYNC_FSM_next_un15_vsync_counter_4.sum_lutc_input="datac";
1983 // @13:111
1984   stratix_lcell COLUMN_COUNT_next_un10_column_counter_siglt6 (
1985         .combout(un10_column_counter_siglt6),
1986         .clk(GND),
1987         .dataa(column_counter_sig_0),
1988         .datab(column_counter_sig_1),
1989         .datac(un10_column_counter_siglt6_1),
1990         .datad(un10_column_counter_siglt6_2),
1991         .aclr(GND),
1992         .sclr(GND),
1993         .sload(GND),
1994         .ena(VCC),
1995         .inverta(GND),
1996         .aload(GND),
1997         .regcascin(GND)
1998 );
1999 defparam COLUMN_COUNT_next_un10_column_counter_siglt6.operation_mode="normal";
2000 defparam COLUMN_COUNT_next_un10_column_counter_siglt6.output_mode="comb_only";
2001 defparam COLUMN_COUNT_next_un10_column_counter_siglt6.lut_mask="fff7";
2002 defparam COLUMN_COUNT_next_un10_column_counter_siglt6.synch_mode="off";
2003 defparam COLUMN_COUNT_next_un10_column_counter_siglt6.sum_lutc_input="datac";
2004 // @13:169
2005   stratix_lcell hsync_counter_next_1_sqmuxa_cZ (
2006         .combout(hsync_counter_next_1_sqmuxa),
2007         .clk(GND),
2008         .dataa(reset_pin_c),
2009         .datab(dly_counter_0),
2010         .datac(dly_counter_1),
2011         .datad(d_set_hsync_counter),
2012         .aclr(GND),
2013         .sclr(GND),
2014         .sload(GND),
2015         .ena(VCC),
2016         .inverta(GND),
2017         .aload(GND),
2018         .regcascin(GND)
2019 );
2020 defparam hsync_counter_next_1_sqmuxa_cZ.operation_mode="normal";
2021 defparam hsync_counter_next_1_sqmuxa_cZ.output_mode="comb_only";
2022 defparam hsync_counter_next_1_sqmuxa_cZ.lut_mask="0080";
2023 defparam hsync_counter_next_1_sqmuxa_cZ.synch_mode="off";
2024 defparam hsync_counter_next_1_sqmuxa_cZ.sum_lutc_input="datac";
2025 // @13:111
2026   stratix_lcell column_counter_next_0_sqmuxa_1_1_cZ (
2027         .combout(column_counter_next_0_sqmuxa_1_1),
2028         .clk(GND),
2029         .dataa(reset_pin_c),
2030         .datab(dly_counter_0),
2031         .datac(dly_counter_1),
2032         .datad(hsync_state_1),
2033         .aclr(GND),
2034         .sclr(GND),
2035         .sload(GND),
2036         .ena(VCC),
2037         .inverta(GND),
2038         .aload(GND),
2039         .regcascin(GND)
2040 );
2041 defparam column_counter_next_0_sqmuxa_1_1_cZ.operation_mode="normal";
2042 defparam column_counter_next_0_sqmuxa_1_1_cZ.output_mode="comb_only";
2043 defparam column_counter_next_0_sqmuxa_1_1_cZ.lut_mask="0080";
2044 defparam column_counter_next_0_sqmuxa_1_1_cZ.synch_mode="off";
2045 defparam column_counter_next_0_sqmuxa_1_1_cZ.sum_lutc_input="datac";
2046   stratix_lcell h_sync_1_0_0_0_g1_cZ (
2047         .combout(h_sync_1_0_0_0_g1),
2048         .clk(GND),
2049         .dataa(hsync_state_2),
2050         .datab(h_sync),
2051         .datac(hsync_state_4),
2052         .datad(un1_hsync_state_3_0),
2053         .aclr(GND),
2054         .sclr(GND),
2055         .sload(GND),
2056         .ena(VCC),
2057         .inverta(GND),
2058         .aload(GND),
2059         .regcascin(GND)
2060 );
2061 defparam h_sync_1_0_0_0_g1_cZ.operation_mode="normal";
2062 defparam h_sync_1_0_0_0_g1_cZ.output_mode="comb_only";
2063 defparam h_sync_1_0_0_0_g1_cZ.lut_mask="ccd8";
2064 defparam h_sync_1_0_0_0_g1_cZ.synch_mode="off";
2065 defparam h_sync_1_0_0_0_g1_cZ.sum_lutc_input="datac";
2066 // @13:139
2067   stratix_lcell line_counter_next_0_sqmuxa_1_1_cZ (
2068         .combout(line_counter_next_0_sqmuxa_1_1),
2069         .clk(GND),
2070         .dataa(reset_pin_c),
2071         .datab(dly_counter_0),
2072         .datac(dly_counter_1),
2073         .datad(vsync_state_1),
2074         .aclr(GND),
2075         .sclr(GND),
2076         .sload(GND),
2077         .ena(VCC),
2078         .inverta(GND),
2079         .aload(GND),
2080         .regcascin(GND)
2081 );
2082 defparam line_counter_next_0_sqmuxa_1_1_cZ.operation_mode="normal";
2083 defparam line_counter_next_0_sqmuxa_1_1_cZ.output_mode="comb_only";
2084 defparam line_counter_next_0_sqmuxa_1_1_cZ.lut_mask="0080";
2085 defparam line_counter_next_0_sqmuxa_1_1_cZ.synch_mode="off";
2086 defparam line_counter_next_0_sqmuxa_1_1_cZ.sum_lutc_input="datac";
2087   stratix_lcell v_sync_1_0_0_0_g1_cZ (
2088         .combout(v_sync_1_0_0_0_g1),
2089         .clk(GND),
2090         .dataa(vsync_state_2),
2091         .datab(v_sync),
2092         .datac(vsync_state_4),
2093         .datad(un1_vsync_state_2_0),
2094         .aclr(GND),
2095         .sclr(GND),
2096         .sload(GND),
2097         .ena(VCC),
2098         .inverta(GND),
2099         .aload(GND),
2100         .regcascin(GND)
2101 );
2102 defparam v_sync_1_0_0_0_g1_cZ.operation_mode="normal";
2103 defparam v_sync_1_0_0_0_g1_cZ.output_mode="comb_only";
2104 defparam v_sync_1_0_0_0_g1_cZ.lut_mask="ccd8";
2105 defparam v_sync_1_0_0_0_g1_cZ.synch_mode="off";
2106 defparam v_sync_1_0_0_0_g1_cZ.sum_lutc_input="datac";
2107   stratix_lcell h_enable_sig_1_0_0_0_g0_i_o4_cZ (
2108         .combout(h_enable_sig_1_0_0_0_g0_i_o4),
2109         .clk(GND),
2110         .dataa(vsync_state_4),
2111         .datab(vsync_state_5),
2112         .datac(un6_dly_counter_0_x),
2113         .datad(VCC),
2114         .aclr(GND),
2115         .sclr(GND),
2116         .sload(GND),
2117         .ena(VCC),
2118         .inverta(GND),
2119         .aload(GND),
2120         .regcascin(GND)
2121 );
2122 defparam h_enable_sig_1_0_0_0_g0_i_o4_cZ.operation_mode="normal";
2123 defparam h_enable_sig_1_0_0_0_g0_i_o4_cZ.output_mode="comb_only";
2124 defparam h_enable_sig_1_0_0_0_g0_i_o4_cZ.lut_mask="f1f1";
2125 defparam h_enable_sig_1_0_0_0_g0_i_o4_cZ.synch_mode="off";
2126 defparam h_enable_sig_1_0_0_0_g0_i_o4_cZ.sum_lutc_input="datac";
2127 // @13:278
2128   stratix_lcell vsync_counter_next_1_sqmuxa_cZ (
2129         .combout(vsync_counter_next_1_sqmuxa),
2130         .clk(GND),
2131         .dataa(reset_pin_c),
2132         .datab(dly_counter_0),
2133         .datac(dly_counter_1),
2134         .datad(d_set_vsync_counter),
2135         .aclr(GND),
2136         .sclr(GND),
2137         .sload(GND),
2138         .ena(VCC),
2139         .inverta(GND),
2140         .aload(GND),
2141         .regcascin(GND)
2142 );
2143 defparam vsync_counter_next_1_sqmuxa_cZ.operation_mode="normal";
2144 defparam vsync_counter_next_1_sqmuxa_cZ.output_mode="comb_only";
2145 defparam vsync_counter_next_1_sqmuxa_cZ.lut_mask="0080";
2146 defparam vsync_counter_next_1_sqmuxa_cZ.synch_mode="off";
2147 defparam vsync_counter_next_1_sqmuxa_cZ.sum_lutc_input="datac";
2148 // @13:339
2149   stratix_lcell VSYNC_FSM_next_un14_vsync_counter_8 (
2150         .combout(un14_vsync_counter_8),
2151         .clk(GND),
2152         .dataa(un12_vsync_counter_6),
2153         .datab(un12_vsync_counter_7),
2154         .datac(VCC),
2155         .datad(VCC),
2156         .aclr(GND),
2157         .sclr(GND),
2158         .sload(GND),
2159         .ena(VCC),
2160         .inverta(GND),
2161         .aload(GND),
2162         .regcascin(GND)
2163 );
2164 defparam VSYNC_FSM_next_un14_vsync_counter_8.operation_mode="normal";
2165 defparam VSYNC_FSM_next_un14_vsync_counter_8.output_mode="comb_only";
2166 defparam VSYNC_FSM_next_un14_vsync_counter_8.lut_mask="8888";
2167 defparam VSYNC_FSM_next_un14_vsync_counter_8.synch_mode="off";
2168 defparam VSYNC_FSM_next_un14_vsync_counter_8.sum_lutc_input="datac";
2169   stratix_lcell v_enable_sig_1_0_0_0_g0_i_o4_cZ (
2170         .combout(v_enable_sig_1_0_0_0_g0_i_o4),
2171         .clk(GND),
2172         .dataa(hsync_state_4),
2173         .datab(hsync_state_5),
2174         .datac(un6_dly_counter_0_x),
2175         .datad(VCC),
2176         .aclr(GND),
2177         .sclr(GND),
2178         .sload(GND),
2179         .ena(VCC),
2180         .inverta(GND),
2181         .aload(GND),
2182         .regcascin(GND)
2183 );
2184 defparam v_enable_sig_1_0_0_0_g0_i_o4_cZ.operation_mode="normal";
2185 defparam v_enable_sig_1_0_0_0_g0_i_o4_cZ.output_mode="comb_only";
2186 defparam v_enable_sig_1_0_0_0_g0_i_o4_cZ.lut_mask="f1f1";
2187 defparam v_enable_sig_1_0_0_0_g0_i_o4_cZ.synch_mode="off";
2188 defparam v_enable_sig_1_0_0_0_g0_i_o4_cZ.sum_lutc_input="datac";
2189 // @13:218
2190   stratix_lcell HSYNC_FSM_next_un11_hsync_counter_3 (
2191         .combout(un11_hsync_counter_3),
2192         .clk(GND),
2193         .dataa(hsync_counter_0),
2194         .datab(hsync_counter_1),
2195         .datac(hsync_counter_3),
2196         .datad(hsync_counter_4),
2197         .aclr(GND),
2198         .sclr(GND),
2199         .sload(GND),
2200         .ena(VCC),
2201         .inverta(GND),
2202         .aload(GND),
2203         .regcascin(GND)
2204 );
2205 defparam HSYNC_FSM_next_un11_hsync_counter_3.operation_mode="normal";
2206 defparam HSYNC_FSM_next_un11_hsync_counter_3.output_mode="comb_only";
2207 defparam HSYNC_FSM_next_un11_hsync_counter_3.lut_mask="0008";
2208 defparam HSYNC_FSM_next_un11_hsync_counter_3.synch_mode="off";
2209 defparam HSYNC_FSM_next_un11_hsync_counter_3.sum_lutc_input="datac";
2210 // @13:218
2211   stratix_lcell HSYNC_FSM_next_un11_hsync_counter_2 (
2212         .combout(un11_hsync_counter_2),
2213         .clk(GND),
2214         .dataa(hsync_counter_2),
2215         .datab(hsync_counter_7),
2216         .datac(hsync_counter_6),
2217         .datad(VCC),
2218         .aclr(GND),
2219         .sclr(GND),
2220         .sload(GND),
2221         .ena(VCC),
2222         .inverta(GND),
2223         .aload(GND),
2224         .regcascin(GND)
2225 );
2226 defparam HSYNC_FSM_next_un11_hsync_counter_2.operation_mode="normal";
2227 defparam HSYNC_FSM_next_un11_hsync_counter_2.output_mode="comb_only";
2228 defparam HSYNC_FSM_next_un11_hsync_counter_2.lut_mask="0808";
2229 defparam HSYNC_FSM_next_un11_hsync_counter_2.synch_mode="off";
2230 defparam HSYNC_FSM_next_un11_hsync_counter_2.sum_lutc_input="datac";
2231 // @13:226
2232   stratix_lcell HSYNC_FSM_next_un12_hsync_counter_4 (
2233         .combout(un12_hsync_counter_4),
2234         .clk(GND),
2235         .dataa(hsync_counter_6),
2236         .datab(hsync_counter_7),
2237         .datac(hsync_counter_2),
2238         .datad(hsync_counter_4),
2239         .aclr(GND),
2240         .sclr(GND),
2241         .sload(GND),
2242         .ena(VCC),
2243         .inverta(GND),
2244         .aload(GND),
2245         .regcascin(GND)
2246 );
2247 defparam HSYNC_FSM_next_un12_hsync_counter_4.operation_mode="normal";
2248 defparam HSYNC_FSM_next_un12_hsync_counter_4.output_mode="comb_only";
2249 defparam HSYNC_FSM_next_un12_hsync_counter_4.lut_mask="0010";
2250 defparam HSYNC_FSM_next_un12_hsync_counter_4.synch_mode="off";
2251 defparam HSYNC_FSM_next_un12_hsync_counter_4.sum_lutc_input="datac";
2252 // @13:226
2253   stratix_lcell HSYNC_FSM_next_un12_hsync_counter_3 (
2254         .combout(un12_hsync_counter_3),
2255         .clk(GND),
2256         .dataa(hsync_counter_9),
2257         .datab(hsync_counter_5),
2258         .datac(hsync_counter_8),
2259         .datad(hsync_counter_3),
2260         .aclr(GND),
2261         .sclr(GND),
2262         .sload(GND),
2263         .ena(VCC),
2264         .inverta(GND),
2265         .aload(GND),
2266         .regcascin(GND)
2267 );
2268 defparam HSYNC_FSM_next_un12_hsync_counter_3.operation_mode="normal";
2269 defparam HSYNC_FSM_next_un12_hsync_counter_3.output_mode="comb_only";
2270 defparam HSYNC_FSM_next_un12_hsync_counter_3.lut_mask="0020";
2271 defparam HSYNC_FSM_next_un12_hsync_counter_3.synch_mode="off";
2272 defparam HSYNC_FSM_next_un12_hsync_counter_3.sum_lutc_input="datac";
2273 // @13:172
2274   stratix_lcell HSYNC_COUNT_next_un9_hsync_counterlt9_3 (
2275         .combout(un9_hsync_counterlt9_3),
2276         .clk(GND),
2277         .dataa(hsync_counter_6),
2278         .datab(hsync_counter_7),
2279         .datac(hsync_counter_4),
2280         .datad(hsync_counter_5),
2281         .aclr(GND),
2282         .sclr(GND),
2283         .sload(GND),
2284         .ena(VCC),
2285         .inverta(GND),
2286         .aload(GND),
2287         .regcascin(GND)
2288 );
2289 defparam HSYNC_COUNT_next_un9_hsync_counterlt9_3.operation_mode="normal";
2290 defparam HSYNC_COUNT_next_un9_hsync_counterlt9_3.output_mode="comb_only";
2291 defparam HSYNC_COUNT_next_un9_hsync_counterlt9_3.lut_mask="7fff";
2292 defparam HSYNC_COUNT_next_un9_hsync_counterlt9_3.synch_mode="off";
2293 defparam HSYNC_COUNT_next_un9_hsync_counterlt9_3.sum_lutc_input="datac";
2294 // @13:231
2295   stratix_lcell HSYNC_FSM_next_un13_hsync_counter_2 (
2296         .combout(un13_hsync_counter_2),
2297         .clk(GND),
2298         .dataa(hsync_counter_8),
2299         .datab(hsync_counter_9),
2300         .datac(hsync_counter_4),
2301         .datad(hsync_counter_5),
2302         .aclr(GND),
2303         .sclr(GND),
2304         .sload(GND),
2305         .ena(VCC),
2306         .inverta(GND),
2307         .aload(GND),
2308         .regcascin(GND)
2309 );
2310 defparam HSYNC_FSM_next_un13_hsync_counter_2.operation_mode="normal";
2311 defparam HSYNC_FSM_next_un13_hsync_counter_2.output_mode="comb_only";
2312 defparam HSYNC_FSM_next_un13_hsync_counter_2.lut_mask="0080";
2313 defparam HSYNC_FSM_next_un13_hsync_counter_2.synch_mode="off";
2314 defparam HSYNC_FSM_next_un13_hsync_counter_2.sum_lutc_input="datac";
2315 // @13:281
2316   stratix_lcell VSYNC_COUNT_next_un9_vsync_counterlt9_6 (
2317         .combout(un9_vsync_counterlt9_6),
2318         .clk(GND),
2319         .dataa(vsync_counter_2),
2320         .datab(vsync_counter_3),
2321         .datac(vsync_counter_0),
2322         .datad(vsync_counter_1),
2323         .aclr(GND),
2324         .sclr(GND),
2325         .sload(GND),
2326         .ena(VCC),
2327         .inverta(GND),
2328         .aload(GND),
2329         .regcascin(GND)
2330 );
2331 defparam VSYNC_COUNT_next_un9_vsync_counterlt9_6.operation_mode="normal";
2332 defparam VSYNC_COUNT_next_un9_vsync_counterlt9_6.output_mode="comb_only";
2333 defparam VSYNC_COUNT_next_un9_vsync_counterlt9_6.lut_mask="7fff";
2334 defparam VSYNC_COUNT_next_un9_vsync_counterlt9_6.synch_mode="off";
2335 defparam VSYNC_COUNT_next_un9_vsync_counterlt9_6.sum_lutc_input="datac";
2336 // @13:281
2337   stratix_lcell VSYNC_COUNT_next_un9_vsync_counterlt9_5 (
2338         .combout(un9_vsync_counterlt9_5),
2339         .clk(GND),
2340         .dataa(vsync_counter_8),
2341         .datab(vsync_counter_9),
2342         .datac(vsync_counter_6),
2343         .datad(vsync_counter_7),
2344         .aclr(GND),
2345         .sclr(GND),
2346         .sload(GND),
2347         .ena(VCC),
2348         .inverta(GND),
2349         .aload(GND),
2350         .regcascin(GND)
2351 );
2352 defparam VSYNC_COUNT_next_un9_vsync_counterlt9_5.operation_mode="normal";
2353 defparam VSYNC_COUNT_next_un9_vsync_counterlt9_5.output_mode="comb_only";
2354 defparam VSYNC_COUNT_next_un9_vsync_counterlt9_5.lut_mask="7fff";
2355 defparam VSYNC_COUNT_next_un9_vsync_counterlt9_5.synch_mode="off";
2356 defparam VSYNC_COUNT_next_un9_vsync_counterlt9_5.sum_lutc_input="datac";
2357 // @13:331
2358   stratix_lcell VSYNC_FSM_next_un13_vsync_counter_3 (
2359         .combout(un13_vsync_counter_3),
2360         .clk(GND),
2361         .dataa(vsync_counter_6),
2362         .datab(vsync_counter_7),
2363         .datac(vsync_counter_8),
2364         .datad(vsync_counter_9),
2365         .aclr(GND),
2366         .sclr(GND),
2367         .sload(GND),
2368         .ena(VCC),
2369         .inverta(GND),
2370         .aload(GND),
2371         .regcascin(GND)
2372 );
2373 defparam VSYNC_FSM_next_un13_vsync_counter_3.operation_mode="normal";
2374 defparam VSYNC_FSM_next_un13_vsync_counter_3.output_mode="comb_only";
2375 defparam VSYNC_FSM_next_un13_vsync_counter_3.lut_mask="0001";
2376 defparam VSYNC_FSM_next_un13_vsync_counter_3.synch_mode="off";
2377 defparam VSYNC_FSM_next_un13_vsync_counter_3.sum_lutc_input="datac";
2378 // @13:213
2379   stratix_lcell HSYNC_FSM_next_un10_hsync_counter_4 (
2380         .combout(un10_hsync_counter_4),
2381         .clk(GND),
2382         .dataa(hsync_counter_4),
2383         .datab(hsync_counter_6),
2384         .datac(hsync_counter_1),
2385         .datad(hsync_counter_3),
2386         .aclr(GND),
2387         .sclr(GND),
2388         .sload(GND),
2389         .ena(VCC),
2390         .inverta(GND),
2391         .aload(GND),
2392         .regcascin(GND)
2393 );
2394 defparam HSYNC_FSM_next_un10_hsync_counter_4.operation_mode="normal";
2395 defparam HSYNC_FSM_next_un10_hsync_counter_4.output_mode="comb_only";
2396 defparam HSYNC_FSM_next_un10_hsync_counter_4.lut_mask="8000";
2397 defparam HSYNC_FSM_next_un10_hsync_counter_4.synch_mode="off";
2398 defparam HSYNC_FSM_next_un10_hsync_counter_4.sum_lutc_input="datac";
2399 // @13:213
2400   stratix_lcell HSYNC_FSM_next_un10_hsync_counter_3 (
2401         .combout(un10_hsync_counter_3),
2402         .clk(GND),
2403         .dataa(hsync_counter_0),
2404         .datab(hsync_counter_7),
2405         .datac(hsync_counter_2),
2406         .datad(VCC),
2407         .aclr(GND),
2408         .sclr(GND),
2409         .sload(GND),
2410         .ena(VCC),
2411         .inverta(GND),
2412         .aload(GND),
2413         .regcascin(GND)
2414 );
2415 defparam HSYNC_FSM_next_un10_hsync_counter_3.operation_mode="normal";
2416 defparam HSYNC_FSM_next_un10_hsync_counter_3.output_mode="comb_only";
2417 defparam HSYNC_FSM_next_un10_hsync_counter_3.lut_mask="0101";
2418 defparam HSYNC_FSM_next_un10_hsync_counter_3.synch_mode="off";
2419 defparam HSYNC_FSM_next_un10_hsync_counter_3.sum_lutc_input="datac";
2420 // @13:344
2421   stratix_lcell VSYNC_FSM_next_un15_vsync_counter_3 (
2422         .combout(un15_vsync_counter_3),
2423         .clk(GND),
2424         .dataa(vsync_counter_9),
2425         .datab(vsync_counter_2),
2426         .datac(vsync_counter_3),
2427         .datad(vsync_counter_0),
2428         .aclr(GND),
2429         .sclr(GND),
2430         .sload(GND),
2431         .ena(VCC),
2432         .inverta(GND),
2433         .aload(GND),
2434         .regcascin(GND)
2435 );
2436 defparam VSYNC_FSM_next_un15_vsync_counter_3.operation_mode="normal";
2437 defparam VSYNC_FSM_next_un15_vsync_counter_3.output_mode="comb_only";
2438 defparam VSYNC_FSM_next_un15_vsync_counter_3.lut_mask="0020";
2439 defparam VSYNC_FSM_next_un15_vsync_counter_3.synch_mode="off";
2440 defparam VSYNC_FSM_next_un15_vsync_counter_3.sum_lutc_input="datac";
2441 // @13:111
2442   stratix_lcell COLUMN_COUNT_next_un10_column_counter_siglt6_2 (
2443         .combout(un10_column_counter_siglt6_2),
2444         .clk(GND),
2445         .dataa(column_counter_sig_2),
2446         .datab(column_counter_sig_3),
2447         .datac(column_counter_sig_4),
2448         .datad(VCC),
2449         .aclr(GND),
2450         .sclr(GND),
2451         .sload(GND),
2452         .ena(VCC),
2453         .inverta(GND),
2454         .aload(GND),
2455         .regcascin(GND)
2456 );
2457 defparam COLUMN_COUNT_next_un10_column_counter_siglt6_2.operation_mode="normal";
2458 defparam COLUMN_COUNT_next_un10_column_counter_siglt6_2.output_mode="comb_only";
2459 defparam COLUMN_COUNT_next_un10_column_counter_siglt6_2.lut_mask="7f7f";
2460 defparam COLUMN_COUNT_next_un10_column_counter_siglt6_2.synch_mode="off";
2461 defparam COLUMN_COUNT_next_un10_column_counter_siglt6_2.sum_lutc_input="datac";
2462 // @13:139
2463   stratix_lcell LINE_COUNT_next_un10_line_counter_siglt4_2 (
2464         .combout(un10_line_counter_siglt4_2),
2465         .clk(GND),
2466         .dataa(line_counter_sig_0),
2467         .datab(line_counter_sig_4),
2468         .datac(line_counter_sig_3),
2469         .datad(VCC),
2470         .aclr(GND),
2471         .sclr(GND),
2472         .sload(GND),
2473         .ena(VCC),
2474         .inverta(GND),
2475         .aload(GND),
2476         .regcascin(GND)
2477 );
2478 defparam LINE_COUNT_next_un10_line_counter_siglt4_2.operation_mode="normal";
2479 defparam LINE_COUNT_next_un10_line_counter_siglt4_2.output_mode="comb_only";
2480 defparam LINE_COUNT_next_un10_line_counter_siglt4_2.lut_mask="7f7f";
2481 defparam LINE_COUNT_next_un10_line_counter_siglt4_2.synch_mode="off";
2482 defparam LINE_COUNT_next_un10_line_counter_siglt4_2.sum_lutc_input="datac";
2483 // @13:213
2484   stratix_lcell HSYNC_FSM_next_un10_hsync_counter_1 (
2485         .combout(un10_hsync_counter_1),
2486         .clk(GND),
2487         .dataa(hsync_counter_5),
2488         .datab(hsync_counter_8),
2489         .datac(hsync_counter_9),
2490         .datad(VCC),
2491         .aclr(GND),
2492         .sclr(GND),
2493         .sload(GND),
2494         .ena(VCC),
2495         .inverta(GND),
2496         .aload(GND),
2497         .regcascin(GND)
2498 );
2499 defparam HSYNC_FSM_next_un10_hsync_counter_1.operation_mode="normal";
2500 defparam HSYNC_FSM_next_un10_hsync_counter_1.output_mode="comb_only";
2501 defparam HSYNC_FSM_next_un10_hsync_counter_1.lut_mask="0101";
2502 defparam HSYNC_FSM_next_un10_hsync_counter_1.synch_mode="off";
2503 defparam HSYNC_FSM_next_un10_hsync_counter_1.sum_lutc_input="datac";
2504 // @13:231
2505   stratix_lcell HSYNC_FSM_next_un13_hsync_counter_7 (
2506         .combout(un13_hsync_counter_7),
2507         .clk(GND),
2508         .dataa(hsync_counter_2),
2509         .datab(hsync_counter_3),
2510         .datac(hsync_counter_0),
2511         .datad(hsync_counter_1),
2512         .aclr(GND),
2513         .sclr(GND),
2514         .sload(GND),
2515         .ena(VCC),
2516         .inverta(GND),
2517         .aload(GND),
2518         .regcascin(GND)
2519 );
2520 defparam HSYNC_FSM_next_un13_hsync_counter_7.operation_mode="normal";
2521 defparam HSYNC_FSM_next_un13_hsync_counter_7.output_mode="comb_only";
2522 defparam HSYNC_FSM_next_un13_hsync_counter_7.lut_mask="8000";
2523 defparam HSYNC_FSM_next_un13_hsync_counter_7.synch_mode="off";
2524 defparam HSYNC_FSM_next_un13_hsync_counter_7.sum_lutc_input="datac";
2525 // @13:326
2526   stratix_lcell VSYNC_FSM_next_un12_vsync_counter_6 (
2527         .combout(un12_vsync_counter_6),
2528         .clk(GND),
2529         .dataa(vsync_counter_7),
2530         .datab(vsync_counter_8),
2531         .datac(vsync_counter_5),
2532         .datad(vsync_counter_6),
2533         .aclr(GND),
2534         .sclr(GND),
2535         .sload(GND),
2536         .ena(VCC),
2537         .inverta(GND),
2538         .aload(GND),
2539         .regcascin(GND)
2540 );
2541 defparam VSYNC_FSM_next_un12_vsync_counter_6.operation_mode="normal";
2542 defparam VSYNC_FSM_next_un12_vsync_counter_6.output_mode="comb_only";
2543 defparam VSYNC_FSM_next_un12_vsync_counter_6.lut_mask="0001";
2544 defparam VSYNC_FSM_next_un12_vsync_counter_6.synch_mode="off";
2545 defparam VSYNC_FSM_next_un12_vsync_counter_6.sum_lutc_input="datac";
2546 // @13:326
2547   stratix_lcell VSYNC_FSM_next_un12_vsync_counter_7 (
2548         .combout(un12_vsync_counter_7),
2549         .clk(GND),
2550         .dataa(vsync_counter_3),
2551         .datab(vsync_counter_4),
2552         .datac(vsync_counter_1),
2553         .datad(vsync_counter_2),
2554         .aclr(GND),
2555         .sclr(GND),
2556         .sload(GND),
2557         .ena(VCC),
2558         .inverta(GND),
2559         .aload(GND),
2560         .regcascin(GND)
2561 );
2562 defparam VSYNC_FSM_next_un12_vsync_counter_7.operation_mode="normal";
2563 defparam VSYNC_FSM_next_un12_vsync_counter_7.output_mode="comb_only";
2564 defparam VSYNC_FSM_next_un12_vsync_counter_7.lut_mask="0001";
2565 defparam VSYNC_FSM_next_un12_vsync_counter_7.synch_mode="off";
2566 defparam VSYNC_FSM_next_un12_vsync_counter_7.sum_lutc_input="datac";
2567 // @13:206
2568   stratix_lcell un1_hsync_state_3_0_cZ (
2569         .combout(un1_hsync_state_3_0),
2570         .clk(GND),
2571         .dataa(hsync_state_3),
2572         .datab(hsync_state_1),
2573         .datac(VCC),
2574         .datad(VCC),
2575         .aclr(GND),
2576         .sclr(GND),
2577         .sload(GND),
2578         .ena(VCC),
2579         .inverta(GND),
2580         .aload(GND),
2581         .regcascin(GND)
2582 );
2583 defparam un1_hsync_state_3_0_cZ.operation_mode="normal";
2584 defparam un1_hsync_state_3_0_cZ.output_mode="comb_only";
2585 defparam un1_hsync_state_3_0_cZ.lut_mask="eeee";
2586 defparam un1_hsync_state_3_0_cZ.synch_mode="off";
2587 defparam un1_hsync_state_3_0_cZ.sum_lutc_input="datac";
2588 // @13:111
2589   stratix_lcell COLUMN_COUNT_next_un10_column_counter_siglt6_1 (
2590         .combout(un10_column_counter_siglt6_1),
2591         .clk(GND),
2592         .dataa(column_counter_sig_6),
2593         .datab(column_counter_sig_5),
2594         .datac(VCC),
2595         .datad(VCC),
2596         .aclr(GND),
2597         .sclr(GND),
2598         .sload(GND),
2599         .ena(VCC),
2600         .inverta(GND),
2601         .aload(GND),
2602         .regcascin(GND)
2603 );
2604 defparam COLUMN_COUNT_next_un10_column_counter_siglt6_1.operation_mode="normal";
2605 defparam COLUMN_COUNT_next_un10_column_counter_siglt6_1.output_mode="comb_only";
2606 defparam COLUMN_COUNT_next_un10_column_counter_siglt6_1.lut_mask="7777";
2607 defparam COLUMN_COUNT_next_un10_column_counter_siglt6_1.synch_mode="off";
2608 defparam COLUMN_COUNT_next_un10_column_counter_siglt6_1.sum_lutc_input="datac";
2609 // @13:319
2610   stratix_lcell un1_vsync_state_2_0_cZ (
2611         .combout(un1_vsync_state_2_0),
2612         .clk(GND),
2613         .dataa(vsync_state_3),
2614         .datab(vsync_state_1),
2615         .datac(VCC),
2616         .datad(VCC),
2617         .aclr(GND),
2618         .sclr(GND),
2619         .sload(GND),
2620         .ena(VCC),
2621         .inverta(GND),
2622         .aload(GND),
2623         .regcascin(GND)
2624 );
2625 defparam un1_vsync_state_2_0_cZ.operation_mode="normal";
2626 defparam un1_vsync_state_2_0_cZ.output_mode="comb_only";
2627 defparam un1_vsync_state_2_0_cZ.lut_mask="eeee";
2628 defparam un1_vsync_state_2_0_cZ.synch_mode="off";
2629 defparam un1_vsync_state_2_0_cZ.sum_lutc_input="datac";
2630 // @13:248
2631   stratix_lcell d_set_hsync_counter_cZ (
2632         .combout(d_set_hsync_counter),
2633         .clk(GND),
2634         .dataa(hsync_state_6),
2635         .datab(hsync_state_0),
2636         .datac(VCC),
2637         .datad(VCC),
2638         .aclr(GND),
2639         .sclr(GND),
2640         .sload(GND),
2641         .ena(VCC),
2642         .inverta(GND),
2643         .aload(GND),
2644         .regcascin(GND)
2645 );
2646 defparam d_set_hsync_counter_cZ.operation_mode="normal";
2647 defparam d_set_hsync_counter_cZ.output_mode="comb_only";
2648 defparam d_set_hsync_counter_cZ.lut_mask="eeee";
2649 defparam d_set_hsync_counter_cZ.synch_mode="off";
2650 defparam d_set_hsync_counter_cZ.sum_lutc_input="datac";
2651 // @13:361
2652   stratix_lcell d_set_vsync_counter_cZ (
2653         .combout(d_set_vsync_counter),
2654         .clk(GND),
2655         .dataa(vsync_state_6),
2656         .datab(vsync_state_0),
2657         .datac(VCC),
2658         .datad(VCC),
2659         .aclr(GND),
2660         .sclr(GND),
2661         .sload(GND),
2662         .ena(VCC),
2663         .inverta(GND),
2664         .aload(GND),
2665         .regcascin(GND)
2666 );
2667 defparam d_set_vsync_counter_cZ.operation_mode="normal";
2668 defparam d_set_vsync_counter_cZ.output_mode="comb_only";
2669 defparam d_set_vsync_counter_cZ.lut_mask="eeee";
2670 defparam d_set_vsync_counter_cZ.synch_mode="off";
2671 defparam d_set_vsync_counter_cZ.sum_lutc_input="datac";
2672 // @13:141
2673   stratix_lcell un1_line_counter_sig_9_ (
2674         .combout(un1_line_counter_sig_combout[9]),
2675         .clk(GND),
2676         .dataa(line_counter_sig_7),
2677         .datab(line_counter_sig_8),
2678         .datac(VCC),
2679         .datad(VCC),
2680         .aclr(GND),
2681         .sclr(GND),
2682         .sload(GND),
2683         .ena(VCC),
2684         .cin(un1_line_counter_sig_cout[7]),
2685         .inverta(GND),
2686         .aload(GND),
2687         .regcascin(GND)
2688 );
2689 defparam un1_line_counter_sig_9_.cin_used="true";
2690 defparam un1_line_counter_sig_9_.operation_mode="normal";
2691 defparam un1_line_counter_sig_9_.output_mode="comb_only";
2692 defparam un1_line_counter_sig_9_.lut_mask="6c6c";
2693 defparam un1_line_counter_sig_9_.synch_mode="off";
2694 defparam un1_line_counter_sig_9_.sum_lutc_input="cin";
2695 // @13:141
2696   stratix_lcell un1_line_counter_sig_8_ (
2697         .combout(un1_line_counter_sig_combout[8]),
2698         .clk(GND),
2699         .dataa(line_counter_sig_7),
2700         .datab(VCC),
2701         .datac(VCC),
2702         .datad(VCC),
2703         .aclr(GND),
2704         .sclr(GND),
2705         .sload(GND),
2706         .ena(VCC),
2707         .cin(un1_line_counter_sig_cout[6]),
2708         .inverta(GND),
2709         .aload(GND),
2710         .regcascin(GND)
2711 );
2712 defparam un1_line_counter_sig_8_.cin_used="true";
2713 defparam un1_line_counter_sig_8_.operation_mode="normal";
2714 defparam un1_line_counter_sig_8_.output_mode="comb_only";
2715 defparam un1_line_counter_sig_8_.lut_mask="5a5a";
2716 defparam un1_line_counter_sig_8_.synch_mode="off";
2717 defparam un1_line_counter_sig_8_.sum_lutc_input="cin";
2718 // @13:141
2719   stratix_lcell un1_line_counter_sig_7_ (
2720         .combout(un1_line_counter_sig_combout[7]),
2721         .cout(un1_line_counter_sig_cout[7]),
2722         .clk(GND),
2723         .dataa(line_counter_sig_5),
2724         .datab(line_counter_sig_6),
2725         .datac(VCC),
2726         .datad(VCC),
2727         .aclr(GND),
2728         .sclr(GND),
2729         .sload(GND),
2730         .ena(VCC),
2731         .cin(un1_line_counter_sig_cout[5]),
2732         .inverta(GND),
2733         .aload(GND),
2734         .regcascin(GND)
2735 );
2736 defparam un1_line_counter_sig_7_.cin_used="true";
2737 defparam un1_line_counter_sig_7_.operation_mode="arithmetic";
2738 defparam un1_line_counter_sig_7_.output_mode="comb_only";
2739 defparam un1_line_counter_sig_7_.lut_mask="6c80";
2740 defparam un1_line_counter_sig_7_.synch_mode="off";
2741 defparam un1_line_counter_sig_7_.sum_lutc_input="cin";
2742 // @13:141
2743   stratix_lcell un1_line_counter_sig_6_ (
2744         .combout(un1_line_counter_sig_combout[6]),
2745         .cout(un1_line_counter_sig_cout[6]),
2746         .clk(GND),
2747         .dataa(line_counter_sig_5),
2748         .datab(line_counter_sig_6),
2749         .datac(VCC),
2750         .datad(VCC),
2751         .aclr(GND),
2752         .sclr(GND),
2753         .sload(GND),
2754         .ena(VCC),
2755         .cin(un1_line_counter_sig_cout[4]),
2756         .inverta(GND),
2757         .aload(GND),
2758         .regcascin(GND)
2759 );
2760 defparam un1_line_counter_sig_6_.cin_used="true";
2761 defparam un1_line_counter_sig_6_.operation_mode="arithmetic";
2762 defparam un1_line_counter_sig_6_.output_mode="comb_only";
2763 defparam un1_line_counter_sig_6_.lut_mask="5a80";
2764 defparam un1_line_counter_sig_6_.synch_mode="off";
2765 defparam un1_line_counter_sig_6_.sum_lutc_input="cin";
2766 // @13:141
2767   stratix_lcell un1_line_counter_sig_5_ (
2768         .combout(un1_line_counter_sig_combout[5]),
2769         .cout(un1_line_counter_sig_cout[5]),
2770         .clk(GND),
2771         .dataa(line_counter_sig_3),
2772         .datab(line_counter_sig_4),
2773         .datac(VCC),
2774         .datad(VCC),
2775         .aclr(GND),
2776         .sclr(GND),
2777         .sload(GND),
2778         .ena(VCC),
2779         .cin(un1_line_counter_sig_cout[3]),
2780         .inverta(GND),
2781         .aload(GND),
2782         .regcascin(GND)
2783 );
2784 defparam un1_line_counter_sig_5_.cin_used="true";
2785 defparam un1_line_counter_sig_5_.operation_mode="arithmetic";
2786 defparam un1_line_counter_sig_5_.output_mode="comb_only";
2787 defparam un1_line_counter_sig_5_.lut_mask="6c80";
2788 defparam un1_line_counter_sig_5_.synch_mode="off";
2789 defparam un1_line_counter_sig_5_.sum_lutc_input="cin";
2790 // @13:141
2791   stratix_lcell un1_line_counter_sig_4_ (
2792         .combout(un1_line_counter_sig_combout[4]),
2793         .cout(un1_line_counter_sig_cout[4]),
2794         .clk(GND),
2795         .dataa(line_counter_sig_3),
2796         .datab(line_counter_sig_4),
2797         .datac(VCC),
2798         .datad(VCC),
2799         .aclr(GND),
2800         .sclr(GND),
2801         .sload(GND),
2802         .ena(VCC),
2803         .cin(un1_line_counter_sig_cout[2]),
2804         .inverta(GND),
2805         .aload(GND),
2806         .regcascin(GND)
2807 );
2808 defparam un1_line_counter_sig_4_.cin_used="true";
2809 defparam un1_line_counter_sig_4_.operation_mode="arithmetic";
2810 defparam un1_line_counter_sig_4_.output_mode="comb_only";
2811 defparam un1_line_counter_sig_4_.lut_mask="5a80";
2812 defparam un1_line_counter_sig_4_.synch_mode="off";
2813 defparam un1_line_counter_sig_4_.sum_lutc_input="cin";
2814 // @13:141
2815   stratix_lcell un1_line_counter_sig_3_ (
2816         .combout(un1_line_counter_sig_combout[3]),
2817         .cout(un1_line_counter_sig_cout[3]),
2818         .clk(GND),
2819         .dataa(line_counter_sig_1),
2820         .datab(line_counter_sig_2),
2821         .datac(VCC),
2822         .datad(VCC),
2823         .aclr(GND),
2824         .sclr(GND),
2825         .sload(GND),
2826         .ena(VCC),
2827         .cin(un1_line_counter_sig_cout[1]),
2828         .inverta(GND),
2829         .aload(GND),
2830         .regcascin(GND)
2831 );
2832 defparam un1_line_counter_sig_3_.cin_used="true";
2833 defparam un1_line_counter_sig_3_.operation_mode="arithmetic";
2834 defparam un1_line_counter_sig_3_.output_mode="comb_only";
2835 defparam un1_line_counter_sig_3_.lut_mask="6c80";
2836 defparam un1_line_counter_sig_3_.synch_mode="off";
2837 defparam un1_line_counter_sig_3_.sum_lutc_input="cin";
2838 // @13:141
2839   stratix_lcell un1_line_counter_sig_2_ (
2840         .combout(un1_line_counter_sig_combout[2]),
2841         .cout(un1_line_counter_sig_cout[2]),
2842         .clk(GND),
2843         .dataa(line_counter_sig_1),
2844         .datab(line_counter_sig_2),
2845         .datac(VCC),
2846         .datad(VCC),
2847         .aclr(GND),
2848         .sclr(GND),
2849         .sload(GND),
2850         .ena(VCC),
2851         .cin(un1_line_counter_sig_a_cout[1]),
2852         .inverta(GND),
2853         .aload(GND),
2854         .regcascin(GND)
2855 );
2856 defparam un1_line_counter_sig_2_.cin_used="true";
2857 defparam un1_line_counter_sig_2_.operation_mode="arithmetic";
2858 defparam un1_line_counter_sig_2_.output_mode="comb_only";
2859 defparam un1_line_counter_sig_2_.lut_mask="5a80";
2860 defparam un1_line_counter_sig_2_.synch_mode="off";
2861 defparam un1_line_counter_sig_2_.sum_lutc_input="cin";
2862 // @13:141
2863   stratix_lcell un1_line_counter_sig_a_1_ (
2864         .cout(un1_line_counter_sig_a_cout[1]),
2865         .clk(GND),
2866         .dataa(d_set_hsync_counter),
2867         .datab(line_counter_sig_0),
2868         .datac(VCC),
2869         .datad(VCC),
2870         .aclr(GND),
2871         .sclr(GND),
2872         .sload(GND),
2873         .ena(VCC),
2874         .inverta(GND),
2875         .aload(GND),
2876         .regcascin(GND)
2877 );
2878 defparam un1_line_counter_sig_a_1_.operation_mode="arithmetic";
2879 defparam un1_line_counter_sig_a_1_.output_mode="comb_only";
2880 defparam un1_line_counter_sig_a_1_.lut_mask="0088";
2881 defparam un1_line_counter_sig_a_1_.synch_mode="off";
2882 defparam un1_line_counter_sig_a_1_.sum_lutc_input="datac";
2883 // @13:141
2884   stratix_lcell un1_line_counter_sig_1_ (
2885         .combout(un1_line_counter_sig_combout[1]),
2886         .cout(un1_line_counter_sig_cout[1]),
2887         .clk(GND),
2888         .dataa(d_set_hsync_counter),
2889         .datab(line_counter_sig_0),
2890         .datac(VCC),
2891         .datad(VCC),
2892         .aclr(GND),
2893         .sclr(GND),
2894         .sload(GND),
2895         .ena(VCC),
2896         .inverta(GND),
2897         .aload(GND),
2898         .regcascin(GND)
2899 );
2900 defparam un1_line_counter_sig_1_.operation_mode="arithmetic";
2901 defparam un1_line_counter_sig_1_.output_mode="comb_only";
2902 defparam un1_line_counter_sig_1_.lut_mask="6688";
2903 defparam un1_line_counter_sig_1_.synch_mode="off";
2904 defparam un1_line_counter_sig_1_.sum_lutc_input="datac";
2905 // @13:112
2906   stratix_lcell un2_column_counter_next_9_ (
2907         .combout(un2_column_counter_next_combout[9]),
2908         .clk(GND),
2909         .dataa(column_counter_sig_8),
2910         .datab(column_counter_sig_9),
2911         .datac(VCC),
2912         .datad(VCC),
2913         .aclr(GND),
2914         .sclr(GND),
2915         .sload(GND),
2916         .ena(VCC),
2917         .cin(un2_column_counter_next_cout[7]),
2918         .inverta(GND),
2919         .aload(GND),
2920         .regcascin(GND)
2921 );
2922 defparam un2_column_counter_next_9_.cin_used="true";
2923 defparam un2_column_counter_next_9_.operation_mode="normal";
2924 defparam un2_column_counter_next_9_.output_mode="comb_only";
2925 defparam un2_column_counter_next_9_.lut_mask="6c6c";
2926 defparam un2_column_counter_next_9_.synch_mode="off";
2927 defparam un2_column_counter_next_9_.sum_lutc_input="cin";
2928 // @13:112
2929   stratix_lcell un2_column_counter_next_8_ (
2930         .combout(un2_column_counter_next_combout[8]),
2931         .clk(GND),
2932         .dataa(column_counter_sig_8),
2933         .datab(VCC),
2934         .datac(VCC),
2935         .datad(VCC),
2936         .aclr(GND),
2937         .sclr(GND),
2938         .sload(GND),
2939         .ena(VCC),
2940         .cin(un2_column_counter_next_cout[6]),
2941         .inverta(GND),
2942         .aload(GND),
2943         .regcascin(GND)
2944 );
2945 defparam un2_column_counter_next_8_.cin_used="true";
2946 defparam un2_column_counter_next_8_.operation_mode="normal";
2947 defparam un2_column_counter_next_8_.output_mode="comb_only";
2948 defparam un2_column_counter_next_8_.lut_mask="5a5a";
2949 defparam un2_column_counter_next_8_.synch_mode="off";
2950 defparam un2_column_counter_next_8_.sum_lutc_input="cin";
2951 // @13:112
2952   stratix_lcell un2_column_counter_next_7_ (
2953         .combout(un2_column_counter_next_combout[7]),
2954         .cout(un2_column_counter_next_cout[7]),
2955         .clk(GND),
2956         .dataa(column_counter_sig_6),
2957         .datab(column_counter_sig_7),
2958         .datac(VCC),
2959         .datad(VCC),
2960         .aclr(GND),
2961         .sclr(GND),
2962         .sload(GND),
2963         .ena(VCC),
2964         .cin(un2_column_counter_next_cout[5]),
2965         .inverta(GND),
2966         .aload(GND),
2967         .regcascin(GND)
2968 );
2969 defparam un2_column_counter_next_7_.cin_used="true";
2970 defparam un2_column_counter_next_7_.operation_mode="arithmetic";
2971 defparam un2_column_counter_next_7_.output_mode="comb_only";
2972 defparam un2_column_counter_next_7_.lut_mask="6c80";
2973 defparam un2_column_counter_next_7_.synch_mode="off";
2974 defparam un2_column_counter_next_7_.sum_lutc_input="cin";
2975 // @13:112
2976   stratix_lcell un2_column_counter_next_6_ (
2977         .combout(un2_column_counter_next_combout[6]),
2978         .cout(un2_column_counter_next_cout[6]),
2979         .clk(GND),
2980         .dataa(column_counter_sig_6),
2981         .datab(column_counter_sig_7),
2982         .datac(VCC),
2983         .datad(VCC),
2984         .aclr(GND),
2985         .sclr(GND),
2986         .sload(GND),
2987         .ena(VCC),
2988         .cin(un2_column_counter_next_cout[4]),
2989         .inverta(GND),
2990         .aload(GND),
2991         .regcascin(GND)
2992 );
2993 defparam un2_column_counter_next_6_.cin_used="true";
2994 defparam un2_column_counter_next_6_.operation_mode="arithmetic";
2995 defparam un2_column_counter_next_6_.output_mode="comb_only";
2996 defparam un2_column_counter_next_6_.lut_mask="5a80";
2997 defparam un2_column_counter_next_6_.synch_mode="off";
2998 defparam un2_column_counter_next_6_.sum_lutc_input="cin";
2999 // @13:112
3000   stratix_lcell un2_column_counter_next_5_ (
3001         .combout(un2_column_counter_next_combout[5]),
3002         .cout(un2_column_counter_next_cout[5]),
3003         .clk(GND),
3004         .dataa(column_counter_sig_4),
3005         .datab(column_counter_sig_5),
3006         .datac(VCC),
3007         .datad(VCC),
3008         .aclr(GND),
3009         .sclr(GND),
3010         .sload(GND),
3011         .ena(VCC),
3012         .cin(un2_column_counter_next_cout[3]),
3013         .inverta(GND),
3014         .aload(GND),
3015         .regcascin(GND)
3016 );
3017 defparam un2_column_counter_next_5_.cin_used="true";
3018 defparam un2_column_counter_next_5_.operation_mode="arithmetic";
3019 defparam un2_column_counter_next_5_.output_mode="comb_only";
3020 defparam un2_column_counter_next_5_.lut_mask="6c80";
3021 defparam un2_column_counter_next_5_.synch_mode="off";
3022 defparam un2_column_counter_next_5_.sum_lutc_input="cin";
3023 // @13:112
3024   stratix_lcell un2_column_counter_next_4_ (
3025         .combout(un2_column_counter_next_combout[4]),
3026         .cout(un2_column_counter_next_cout[4]),
3027         .clk(GND),
3028         .dataa(column_counter_sig_4),
3029         .datab(column_counter_sig_5),
3030         .datac(VCC),
3031         .datad(VCC),
3032         .aclr(GND),
3033         .sclr(GND),
3034         .sload(GND),
3035         .ena(VCC),
3036         .cin(un2_column_counter_next_cout[2]),
3037         .inverta(GND),
3038         .aload(GND),
3039         .regcascin(GND)
3040 );
3041 defparam un2_column_counter_next_4_.cin_used="true";
3042 defparam un2_column_counter_next_4_.operation_mode="arithmetic";
3043 defparam un2_column_counter_next_4_.output_mode="comb_only";
3044 defparam un2_column_counter_next_4_.lut_mask="5a80";
3045 defparam un2_column_counter_next_4_.synch_mode="off";
3046 defparam un2_column_counter_next_4_.sum_lutc_input="cin";
3047 // @13:112
3048   stratix_lcell un2_column_counter_next_3_ (
3049         .combout(un2_column_counter_next_combout[3]),
3050         .cout(un2_column_counter_next_cout[3]),
3051         .clk(GND),
3052         .dataa(column_counter_sig_2),
3053         .datab(column_counter_sig_3),
3054         .datac(VCC),
3055         .datad(VCC),
3056         .aclr(GND),
3057         .sclr(GND),
3058         .sload(GND),
3059         .ena(VCC),
3060         .cin(un2_column_counter_next_cout[1]),
3061         .inverta(GND),
3062         .aload(GND),
3063         .regcascin(GND)
3064 );
3065 defparam un2_column_counter_next_3_.cin_used="true";
3066 defparam un2_column_counter_next_3_.operation_mode="arithmetic";
3067 defparam un2_column_counter_next_3_.output_mode="comb_only";
3068 defparam un2_column_counter_next_3_.lut_mask="6c80";
3069 defparam un2_column_counter_next_3_.synch_mode="off";
3070 defparam un2_column_counter_next_3_.sum_lutc_input="cin";
3071 // @13:112
3072   stratix_lcell un2_column_counter_next_2_ (
3073         .combout(un2_column_counter_next_combout[2]),
3074         .cout(un2_column_counter_next_cout[2]),
3075         .clk(GND),
3076         .dataa(column_counter_sig_2),
3077         .datab(column_counter_sig_3),
3078         .datac(VCC),
3079         .datad(VCC),
3080         .aclr(GND),
3081         .sclr(GND),
3082         .sload(GND),
3083         .ena(VCC),
3084         .cin(un2_column_counter_next_cout[0]),
3085         .inverta(GND),
3086         .aload(GND),
3087         .regcascin(GND)
3088 );
3089 defparam un2_column_counter_next_2_.cin_used="true";
3090 defparam un2_column_counter_next_2_.operation_mode="arithmetic";
3091 defparam un2_column_counter_next_2_.output_mode="comb_only";
3092 defparam un2_column_counter_next_2_.lut_mask="5a80";
3093 defparam un2_column_counter_next_2_.synch_mode="off";
3094 defparam un2_column_counter_next_2_.sum_lutc_input="cin";
3095 // @13:112
3096   stratix_lcell un2_column_counter_next_1_ (
3097         .combout(un2_column_counter_next_combout[1]),
3098         .cout(un2_column_counter_next_cout[1]),
3099         .clk(GND),
3100         .dataa(column_counter_sig_0),
3101         .datab(column_counter_sig_1),
3102         .datac(VCC),
3103         .datad(VCC),
3104         .aclr(GND),
3105         .sclr(GND),
3106         .sload(GND),
3107         .ena(VCC),
3108         .inverta(GND),
3109         .aload(GND),
3110         .regcascin(GND)
3111 );
3112 defparam un2_column_counter_next_1_.operation_mode="arithmetic";
3113 defparam un2_column_counter_next_1_.output_mode="comb_only";
3114 defparam un2_column_counter_next_1_.lut_mask="6688";
3115 defparam un2_column_counter_next_1_.synch_mode="off";
3116 defparam un2_column_counter_next_1_.sum_lutc_input="datac";
3117 // @13:112
3118   stratix_lcell un2_column_counter_next_0_ (
3119         .cout(un2_column_counter_next_cout[0]),
3120         .clk(GND),
3121         .dataa(column_counter_sig_0),
3122         .datab(column_counter_sig_1),
3123         .datac(VCC),
3124         .datad(VCC),
3125         .aclr(GND),
3126         .sclr(GND),
3127         .sload(GND),
3128         .ena(VCC),
3129         .inverta(GND),
3130         .aload(GND),
3131         .regcascin(GND)
3132 );
3133 defparam un2_column_counter_next_0_.operation_mode="arithmetic";
3134 defparam un2_column_counter_next_0_.output_mode="comb_only";
3135 defparam un2_column_counter_next_0_.lut_mask="5588";
3136 defparam un2_column_counter_next_0_.synch_mode="off";
3137 defparam un2_column_counter_next_0_.sum_lutc_input="datac";
3138   assign  line_counter_next_0_sqmuxa_1_1_i = ~ line_counter_next_0_sqmuxa_1_1;
3139   assign  column_counter_next_0_sqmuxa_1_1_i = ~ column_counter_next_0_sqmuxa_1_1;
3140   assign  un9_vsync_counterlt9_i = ~ un9_vsync_counterlt9;
3141   assign  G_16_i_i = ~ G_16_i;
3142   assign  un9_hsync_counterlt9_i = ~ un9_hsync_counterlt9;
3143   assign  G_2_i_i = ~ G_2_i;
3144 endmodule /* vga_driver */
3145
3146 // VQM4.1+
3147 module vga_control (
3148   column_counter_sig_5,
3149   column_counter_sig_0,
3150   column_counter_sig_1,
3151   column_counter_sig_3,
3152   column_counter_sig_4,
3153   column_counter_sig_2,
3154   column_counter_sig_9,
3155   column_counter_sig_8,
3156   column_counter_sig_7,
3157   column_counter_sig_6,
3158   line_counter_sig_0,
3159   line_counter_sig_1,
3160   line_counter_sig_2,
3161   line_counter_sig_8,
3162   line_counter_sig_3,
3163   line_counter_sig_5,
3164   line_counter_sig_4,
3165   line_counter_sig_7,
3166   line_counter_sig_6,
3167   toggle_counter_sig_0,
3168   toggle_counter_sig_1,
3169   toggle_counter_sig_2,
3170   toggle_counter_sig_3,
3171   toggle_counter_sig_4,
3172   toggle_counter_sig_5,
3173   toggle_counter_sig_6,
3174   toggle_counter_sig_7,
3175   toggle_counter_sig_8,
3176   toggle_counter_sig_9,
3177   toggle_counter_sig_10,
3178   toggle_counter_sig_11,
3179   toggle_counter_sig_12,
3180   toggle_counter_sig_13,
3181   toggle_counter_sig_14,
3182   toggle_counter_sig_15,
3183   toggle_counter_sig_16,
3184   toggle_counter_sig_17,
3185   toggle_counter_sig_18,
3186   toggle_counter_sig_19,
3187   toggle_counter_sig_20,
3188   toggle_counter_sig_21,
3189   toggle_counter_sig_22,
3190   toggle_counter_sig_23,
3191   toggle_counter_sig_24,
3192   v_enable_sig,
3193   un10_column_counter_siglt6_1,
3194   h_enable_sig,
3195   g,
3196   r,
3197   b,
3198   toggle_sig,
3199   un6_dly_counter_0_x,
3200   clk_pin_c
3201 )
3202 ;
3203 input column_counter_sig_5 ;
3204 input column_counter_sig_0 ;
3205 input column_counter_sig_1 ;
3206 input column_counter_sig_3 ;
3207 input column_counter_sig_4 ;
3208 input column_counter_sig_2 ;
3209 input column_counter_sig_9 ;
3210 input column_counter_sig_8 ;
3211 input column_counter_sig_7 ;
3212 input column_counter_sig_6 ;
3213 input line_counter_sig_0 ;
3214 input line_counter_sig_1 ;
3215 input line_counter_sig_2 ;
3216 input line_counter_sig_8 ;
3217 input line_counter_sig_3 ;
3218 input line_counter_sig_5 ;
3219 input line_counter_sig_4 ;
3220 input line_counter_sig_7 ;
3221 input line_counter_sig_6 ;
3222 output toggle_counter_sig_0 ;
3223 output toggle_counter_sig_1 ;
3224 output toggle_counter_sig_2 ;
3225 output toggle_counter_sig_3 ;
3226 output toggle_counter_sig_4 ;
3227 output toggle_counter_sig_5 ;
3228 output toggle_counter_sig_6 ;
3229 output toggle_counter_sig_7 ;
3230 output toggle_counter_sig_8 ;
3231 output toggle_counter_sig_9 ;
3232 output toggle_counter_sig_10 ;
3233 output toggle_counter_sig_11 ;
3234 output toggle_counter_sig_12 ;
3235 output toggle_counter_sig_13 ;
3236 output toggle_counter_sig_14 ;
3237 output toggle_counter_sig_15 ;
3238 output toggle_counter_sig_16 ;
3239 output toggle_counter_sig_17 ;
3240 output toggle_counter_sig_18 ;
3241 output toggle_counter_sig_19 ;
3242 output toggle_counter_sig_20 ;
3243 output toggle_counter_sig_21 ;
3244 output toggle_counter_sig_22 ;
3245 output toggle_counter_sig_23 ;
3246 output toggle_counter_sig_24 ;
3247 input v_enable_sig ;
3248 input un10_column_counter_siglt6_1 ;
3249 input h_enable_sig ;
3250 output g ;
3251 output r ;
3252 output b ;
3253 output toggle_sig ;
3254 input un6_dly_counter_0_x ;
3255 input clk_pin_c ;
3256 wire column_counter_sig_5 ;
3257 wire column_counter_sig_0 ;
3258 wire column_counter_sig_1 ;
3259 wire column_counter_sig_3 ;
3260 wire column_counter_sig_4 ;
3261 wire column_counter_sig_2 ;
3262 wire column_counter_sig_9 ;
3263 wire column_counter_sig_8 ;
3264 wire column_counter_sig_7 ;
3265 wire column_counter_sig_6 ;
3266 wire line_counter_sig_0 ;
3267 wire line_counter_sig_1 ;
3268 wire line_counter_sig_2 ;
3269 wire line_counter_sig_8 ;
3270 wire line_counter_sig_3 ;
3271 wire line_counter_sig_5 ;
3272 wire line_counter_sig_4 ;
3273 wire line_counter_sig_7 ;
3274 wire line_counter_sig_6 ;
3275 wire toggle_counter_sig_0 ;
3276 wire toggle_counter_sig_1 ;
3277 wire toggle_counter_sig_2 ;
3278 wire toggle_counter_sig_3 ;
3279 wire toggle_counter_sig_4 ;
3280 wire toggle_counter_sig_5 ;
3281 wire toggle_counter_sig_6 ;
3282 wire toggle_counter_sig_7 ;
3283 wire toggle_counter_sig_8 ;
3284 wire toggle_counter_sig_9 ;
3285 wire toggle_counter_sig_10 ;
3286 wire toggle_counter_sig_11 ;
3287 wire toggle_counter_sig_12 ;
3288 wire toggle_counter_sig_13 ;
3289 wire toggle_counter_sig_14 ;
3290 wire toggle_counter_sig_15 ;
3291 wire toggle_counter_sig_16 ;
3292 wire toggle_counter_sig_17 ;
3293 wire toggle_counter_sig_18 ;
3294 wire toggle_counter_sig_19 ;
3295 wire toggle_counter_sig_20 ;
3296 wire toggle_counter_sig_21 ;
3297 wire toggle_counter_sig_22 ;
3298 wire toggle_counter_sig_23 ;
3299 wire toggle_counter_sig_24 ;
3300 wire v_enable_sig ;
3301 wire un10_column_counter_siglt6_1 ;
3302 wire h_enable_sig ;
3303 wire g ;
3304 wire r ;
3305 wire b ;
3306 wire toggle_sig ;
3307 wire un6_dly_counter_0_x ;
3308 wire clk_pin_c ;
3309 wire [17:1] toggle_counter_sig_cout;
3310 wire [0:0] un2_toggle_counter_next_cout;
3311 wire GND ;
3312 wire toggle_sig_0_0_0_g1 ;
3313 wire un13_v_enablelto8 ;
3314 wire un5_v_enablelto7 ;
3315 wire un17_v_enablelto7 ;
3316 wire b_next_0_g0_5 ;
3317 wire toggle_sig_0_0_0_g1_2 ;
3318 wire un1_toggle_counter_siglto19 ;
3319 wire un1_toggle_counter_siglto19_5 ;
3320 wire un1_toggle_counter_siglto10 ;
3321 wire un1_toggle_counter_siglto7 ;
3322 wire b_next_0_g0_3 ;
3323 wire un9_v_enablelto9 ;
3324 wire un17_v_enablelto5 ;
3325 wire un5_v_enablelto5_0 ;
3326 wire un5_v_enablelto3 ;
3327 wire un17_v_enablelt2 ;
3328 wire un13_v_enablelto8_a ;
3329 wire un9_v_enablelto6 ;
3330 wire un1_toggle_counter_siglto19_4 ;
3331 wire un1_toggle_counter_siglto7_4 ;
3332 wire VCC ;
3333 wire toggle_sig_0_0_0_g1_i ;
3334   assign VCC = 1'b1;
3335 //@1:1
3336   assign GND = 1'b0;
3337 // @12:100
3338   stratix_lcell toggle_counter_sig_24_ (
3339         .regout(toggle_counter_sig_24),
3340         .clk(clk_pin_c),
3341         .dataa(VCC),
3342         .datab(VCC),
3343         .datac(VCC),
3344         .datad(GND),
3345         .aclr(un6_dly_counter_0_x),
3346         .sclr(GND),
3347         .sload(GND),
3348         .ena(VCC),
3349         .inverta(GND),
3350         .aload(GND),
3351         .regcascin(GND)
3352 );
3353 defparam toggle_counter_sig_24_.operation_mode="normal";
3354 defparam toggle_counter_sig_24_.output_mode="reg_only";
3355 defparam toggle_counter_sig_24_.lut_mask="ff00";
3356 defparam toggle_counter_sig_24_.synch_mode="off";
3357 defparam toggle_counter_sig_24_.sum_lutc_input="datac";
3358 // @12:100
3359   stratix_lcell toggle_counter_sig_23_ (
3360         .regout(toggle_counter_sig_23),
3361         .clk(clk_pin_c),
3362         .dataa(VCC),
3363         .datab(VCC),
3364         .datac(VCC),
3365         .datad(GND),
3366         .aclr(un6_dly_counter_0_x),
3367         .sclr(GND),
3368         .sload(GND),
3369         .ena(VCC),
3370         .inverta(GND),
3371         .aload(GND),
3372         .regcascin(GND)
3373 );
3374 defparam toggle_counter_sig_23_.operation_mode="normal";
3375 defparam toggle_counter_sig_23_.output_mode="reg_only";
3376 defparam toggle_counter_sig_23_.lut_mask="ff00";
3377 defparam toggle_counter_sig_23_.synch_mode="off";
3378 defparam toggle_counter_sig_23_.sum_lutc_input="datac";
3379 // @12:100
3380   stratix_lcell toggle_counter_sig_22_ (
3381         .regout(toggle_counter_sig_22),
3382         .clk(clk_pin_c),
3383         .dataa(VCC),
3384         .datab(VCC),
3385         .datac(VCC),
3386         .datad(GND),
3387         .aclr(un6_dly_counter_0_x),
3388         .sclr(GND),
3389         .sload(GND),
3390         .ena(VCC),
3391         .inverta(GND),
3392         .aload(GND),
3393         .regcascin(GND)
3394 );
3395 defparam toggle_counter_sig_22_.operation_mode="normal";
3396 defparam toggle_counter_sig_22_.output_mode="reg_only";
3397 defparam toggle_counter_sig_22_.lut_mask="ff00";
3398 defparam toggle_counter_sig_22_.synch_mode="off";
3399 defparam toggle_counter_sig_22_.sum_lutc_input="datac";
3400 // @12:100
3401   stratix_lcell toggle_counter_sig_21_ (
3402         .regout(toggle_counter_sig_21),
3403         .clk(clk_pin_c),
3404         .dataa(VCC),
3405         .datab(VCC),
3406         .datac(VCC),
3407         .datad(GND),
3408         .aclr(un6_dly_counter_0_x),
3409         .sclr(GND),
3410         .sload(GND),
3411         .ena(VCC),
3412         .inverta(GND),
3413         .aload(GND),
3414         .regcascin(GND)
3415 );
3416 defparam toggle_counter_sig_21_.operation_mode="normal";
3417 defparam toggle_counter_sig_21_.output_mode="reg_only";
3418 defparam toggle_counter_sig_21_.lut_mask="ff00";
3419 defparam toggle_counter_sig_21_.synch_mode="off";
3420 defparam toggle_counter_sig_21_.sum_lutc_input="datac";
3421 // @12:100
3422   stratix_lcell toggle_counter_sig_20_ (
3423         .regout(toggle_counter_sig_20),
3424         .clk(clk_pin_c),
3425         .dataa(VCC),
3426         .datab(VCC),
3427         .datac(VCC),
3428         .datad(GND),
3429         .aclr(un6_dly_counter_0_x),
3430         .sclr(GND),
3431         .sload(GND),
3432         .ena(VCC),
3433         .inverta(GND),
3434         .aload(GND),
3435         .regcascin(GND)
3436 );
3437 defparam toggle_counter_sig_20_.operation_mode="normal";
3438 defparam toggle_counter_sig_20_.output_mode="reg_only";
3439 defparam toggle_counter_sig_20_.lut_mask="ff00";
3440 defparam toggle_counter_sig_20_.synch_mode="off";
3441 defparam toggle_counter_sig_20_.sum_lutc_input="datac";
3442 // @12:100
3443   stratix_lcell toggle_counter_sig_19_ (
3444         .regout(toggle_counter_sig_19),
3445         .clk(clk_pin_c),
3446         .dataa(toggle_counter_sig_18),
3447         .datab(toggle_counter_sig_19),
3448         .datac(VCC),
3449         .datad(VCC),
3450         .aclr(un6_dly_counter_0_x),
3451         .sclr(toggle_sig_0_0_0_g1_i),
3452         .sload(GND),
3453         .ena(VCC),
3454         .cin(toggle_counter_sig_cout[17]),
3455         .inverta(GND),
3456         .aload(GND),
3457         .regcascin(GND)
3458 );
3459 defparam toggle_counter_sig_19_.cin_used="true";
3460 defparam toggle_counter_sig_19_.operation_mode="normal";
3461 defparam toggle_counter_sig_19_.output_mode="reg_only";
3462 defparam toggle_counter_sig_19_.lut_mask="6c6c";
3463 defparam toggle_counter_sig_19_.synch_mode="on";
3464 defparam toggle_counter_sig_19_.sum_lutc_input="cin";
3465 // @12:100
3466   stratix_lcell toggle_counter_sig_18_ (
3467         .regout(toggle_counter_sig_18),
3468         .clk(clk_pin_c),
3469         .dataa(toggle_counter_sig_18),
3470         .datab(VCC),
3471         .datac(VCC),
3472         .datad(VCC),
3473         .aclr(un6_dly_counter_0_x),
3474         .sclr(toggle_sig_0_0_0_g1_i),
3475         .sload(GND),
3476         .ena(VCC),
3477         .cin(toggle_counter_sig_cout[16]),
3478         .inverta(GND),
3479         .aload(GND),
3480         .regcascin(GND)
3481 );
3482 defparam toggle_counter_sig_18_.cin_used="true";
3483 defparam toggle_counter_sig_18_.operation_mode="normal";
3484 defparam toggle_counter_sig_18_.output_mode="reg_only";
3485 defparam toggle_counter_sig_18_.lut_mask="5a5a";
3486 defparam toggle_counter_sig_18_.synch_mode="on";
3487 defparam toggle_counter_sig_18_.sum_lutc_input="cin";
3488 // @12:100
3489   stratix_lcell toggle_counter_sig_17_ (
3490         .regout(toggle_counter_sig_17),
3491         .cout(toggle_counter_sig_cout[17]),
3492         .clk(clk_pin_c),
3493         .dataa(toggle_counter_sig_16),
3494         .datab(toggle_counter_sig_17),
3495         .datac(VCC),
3496         .datad(VCC),
3497         .aclr(un6_dly_counter_0_x),
3498         .sclr(toggle_sig_0_0_0_g1_i),
3499         .sload(GND),
3500         .ena(VCC),
3501         .cin(toggle_counter_sig_cout[15]),
3502         .inverta(GND),
3503         .aload(GND),
3504         .regcascin(GND)
3505 );
3506 defparam toggle_counter_sig_17_.cin_used="true";
3507 defparam toggle_counter_sig_17_.operation_mode="arithmetic";
3508 defparam toggle_counter_sig_17_.output_mode="reg_only";
3509 defparam toggle_counter_sig_17_.lut_mask="6c80";
3510 defparam toggle_counter_sig_17_.synch_mode="on";
3511 defparam toggle_counter_sig_17_.sum_lutc_input="cin";
3512 // @12:100
3513   stratix_lcell toggle_counter_sig_16_ (
3514         .regout(toggle_counter_sig_16),
3515         .cout(toggle_counter_sig_cout[16]),
3516         .clk(clk_pin_c),
3517         .dataa(toggle_counter_sig_16),
3518         .datab(toggle_counter_sig_17),
3519         .datac(VCC),
3520         .datad(VCC),
3521         .aclr(un6_dly_counter_0_x),
3522         .sclr(toggle_sig_0_0_0_g1_i),
3523         .sload(GND),
3524         .ena(VCC),
3525         .cin(toggle_counter_sig_cout[14]),
3526         .inverta(GND),
3527         .aload(GND),
3528         .regcascin(GND)
3529 );
3530 defparam toggle_counter_sig_16_.cin_used="true";
3531 defparam toggle_counter_sig_16_.operation_mode="arithmetic";
3532 defparam toggle_counter_sig_16_.output_mode="reg_only";
3533 defparam toggle_counter_sig_16_.lut_mask="5a80";
3534 defparam toggle_counter_sig_16_.synch_mode="on";
3535 defparam toggle_counter_sig_16_.sum_lutc_input="cin";
3536 // @12:100
3537   stratix_lcell toggle_counter_sig_15_ (
3538         .regout(toggle_counter_sig_15),
3539         .cout(toggle_counter_sig_cout[15]),
3540         .clk(clk_pin_c),
3541         .dataa(toggle_counter_sig_14),
3542         .datab(toggle_counter_sig_15),
3543         .datac(VCC),
3544         .datad(VCC),
3545         .aclr(un6_dly_counter_0_x),
3546         .sclr(toggle_sig_0_0_0_g1_i),
3547         .sload(GND),
3548         .ena(VCC),
3549         .cin(toggle_counter_sig_cout[13]),
3550         .inverta(GND),
3551         .aload(GND),
3552         .regcascin(GND)
3553 );
3554 defparam toggle_counter_sig_15_.cin_used="true";
3555 defparam toggle_counter_sig_15_.operation_mode="arithmetic";
3556 defparam toggle_counter_sig_15_.output_mode="reg_only";
3557 defparam toggle_counter_sig_15_.lut_mask="6c80";
3558 defparam toggle_counter_sig_15_.synch_mode="on";
3559 defparam toggle_counter_sig_15_.sum_lutc_input="cin";
3560 // @12:100
3561   stratix_lcell toggle_counter_sig_14_ (
3562         .regout(toggle_counter_sig_14),
3563         .cout(toggle_counter_sig_cout[14]),
3564         .clk(clk_pin_c),
3565         .dataa(toggle_counter_sig_14),
3566         .datab(toggle_counter_sig_15),
3567         .datac(VCC),
3568         .datad(VCC),
3569         .aclr(un6_dly_counter_0_x),
3570         .sclr(toggle_sig_0_0_0_g1_i),
3571         .sload(GND),
3572         .ena(VCC),
3573         .cin(toggle_counter_sig_cout[12]),
3574         .inverta(GND),
3575         .aload(GND),
3576         .regcascin(GND)
3577 );
3578 defparam toggle_counter_sig_14_.cin_used="true";
3579 defparam toggle_counter_sig_14_.operation_mode="arithmetic";
3580 defparam toggle_counter_sig_14_.output_mode="reg_only";
3581 defparam toggle_counter_sig_14_.lut_mask="5a80";
3582 defparam toggle_counter_sig_14_.synch_mode="on";
3583 defparam toggle_counter_sig_14_.sum_lutc_input="cin";
3584 // @12:100
3585   stratix_lcell toggle_counter_sig_13_ (
3586         .regout(toggle_counter_sig_13),
3587         .cout(toggle_counter_sig_cout[13]),
3588         .clk(clk_pin_c),
3589         .dataa(toggle_counter_sig_12),
3590         .datab(toggle_counter_sig_13),
3591         .datac(VCC),
3592         .datad(VCC),
3593         .aclr(un6_dly_counter_0_x),
3594         .sclr(toggle_sig_0_0_0_g1_i),
3595         .sload(GND),
3596         .ena(VCC),
3597         .cin(toggle_counter_sig_cout[11]),
3598         .inverta(GND),
3599         .aload(GND),
3600         .regcascin(GND)
3601 );
3602 defparam toggle_counter_sig_13_.cin_used="true";
3603 defparam toggle_counter_sig_13_.operation_mode="arithmetic";
3604 defparam toggle_counter_sig_13_.output_mode="reg_only";
3605 defparam toggle_counter_sig_13_.lut_mask="6c80";
3606 defparam toggle_counter_sig_13_.synch_mode="on";
3607 defparam toggle_counter_sig_13_.sum_lutc_input="cin";
3608 // @12:100
3609   stratix_lcell toggle_counter_sig_12_ (
3610         .regout(toggle_counter_sig_12),
3611         .cout(toggle_counter_sig_cout[12]),
3612         .clk(clk_pin_c),
3613         .dataa(toggle_counter_sig_12),
3614         .datab(toggle_counter_sig_13),
3615         .datac(VCC),
3616         .datad(VCC),
3617         .aclr(un6_dly_counter_0_x),
3618         .sclr(toggle_sig_0_0_0_g1_i),
3619         .sload(GND),
3620         .ena(VCC),
3621         .cin(toggle_counter_sig_cout[10]),
3622         .inverta(GND),
3623         .aload(GND),
3624         .regcascin(GND)
3625 );
3626 defparam toggle_counter_sig_12_.cin_used="true";
3627 defparam toggle_counter_sig_12_.operation_mode="arithmetic";
3628 defparam toggle_counter_sig_12_.output_mode="reg_only";
3629 defparam toggle_counter_sig_12_.lut_mask="5a80";
3630 defparam toggle_counter_sig_12_.synch_mode="on";
3631 defparam toggle_counter_sig_12_.sum_lutc_input="cin";
3632 // @12:100
3633   stratix_lcell toggle_counter_sig_11_ (
3634         .regout(toggle_counter_sig_11),
3635         .cout(toggle_counter_sig_cout[11]),
3636         .clk(clk_pin_c),
3637         .dataa(toggle_counter_sig_10),
3638         .datab(toggle_counter_sig_11),
3639         .datac(VCC),
3640         .datad(VCC),
3641         .aclr(un6_dly_counter_0_x),
3642         .sclr(toggle_sig_0_0_0_g1_i),
3643         .sload(GND),
3644         .ena(VCC),
3645         .cin(toggle_counter_sig_cout[9]),
3646         .inverta(GND),
3647         .aload(GND),
3648         .regcascin(GND)
3649 );
3650 defparam toggle_counter_sig_11_.cin_used="true";
3651 defparam toggle_counter_sig_11_.operation_mode="arithmetic";
3652 defparam toggle_counter_sig_11_.output_mode="reg_only";
3653 defparam toggle_counter_sig_11_.lut_mask="6c80";
3654 defparam toggle_counter_sig_11_.synch_mode="on";
3655 defparam toggle_counter_sig_11_.sum_lutc_input="cin";
3656 // @12:100
3657   stratix_lcell toggle_counter_sig_10_ (
3658         .regout(toggle_counter_sig_10),
3659         .cout(toggle_counter_sig_cout[10]),
3660         .clk(clk_pin_c),
3661         .dataa(toggle_counter_sig_10),
3662         .datab(toggle_counter_sig_11),
3663         .datac(VCC),
3664         .datad(VCC),
3665         .aclr(un6_dly_counter_0_x),
3666         .sclr(toggle_sig_0_0_0_g1_i),
3667         .sload(GND),
3668         .ena(VCC),
3669         .cin(toggle_counter_sig_cout[8]),
3670         .inverta(GND),
3671         .aload(GND),
3672         .regcascin(GND)
3673 );
3674 defparam toggle_counter_sig_10_.cin_used="true";
3675 defparam toggle_counter_sig_10_.operation_mode="arithmetic";
3676 defparam toggle_counter_sig_10_.output_mode="reg_only";
3677 defparam toggle_counter_sig_10_.lut_mask="5a80";
3678 defparam toggle_counter_sig_10_.synch_mode="on";
3679 defparam toggle_counter_sig_10_.sum_lutc_input="cin";
3680 // @12:100
3681   stratix_lcell toggle_counter_sig_9_ (
3682         .regout(toggle_counter_sig_9),
3683         .cout(toggle_counter_sig_cout[9]),
3684         .clk(clk_pin_c),
3685         .dataa(toggle_counter_sig_8),
3686         .datab(toggle_counter_sig_9),
3687         .datac(VCC),
3688         .datad(VCC),
3689         .aclr(un6_dly_counter_0_x),
3690         .sclr(toggle_sig_0_0_0_g1_i),
3691         .sload(GND),
3692         .ena(VCC),
3693         .cin(toggle_counter_sig_cout[7]),
3694         .inverta(GND),
3695         .aload(GND),
3696         .regcascin(GND)
3697 );
3698 defparam toggle_counter_sig_9_.cin_used="true";
3699 defparam toggle_counter_sig_9_.operation_mode="arithmetic";
3700 defparam toggle_counter_sig_9_.output_mode="reg_only";
3701 defparam toggle_counter_sig_9_.lut_mask="6c80";
3702 defparam toggle_counter_sig_9_.synch_mode="on";
3703 defparam toggle_counter_sig_9_.sum_lutc_input="cin";
3704 // @12:100
3705   stratix_lcell toggle_counter_sig_8_ (
3706         .regout(toggle_counter_sig_8),
3707         .cout(toggle_counter_sig_cout[8]),
3708         .clk(clk_pin_c),
3709         .dataa(toggle_counter_sig_8),
3710         .datab(toggle_counter_sig_9),
3711         .datac(VCC),
3712         .datad(VCC),
3713         .aclr(un6_dly_counter_0_x),
3714         .sclr(toggle_sig_0_0_0_g1_i),
3715         .sload(GND),
3716         .ena(VCC),
3717         .cin(toggle_counter_sig_cout[6]),
3718         .inverta(GND),
3719         .aload(GND),
3720         .regcascin(GND)
3721 );
3722 defparam toggle_counter_sig_8_.cin_used="true";
3723 defparam toggle_counter_sig_8_.operation_mode="arithmetic";
3724 defparam toggle_counter_sig_8_.output_mode="reg_only";
3725 defparam toggle_counter_sig_8_.lut_mask="5a80";
3726 defparam toggle_counter_sig_8_.synch_mode="on";
3727 defparam toggle_counter_sig_8_.sum_lutc_input="cin";
3728 // @12:100
3729   stratix_lcell toggle_counter_sig_7_ (
3730         .regout(toggle_counter_sig_7),
3731         .cout(toggle_counter_sig_cout[7]),
3732         .clk(clk_pin_c),
3733         .dataa(toggle_counter_sig_6),
3734         .datab(toggle_counter_sig_7),
3735         .datac(VCC),
3736         .datad(VCC),
3737         .aclr(un6_dly_counter_0_x),
3738         .sclr(toggle_sig_0_0_0_g1_i),
3739         .sload(GND),
3740         .ena(VCC),
3741         .cin(toggle_counter_sig_cout[5]),
3742         .inverta(GND),
3743         .aload(GND),
3744         .regcascin(GND)
3745 );
3746 defparam toggle_counter_sig_7_.cin_used="true";
3747 defparam toggle_counter_sig_7_.operation_mode="arithmetic";
3748 defparam toggle_counter_sig_7_.output_mode="reg_only";
3749 defparam toggle_counter_sig_7_.lut_mask="6c80";
3750 defparam toggle_counter_sig_7_.synch_mode="on";
3751 defparam toggle_counter_sig_7_.sum_lutc_input="cin";
3752 // @12:100
3753   stratix_lcell toggle_counter_sig_6_ (
3754         .regout(toggle_counter_sig_6),
3755         .cout(toggle_counter_sig_cout[6]),
3756         .clk(clk_pin_c),
3757         .dataa(toggle_counter_sig_6),
3758         .datab(toggle_counter_sig_7),
3759         .datac(VCC),
3760         .datad(VCC),
3761         .aclr(un6_dly_counter_0_x),
3762         .sclr(toggle_sig_0_0_0_g1_i),
3763         .sload(GND),
3764         .ena(VCC),
3765         .cin(toggle_counter_sig_cout[4]),
3766         .inverta(GND),
3767         .aload(GND),
3768         .regcascin(GND)
3769 );
3770 defparam toggle_counter_sig_6_.cin_used="true";
3771 defparam toggle_counter_sig_6_.operation_mode="arithmetic";
3772 defparam toggle_counter_sig_6_.output_mode="reg_only";
3773 defparam toggle_counter_sig_6_.lut_mask="5a80";
3774 defparam toggle_counter_sig_6_.synch_mode="on";
3775 defparam toggle_counter_sig_6_.sum_lutc_input="cin";
3776 // @12:100
3777   stratix_lcell toggle_counter_sig_5_ (
3778         .regout(toggle_counter_sig_5),
3779         .cout(toggle_counter_sig_cout[5]),
3780         .clk(clk_pin_c),
3781         .dataa(toggle_counter_sig_4),
3782         .datab(toggle_counter_sig_5),
3783         .datac(VCC),
3784         .datad(VCC),
3785         .aclr(un6_dly_counter_0_x),
3786         .sclr(toggle_sig_0_0_0_g1_i),
3787         .sload(GND),
3788         .ena(VCC),
3789         .cin(toggle_counter_sig_cout[3]),
3790         .inverta(GND),
3791         .aload(GND),
3792         .regcascin(GND)
3793 );
3794 defparam toggle_counter_sig_5_.cin_used="true";
3795 defparam toggle_counter_sig_5_.operation_mode="arithmetic";
3796 defparam toggle_counter_sig_5_.output_mode="reg_only";
3797 defparam toggle_counter_sig_5_.lut_mask="6c80";
3798 defparam toggle_counter_sig_5_.synch_mode="on";
3799 defparam toggle_counter_sig_5_.sum_lutc_input="cin";
3800 // @12:100
3801   stratix_lcell toggle_counter_sig_4_ (
3802         .regout(toggle_counter_sig_4),
3803         .cout(toggle_counter_sig_cout[4]),
3804         .clk(clk_pin_c),
3805         .dataa(toggle_counter_sig_4),
3806         .datab(toggle_counter_sig_5),
3807         .datac(VCC),
3808         .datad(VCC),
3809         .aclr(un6_dly_counter_0_x),
3810         .sclr(toggle_sig_0_0_0_g1_i),
3811         .sload(GND),
3812         .ena(VCC),
3813         .cin(toggle_counter_sig_cout[2]),
3814         .inverta(GND),
3815         .aload(GND),
3816         .regcascin(GND)
3817 );
3818 defparam toggle_counter_sig_4_.cin_used="true";
3819 defparam toggle_counter_sig_4_.operation_mode="arithmetic";
3820 defparam toggle_counter_sig_4_.output_mode="reg_only";
3821 defparam toggle_counter_sig_4_.lut_mask="5a80";
3822 defparam toggle_counter_sig_4_.synch_mode="on";
3823 defparam toggle_counter_sig_4_.sum_lutc_input="cin";
3824 // @12:100
3825   stratix_lcell toggle_counter_sig_3_ (
3826         .regout(toggle_counter_sig_3),
3827         .cout(toggle_counter_sig_cout[3]),
3828         .clk(clk_pin_c),
3829         .dataa(toggle_counter_sig_2),
3830         .datab(toggle_counter_sig_3),
3831         .datac(VCC),
3832         .datad(VCC),
3833         .aclr(un6_dly_counter_0_x),
3834         .sclr(toggle_sig_0_0_0_g1_i),
3835         .sload(GND),
3836         .ena(VCC),
3837         .cin(toggle_counter_sig_cout[1]),
3838         .inverta(GND),
3839         .aload(GND),
3840         .regcascin(GND)
3841 );
3842 defparam toggle_counter_sig_3_.cin_used="true";
3843 defparam toggle_counter_sig_3_.operation_mode="arithmetic";
3844 defparam toggle_counter_sig_3_.output_mode="reg_only";
3845 defparam toggle_counter_sig_3_.lut_mask="6c80";
3846 defparam toggle_counter_sig_3_.synch_mode="on";
3847 defparam toggle_counter_sig_3_.sum_lutc_input="cin";
3848 // @12:100
3849   stratix_lcell toggle_counter_sig_2_ (
3850         .regout(toggle_counter_sig_2),
3851         .cout(toggle_counter_sig_cout[2]),
3852         .clk(clk_pin_c),
3853         .dataa(toggle_counter_sig_2),
3854         .datab(toggle_counter_sig_3),
3855         .datac(VCC),
3856         .datad(VCC),
3857         .aclr(un6_dly_counter_0_x),
3858         .sclr(toggle_sig_0_0_0_g1_i),
3859         .sload(GND),
3860         .ena(VCC),
3861         .cin(un2_toggle_counter_next_cout[0]),
3862         .inverta(GND),
3863         .aload(GND),
3864         .regcascin(GND)
3865 );
3866 defparam toggle_counter_sig_2_.cin_used="true";
3867 defparam toggle_counter_sig_2_.operation_mode="arithmetic";
3868 defparam toggle_counter_sig_2_.output_mode="reg_only";
3869 defparam toggle_counter_sig_2_.lut_mask="5a80";
3870 defparam toggle_counter_sig_2_.synch_mode="on";
3871 defparam toggle_counter_sig_2_.sum_lutc_input="cin";
3872 // @12:100
3873   stratix_lcell toggle_counter_sig_1_ (
3874         .regout(toggle_counter_sig_1),
3875         .cout(toggle_counter_sig_cout[1]),
3876         .clk(clk_pin_c),
3877         .dataa(toggle_counter_sig_0),
3878         .datab(toggle_counter_sig_1),
3879         .datac(VCC),
3880         .datad(VCC),
3881         .aclr(un6_dly_counter_0_x),
3882         .sclr(toggle_sig_0_0_0_g1_i),
3883         .sload(GND),
3884         .ena(VCC),
3885         .inverta(GND),
3886         .aload(GND),
3887         .regcascin(GND)
3888 );
3889 defparam toggle_counter_sig_1_.operation_mode="arithmetic";
3890 defparam toggle_counter_sig_1_.output_mode="reg_only";
3891 defparam toggle_counter_sig_1_.lut_mask="6688";
3892 defparam toggle_counter_sig_1_.synch_mode="on";
3893 defparam toggle_counter_sig_1_.sum_lutc_input="datac";
3894 // @12:100
3895   stratix_lcell toggle_counter_sig_0_ (
3896         .regout(toggle_counter_sig_0),
3897         .clk(clk_pin_c),
3898         .dataa(toggle_counter_sig_0),
3899         .datab(VCC),
3900         .datac(VCC),
3901         .datad(VCC),
3902         .aclr(un6_dly_counter_0_x),
3903         .sclr(toggle_sig_0_0_0_g1_i),
3904         .sload(GND),
3905         .ena(VCC),
3906         .inverta(GND),
3907         .aload(GND),
3908         .regcascin(GND)
3909 );
3910 defparam toggle_counter_sig_0_.operation_mode="normal";
3911 defparam toggle_counter_sig_0_.output_mode="reg_only";
3912 defparam toggle_counter_sig_0_.lut_mask="5555";
3913 defparam toggle_counter_sig_0_.synch_mode="on";
3914 defparam toggle_counter_sig_0_.sum_lutc_input="datac";
3915 // @12:100
3916   stratix_lcell toggle_sig_Z (
3917         .regout(toggle_sig),
3918         .clk(clk_pin_c),
3919         .dataa(toggle_sig),
3920         .datab(toggle_sig_0_0_0_g1),
3921         .datac(VCC),
3922         .datad(VCC),
3923         .aclr(un6_dly_counter_0_x),
3924         .sclr(GND),
3925         .sload(GND),
3926         .ena(VCC),
3927         .inverta(GND),
3928         .aload(GND),
3929         .regcascin(GND)
3930 );
3931 defparam toggle_sig_Z.operation_mode="normal";
3932 defparam toggle_sig_Z.output_mode="reg_only";
3933 defparam toggle_sig_Z.lut_mask="9999";
3934 defparam toggle_sig_Z.synch_mode="off";
3935 defparam toggle_sig_Z.sum_lutc_input="datac";
3936 // @12:61
3937   stratix_lcell b_Z (
3938         .regout(b),
3939         .clk(clk_pin_c),
3940         .dataa(un13_v_enablelto8),
3941         .datab(un5_v_enablelto7),
3942         .datac(un17_v_enablelto7),
3943         .datad(b_next_0_g0_5),
3944         .aclr(un6_dly_counter_0_x),
3945         .sclr(GND),
3946         .sload(GND),
3947         .ena(VCC),
3948         .inverta(GND),
3949         .aload(GND),
3950         .regcascin(GND)
3951 );
3952 defparam b_Z.operation_mode="normal";
3953 defparam b_Z.output_mode="reg_only";
3954 defparam b_Z.lut_mask="0100";
3955 defparam b_Z.synch_mode="off";
3956 defparam b_Z.sum_lutc_input="datac";
3957 // @12:61
3958   stratix_lcell r_Z (
3959         .regout(r),
3960         .clk(clk_pin_c),
3961         .dataa(VCC),
3962         .datab(VCC),
3963         .datac(VCC),
3964         .datad(GND),
3965         .aclr(un6_dly_counter_0_x),
3966         .sclr(GND),
3967         .sload(GND),
3968         .ena(VCC),
3969         .inverta(GND),
3970         .aload(GND),
3971         .regcascin(GND)
3972 );
3973 defparam r_Z.operation_mode="normal";
3974 defparam r_Z.output_mode="reg_only";
3975 defparam r_Z.lut_mask="ff00";
3976 defparam r_Z.synch_mode="off";
3977 defparam r_Z.sum_lutc_input="datac";
3978 // @12:61
3979   stratix_lcell g_Z (
3980         .regout(g),
3981         .clk(clk_pin_c),
3982         .dataa(VCC),
3983         .datab(VCC),
3984         .datac(VCC),
3985         .datad(GND),
3986         .aclr(un6_dly_counter_0_x),
3987         .sclr(GND),
3988         .sload(GND),
3989         .ena(VCC),
3990         .inverta(GND),
3991         .aload(GND),
3992         .regcascin(GND)
3993 );
3994 defparam g_Z.operation_mode="normal";
3995 defparam g_Z.output_mode="reg_only";
3996 defparam g_Z.lut_mask="ff00";
3997 defparam g_Z.synch_mode="off";
3998 defparam g_Z.sum_lutc_input="datac";
3999   stratix_lcell toggle_sig_0_0_0_g1_cZ (
4000         .combout(toggle_sig_0_0_0_g1),
4001         .clk(GND),
4002         .dataa(toggle_counter_sig_20),
4003         .datab(toggle_counter_sig_21),
4004         .datac(toggle_sig_0_0_0_g1_2),
4005         .datad(un1_toggle_counter_siglto19),
4006         .aclr(GND),
4007         .sclr(GND),
4008         .sload(GND),
4009         .ena(VCC),
4010         .inverta(GND),
4011         .aload(GND),
4012         .regcascin(GND)
4013 );
4014 defparam toggle_sig_0_0_0_g1_cZ.operation_mode="normal";
4015 defparam toggle_sig_0_0_0_g1_cZ.output_mode="comb_only";
4016 defparam toggle_sig_0_0_0_g1_cZ.lut_mask="0100";
4017 defparam toggle_sig_0_0_0_g1_cZ.synch_mode="off";
4018 defparam toggle_sig_0_0_0_g1_cZ.sum_lutc_input="datac";
4019 // @12:112
4020   stratix_lcell BLINKER_next_un1_toggle_counter_siglto19 (
4021         .combout(un1_toggle_counter_siglto19),
4022         .clk(GND),
4023         .dataa(toggle_counter_sig_11),
4024         .datab(toggle_counter_sig_12),
4025         .datac(un1_toggle_counter_siglto19_5),
4026         .datad(un1_toggle_counter_siglto10),
4027         .aclr(GND),
4028         .sclr(GND),
4029         .sload(GND),
4030         .ena(VCC),
4031         .inverta(GND),
4032         .aload(GND),
4033         .regcascin(GND)
4034 );
4035 defparam BLINKER_next_un1_toggle_counter_siglto19.operation_mode="normal";
4036 defparam BLINKER_next_un1_toggle_counter_siglto19.output_mode="comb_only";
4037 defparam BLINKER_next_un1_toggle_counter_siglto19.lut_mask="f1f0";
4038 defparam BLINKER_next_un1_toggle_counter_siglto19.synch_mode="off";
4039 defparam BLINKER_next_un1_toggle_counter_siglto19.sum_lutc_input="datac";
4040 // @12:112
4041   stratix_lcell BLINKER_next_un1_toggle_counter_siglto10 (
4042         .combout(un1_toggle_counter_siglto10),
4043         .clk(GND),
4044         .dataa(toggle_counter_sig_8),
4045         .datab(toggle_counter_sig_9),
4046         .datac(toggle_counter_sig_10),
4047         .datad(un1_toggle_counter_siglto7),
4048         .aclr(GND),
4049         .sclr(GND),
4050         .sload(GND),
4051         .ena(VCC),
4052         .inverta(GND),
4053         .aload(GND),
4054         .regcascin(GND)
4055 );
4056 defparam BLINKER_next_un1_toggle_counter_siglto10.operation_mode="normal";
4057 defparam BLINKER_next_un1_toggle_counter_siglto10.output_mode="comb_only";
4058 defparam BLINKER_next_un1_toggle_counter_siglto10.lut_mask="3f1f";
4059 defparam BLINKER_next_un1_toggle_counter_siglto10.synch_mode="off";
4060 defparam BLINKER_next_un1_toggle_counter_siglto10.sum_lutc_input="datac";
4061   stratix_lcell b_next_0_g0_5_cZ (
4062         .combout(b_next_0_g0_5),
4063         .clk(GND),
4064         .dataa(h_enable_sig),
4065         .datab(toggle_sig),
4066         .datac(b_next_0_g0_3),
4067         .datad(un9_v_enablelto9),
4068         .aclr(GND),
4069         .sclr(GND),
4070         .sload(GND),
4071         .ena(VCC),
4072         .inverta(GND),
4073         .aload(GND),
4074         .regcascin(GND)
4075 );
4076 defparam b_next_0_g0_5_cZ.operation_mode="normal";
4077 defparam b_next_0_g0_5_cZ.output_mode="comb_only";
4078 defparam b_next_0_g0_5_cZ.lut_mask="0080";
4079 defparam b_next_0_g0_5_cZ.synch_mode="off";
4080 defparam b_next_0_g0_5_cZ.sum_lutc_input="datac";
4081 // @12:77
4082   stratix_lcell DRAW_SQUARE_next_un17_v_enablelto7 (
4083         .combout(un17_v_enablelto7),
4084         .clk(GND),
4085         .dataa(line_counter_sig_6),
4086         .datab(line_counter_sig_7),
4087         .datac(un17_v_enablelto5),
4088         .datad(VCC),
4089         .aclr(GND),
4090         .sclr(GND),
4091         .sload(GND),
4092         .ena(VCC),
4093         .inverta(GND),
4094         .aload(GND),
4095         .regcascin(GND)
4096 );
4097 defparam DRAW_SQUARE_next_un17_v_enablelto7.operation_mode="normal";
4098 defparam DRAW_SQUARE_next_un17_v_enablelto7.output_mode="comb_only";
4099 defparam DRAW_SQUARE_next_un17_v_enablelto7.lut_mask="8080";
4100 defparam DRAW_SQUARE_next_un17_v_enablelto7.synch_mode="off";
4101 defparam DRAW_SQUARE_next_un17_v_enablelto7.sum_lutc_input="datac";
4102 // @12:76
4103   stratix_lcell DRAW_SQUARE_next_un5_v_enablelto7 (
4104         .combout(un5_v_enablelto7),
4105         .clk(GND),
4106         .dataa(column_counter_sig_6),
4107         .datab(column_counter_sig_7),
4108         .datac(un5_v_enablelto5_0),
4109         .datad(un5_v_enablelto3),
4110         .aclr(GND),
4111         .sclr(GND),
4112         .sload(GND),
4113         .ena(VCC),
4114         .inverta(GND),
4115         .aload(GND),
4116         .regcascin(GND)
4117 );
4118 defparam DRAW_SQUARE_next_un5_v_enablelto7.operation_mode="normal";
4119 defparam DRAW_SQUARE_next_un5_v_enablelto7.output_mode="comb_only";
4120 defparam DRAW_SQUARE_next_un5_v_enablelto7.lut_mask="8880";
4121 defparam DRAW_SQUARE_next_un5_v_enablelto7.synch_mode="off";
4122 defparam DRAW_SQUARE_next_un5_v_enablelto7.sum_lutc_input="datac";
4123 // @12:77
4124   stratix_lcell DRAW_SQUARE_next_un17_v_enablelto5 (
4125         .combout(un17_v_enablelto5),
4126         .clk(GND),
4127         .dataa(line_counter_sig_4),
4128         .datab(line_counter_sig_5),
4129         .datac(line_counter_sig_3),
4130         .datad(un17_v_enablelt2),
4131         .aclr(GND),
4132         .sclr(GND),
4133         .sload(GND),
4134         .ena(VCC),
4135         .inverta(GND),
4136         .aload(GND),
4137         .regcascin(GND)
4138 );
4139 defparam DRAW_SQUARE_next_un17_v_enablelto5.operation_mode="normal";
4140 defparam DRAW_SQUARE_next_un17_v_enablelto5.output_mode="comb_only";
4141 defparam DRAW_SQUARE_next_un17_v_enablelto5.lut_mask="feee";
4142 defparam DRAW_SQUARE_next_un17_v_enablelto5.synch_mode="off";
4143 defparam DRAW_SQUARE_next_un17_v_enablelto5.sum_lutc_input="datac";
4144 // @12:77
4145   stratix_lcell DRAW_SQUARE_next_un13_v_enablelto8 (
4146         .combout(un13_v_enablelto8),
4147         .clk(GND),
4148         .dataa(line_counter_sig_8),
4149         .datab(line_counter_sig_7),
4150         .datac(line_counter_sig_6),
4151         .datad(un13_v_enablelto8_a),
4152         .aclr(GND),
4153         .sclr(GND),
4154         .sload(GND),
4155         .ena(VCC),
4156         .inverta(GND),
4157         .aload(GND),
4158         .regcascin(GND)
4159 );
4160 defparam DRAW_SQUARE_next_un13_v_enablelto8.operation_mode="normal";
4161 defparam DRAW_SQUARE_next_un13_v_enablelto8.output_mode="comb_only";
4162 defparam DRAW_SQUARE_next_un13_v_enablelto8.lut_mask="1101";
4163 defparam DRAW_SQUARE_next_un13_v_enablelto8.synch_mode="off";
4164 defparam DRAW_SQUARE_next_un13_v_enablelto8.sum_lutc_input="datac";
4165 // @12:77
4166   stratix_lcell DRAW_SQUARE_next_un13_v_enablelto8_a (
4167         .combout(un13_v_enablelto8_a),
4168         .clk(GND),
4169         .dataa(line_counter_sig_2),
4170         .datab(line_counter_sig_4),
4171         .datac(line_counter_sig_3),
4172         .datad(line_counter_sig_5),
4173         .aclr(GND),
4174         .sclr(GND),
4175         .sload(GND),
4176         .ena(VCC),
4177         .inverta(GND),
4178         .aload(GND),
4179         .regcascin(GND)
4180 );
4181 defparam DRAW_SQUARE_next_un13_v_enablelto8_a.operation_mode="normal";
4182 defparam DRAW_SQUARE_next_un13_v_enablelto8_a.output_mode="comb_only";
4183 defparam DRAW_SQUARE_next_un13_v_enablelto8_a.lut_mask="01ff";
4184 defparam DRAW_SQUARE_next_un13_v_enablelto8_a.synch_mode="off";
4185 defparam DRAW_SQUARE_next_un13_v_enablelto8_a.sum_lutc_input="datac";
4186 // @12:76
4187   stratix_lcell DRAW_SQUARE_next_un9_v_enablelto9 (
4188         .combout(un9_v_enablelto9),
4189         .clk(GND),
4190         .dataa(column_counter_sig_7),
4191         .datab(column_counter_sig_8),
4192         .datac(column_counter_sig_9),
4193         .datad(un9_v_enablelto6),
4194         .aclr(GND),
4195         .sclr(GND),
4196         .sload(GND),
4197         .ena(VCC),
4198         .inverta(GND),
4199         .aload(GND),
4200         .regcascin(GND)
4201 );
4202 defparam DRAW_SQUARE_next_un9_v_enablelto9.operation_mode="normal";
4203 defparam DRAW_SQUARE_next_un9_v_enablelto9.output_mode="comb_only";
4204 defparam DRAW_SQUARE_next_un9_v_enablelto9.lut_mask="0100";
4205 defparam DRAW_SQUARE_next_un9_v_enablelto9.synch_mode="off";
4206 defparam DRAW_SQUARE_next_un9_v_enablelto9.sum_lutc_input="datac";
4207 // @12:112
4208   stratix_lcell BLINKER_next_un1_toggle_counter_siglto19_5 (
4209         .combout(un1_toggle_counter_siglto19_5),
4210         .clk(GND),
4211         .dataa(toggle_counter_sig_13),
4212         .datab(toggle_counter_sig_14),
4213         .datac(toggle_counter_sig_15),
4214         .datad(un1_toggle_counter_siglto19_4),
4215         .aclr(GND),
4216         .sclr(GND),
4217         .sload(GND),
4218         .ena(VCC),
4219         .inverta(GND),
4220         .aload(GND),
4221         .regcascin(GND)
4222 );
4223 defparam BLINKER_next_un1_toggle_counter_siglto19_5.operation_mode="normal";
4224 defparam BLINKER_next_un1_toggle_counter_siglto19_5.output_mode="comb_only";
4225 defparam BLINKER_next_un1_toggle_counter_siglto19_5.lut_mask="ff7f";
4226 defparam BLINKER_next_un1_toggle_counter_siglto19_5.synch_mode="off";
4227 defparam BLINKER_next_un1_toggle_counter_siglto19_5.sum_lutc_input="datac";
4228 // @12:112
4229   stratix_lcell BLINKER_next_un1_toggle_counter_siglto7 (
4230         .combout(un1_toggle_counter_siglto7),
4231         .clk(GND),
4232         .dataa(toggle_counter_sig_2),
4233         .datab(toggle_counter_sig_3),
4234         .datac(toggle_counter_sig_4),
4235         .datad(un1_toggle_counter_siglto7_4),
4236         .aclr(GND),
4237         .sclr(GND),
4238         .sload(GND),
4239         .ena(VCC),
4240         .inverta(GND),
4241         .aload(GND),
4242         .regcascin(GND)
4243 );
4244 defparam BLINKER_next_un1_toggle_counter_siglto7.operation_mode="normal";
4245 defparam BLINKER_next_un1_toggle_counter_siglto7.output_mode="comb_only";
4246 defparam BLINKER_next_un1_toggle_counter_siglto7.lut_mask="0100";
4247 defparam BLINKER_next_un1_toggle_counter_siglto7.synch_mode="off";
4248 defparam BLINKER_next_un1_toggle_counter_siglto7.sum_lutc_input="datac";
4249 // @12:76
4250   stratix_lcell DRAW_SQUARE_next_un9_v_enablelto6 (
4251         .combout(un9_v_enablelto6),
4252         .clk(GND),
4253         .dataa(column_counter_sig_2),
4254         .datab(column_counter_sig_4),
4255         .datac(column_counter_sig_3),
4256         .datad(un10_column_counter_siglt6_1),
4257         .aclr(GND),
4258         .sclr(GND),
4259         .sload(GND),
4260         .ena(VCC),
4261         .inverta(GND),
4262         .aload(GND),
4263         .regcascin(GND)
4264 );
4265 defparam DRAW_SQUARE_next_un9_v_enablelto6.operation_mode="normal";
4266 defparam DRAW_SQUARE_next_un9_v_enablelto6.output_mode="comb_only";
4267 defparam DRAW_SQUARE_next_un9_v_enablelto6.lut_mask="ff01";
4268 defparam DRAW_SQUARE_next_un9_v_enablelto6.synch_mode="off";
4269 defparam DRAW_SQUARE_next_un9_v_enablelto6.sum_lutc_input="datac";
4270 // @12:76
4271   stratix_lcell DRAW_SQUARE_next_un5_v_enablelto3 (
4272         .combout(un5_v_enablelto3),
4273         .clk(GND),
4274         .dataa(column_counter_sig_1),
4275         .datab(column_counter_sig_2),
4276         .datac(column_counter_sig_0),
4277         .datad(column_counter_sig_3),
4278         .aclr(GND),
4279         .sclr(GND),
4280         .sload(GND),
4281         .ena(VCC),
4282         .inverta(GND),
4283         .aload(GND),
4284         .regcascin(GND)
4285 );
4286 defparam DRAW_SQUARE_next_un5_v_enablelto3.operation_mode="normal";
4287 defparam DRAW_SQUARE_next_un5_v_enablelto3.output_mode="comb_only";
4288 defparam DRAW_SQUARE_next_un5_v_enablelto3.lut_mask="fe00";
4289 defparam DRAW_SQUARE_next_un5_v_enablelto3.synch_mode="off";
4290 defparam DRAW_SQUARE_next_un5_v_enablelto3.sum_lutc_input="datac";
4291   stratix_lcell toggle_sig_0_0_0_g1_2_cZ (
4292         .combout(toggle_sig_0_0_0_g1_2),
4293         .clk(GND),
4294         .dataa(toggle_counter_sig_22),
4295         .datab(toggle_counter_sig_23),
4296         .datac(toggle_counter_sig_24),
4297         .datad(VCC),
4298         .aclr(GND),
4299         .sclr(GND),
4300         .sload(GND),
4301         .ena(VCC),
4302         .inverta(GND),
4303         .aload(GND),
4304         .regcascin(GND)
4305 );
4306 defparam toggle_sig_0_0_0_g1_2_cZ.operation_mode="normal";
4307 defparam toggle_sig_0_0_0_g1_2_cZ.output_mode="comb_only";
4308 defparam toggle_sig_0_0_0_g1_2_cZ.lut_mask="fefe";
4309 defparam toggle_sig_0_0_0_g1_2_cZ.synch_mode="off";
4310 defparam toggle_sig_0_0_0_g1_2_cZ.sum_lutc_input="datac";
4311 // @12:112
4312   stratix_lcell BLINKER_next_un1_toggle_counter_siglto19_4 (
4313         .combout(un1_toggle_counter_siglto19_4),
4314         .clk(GND),
4315         .dataa(toggle_counter_sig_16),
4316         .datab(toggle_counter_sig_17),
4317         .datac(toggle_counter_sig_18),
4318         .datad(toggle_counter_sig_19),
4319         .aclr(GND),
4320         .sclr(GND),
4321         .sload(GND),
4322         .ena(VCC),
4323         .inverta(GND),
4324         .aload(GND),
4325         .regcascin(GND)
4326 );
4327 defparam BLINKER_next_un1_toggle_counter_siglto19_4.operation_mode="normal";
4328 defparam BLINKER_next_un1_toggle_counter_siglto19_4.output_mode="comb_only";
4329 defparam BLINKER_next_un1_toggle_counter_siglto19_4.lut_mask="7fff";
4330 defparam BLINKER_next_un1_toggle_counter_siglto19_4.synch_mode="off";
4331 defparam BLINKER_next_un1_toggle_counter_siglto19_4.sum_lutc_input="datac";
4332   stratix_lcell b_next_0_g0_3_cZ (
4333         .combout(b_next_0_g0_3),
4334         .clk(GND),
4335         .dataa(line_counter_sig_8),
4336         .datab(v_enable_sig),
4337         .datac(column_counter_sig_8),
4338         .datad(column_counter_sig_9),
4339         .aclr(GND),
4340         .sclr(GND),
4341         .sload(GND),
4342         .ena(VCC),
4343         .inverta(GND),
4344         .aload(GND),
4345         .regcascin(GND)
4346 );
4347 defparam b_next_0_g0_3_cZ.operation_mode="normal";
4348 defparam b_next_0_g0_3_cZ.output_mode="comb_only";
4349 defparam b_next_0_g0_3_cZ.lut_mask="0004";
4350 defparam b_next_0_g0_3_cZ.synch_mode="off";
4351 defparam b_next_0_g0_3_cZ.sum_lutc_input="datac";
4352 // @12:112
4353   stratix_lcell BLINKER_next_un1_toggle_counter_siglto7_4 (
4354         .combout(un1_toggle_counter_siglto7_4),
4355         .clk(GND),
4356         .dataa(toggle_counter_sig_1),
4357         .datab(toggle_counter_sig_5),
4358         .datac(toggle_counter_sig_6),
4359         .datad(toggle_counter_sig_7),
4360         .aclr(GND),
4361         .sclr(GND),
4362         .sload(GND),
4363         .ena(VCC),
4364         .inverta(GND),
4365         .aload(GND),
4366         .regcascin(GND)
4367 );
4368 defparam BLINKER_next_un1_toggle_counter_siglto7_4.operation_mode="normal";
4369 defparam BLINKER_next_un1_toggle_counter_siglto7_4.output_mode="comb_only";
4370 defparam BLINKER_next_un1_toggle_counter_siglto7_4.lut_mask="0001";
4371 defparam BLINKER_next_un1_toggle_counter_siglto7_4.synch_mode="off";
4372 defparam BLINKER_next_un1_toggle_counter_siglto7_4.sum_lutc_input="datac";
4373 // @12:77
4374   stratix_lcell DRAW_SQUARE_next_un17_v_enablelt2 (
4375         .combout(un17_v_enablelt2),
4376         .clk(GND),
4377         .dataa(line_counter_sig_1),
4378         .datab(line_counter_sig_2),
4379         .datac(line_counter_sig_0),
4380         .datad(VCC),
4381         .aclr(GND),
4382         .sclr(GND),
4383         .sload(GND),
4384         .ena(VCC),
4385         .inverta(GND),
4386         .aload(GND),
4387         .regcascin(GND)
4388 );
4389 defparam DRAW_SQUARE_next_un17_v_enablelt2.operation_mode="normal";
4390 defparam DRAW_SQUARE_next_un17_v_enablelt2.output_mode="comb_only";
4391 defparam DRAW_SQUARE_next_un17_v_enablelt2.lut_mask="fefe";
4392 defparam DRAW_SQUARE_next_un17_v_enablelt2.synch_mode="off";
4393 defparam DRAW_SQUARE_next_un17_v_enablelt2.sum_lutc_input="datac";
4394 // @12:76
4395   stratix_lcell DRAW_SQUARE_next_un5_v_enablelto5_0 (
4396         .combout(un5_v_enablelto5_0),
4397         .clk(GND),
4398         .dataa(column_counter_sig_5),
4399         .datab(column_counter_sig_4),
4400         .datac(VCC),
4401         .datad(VCC),
4402         .aclr(GND),
4403         .sclr(GND),
4404         .sload(GND),
4405         .ena(VCC),
4406         .inverta(GND),
4407         .aload(GND),
4408         .regcascin(GND)
4409 );
4410 defparam DRAW_SQUARE_next_un5_v_enablelto5_0.operation_mode="normal";
4411 defparam DRAW_SQUARE_next_un5_v_enablelto5_0.output_mode="comb_only";
4412 defparam DRAW_SQUARE_next_un5_v_enablelto5_0.lut_mask="eeee";
4413 defparam DRAW_SQUARE_next_un5_v_enablelto5_0.synch_mode="off";
4414 defparam DRAW_SQUARE_next_un5_v_enablelto5_0.sum_lutc_input="datac";
4415 // @12:116
4416   stratix_lcell un2_toggle_counter_next_0_ (
4417         .cout(un2_toggle_counter_next_cout[0]),
4418         .clk(GND),
4419         .dataa(toggle_counter_sig_0),
4420         .datab(toggle_counter_sig_1),
4421         .datac(VCC),
4422         .datad(VCC),
4423         .aclr(GND),
4424         .sclr(GND),
4425         .sload(GND),
4426         .ena(VCC),
4427         .inverta(GND),
4428         .aload(GND),
4429         .regcascin(GND)
4430 );
4431 defparam un2_toggle_counter_next_0_.operation_mode="arithmetic";
4432 defparam un2_toggle_counter_next_0_.output_mode="comb_only";
4433 defparam un2_toggle_counter_next_0_.lut_mask="5588";
4434 defparam un2_toggle_counter_next_0_.synch_mode="off";
4435 defparam un2_toggle_counter_next_0_.sum_lutc_input="datac";
4436   assign  toggle_sig_0_0_0_g1_i = ~ toggle_sig_0_0_0_g1;
4437 endmodule /* vga_control */
4438
4439 // VQM4.1+
4440 module vga (
4441   clk_pin,
4442   reset_pin,
4443   r0_pin,
4444   r1_pin,
4445   r2_pin,
4446   g0_pin,
4447   g1_pin,
4448   g2_pin,
4449   b0_pin,
4450   b1_pin,
4451   hsync_pin,
4452   vsync_pin,
4453   seven_seg_pin,
4454   d_hsync,
4455   d_vsync,
4456   d_column_counter,
4457   d_line_counter,
4458   d_set_column_counter,
4459   d_set_line_counter,
4460   d_hsync_counter,
4461   d_vsync_counter,
4462   d_set_hsync_counter,
4463   d_set_vsync_counter,
4464   d_h_enable,
4465   d_v_enable,
4466   d_r,
4467   d_g,
4468   d_b,
4469   d_hsync_state,
4470   d_vsync_state,
4471   d_state_clk,
4472   d_toggle,
4473   d_toggle_counter
4474 )
4475 ;
4476 input clk_pin ;
4477 input reset_pin ;
4478 output r0_pin ;
4479 output r1_pin ;
4480 output r2_pin ;
4481 output g0_pin ;
4482 output g1_pin ;
4483 output g2_pin ;
4484 output b0_pin ;
4485 output b1_pin ;
4486 output hsync_pin ;
4487 output vsync_pin ;
4488 output [13:0] seven_seg_pin ;
4489 output d_hsync ;
4490 output d_vsync ;
4491 output [9:0] d_column_counter ;
4492 output [8:0] d_line_counter ;
4493 output d_set_column_counter ;
4494 output d_set_line_counter ;
4495 output [9:0] d_hsync_counter ;
4496 output [9:0] d_vsync_counter ;
4497 output d_set_hsync_counter ;
4498 output d_set_vsync_counter ;
4499 output d_h_enable ;
4500 output d_v_enable ;
4501 output d_r ;
4502 output d_g ;
4503 output d_b ;
4504 output [0:6] d_hsync_state ;
4505 output [0:6] d_vsync_state ;
4506 output d_state_clk ;
4507 output d_toggle ;
4508 output [24:0] d_toggle_counter ;
4509 wire clk_pin ;
4510 wire reset_pin ;
4511 wire r0_pin ;
4512 wire r1_pin ;
4513 wire r2_pin ;
4514 wire g0_pin ;
4515 wire g1_pin ;
4516 wire g2_pin ;
4517 wire b0_pin ;
4518 wire b1_pin ;
4519 wire hsync_pin ;
4520 wire vsync_pin ;
4521 wire d_hsync ;
4522 wire d_vsync ;
4523 wire d_set_column_counter ;
4524 wire d_set_line_counter ;
4525 wire d_set_hsync_counter ;
4526 wire d_set_vsync_counter ;
4527 wire d_h_enable ;
4528 wire d_v_enable ;
4529 wire d_r ;
4530 wire d_g ;
4531 wire d_b ;
4532 wire d_state_clk ;
4533 wire d_toggle ;
4534 wire [1:0] dly_counter;
4535 wire [9:0] vga_driver_unit_column_counter_sig;
4536 wire [8:0] vga_driver_unit_line_counter_sig;
4537 wire [9:0] vga_driver_unit_hsync_counter;
4538 wire [9:0] vga_driver_unit_vsync_counter;
4539 wire [6:0] vga_driver_unit_hsync_state;
4540 wire [6:0] vga_driver_unit_vsync_state;
4541 wire [24:0] vga_control_unit_toggle_counter_sig;
4542 wire VCC ;
4543 wire GND ;
4544 wire vga_driver_unit_COLUMN_COUNT_next_un10_column_counter_siglt6_1 ;
4545 wire DELAY_RESET_next_un6_dly_counter_0_x ;
4546 wire vga_driver_unit_h_sync ;
4547 wire vga_driver_unit_v_sync ;
4548 wire vga_driver_unit_d_set_hsync_counter ;
4549 wire vga_driver_unit_d_set_vsync_counter ;
4550 wire vga_driver_unit_h_enable_sig ;
4551 wire vga_driver_unit_v_enable_sig ;
4552 wire vga_control_unit_r ;
4553 wire vga_control_unit_g ;
4554 wire vga_control_unit_b ;
4555 wire G_33 ;
4556 wire vga_control_unit_toggle_sig ;
4557 wire reset_pin_c ;
4558 //@1:1
4559   assign VCC = 1'b1;
4560 //@1:1
4561   assign GND = 1'b0;
4562 // @10:113
4563   stratix_lcell dly_counter_1_ (
4564         .regout(dly_counter[1]),
4565         .clk(G_33),
4566         .dataa(reset_pin_c),
4567         .datab(dly_counter[0]),
4568         .datac(dly_counter[1]),
4569         .datad(VCC),
4570         .aclr(GND),
4571         .sclr(GND),
4572         .sload(GND),
4573         .ena(VCC),
4574         .inverta(GND),
4575         .aload(GND),
4576         .regcascin(GND)
4577 );
4578 defparam dly_counter_1_.operation_mode="normal";
4579 defparam dly_counter_1_.output_mode="reg_only";
4580 defparam dly_counter_1_.lut_mask="a8a8";
4581 defparam dly_counter_1_.synch_mode="off";
4582 defparam dly_counter_1_.sum_lutc_input="datac";
4583 // @10:113
4584   stratix_lcell dly_counter_0_ (
4585         .regout(dly_counter[0]),
4586         .clk(G_33),
4587         .dataa(reset_pin_c),
4588         .datab(dly_counter[0]),
4589         .datac(dly_counter[1]),
4590         .datad(VCC),
4591         .aclr(GND),
4592         .sclr(GND),
4593         .sload(GND),
4594         .ena(VCC),
4595         .inverta(GND),
4596         .aload(GND),
4597         .regcascin(GND)
4598 );
4599 defparam dly_counter_0_.operation_mode="normal";
4600 defparam dly_counter_0_.output_mode="reg_only";
4601 defparam dly_counter_0_.lut_mask="a2a2";
4602 defparam dly_counter_0_.synch_mode="off";
4603 defparam dly_counter_0_.sum_lutc_input="datac";
4604 // @6:43
4605   stratix_io reset_pin_in (
4606         .padio(reset_pin),
4607         .combout(reset_pin_c),
4608         .datain(GND),
4609         .oe(GND),
4610         .outclk(GND),
4611         .outclkena(VCC),
4612         .inclk(GND),
4613         .inclkena(VCC),
4614         .areset(GND),
4615         .sreset(GND)
4616 );
4617 defparam reset_pin_in.operation_mode = "input";
4618 // @6:42
4619   stratix_io clk_pin_in (
4620         .padio(clk_pin),
4621         .combout(G_33),
4622         .datain(GND),
4623         .oe(GND),
4624         .outclk(GND),
4625         .outclkena(VCC),
4626         .inclk(GND),
4627         .inclkena(VCC),
4628         .areset(GND),
4629         .sreset(GND)
4630 );
4631 defparam clk_pin_in.operation_mode = "input";
4632 // @6:67
4633   stratix_io d_toggle_counter_out_24_ (
4634         .padio(d_toggle_counter[24]),
4635         .datain(vga_control_unit_toggle_counter_sig[24]),
4636         .oe(VCC),
4637         .outclk(GND),
4638         .outclkena(VCC),
4639         .inclk(GND),
4640         .inclkena(VCC),
4641         .areset(GND),
4642         .sreset(GND)
4643 );
4644 defparam d_toggle_counter_out_24_.operation_mode = "output";
4645 // @6:67
4646   stratix_io d_toggle_counter_out_23_ (
4647         .padio(d_toggle_counter[23]),
4648         .datain(vga_control_unit_toggle_counter_sig[23]),
4649         .oe(VCC),
4650         .outclk(GND),
4651         .outclkena(VCC),
4652         .inclk(GND),
4653         .inclkena(VCC),
4654         .areset(GND),
4655         .sreset(GND)
4656 );
4657 defparam d_toggle_counter_out_23_.operation_mode = "output";
4658 // @6:67
4659   stratix_io d_toggle_counter_out_22_ (
4660         .padio(d_toggle_counter[22]),
4661         .datain(vga_control_unit_toggle_counter_sig[22]),
4662         .oe(VCC),
4663         .outclk(GND),
4664         .outclkena(VCC),
4665         .inclk(GND),
4666         .inclkena(VCC),
4667         .areset(GND),
4668         .sreset(GND)
4669 );
4670 defparam d_toggle_counter_out_22_.operation_mode = "output";
4671 // @6:67
4672   stratix_io d_toggle_counter_out_21_ (
4673         .padio(d_toggle_counter[21]),
4674         .datain(vga_control_unit_toggle_counter_sig[21]),
4675         .oe(VCC),
4676         .outclk(GND),
4677         .outclkena(VCC),
4678         .inclk(GND),
4679         .inclkena(VCC),
4680         .areset(GND),
4681         .sreset(GND)
4682 );
4683 defparam d_toggle_counter_out_21_.operation_mode = "output";
4684 // @6:67
4685   stratix_io d_toggle_counter_out_20_ (
4686         .padio(d_toggle_counter[20]),
4687         .datain(vga_control_unit_toggle_counter_sig[20]),
4688         .oe(VCC),
4689         .outclk(GND),
4690         .outclkena(VCC),
4691         .inclk(GND),
4692         .inclkena(VCC),
4693         .areset(GND),
4694         .sreset(GND)
4695 );
4696 defparam d_toggle_counter_out_20_.operation_mode = "output";
4697 // @6:67
4698   stratix_io d_toggle_counter_out_19_ (
4699         .padio(d_toggle_counter[19]),
4700         .datain(vga_control_unit_toggle_counter_sig[19]),
4701         .oe(VCC),
4702         .outclk(GND),
4703         .outclkena(VCC),
4704         .inclk(GND),
4705         .inclkena(VCC),
4706         .areset(GND),
4707         .sreset(GND)
4708 );
4709 defparam d_toggle_counter_out_19_.operation_mode = "output";
4710 // @6:67
4711   stratix_io d_toggle_counter_out_18_ (
4712         .padio(d_toggle_counter[18]),
4713         .datain(vga_control_unit_toggle_counter_sig[18]),
4714         .oe(VCC),
4715         .outclk(GND),
4716         .outclkena(VCC),
4717         .inclk(GND),
4718         .inclkena(VCC),
4719         .areset(GND),
4720         .sreset(GND)
4721 );
4722 defparam d_toggle_counter_out_18_.operation_mode = "output";
4723 // @6:67
4724   stratix_io d_toggle_counter_out_17_ (
4725         .padio(d_toggle_counter[17]),
4726         .datain(vga_control_unit_toggle_counter_sig[17]),
4727         .oe(VCC),
4728         .outclk(GND),
4729         .outclkena(VCC),
4730         .inclk(GND),
4731         .inclkena(VCC),
4732         .areset(GND),
4733         .sreset(GND)
4734 );
4735 defparam d_toggle_counter_out_17_.operation_mode = "output";
4736 // @6:67
4737   stratix_io d_toggle_counter_out_16_ (
4738         .padio(d_toggle_counter[16]),
4739         .datain(vga_control_unit_toggle_counter_sig[16]),
4740         .oe(VCC),
4741         .outclk(GND),
4742         .outclkena(VCC),
4743         .inclk(GND),
4744         .inclkena(VCC),
4745         .areset(GND),
4746         .sreset(GND)
4747 );
4748 defparam d_toggle_counter_out_16_.operation_mode = "output";
4749 // @6:67
4750   stratix_io d_toggle_counter_out_15_ (
4751         .padio(d_toggle_counter[15]),
4752         .datain(vga_control_unit_toggle_counter_sig[15]),
4753         .oe(VCC),
4754         .outclk(GND),
4755         .outclkena(VCC),
4756         .inclk(GND),
4757         .inclkena(VCC),
4758         .areset(GND),
4759         .sreset(GND)
4760 );
4761 defparam d_toggle_counter_out_15_.operation_mode = "output";
4762 // @6:67
4763   stratix_io d_toggle_counter_out_14_ (
4764         .padio(d_toggle_counter[14]),
4765         .datain(vga_control_unit_toggle_counter_sig[14]),
4766         .oe(VCC),
4767         .outclk(GND),
4768         .outclkena(VCC),
4769         .inclk(GND),
4770         .inclkena(VCC),
4771         .areset(GND),
4772         .sreset(GND)
4773 );
4774 defparam d_toggle_counter_out_14_.operation_mode = "output";
4775 // @6:67
4776   stratix_io d_toggle_counter_out_13_ (
4777         .padio(d_toggle_counter[13]),
4778         .datain(vga_control_unit_toggle_counter_sig[13]),
4779         .oe(VCC),
4780         .outclk(GND),
4781         .outclkena(VCC),
4782         .inclk(GND),
4783         .inclkena(VCC),
4784         .areset(GND),
4785         .sreset(GND)
4786 );
4787 defparam d_toggle_counter_out_13_.operation_mode = "output";
4788 // @6:67
4789   stratix_io d_toggle_counter_out_12_ (
4790         .padio(d_toggle_counter[12]),
4791         .datain(vga_control_unit_toggle_counter_sig[12]),
4792         .oe(VCC),
4793         .outclk(GND),
4794         .outclkena(VCC),
4795         .inclk(GND),
4796         .inclkena(VCC),
4797         .areset(GND),
4798         .sreset(GND)
4799 );
4800 defparam d_toggle_counter_out_12_.operation_mode = "output";
4801 // @6:67
4802   stratix_io d_toggle_counter_out_11_ (
4803         .padio(d_toggle_counter[11]),
4804         .datain(vga_control_unit_toggle_counter_sig[11]),
4805         .oe(VCC),
4806         .outclk(GND),
4807         .outclkena(VCC),
4808         .inclk(GND),
4809         .inclkena(VCC),
4810         .areset(GND),
4811         .sreset(GND)
4812 );
4813 defparam d_toggle_counter_out_11_.operation_mode = "output";
4814 // @6:67
4815   stratix_io d_toggle_counter_out_10_ (
4816         .padio(d_toggle_counter[10]),
4817         .datain(vga_control_unit_toggle_counter_sig[10]),
4818         .oe(VCC),
4819         .outclk(GND),
4820         .outclkena(VCC),
4821         .inclk(GND),
4822         .inclkena(VCC),
4823         .areset(GND),
4824         .sreset(GND)
4825 );
4826 defparam d_toggle_counter_out_10_.operation_mode = "output";
4827 // @6:67
4828   stratix_io d_toggle_counter_out_9_ (
4829         .padio(d_toggle_counter[9]),
4830         .datain(vga_control_unit_toggle_counter_sig[9]),
4831         .oe(VCC),
4832         .outclk(GND),
4833         .outclkena(VCC),
4834         .inclk(GND),
4835         .inclkena(VCC),
4836         .areset(GND),
4837         .sreset(GND)
4838 );
4839 defparam d_toggle_counter_out_9_.operation_mode = "output";
4840 // @6:67
4841   stratix_io d_toggle_counter_out_8_ (
4842         .padio(d_toggle_counter[8]),
4843         .datain(vga_control_unit_toggle_counter_sig[8]),
4844         .oe(VCC),
4845         .outclk(GND),
4846         .outclkena(VCC),
4847         .inclk(GND),
4848         .inclkena(VCC),
4849         .areset(GND),
4850         .sreset(GND)
4851 );
4852 defparam d_toggle_counter_out_8_.operation_mode = "output";
4853 // @6:67
4854   stratix_io d_toggle_counter_out_7_ (
4855         .padio(d_toggle_counter[7]),
4856         .datain(vga_control_unit_toggle_counter_sig[7]),
4857         .oe(VCC),
4858         .outclk(GND),
4859         .outclkena(VCC),
4860         .inclk(GND),
4861         .inclkena(VCC),
4862         .areset(GND),
4863         .sreset(GND)
4864 );
4865 defparam d_toggle_counter_out_7_.operation_mode = "output";
4866 // @6:67
4867   stratix_io d_toggle_counter_out_6_ (
4868         .padio(d_toggle_counter[6]),
4869         .datain(vga_control_unit_toggle_counter_sig[6]),
4870         .oe(VCC),
4871         .outclk(GND),
4872         .outclkena(VCC),
4873         .inclk(GND),
4874         .inclkena(VCC),
4875         .areset(GND),
4876         .sreset(GND)
4877 );
4878 defparam d_toggle_counter_out_6_.operation_mode = "output";
4879 // @6:67
4880   stratix_io d_toggle_counter_out_5_ (
4881         .padio(d_toggle_counter[5]),
4882         .datain(vga_control_unit_toggle_counter_sig[5]),
4883         .oe(VCC),
4884         .outclk(GND),
4885         .outclkena(VCC),
4886         .inclk(GND),
4887         .inclkena(VCC),
4888         .areset(GND),
4889         .sreset(GND)
4890 );
4891 defparam d_toggle_counter_out_5_.operation_mode = "output";
4892 // @6:67
4893   stratix_io d_toggle_counter_out_4_ (
4894         .padio(d_toggle_counter[4]),
4895         .datain(vga_control_unit_toggle_counter_sig[4]),
4896         .oe(VCC),
4897         .outclk(GND),
4898         .outclkena(VCC),
4899         .inclk(GND),
4900         .inclkena(VCC),
4901         .areset(GND),
4902         .sreset(GND)
4903 );
4904 defparam d_toggle_counter_out_4_.operation_mode = "output";
4905 // @6:67
4906   stratix_io d_toggle_counter_out_3_ (
4907         .padio(d_toggle_counter[3]),
4908         .datain(vga_control_unit_toggle_counter_sig[3]),
4909         .oe(VCC),
4910         .outclk(GND),
4911         .outclkena(VCC),
4912         .inclk(GND),
4913         .inclkena(VCC),
4914         .areset(GND),
4915         .sreset(GND)
4916 );
4917 defparam d_toggle_counter_out_3_.operation_mode = "output";
4918 // @6:67
4919   stratix_io d_toggle_counter_out_2_ (
4920         .padio(d_toggle_counter[2]),
4921         .datain(vga_control_unit_toggle_counter_sig[2]),
4922         .oe(VCC),
4923         .outclk(GND),
4924         .outclkena(VCC),
4925         .inclk(GND),
4926         .inclkena(VCC),
4927         .areset(GND),
4928         .sreset(GND)
4929 );
4930 defparam d_toggle_counter_out_2_.operation_mode = "output";
4931 // @6:67
4932   stratix_io d_toggle_counter_out_1_ (
4933         .padio(d_toggle_counter[1]),
4934         .datain(vga_control_unit_toggle_counter_sig[1]),
4935         .oe(VCC),
4936         .outclk(GND),
4937         .outclkena(VCC),
4938         .inclk(GND),
4939         .inclkena(VCC),
4940         .areset(GND),
4941         .sreset(GND)
4942 );
4943 defparam d_toggle_counter_out_1_.operation_mode = "output";
4944 // @6:67
4945   stratix_io d_toggle_counter_out_0_ (
4946         .padio(d_toggle_counter[0]),
4947         .datain(vga_control_unit_toggle_counter_sig[0]),
4948         .oe(VCC),
4949         .outclk(GND),
4950         .outclkena(VCC),
4951         .inclk(GND),
4952         .inclkena(VCC),
4953         .areset(GND),
4954         .sreset(GND)
4955 );
4956 defparam d_toggle_counter_out_0_.operation_mode = "output";
4957 // @6:66
4958   stratix_io d_toggle_out (
4959         .padio(d_toggle),
4960         .datain(vga_control_unit_toggle_sig),
4961         .oe(VCC),
4962         .outclk(GND),
4963         .outclkena(VCC),
4964         .inclk(GND),
4965         .inclkena(VCC),
4966         .areset(GND),
4967         .sreset(GND)
4968 );
4969 defparam d_toggle_out.operation_mode = "output";
4970 // @6:65
4971   stratix_io d_state_clk_out (
4972         .padio(d_state_clk),
4973         .datain(G_33),
4974         .oe(VCC),
4975         .outclk(GND),
4976         .outclkena(VCC),
4977         .inclk(GND),
4978         .inclkena(VCC),
4979         .areset(GND),
4980         .sreset(GND)
4981 );
4982 defparam d_state_clk_out.operation_mode = "output";
4983 // @6:64
4984   stratix_io d_vsync_state_out_0_ (
4985         .padio(d_vsync_state[0]),
4986         .datain(vga_driver_unit_vsync_state[0]),
4987         .oe(VCC),
4988         .outclk(GND),
4989         .outclkena(VCC),
4990         .inclk(GND),
4991         .inclkena(VCC),
4992         .areset(GND),
4993         .sreset(GND)
4994 );
4995 defparam d_vsync_state_out_0_.operation_mode = "output";
4996 // @6:64
4997   stratix_io d_vsync_state_out_1_ (
4998         .padio(d_vsync_state[1]),
4999         .datain(vga_driver_unit_vsync_state[1]),
5000         .oe(VCC),
5001         .outclk(GND),
5002         .outclkena(VCC),
5003         .inclk(GND),
5004         .inclkena(VCC),
5005         .areset(GND),
5006         .sreset(GND)
5007 );
5008 defparam d_vsync_state_out_1_.operation_mode = "output";
5009 // @6:64
5010   stratix_io d_vsync_state_out_2_ (
5011         .padio(d_vsync_state[2]),
5012         .datain(vga_driver_unit_vsync_state[2]),
5013         .oe(VCC),
5014         .outclk(GND),
5015         .outclkena(VCC),
5016         .inclk(GND),
5017         .inclkena(VCC),
5018         .areset(GND),
5019         .sreset(GND)
5020 );
5021 defparam d_vsync_state_out_2_.operation_mode = "output";
5022 // @6:64
5023   stratix_io d_vsync_state_out_3_ (
5024         .padio(d_vsync_state[3]),
5025         .datain(vga_driver_unit_vsync_state[3]),
5026         .oe(VCC),
5027         .outclk(GND),
5028         .outclkena(VCC),
5029         .inclk(GND),
5030         .inclkena(VCC),
5031         .areset(GND),
5032         .sreset(GND)
5033 );
5034 defparam d_vsync_state_out_3_.operation_mode = "output";
5035 // @6:64
5036   stratix_io d_vsync_state_out_4_ (
5037         .padio(d_vsync_state[4]),
5038         .datain(vga_driver_unit_vsync_state[4]),
5039         .oe(VCC),
5040         .outclk(GND),
5041         .outclkena(VCC),
5042         .inclk(GND),
5043         .inclkena(VCC),
5044         .areset(GND),
5045         .sreset(GND)
5046 );
5047 defparam d_vsync_state_out_4_.operation_mode = "output";
5048 // @6:64
5049   stratix_io d_vsync_state_out_5_ (
5050         .padio(d_vsync_state[5]),
5051         .datain(vga_driver_unit_vsync_state[5]),
5052         .oe(VCC),
5053         .outclk(GND),
5054         .outclkena(VCC),
5055         .inclk(GND),
5056         .inclkena(VCC),
5057         .areset(GND),
5058         .sreset(GND)
5059 );
5060 defparam d_vsync_state_out_5_.operation_mode = "output";
5061 // @6:64
5062   stratix_io d_vsync_state_out_6_ (
5063         .padio(d_vsync_state[6]),
5064         .datain(vga_driver_unit_vsync_state[6]),
5065         .oe(VCC),
5066         .outclk(GND),
5067         .outclkena(VCC),
5068         .inclk(GND),
5069         .inclkena(VCC),
5070         .areset(GND),
5071         .sreset(GND)
5072 );
5073 defparam d_vsync_state_out_6_.operation_mode = "output";
5074 // @6:63
5075   stratix_io d_hsync_state_out_0_ (
5076         .padio(d_hsync_state[0]),
5077         .datain(vga_driver_unit_hsync_state[0]),
5078         .oe(VCC),
5079         .outclk(GND),
5080         .outclkena(VCC),
5081         .inclk(GND),
5082         .inclkena(VCC),
5083         .areset(GND),
5084         .sreset(GND)
5085 );
5086 defparam d_hsync_state_out_0_.operation_mode = "output";
5087 // @6:63
5088   stratix_io d_hsync_state_out_1_ (
5089         .padio(d_hsync_state[1]),
5090         .datain(vga_driver_unit_hsync_state[1]),
5091         .oe(VCC),
5092         .outclk(GND),
5093         .outclkena(VCC),
5094         .inclk(GND),
5095         .inclkena(VCC),
5096         .areset(GND),
5097         .sreset(GND)
5098 );
5099 defparam d_hsync_state_out_1_.operation_mode = "output";
5100 // @6:63
5101   stratix_io d_hsync_state_out_2_ (
5102         .padio(d_hsync_state[2]),
5103         .datain(vga_driver_unit_hsync_state[2]),
5104         .oe(VCC),
5105         .outclk(GND),
5106         .outclkena(VCC),
5107         .inclk(GND),
5108         .inclkena(VCC),
5109         .areset(GND),
5110         .sreset(GND)
5111 );
5112 defparam d_hsync_state_out_2_.operation_mode = "output";
5113 // @6:63
5114   stratix_io d_hsync_state_out_3_ (
5115         .padio(d_hsync_state[3]),
5116         .datain(vga_driver_unit_hsync_state[3]),
5117         .oe(VCC),
5118         .outclk(GND),
5119         .outclkena(VCC),
5120         .inclk(GND),
5121         .inclkena(VCC),
5122         .areset(GND),
5123         .sreset(GND)
5124 );
5125 defparam d_hsync_state_out_3_.operation_mode = "output";
5126 // @6:63
5127   stratix_io d_hsync_state_out_4_ (
5128         .padio(d_hsync_state[4]),
5129         .datain(vga_driver_unit_hsync_state[4]),
5130         .oe(VCC),
5131         .outclk(GND),
5132         .outclkena(VCC),
5133         .inclk(GND),
5134         .inclkena(VCC),
5135         .areset(GND),
5136         .sreset(GND)
5137 );
5138 defparam d_hsync_state_out_4_.operation_mode = "output";
5139 // @6:63
5140   stratix_io d_hsync_state_out_5_ (
5141         .padio(d_hsync_state[5]),
5142         .datain(vga_driver_unit_hsync_state[5]),
5143         .oe(VCC),
5144         .outclk(GND),
5145         .outclkena(VCC),
5146         .inclk(GND),
5147         .inclkena(VCC),
5148         .areset(GND),
5149         .sreset(GND)
5150 );
5151 defparam d_hsync_state_out_5_.operation_mode = "output";
5152 // @6:63
5153   stratix_io d_hsync_state_out_6_ (
5154         .padio(d_hsync_state[6]),
5155         .datain(vga_driver_unit_hsync_state[6]),
5156         .oe(VCC),
5157         .outclk(GND),
5158         .outclkena(VCC),
5159         .inclk(GND),
5160         .inclkena(VCC),
5161         .areset(GND),
5162         .sreset(GND)
5163 );
5164 defparam d_hsync_state_out_6_.operation_mode = "output";
5165 // @6:62
5166   stratix_io d_b_out (
5167         .padio(d_b),
5168         .datain(vga_control_unit_b),
5169         .oe(VCC),
5170         .outclk(GND),
5171         .outclkena(VCC),
5172         .inclk(GND),
5173         .inclkena(VCC),
5174         .areset(GND),
5175         .sreset(GND)
5176 );
5177 defparam d_b_out.operation_mode = "output";
5178 // @6:62
5179   stratix_io d_g_out (
5180         .padio(d_g),
5181         .datain(vga_control_unit_g),
5182         .oe(VCC),
5183         .outclk(GND),
5184         .outclkena(VCC),
5185         .inclk(GND),
5186         .inclkena(VCC),
5187         .areset(GND),
5188         .sreset(GND)
5189 );
5190 defparam d_g_out.operation_mode = "output";
5191 // @6:62
5192   stratix_io d_r_out (
5193         .padio(d_r),
5194         .datain(vga_control_unit_r),
5195         .oe(VCC),
5196         .outclk(GND),
5197         .outclkena(VCC),
5198         .inclk(GND),
5199         .inclkena(VCC),
5200         .areset(GND),
5201         .sreset(GND)
5202 );
5203 defparam d_r_out.operation_mode = "output";
5204 // @6:61
5205   stratix_io d_v_enable_out (
5206         .padio(d_v_enable),
5207         .datain(vga_driver_unit_v_enable_sig),
5208         .oe(VCC),
5209         .outclk(GND),
5210         .outclkena(VCC),
5211         .inclk(GND),
5212         .inclkena(VCC),
5213         .areset(GND),
5214         .sreset(GND)
5215 );
5216 defparam d_v_enable_out.operation_mode = "output";
5217 // @6:60
5218   stratix_io d_h_enable_out (
5219         .padio(d_h_enable),
5220         .datain(vga_driver_unit_h_enable_sig),
5221         .oe(VCC),
5222         .outclk(GND),
5223         .outclkena(VCC),
5224         .inclk(GND),
5225         .inclkena(VCC),
5226         .areset(GND),
5227         .sreset(GND)
5228 );
5229 defparam d_h_enable_out.operation_mode = "output";
5230 // @6:59
5231   stratix_io d_set_vsync_counter_out (
5232         .padio(d_set_vsync_counter),
5233         .datain(vga_driver_unit_d_set_vsync_counter),
5234         .oe(VCC),
5235         .outclk(GND),
5236         .outclkena(VCC),
5237         .inclk(GND),
5238         .inclkena(VCC),
5239         .areset(GND),
5240         .sreset(GND)
5241 );
5242 defparam d_set_vsync_counter_out.operation_mode = "output";
5243 // @6:59
5244   stratix_io d_set_hsync_counter_out (
5245         .padio(d_set_hsync_counter),
5246         .datain(vga_driver_unit_d_set_hsync_counter),
5247         .oe(VCC),
5248         .outclk(GND),
5249         .outclkena(VCC),
5250         .inclk(GND),
5251         .inclkena(VCC),
5252         .areset(GND),
5253         .sreset(GND)
5254 );
5255 defparam d_set_hsync_counter_out.operation_mode = "output";
5256 // @6:58
5257   stratix_io d_vsync_counter_out_9_ (
5258         .padio(d_vsync_counter[9]),
5259         .datain(vga_driver_unit_vsync_counter[9]),
5260         .oe(VCC),
5261         .outclk(GND),
5262         .outclkena(VCC),
5263         .inclk(GND),
5264         .inclkena(VCC),
5265         .areset(GND),
5266         .sreset(GND)
5267 );
5268 defparam d_vsync_counter_out_9_.operation_mode = "output";
5269 // @6:58
5270   stratix_io d_vsync_counter_out_8_ (
5271         .padio(d_vsync_counter[8]),
5272         .datain(vga_driver_unit_vsync_counter[8]),
5273         .oe(VCC),
5274         .outclk(GND),
5275         .outclkena(VCC),
5276         .inclk(GND),
5277         .inclkena(VCC),
5278         .areset(GND),
5279         .sreset(GND)
5280 );
5281 defparam d_vsync_counter_out_8_.operation_mode = "output";
5282 // @6:58
5283   stratix_io d_vsync_counter_out_7_ (
5284         .padio(d_vsync_counter[7]),
5285         .datain(vga_driver_unit_vsync_counter[7]),
5286         .oe(VCC),
5287         .outclk(GND),
5288         .outclkena(VCC),
5289         .inclk(GND),
5290         .inclkena(VCC),
5291         .areset(GND),
5292         .sreset(GND)
5293 );
5294 defparam d_vsync_counter_out_7_.operation_mode = "output";
5295 // @6:58
5296   stratix_io d_vsync_counter_out_6_ (
5297         .padio(d_vsync_counter[6]),
5298         .datain(vga_driver_unit_vsync_counter[6]),
5299         .oe(VCC),
5300         .outclk(GND),
5301         .outclkena(VCC),
5302         .inclk(GND),
5303         .inclkena(VCC),
5304         .areset(GND),
5305         .sreset(GND)
5306 );
5307 defparam d_vsync_counter_out_6_.operation_mode = "output";
5308 // @6:58
5309   stratix_io d_vsync_counter_out_5_ (
5310         .padio(d_vsync_counter[5]),
5311         .datain(vga_driver_unit_vsync_counter[5]),
5312         .oe(VCC),
5313         .outclk(GND),
5314         .outclkena(VCC),
5315         .inclk(GND),
5316         .inclkena(VCC),
5317         .areset(GND),
5318         .sreset(GND)
5319 );
5320 defparam d_vsync_counter_out_5_.operation_mode = "output";
5321 // @6:58
5322   stratix_io d_vsync_counter_out_4_ (
5323         .padio(d_vsync_counter[4]),
5324         .datain(vga_driver_unit_vsync_counter[4]),
5325         .oe(VCC),
5326         .outclk(GND),
5327         .outclkena(VCC),
5328         .inclk(GND),
5329         .inclkena(VCC),
5330         .areset(GND),
5331         .sreset(GND)
5332 );
5333 defparam d_vsync_counter_out_4_.operation_mode = "output";
5334 // @6:58
5335   stratix_io d_vsync_counter_out_3_ (
5336         .padio(d_vsync_counter[3]),
5337         .datain(vga_driver_unit_vsync_counter[3]),
5338         .oe(VCC),
5339         .outclk(GND),
5340         .outclkena(VCC),
5341         .inclk(GND),
5342         .inclkena(VCC),
5343         .areset(GND),
5344         .sreset(GND)
5345 );
5346 defparam d_vsync_counter_out_3_.operation_mode = "output";
5347 // @6:58
5348   stratix_io d_vsync_counter_out_2_ (
5349         .padio(d_vsync_counter[2]),
5350         .datain(vga_driver_unit_vsync_counter[2]),
5351         .oe(VCC),
5352         .outclk(GND),
5353         .outclkena(VCC),
5354         .inclk(GND),
5355         .inclkena(VCC),
5356         .areset(GND),
5357         .sreset(GND)
5358 );
5359 defparam d_vsync_counter_out_2_.operation_mode = "output";
5360 // @6:58
5361   stratix_io d_vsync_counter_out_1_ (
5362         .padio(d_vsync_counter[1]),
5363         .datain(vga_driver_unit_vsync_counter[1]),
5364         .oe(VCC),
5365         .outclk(GND),
5366         .outclkena(VCC),
5367         .inclk(GND),
5368         .inclkena(VCC),
5369         .areset(GND),
5370         .sreset(GND)
5371 );
5372 defparam d_vsync_counter_out_1_.operation_mode = "output";
5373 // @6:58
5374   stratix_io d_vsync_counter_out_0_ (
5375         .padio(d_vsync_counter[0]),
5376         .datain(vga_driver_unit_vsync_counter[0]),
5377         .oe(VCC),
5378         .outclk(GND),
5379         .outclkena(VCC),
5380         .inclk(GND),
5381         .inclkena(VCC),
5382         .areset(GND),
5383         .sreset(GND)
5384 );
5385 defparam d_vsync_counter_out_0_.operation_mode = "output";
5386 // @6:57
5387   stratix_io d_hsync_counter_out_9_ (
5388         .padio(d_hsync_counter[9]),
5389         .datain(vga_driver_unit_hsync_counter[9]),
5390         .oe(VCC),
5391         .outclk(GND),
5392         .outclkena(VCC),
5393         .inclk(GND),
5394         .inclkena(VCC),
5395         .areset(GND),
5396         .sreset(GND)
5397 );
5398 defparam d_hsync_counter_out_9_.operation_mode = "output";
5399 // @6:57
5400   stratix_io d_hsync_counter_out_8_ (
5401         .padio(d_hsync_counter[8]),
5402         .datain(vga_driver_unit_hsync_counter[8]),
5403         .oe(VCC),
5404         .outclk(GND),
5405         .outclkena(VCC),
5406         .inclk(GND),
5407         .inclkena(VCC),
5408         .areset(GND),
5409         .sreset(GND)
5410 );
5411 defparam d_hsync_counter_out_8_.operation_mode = "output";
5412 // @6:57
5413   stratix_io d_hsync_counter_out_7_ (
5414         .padio(d_hsync_counter[7]),
5415         .datain(vga_driver_unit_hsync_counter[7]),
5416         .oe(VCC),
5417         .outclk(GND),
5418         .outclkena(VCC),
5419         .inclk(GND),
5420         .inclkena(VCC),
5421         .areset(GND),
5422         .sreset(GND)
5423 );
5424 defparam d_hsync_counter_out_7_.operation_mode = "output";
5425 // @6:57
5426   stratix_io d_hsync_counter_out_6_ (
5427         .padio(d_hsync_counter[6]),
5428         .datain(vga_driver_unit_hsync_counter[6]),
5429         .oe(VCC),
5430         .outclk(GND),
5431         .outclkena(VCC),
5432         .inclk(GND),
5433         .inclkena(VCC),
5434         .areset(GND),
5435         .sreset(GND)
5436 );
5437 defparam d_hsync_counter_out_6_.operation_mode = "output";
5438 // @6:57
5439   stratix_io d_hsync_counter_out_5_ (
5440         .padio(d_hsync_counter[5]),
5441         .datain(vga_driver_unit_hsync_counter[5]),
5442         .oe(VCC),
5443         .outclk(GND),
5444         .outclkena(VCC),
5445         .inclk(GND),
5446         .inclkena(VCC),
5447         .areset(GND),
5448         .sreset(GND)
5449 );
5450 defparam d_hsync_counter_out_5_.operation_mode = "output";
5451 // @6:57
5452   stratix_io d_hsync_counter_out_4_ (
5453         .padio(d_hsync_counter[4]),
5454         .datain(vga_driver_unit_hsync_counter[4]),
5455         .oe(VCC),
5456         .outclk(GND),
5457         .outclkena(VCC),
5458         .inclk(GND),
5459         .inclkena(VCC),
5460         .areset(GND),
5461         .sreset(GND)
5462 );
5463 defparam d_hsync_counter_out_4_.operation_mode = "output";
5464 // @6:57
5465   stratix_io d_hsync_counter_out_3_ (
5466         .padio(d_hsync_counter[3]),
5467         .datain(vga_driver_unit_hsync_counter[3]),
5468         .oe(VCC),
5469         .outclk(GND),
5470         .outclkena(VCC),
5471         .inclk(GND),
5472         .inclkena(VCC),
5473         .areset(GND),
5474         .sreset(GND)
5475 );
5476 defparam d_hsync_counter_out_3_.operation_mode = "output";
5477 // @6:57
5478   stratix_io d_hsync_counter_out_2_ (
5479         .padio(d_hsync_counter[2]),
5480         .datain(vga_driver_unit_hsync_counter[2]),
5481         .oe(VCC),
5482         .outclk(GND),
5483         .outclkena(VCC),
5484         .inclk(GND),
5485         .inclkena(VCC),
5486         .areset(GND),
5487         .sreset(GND)
5488 );
5489 defparam d_hsync_counter_out_2_.operation_mode = "output";
5490 // @6:57
5491   stratix_io d_hsync_counter_out_1_ (
5492         .padio(d_hsync_counter[1]),
5493         .datain(vga_driver_unit_hsync_counter[1]),
5494         .oe(VCC),
5495         .outclk(GND),
5496         .outclkena(VCC),
5497         .inclk(GND),
5498         .inclkena(VCC),
5499         .areset(GND),
5500         .sreset(GND)
5501 );
5502 defparam d_hsync_counter_out_1_.operation_mode = "output";
5503 // @6:57
5504   stratix_io d_hsync_counter_out_0_ (
5505         .padio(d_hsync_counter[0]),
5506         .datain(vga_driver_unit_hsync_counter[0]),
5507         .oe(VCC),
5508         .outclk(GND),
5509         .outclkena(VCC),
5510         .inclk(GND),
5511         .inclkena(VCC),
5512         .areset(GND),
5513         .sreset(GND)
5514 );
5515 defparam d_hsync_counter_out_0_.operation_mode = "output";
5516 // @6:56
5517   stratix_io d_set_line_counter_out (
5518         .padio(d_set_line_counter),
5519         .datain(vga_driver_unit_vsync_state[1]),
5520         .oe(VCC),
5521         .outclk(GND),
5522         .outclkena(VCC),
5523         .inclk(GND),
5524         .inclkena(VCC),
5525         .areset(GND),
5526         .sreset(GND)
5527 );
5528 defparam d_set_line_counter_out.operation_mode = "output";
5529 // @6:56
5530   stratix_io d_set_column_counter_out (
5531         .padio(d_set_column_counter),
5532         .datain(vga_driver_unit_hsync_state[1]),
5533         .oe(VCC),
5534         .outclk(GND),
5535         .outclkena(VCC),
5536         .inclk(GND),
5537         .inclkena(VCC),
5538         .areset(GND),
5539         .sreset(GND)
5540 );
5541 defparam d_set_column_counter_out.operation_mode = "output";
5542 // @6:55
5543   stratix_io d_line_counter_out_8_ (
5544         .padio(d_line_counter[8]),
5545         .datain(vga_driver_unit_line_counter_sig[8]),
5546         .oe(VCC),
5547         .outclk(GND),
5548         .outclkena(VCC),
5549         .inclk(GND),
5550         .inclkena(VCC),
5551         .areset(GND),
5552         .sreset(GND)
5553 );
5554 defparam d_line_counter_out_8_.operation_mode = "output";
5555 // @6:55
5556   stratix_io d_line_counter_out_7_ (
5557         .padio(d_line_counter[7]),
5558         .datain(vga_driver_unit_line_counter_sig[7]),
5559         .oe(VCC),
5560         .outclk(GND),
5561         .outclkena(VCC),
5562         .inclk(GND),
5563         .inclkena(VCC),
5564         .areset(GND),
5565         .sreset(GND)
5566 );
5567 defparam d_line_counter_out_7_.operation_mode = "output";
5568 // @6:55
5569   stratix_io d_line_counter_out_6_ (
5570         .padio(d_line_counter[6]),
5571         .datain(vga_driver_unit_line_counter_sig[6]),
5572         .oe(VCC),
5573         .outclk(GND),
5574         .outclkena(VCC),
5575         .inclk(GND),
5576         .inclkena(VCC),
5577         .areset(GND),
5578         .sreset(GND)
5579 );
5580 defparam d_line_counter_out_6_.operation_mode = "output";
5581 // @6:55
5582   stratix_io d_line_counter_out_5_ (
5583         .padio(d_line_counter[5]),
5584         .datain(vga_driver_unit_line_counter_sig[5]),
5585         .oe(VCC),
5586         .outclk(GND),
5587         .outclkena(VCC),
5588         .inclk(GND),
5589         .inclkena(VCC),
5590         .areset(GND),
5591         .sreset(GND)
5592 );
5593 defparam d_line_counter_out_5_.operation_mode = "output";
5594 // @6:55
5595   stratix_io d_line_counter_out_4_ (
5596         .padio(d_line_counter[4]),
5597         .datain(vga_driver_unit_line_counter_sig[4]),
5598         .oe(VCC),
5599         .outclk(GND),
5600         .outclkena(VCC),
5601         .inclk(GND),
5602         .inclkena(VCC),
5603         .areset(GND),
5604         .sreset(GND)
5605 );
5606 defparam d_line_counter_out_4_.operation_mode = "output";
5607 // @6:55
5608   stratix_io d_line_counter_out_3_ (
5609         .padio(d_line_counter[3]),
5610         .datain(vga_driver_unit_line_counter_sig[3]),
5611         .oe(VCC),
5612         .outclk(GND),
5613         .outclkena(VCC),
5614         .inclk(GND),
5615         .inclkena(VCC),
5616         .areset(GND),
5617         .sreset(GND)
5618 );
5619 defparam d_line_counter_out_3_.operation_mode = "output";
5620 // @6:55
5621   stratix_io d_line_counter_out_2_ (
5622         .padio(d_line_counter[2]),
5623         .datain(vga_driver_unit_line_counter_sig[2]),
5624         .oe(VCC),
5625         .outclk(GND),
5626         .outclkena(VCC),
5627         .inclk(GND),
5628         .inclkena(VCC),
5629         .areset(GND),
5630         .sreset(GND)
5631 );
5632 defparam d_line_counter_out_2_.operation_mode = "output";
5633 // @6:55
5634   stratix_io d_line_counter_out_1_ (
5635         .padio(d_line_counter[1]),
5636         .datain(vga_driver_unit_line_counter_sig[1]),
5637         .oe(VCC),
5638         .outclk(GND),
5639         .outclkena(VCC),
5640         .inclk(GND),
5641         .inclkena(VCC),
5642         .areset(GND),
5643         .sreset(GND)
5644 );
5645 defparam d_line_counter_out_1_.operation_mode = "output";
5646 // @6:55
5647   stratix_io d_line_counter_out_0_ (
5648         .padio(d_line_counter[0]),
5649         .datain(vga_driver_unit_line_counter_sig[0]),
5650         .oe(VCC),
5651         .outclk(GND),
5652         .outclkena(VCC),
5653         .inclk(GND),
5654         .inclkena(VCC),
5655         .areset(GND),
5656         .sreset(GND)
5657 );
5658 defparam d_line_counter_out_0_.operation_mode = "output";
5659 // @6:54
5660   stratix_io d_column_counter_out_9_ (
5661         .padio(d_column_counter[9]),
5662         .datain(vga_driver_unit_column_counter_sig[9]),
5663         .oe(VCC),
5664         .outclk(GND),
5665         .outclkena(VCC),
5666         .inclk(GND),
5667         .inclkena(VCC),
5668         .areset(GND),
5669         .sreset(GND)
5670 );
5671 defparam d_column_counter_out_9_.operation_mode = "output";
5672 // @6:54
5673   stratix_io d_column_counter_out_8_ (
5674         .padio(d_column_counter[8]),
5675         .datain(vga_driver_unit_column_counter_sig[8]),
5676         .oe(VCC),
5677         .outclk(GND),
5678         .outclkena(VCC),
5679         .inclk(GND),
5680         .inclkena(VCC),
5681         .areset(GND),
5682         .sreset(GND)
5683 );
5684 defparam d_column_counter_out_8_.operation_mode = "output";
5685 // @6:54
5686   stratix_io d_column_counter_out_7_ (
5687         .padio(d_column_counter[7]),
5688         .datain(vga_driver_unit_column_counter_sig[7]),
5689         .oe(VCC),
5690         .outclk(GND),
5691         .outclkena(VCC),
5692         .inclk(GND),
5693         .inclkena(VCC),
5694         .areset(GND),
5695         .sreset(GND)
5696 );
5697 defparam d_column_counter_out_7_.operation_mode = "output";
5698 // @6:54
5699   stratix_io d_column_counter_out_6_ (
5700         .padio(d_column_counter[6]),
5701         .datain(vga_driver_unit_column_counter_sig[6]),
5702         .oe(VCC),
5703         .outclk(GND),
5704         .outclkena(VCC),
5705         .inclk(GND),
5706         .inclkena(VCC),
5707         .areset(GND),
5708         .sreset(GND)
5709 );
5710 defparam d_column_counter_out_6_.operation_mode = "output";
5711 // @6:54
5712   stratix_io d_column_counter_out_5_ (
5713         .padio(d_column_counter[5]),
5714         .datain(vga_driver_unit_column_counter_sig[5]),
5715         .oe(VCC),
5716         .outclk(GND),
5717         .outclkena(VCC),
5718         .inclk(GND),
5719         .inclkena(VCC),
5720         .areset(GND),
5721         .sreset(GND)
5722 );
5723 defparam d_column_counter_out_5_.operation_mode = "output";
5724 // @6:54
5725   stratix_io d_column_counter_out_4_ (
5726         .padio(d_column_counter[4]),
5727         .datain(vga_driver_unit_column_counter_sig[4]),
5728         .oe(VCC),
5729         .outclk(GND),
5730         .outclkena(VCC),
5731         .inclk(GND),
5732         .inclkena(VCC),
5733         .areset(GND),
5734         .sreset(GND)
5735 );
5736 defparam d_column_counter_out_4_.operation_mode = "output";
5737 // @6:54
5738   stratix_io d_column_counter_out_3_ (
5739         .padio(d_column_counter[3]),
5740         .datain(vga_driver_unit_column_counter_sig[3]),
5741         .oe(VCC),
5742         .outclk(GND),
5743         .outclkena(VCC),
5744         .inclk(GND),
5745         .inclkena(VCC),
5746         .areset(GND),
5747         .sreset(GND)
5748 );
5749 defparam d_column_counter_out_3_.operation_mode = "output";
5750 // @6:54
5751   stratix_io d_column_counter_out_2_ (
5752         .padio(d_column_counter[2]),
5753         .datain(vga_driver_unit_column_counter_sig[2]),
5754         .oe(VCC),
5755         .outclk(GND),
5756         .outclkena(VCC),
5757         .inclk(GND),
5758         .inclkena(VCC),
5759         .areset(GND),
5760         .sreset(GND)
5761 );
5762 defparam d_column_counter_out_2_.operation_mode = "output";
5763 // @6:54
5764   stratix_io d_column_counter_out_1_ (
5765         .padio(d_column_counter[1]),
5766         .datain(vga_driver_unit_column_counter_sig[1]),
5767         .oe(VCC),
5768         .outclk(GND),
5769         .outclkena(VCC),
5770         .inclk(GND),
5771         .inclkena(VCC),
5772         .areset(GND),
5773         .sreset(GND)
5774 );
5775 defparam d_column_counter_out_1_.operation_mode = "output";
5776 // @6:54
5777   stratix_io d_column_counter_out_0_ (
5778         .padio(d_column_counter[0]),
5779         .datain(vga_driver_unit_column_counter_sig[0]),
5780         .oe(VCC),
5781         .outclk(GND),
5782         .outclkena(VCC),
5783         .inclk(GND),
5784         .inclkena(VCC),
5785         .areset(GND),
5786         .sreset(GND)
5787 );
5788 defparam d_column_counter_out_0_.operation_mode = "output";
5789 // @6:53
5790   stratix_io d_vsync_out (
5791         .padio(d_vsync),
5792         .datain(vga_driver_unit_v_sync),
5793         .oe(VCC),
5794         .outclk(GND),
5795         .outclkena(VCC),
5796         .inclk(GND),
5797         .inclkena(VCC),
5798         .areset(GND),
5799         .sreset(GND)
5800 );
5801 defparam d_vsync_out.operation_mode = "output";
5802 // @6:53
5803   stratix_io d_hsync_out (
5804         .padio(d_hsync),
5805         .datain(vga_driver_unit_h_sync),
5806         .oe(VCC),
5807         .outclk(GND),
5808         .outclkena(VCC),
5809         .inclk(GND),
5810         .inclkena(VCC),
5811         .areset(GND),
5812         .sreset(GND)
5813 );
5814 defparam d_hsync_out.operation_mode = "output";
5815 // @6:51
5816   stratix_io seven_seg_pin_tri_13_ (
5817         .padio(seven_seg_pin[13]),
5818         .datain(VCC),
5819         .oe(VCC),
5820         .outclk(GND),
5821         .outclkena(VCC),
5822         .inclk(GND),
5823         .inclkena(VCC),
5824         .areset(GND),
5825         .sreset(GND)
5826 );
5827 defparam seven_seg_pin_tri_13_.operation_mode = "output";
5828 // @6:51
5829   stratix_io seven_seg_pin_out_12_ (
5830         .padio(seven_seg_pin[12]),
5831         .datain(DELAY_RESET_next_un6_dly_counter_0_x),
5832         .oe(VCC),
5833         .outclk(GND),
5834         .outclkena(VCC),
5835         .inclk(GND),
5836         .inclkena(VCC),
5837         .areset(GND),
5838         .sreset(GND)
5839 );
5840 defparam seven_seg_pin_out_12_.operation_mode = "output";
5841 // @6:51
5842   stratix_io seven_seg_pin_out_11_ (
5843         .padio(seven_seg_pin[11]),
5844         .datain(DELAY_RESET_next_un6_dly_counter_0_x),
5845         .oe(VCC),
5846         .outclk(GND),
5847         .outclkena(VCC),
5848         .inclk(GND),
5849         .inclkena(VCC),
5850         .areset(GND),
5851         .sreset(GND)
5852 );
5853 defparam seven_seg_pin_out_11_.operation_mode = "output";
5854 // @6:51
5855   stratix_io seven_seg_pin_out_10_ (
5856         .padio(seven_seg_pin[10]),
5857         .datain(DELAY_RESET_next_un6_dly_counter_0_x),
5858         .oe(VCC),
5859         .outclk(GND),
5860         .outclkena(VCC),
5861         .inclk(GND),
5862         .inclkena(VCC),
5863         .areset(GND),
5864         .sreset(GND)
5865 );
5866 defparam seven_seg_pin_out_10_.operation_mode = "output";
5867 // @6:51
5868   stratix_io seven_seg_pin_out_9_ (
5869         .padio(seven_seg_pin[9]),
5870         .datain(DELAY_RESET_next_un6_dly_counter_0_x),
5871         .oe(VCC),
5872         .outclk(GND),
5873         .outclkena(VCC),
5874         .inclk(GND),
5875         .inclkena(VCC),
5876         .areset(GND),
5877         .sreset(GND)
5878 );
5879 defparam seven_seg_pin_out_9_.operation_mode = "output";
5880 // @6:51
5881   stratix_io seven_seg_pin_out_8_ (
5882         .padio(seven_seg_pin[8]),
5883         .datain(DELAY_RESET_next_un6_dly_counter_0_x),
5884         .oe(VCC),
5885         .outclk(GND),
5886         .outclkena(VCC),
5887         .inclk(GND),
5888         .inclkena(VCC),
5889         .areset(GND),
5890         .sreset(GND)
5891 );
5892 defparam seven_seg_pin_out_8_.operation_mode = "output";
5893 // @6:51
5894   stratix_io seven_seg_pin_out_7_ (
5895         .padio(seven_seg_pin[7]),
5896         .datain(DELAY_RESET_next_un6_dly_counter_0_x),
5897         .oe(VCC),
5898         .outclk(GND),
5899         .outclkena(VCC),
5900         .inclk(GND),
5901         .inclkena(VCC),
5902         .areset(GND),
5903         .sreset(GND)
5904 );
5905 defparam seven_seg_pin_out_7_.operation_mode = "output";
5906 // @6:51
5907   stratix_io seven_seg_pin_tri_6_ (
5908         .padio(seven_seg_pin[6]),
5909         .datain(VCC),
5910         .oe(VCC),
5911         .outclk(GND),
5912         .outclkena(VCC),
5913         .inclk(GND),
5914         .inclkena(VCC),
5915         .areset(GND),
5916         .sreset(GND)
5917 );
5918 defparam seven_seg_pin_tri_6_.operation_mode = "output";
5919 // @6:51
5920   stratix_io seven_seg_pin_tri_5_ (
5921         .padio(seven_seg_pin[5]),
5922         .datain(VCC),
5923         .oe(VCC),
5924         .outclk(GND),
5925         .outclkena(VCC),
5926         .inclk(GND),
5927         .inclkena(VCC),
5928         .areset(GND),
5929         .sreset(GND)
5930 );
5931 defparam seven_seg_pin_tri_5_.operation_mode = "output";
5932 // @6:51
5933   stratix_io seven_seg_pin_tri_4_ (
5934         .padio(seven_seg_pin[4]),
5935         .datain(VCC),
5936         .oe(VCC),
5937         .outclk(GND),
5938         .outclkena(VCC),
5939         .inclk(GND),
5940         .inclkena(VCC),
5941         .areset(GND),
5942         .sreset(GND)
5943 );
5944 defparam seven_seg_pin_tri_4_.operation_mode = "output";
5945 // @6:51
5946   stratix_io seven_seg_pin_tri_3_ (
5947         .padio(seven_seg_pin[3]),
5948         .datain(VCC),
5949         .oe(VCC),
5950         .outclk(GND),
5951         .outclkena(VCC),
5952         .inclk(GND),
5953         .inclkena(VCC),
5954         .areset(GND),
5955         .sreset(GND)
5956 );
5957 defparam seven_seg_pin_tri_3_.operation_mode = "output";
5958 // @6:51
5959   stratix_io seven_seg_pin_out_2_ (
5960         .padio(seven_seg_pin[2]),
5961         .datain(DELAY_RESET_next_un6_dly_counter_0_x),
5962         .oe(VCC),
5963         .outclk(GND),
5964         .outclkena(VCC),
5965         .inclk(GND),
5966         .inclkena(VCC),
5967         .areset(GND),
5968         .sreset(GND)
5969 );
5970 defparam seven_seg_pin_out_2_.operation_mode = "output";
5971 // @6:51
5972   stratix_io seven_seg_pin_out_1_ (
5973         .padio(seven_seg_pin[1]),
5974         .datain(DELAY_RESET_next_un6_dly_counter_0_x),
5975         .oe(VCC),
5976         .outclk(GND),
5977         .outclkena(VCC),
5978         .inclk(GND),
5979         .inclkena(VCC),
5980         .areset(GND),
5981         .sreset(GND)
5982 );
5983 defparam seven_seg_pin_out_1_.operation_mode = "output";
5984 // @6:51
5985   stratix_io seven_seg_pin_tri_0_ (
5986         .padio(seven_seg_pin[0]),
5987         .datain(VCC),
5988         .oe(VCC),
5989         .outclk(GND),
5990         .outclkena(VCC),
5991         .inclk(GND),
5992         .inclkena(VCC),
5993         .areset(GND),
5994         .sreset(GND)
5995 );
5996 defparam seven_seg_pin_tri_0_.operation_mode = "output";
5997 // @6:49
5998   stratix_io vsync_pin_out (
5999         .padio(vsync_pin),
6000         .datain(vga_driver_unit_v_sync),
6001         .oe(VCC),
6002         .outclk(GND),
6003         .outclkena(VCC),
6004         .inclk(GND),
6005         .inclkena(VCC),
6006         .areset(GND),
6007         .sreset(GND)
6008 );
6009 defparam vsync_pin_out.operation_mode = "output";
6010 // @6:48
6011   stratix_io hsync_pin_out (
6012         .padio(hsync_pin),
6013         .datain(vga_driver_unit_h_sync),
6014         .oe(VCC),
6015         .outclk(GND),
6016         .outclkena(VCC),
6017         .inclk(GND),
6018         .inclkena(VCC),
6019         .areset(GND),
6020         .sreset(GND)
6021 );
6022 defparam hsync_pin_out.operation_mode = "output";
6023 // @6:47
6024   stratix_io b1_pin_out (
6025         .padio(b1_pin),
6026         .datain(vga_control_unit_b),
6027         .oe(VCC),
6028         .outclk(GND),
6029         .outclkena(VCC),
6030         .inclk(GND),
6031         .inclkena(VCC),
6032         .areset(GND),
6033         .sreset(GND)
6034 );
6035 defparam b1_pin_out.operation_mode = "output";
6036 // @6:47
6037   stratix_io b0_pin_out (
6038         .padio(b0_pin),
6039         .datain(vga_control_unit_b),
6040         .oe(VCC),
6041         .outclk(GND),
6042         .outclkena(VCC),
6043         .inclk(GND),
6044         .inclkena(VCC),
6045         .areset(GND),
6046         .sreset(GND)
6047 );
6048 defparam b0_pin_out.operation_mode = "output";
6049 // @6:46
6050   stratix_io g2_pin_out (
6051         .padio(g2_pin),
6052         .datain(vga_control_unit_g),
6053         .oe(VCC),
6054         .outclk(GND),
6055         .outclkena(VCC),
6056         .inclk(GND),
6057         .inclkena(VCC),
6058         .areset(GND),
6059         .sreset(GND)
6060 );
6061 defparam g2_pin_out.operation_mode = "output";
6062 // @6:46
6063   stratix_io g1_pin_out (
6064         .padio(g1_pin),
6065         .datain(vga_control_unit_g),
6066         .oe(VCC),
6067         .outclk(GND),
6068         .outclkena(VCC),
6069         .inclk(GND),
6070         .inclkena(VCC),
6071         .areset(GND),
6072         .sreset(GND)
6073 );
6074 defparam g1_pin_out.operation_mode = "output";
6075 // @6:46
6076   stratix_io g0_pin_out (
6077         .padio(g0_pin),
6078         .datain(vga_control_unit_g),
6079         .oe(VCC),
6080         .outclk(GND),
6081         .outclkena(VCC),
6082         .inclk(GND),
6083         .inclkena(VCC),
6084         .areset(GND),
6085         .sreset(GND)
6086 );
6087 defparam g0_pin_out.operation_mode = "output";
6088 // @6:45
6089   stratix_io r2_pin_out (
6090         .padio(r2_pin),
6091         .datain(vga_control_unit_r),
6092         .oe(VCC),
6093         .outclk(GND),
6094         .outclkena(VCC),
6095         .inclk(GND),
6096         .inclkena(VCC),
6097         .areset(GND),
6098         .sreset(GND)
6099 );
6100 defparam r2_pin_out.operation_mode = "output";
6101 // @6:45
6102   stratix_io r1_pin_out (
6103         .padio(r1_pin),
6104         .datain(vga_control_unit_r),
6105         .oe(VCC),
6106         .outclk(GND),
6107         .outclkena(VCC),
6108         .inclk(GND),
6109         .inclkena(VCC),
6110         .areset(GND),
6111         .sreset(GND)
6112 );
6113 defparam r1_pin_out.operation_mode = "output";
6114 // @6:45
6115   stratix_io r0_pin_out (
6116         .padio(r0_pin),
6117         .datain(vga_control_unit_r),
6118         .oe(VCC),
6119         .outclk(GND),
6120         .outclkena(VCC),
6121         .inclk(GND),
6122         .inclkena(VCC),
6123         .areset(GND),
6124         .sreset(GND)
6125 );
6126 defparam r0_pin_out.operation_mode = "output";
6127 //@6:42
6128 // @10:161
6129   vga_driver vga_driver_unit (
6130         .line_counter_sig_0(vga_driver_unit_line_counter_sig[0]),
6131         .line_counter_sig_1(vga_driver_unit_line_counter_sig[1]),
6132         .line_counter_sig_2(vga_driver_unit_line_counter_sig[2]),
6133         .line_counter_sig_3(vga_driver_unit_line_counter_sig[3]),
6134         .line_counter_sig_4(vga_driver_unit_line_counter_sig[4]),
6135         .line_counter_sig_5(vga_driver_unit_line_counter_sig[5]),
6136         .line_counter_sig_6(vga_driver_unit_line_counter_sig[6]),
6137         .line_counter_sig_7(vga_driver_unit_line_counter_sig[7]),
6138         .line_counter_sig_8(vga_driver_unit_line_counter_sig[8]),
6139         .dly_counter_1(dly_counter[1]),
6140         .dly_counter_0(dly_counter[0]),
6141         .vsync_state_2(vga_driver_unit_vsync_state[2]),
6142         .vsync_state_5(vga_driver_unit_vsync_state[5]),
6143         .vsync_state_3(vga_driver_unit_vsync_state[3]),
6144         .vsync_state_6(vga_driver_unit_vsync_state[6]),
6145         .vsync_state_4(vga_driver_unit_vsync_state[4]),
6146         .vsync_state_1(vga_driver_unit_vsync_state[1]),
6147         .vsync_state_0(vga_driver_unit_vsync_state[0]),
6148         .hsync_state_2(vga_driver_unit_hsync_state[2]),
6149         .hsync_state_4(vga_driver_unit_hsync_state[4]),
6150         .hsync_state_0(vga_driver_unit_hsync_state[0]),
6151         .hsync_state_5(vga_driver_unit_hsync_state[5]),
6152         .hsync_state_1(vga_driver_unit_hsync_state[1]),
6153         .hsync_state_3(vga_driver_unit_hsync_state[3]),
6154         .hsync_state_6(vga_driver_unit_hsync_state[6]),
6155         .column_counter_sig_0(vga_driver_unit_column_counter_sig[0]),
6156         .column_counter_sig_1(vga_driver_unit_column_counter_sig[1]),
6157         .column_counter_sig_2(vga_driver_unit_column_counter_sig[2]),
6158         .column_counter_sig_3(vga_driver_unit_column_counter_sig[3]),
6159         .column_counter_sig_4(vga_driver_unit_column_counter_sig[4]),
6160         .column_counter_sig_5(vga_driver_unit_column_counter_sig[5]),
6161         .column_counter_sig_6(vga_driver_unit_column_counter_sig[6]),
6162         .column_counter_sig_7(vga_driver_unit_column_counter_sig[7]),
6163         .column_counter_sig_8(vga_driver_unit_column_counter_sig[8]),
6164         .column_counter_sig_9(vga_driver_unit_column_counter_sig[9]),
6165         .vsync_counter_9(vga_driver_unit_vsync_counter[9]),
6166         .vsync_counter_8(vga_driver_unit_vsync_counter[8]),
6167         .vsync_counter_7(vga_driver_unit_vsync_counter[7]),
6168         .vsync_counter_6(vga_driver_unit_vsync_counter[6]),
6169         .vsync_counter_5(vga_driver_unit_vsync_counter[5]),
6170         .vsync_counter_4(vga_driver_unit_vsync_counter[4]),
6171         .vsync_counter_3(vga_driver_unit_vsync_counter[3]),
6172         .vsync_counter_2(vga_driver_unit_vsync_counter[2]),
6173         .vsync_counter_1(vga_driver_unit_vsync_counter[1]),
6174         .vsync_counter_0(vga_driver_unit_vsync_counter[0]),
6175         .hsync_counter_9(vga_driver_unit_hsync_counter[9]),
6176         .hsync_counter_8(vga_driver_unit_hsync_counter[8]),
6177         .hsync_counter_7(vga_driver_unit_hsync_counter[7]),
6178         .hsync_counter_6(vga_driver_unit_hsync_counter[6]),
6179         .hsync_counter_5(vga_driver_unit_hsync_counter[5]),
6180         .hsync_counter_4(vga_driver_unit_hsync_counter[4]),
6181         .hsync_counter_3(vga_driver_unit_hsync_counter[3]),
6182         .hsync_counter_2(vga_driver_unit_hsync_counter[2]),
6183         .hsync_counter_1(vga_driver_unit_hsync_counter[1]),
6184         .hsync_counter_0(vga_driver_unit_hsync_counter[0]),
6185         .d_set_vsync_counter(vga_driver_unit_d_set_vsync_counter),
6186         .un10_column_counter_siglt6_1(vga_driver_unit_COLUMN_COUNT_next_un10_column_counter_siglt6_1),
6187         .v_sync(vga_driver_unit_v_sync),
6188         .h_sync(vga_driver_unit_h_sync),
6189         .h_enable_sig(vga_driver_unit_h_enable_sig),
6190         .v_enable_sig(vga_driver_unit_v_enable_sig),
6191         .reset_pin_c(reset_pin_c),
6192         .un6_dly_counter_0_x(DELAY_RESET_next_un6_dly_counter_0_x),
6193         .d_set_hsync_counter(vga_driver_unit_d_set_hsync_counter),
6194         .clk_pin_c(G_33)
6195 );
6196 // @10:186
6197   vga_control vga_control_unit (
6198         .column_counter_sig_5(vga_driver_unit_column_counter_sig[5]),
6199         .column_counter_sig_0(vga_driver_unit_column_counter_sig[0]),
6200         .column_counter_sig_1(vga_driver_unit_column_counter_sig[1]),
6201         .column_counter_sig_3(vga_driver_unit_column_counter_sig[3]),
6202         .column_counter_sig_4(vga_driver_unit_column_counter_sig[4]),
6203         .column_counter_sig_2(vga_driver_unit_column_counter_sig[2]),
6204         .column_counter_sig_9(vga_driver_unit_column_counter_sig[9]),
6205         .column_counter_sig_8(vga_driver_unit_column_counter_sig[8]),
6206         .column_counter_sig_7(vga_driver_unit_column_counter_sig[7]),
6207         .column_counter_sig_6(vga_driver_unit_column_counter_sig[6]),
6208         .line_counter_sig_0(vga_driver_unit_line_counter_sig[0]),
6209         .line_counter_sig_1(vga_driver_unit_line_counter_sig[1]),
6210         .line_counter_sig_2(vga_driver_unit_line_counter_sig[2]),
6211         .line_counter_sig_8(vga_driver_unit_line_counter_sig[8]),
6212         .line_counter_sig_3(vga_driver_unit_line_counter_sig[3]),
6213         .line_counter_sig_5(vga_driver_unit_line_counter_sig[5]),
6214         .line_counter_sig_4(vga_driver_unit_line_counter_sig[4]),
6215         .line_counter_sig_7(vga_driver_unit_line_counter_sig[7]),
6216         .line_counter_sig_6(vga_driver_unit_line_counter_sig[6]),
6217         .toggle_counter_sig_0(vga_control_unit_toggle_counter_sig[0]),
6218         .toggle_counter_sig_1(vga_control_unit_toggle_counter_sig[1]),
6219         .toggle_counter_sig_2(vga_control_unit_toggle_counter_sig[2]),
6220         .toggle_counter_sig_3(vga_control_unit_toggle_counter_sig[3]),
6221         .toggle_counter_sig_4(vga_control_unit_toggle_counter_sig[4]),
6222         .toggle_counter_sig_5(vga_control_unit_toggle_counter_sig[5]),
6223         .toggle_counter_sig_6(vga_control_unit_toggle_counter_sig[6]),
6224         .toggle_counter_sig_7(vga_control_unit_toggle_counter_sig[7]),
6225         .toggle_counter_sig_8(vga_control_unit_toggle_counter_sig[8]),
6226         .toggle_counter_sig_9(vga_control_unit_toggle_counter_sig[9]),
6227         .toggle_counter_sig_10(vga_control_unit_toggle_counter_sig[10]),
6228         .toggle_counter_sig_11(vga_control_unit_toggle_counter_sig[11]),
6229         .toggle_counter_sig_12(vga_control_unit_toggle_counter_sig[12]),
6230         .toggle_counter_sig_13(vga_control_unit_toggle_counter_sig[13]),
6231         .toggle_counter_sig_14(vga_control_unit_toggle_counter_sig[14]),
6232         .toggle_counter_sig_15(vga_control_unit_toggle_counter_sig[15]),
6233         .toggle_counter_sig_16(vga_control_unit_toggle_counter_sig[16]),
6234         .toggle_counter_sig_17(vga_control_unit_toggle_counter_sig[17]),
6235         .toggle_counter_sig_18(vga_control_unit_toggle_counter_sig[18]),
6236         .toggle_counter_sig_19(vga_control_unit_toggle_counter_sig[19]),
6237         .toggle_counter_sig_20(vga_control_unit_toggle_counter_sig[20]),
6238         .toggle_counter_sig_21(vga_control_unit_toggle_counter_sig[21]),
6239         .toggle_counter_sig_22(vga_control_unit_toggle_counter_sig[22]),
6240         .toggle_counter_sig_23(vga_control_unit_toggle_counter_sig[23]),
6241         .toggle_counter_sig_24(vga_control_unit_toggle_counter_sig[24]),
6242         .v_enable_sig(vga_driver_unit_v_enable_sig),
6243         .un10_column_counter_siglt6_1(vga_driver_unit_COLUMN_COUNT_next_un10_column_counter_siglt6_1),
6244         .h_enable_sig(vga_driver_unit_h_enable_sig),
6245         .g(vga_control_unit_g),
6246         .r(vga_control_unit_r),
6247         .b(vga_control_unit_b),
6248         .toggle_sig(vga_control_unit_toggle_sig),
6249         .un6_dly_counter_0_x(DELAY_RESET_next_un6_dly_counter_0_x),
6250         .clk_pin_c(G_33)
6251 );
6252 endmodule /* vga */
6253