bsp4/Designflow/syn/rev_1/vga.vhm

   1 --
   2 -- Written by Synplicity
   3 -- Product Version "C-2009.06"
   4 -- Program "Synplify Pro", Mapper "map450rc, Build 029R"
   5 -- Tue Nov  3 17:21:45 2009
   6 --
   7
   8 --
   9 -- Written by Synplify Pro version Build 029R
  10 -- Tue Nov  3 17:21:45 2009
  11 --
  12
  13 --
  14 library ieee, stratix;
  15 use ieee.std_logic_1164.all;
  16 use ieee.numeric_std.all;
  17 library synplify;
  18 use synplify.components.all;
  19 use stratix.stratix_components.all;
  20
  21 entity vga_control is
  22 port(
  23   column_counter_sig_5 :  in std_logic;
  24   column_counter_sig_0 :  in std_logic;
  25   column_counter_sig_1 :  in std_logic;
  26   column_counter_sig_3 :  in std_logic;
  27   column_counter_sig_4 :  in std_logic;
  28   column_counter_sig_2 :  in std_logic;
  29   column_counter_sig_9 :  in std_logic;
  30   column_counter_sig_8 :  in std_logic;
  31   column_counter_sig_7 :  in std_logic;
  32   column_counter_sig_6 :  in std_logic;
  33   line_counter_sig_0 :  in std_logic;
  34   line_counter_sig_1 :  in std_logic;
  35   line_counter_sig_2 :  in std_logic;
  36   line_counter_sig_8 :  in std_logic;
  37   line_counter_sig_3 :  in std_logic;
  38   line_counter_sig_5 :  in std_logic;
  39   line_counter_sig_4 :  in std_logic;
  40   line_counter_sig_7 :  in std_logic;
  41   line_counter_sig_6 :  in std_logic;
  42   toggle_counter_sig_0 :  out std_logic;
  43   toggle_counter_sig_1 :  out std_logic;
  44   toggle_counter_sig_2 :  out std_logic;
  45   toggle_counter_sig_3 :  out std_logic;
  46   toggle_counter_sig_4 :  out std_logic;
  47   toggle_counter_sig_5 :  out std_logic;
  48   toggle_counter_sig_6 :  out std_logic;
  49   toggle_counter_sig_7 :  out std_logic;
  50   toggle_counter_sig_8 :  out std_logic;
  51   toggle_counter_sig_9 :  out std_logic;
  52   toggle_counter_sig_10 :  out std_logic;
  53   toggle_counter_sig_11 :  out std_logic;
  54   toggle_counter_sig_12 :  out std_logic;
  55   toggle_counter_sig_13 :  out std_logic;
  56   toggle_counter_sig_14 :  out std_logic;
  57   toggle_counter_sig_15 :  out std_logic;
  58   toggle_counter_sig_16 :  out std_logic;
  59   toggle_counter_sig_17 :  out std_logic;
  60   toggle_counter_sig_18 :  out std_logic;
  61   toggle_counter_sig_19 :  out std_logic;
  62   toggle_counter_sig_20 :  out std_logic;
  63   toggle_counter_sig_21 :  out std_logic;
  64   toggle_counter_sig_22 :  out std_logic;
  65   toggle_counter_sig_23 :  out std_logic;
  66   toggle_counter_sig_24 :  out std_logic;
  67   v_enable_sig :  in std_logic;
  68   un10_column_counter_siglt6_1 :  in std_logic;
  69   h_enable_sig :  in std_logic;
  70   g :  out std_logic;
  71   r :  out std_logic;
  72   b :  out std_logic;
  73   toggle_sig :  out std_logic;
  74   un6_dly_counter_0_x :  in std_logic;
  75   clk_pin_c :  in std_logic);
  76 end vga_control;
  77
  78 architecture beh of vga_control is
  79   signal devclrn : std_logic := '1';
  80   signal devpor : std_logic := '1';
  81   signal devoe : std_logic := '0';
  82   signal TOGGLE_COUNTER_SIG_COUT : std_logic_vector(17 downto 1);
  83   signal UN2_TOGGLE_COUNTER_NEXT_COUT : std_logic_vector(0 to 0);
  84   signal GND : std_logic ;
  85   signal TOGGLE_SIG_0_0_0_G1 : std_logic ;
  86   signal TOGGLE_SIG_84 : std_logic ;
  87   signal UN13_V_ENABLELTO8 : std_logic ;
  88   signal UN5_V_ENABLELTO7 : std_logic ;
  89   signal UN17_V_ENABLELTO7 : std_logic ;
  90   signal B_NEXT_0_G0_5 : std_logic ;
  91   signal TOGGLE_SIG_0_0_0_G1_2 : std_logic ;
  92   signal UN1_TOGGLE_COUNTER_SIGLTO19 : std_logic ;
  93   signal UN1_TOGGLE_COUNTER_SIGLTO19_5 : std_logic ;
  94   signal UN1_TOGGLE_COUNTER_SIGLTO10 : std_logic ;
  95   signal UN1_TOGGLE_COUNTER_SIGLTO7 : std_logic ;
  96   signal B_NEXT_0_G0_3 : std_logic ;
  97   signal UN9_V_ENABLELTO9 : std_logic ;
  98   signal UN17_V_ENABLELTO5 : std_logic ;
  99   signal UN5_V_ENABLELTO5_0 : std_logic ;
 100   signal UN5_V_ENABLELTO3 : std_logic ;
 101   signal UN17_V_ENABLELT2 : std_logic ;
 102   signal UN13_V_ENABLELTO8_A : std_logic ;
 103   signal UN9_V_ENABLELTO6 : std_logic ;
 104   signal UN1_TOGGLE_COUNTER_SIGLTO19_4 : std_logic ;
 105   signal UN1_TOGGLE_COUNTER_SIGLTO7_4 : std_logic ;
 106   signal TOGGLE_COUNTER_SIG_59 : std_logic ;
 107   signal TOGGLE_COUNTER_SIG_60 : std_logic ;
 108   signal TOGGLE_COUNTER_SIG_61 : std_logic ;
 109   signal TOGGLE_COUNTER_SIG_62 : std_logic ;
 110   signal TOGGLE_COUNTER_SIG_63 : std_logic ;
 111   signal TOGGLE_COUNTER_SIG_64 : std_logic ;
 112   signal TOGGLE_COUNTER_SIG_65 : std_logic ;
 113   signal TOGGLE_COUNTER_SIG_66 : std_logic ;
 114   signal TOGGLE_COUNTER_SIG_67 : std_logic ;
 115   signal TOGGLE_COUNTER_SIG_68 : std_logic ;
 116   signal TOGGLE_COUNTER_SIG_69 : std_logic ;
 117   signal TOGGLE_COUNTER_SIG_70 : std_logic ;
 118   signal TOGGLE_COUNTER_SIG_71 : std_logic ;
 119   signal TOGGLE_COUNTER_SIG_72 : std_logic ;
 120   signal TOGGLE_COUNTER_SIG_73 : std_logic ;
 121   signal TOGGLE_COUNTER_SIG_74 : std_logic ;
 122   signal TOGGLE_COUNTER_SIG_75 : std_logic ;
 123   signal TOGGLE_COUNTER_SIG_76 : std_logic ;
 124   signal TOGGLE_COUNTER_SIG_77 : std_logic ;
 125   signal TOGGLE_COUNTER_SIG_78 : std_logic ;
 126   signal TOGGLE_COUNTER_SIG_79 : std_logic ;
 127   signal TOGGLE_COUNTER_SIG_80 : std_logic ;
 128   signal TOGGLE_COUNTER_SIG_81 : std_logic ;
 129   signal TOGGLE_COUNTER_SIG_82 : std_logic ;
 130   signal TOGGLE_COUNTER_SIG_83 : std_logic ;
 131   signal VCC : std_logic ;
 132   signal TOGGLE_SIG_0_0_0_G1_I : std_logic ;
 133 begin
 134 \TOGGLE_COUNTER_SIG_24_\: stratix_lcell generic map (
 135     operation_mode => "normal",
 136     output_mode => "reg_only",
 137     synch_mode => "off",
 138      sum_lutc_input => "datac",
 139     lut_mask => "ff00")
 140 port map (
 141 regout => TOGGLE_COUNTER_SIG_83,
 142 clk => clk_pin_c,
 143 datad => GND,
 144 aclr => un6_dly_counter_0_x,
 145         devpor => devpor,
 146         devclrn => devclrn,
 147         dataa => VCC,
 148         datab => VCC,
 149         datac => VCC,
 150         sclr => GND,
 151         sload => GND,
 152         ena => VCC,
 153         cin => GND,
 154         inverta => GND,
 155         aload => GND);
 156 \TOGGLE_COUNTER_SIG_23_\: stratix_lcell generic map (
 157     operation_mode => "normal",
 158     output_mode => "reg_only",
 159     synch_mode => "off",
 160      sum_lutc_input => "datac",
 161     lut_mask => "ff00")
 162 port map (
 163 regout => TOGGLE_COUNTER_SIG_82,
 164 clk => clk_pin_c,
 165 datad => GND,
 166 aclr => un6_dly_counter_0_x,
 167         devpor => devpor,
 168         devclrn => devclrn,
 169         dataa => VCC,
 170         datab => VCC,
 171         datac => VCC,
 172         sclr => GND,
 173         sload => GND,
 174         ena => VCC,
 175         cin => GND,
 176         inverta => GND,
 177         aload => GND);
 178 \TOGGLE_COUNTER_SIG_22_\: stratix_lcell generic map (
 179     operation_mode => "normal",
 180     output_mode => "reg_only",
 181     synch_mode => "off",
 182      sum_lutc_input => "datac",
 183     lut_mask => "ff00")
 184 port map (
 185 regout => TOGGLE_COUNTER_SIG_81,
 186 clk => clk_pin_c,
 187 datad => GND,
 188 aclr => un6_dly_counter_0_x,
 189         devpor => devpor,
 190         devclrn => devclrn,
 191         dataa => VCC,
 192         datab => VCC,
 193         datac => VCC,
 194         sclr => GND,
 195         sload => GND,
 196         ena => VCC,
 197         cin => GND,
 198         inverta => GND,
 199         aload => GND);
 200 \TOGGLE_COUNTER_SIG_21_\: stratix_lcell generic map (
 201     operation_mode => "normal",
 202     output_mode => "reg_only",
 203     synch_mode => "off",
 204      sum_lutc_input => "datac",
 205     lut_mask => "ff00")
 206 port map (
 207 regout => TOGGLE_COUNTER_SIG_80,
 208 clk => clk_pin_c,
 209 datad => GND,
 210 aclr => un6_dly_counter_0_x,
 211         devpor => devpor,
 212         devclrn => devclrn,
 213         dataa => VCC,
 214         datab => VCC,
 215         datac => VCC,
 216         sclr => GND,
 217         sload => GND,
 218         ena => VCC,
 219         cin => GND,
 220         inverta => GND,
 221         aload => GND);
 222 \TOGGLE_COUNTER_SIG_20_\: stratix_lcell generic map (
 223     operation_mode => "normal",
 224     output_mode => "reg_only",
 225     synch_mode => "off",
 226      sum_lutc_input => "datac",
 227     lut_mask => "ff00")
 228 port map (
 229 regout => TOGGLE_COUNTER_SIG_79,
 230 clk => clk_pin_c,
 231 datad => GND,
 232 aclr => un6_dly_counter_0_x,
 233         devpor => devpor,
 234         devclrn => devclrn,
 235         dataa => VCC,
 236         datab => VCC,
 237         datac => VCC,
 238         sclr => GND,
 239         sload => GND,
 240         ena => VCC,
 241         cin => GND,
 242         inverta => GND,
 243         aload => GND);
 244 \TOGGLE_COUNTER_SIG_19_\: stratix_lcell generic map (
 245     operation_mode => "normal",
 246     output_mode => "reg_only",
 247     synch_mode => "on",
 248      sum_lutc_input => "cin",
 249      cin_used => "true",
 250     lut_mask => "6c6c")
 251 port map (
 252 regout => TOGGLE_COUNTER_SIG_78,
 253 clk => clk_pin_c,
 254 dataa => TOGGLE_COUNTER_SIG_77,
 255 datab => TOGGLE_COUNTER_SIG_78,
 256 aclr => un6_dly_counter_0_x,
 257 sclr => TOGGLE_SIG_0_0_0_G1_I,
 258 cin => TOGGLE_COUNTER_SIG_COUT(17),
 259         devpor => devpor,
 260         devclrn => devclrn,
 261         datac => VCC,
 262         datad => VCC,
 263         sload => GND,
 264         ena => VCC,
 265         inverta => GND,
 266         aload => GND);
 267 \TOGGLE_COUNTER_SIG_18_\: stratix_lcell generic map (
 268     operation_mode => "normal",
 269     output_mode => "reg_only",
 270     synch_mode => "on",
 271      sum_lutc_input => "cin",
 272      cin_used => "true",
 273     lut_mask => "5a5a")
 274 port map (
 275 regout => TOGGLE_COUNTER_SIG_77,
 276 clk => clk_pin_c,
 277 dataa => TOGGLE_COUNTER_SIG_77,
 278 aclr => un6_dly_counter_0_x,
 279 sclr => TOGGLE_SIG_0_0_0_G1_I,
 280 cin => TOGGLE_COUNTER_SIG_COUT(16),
 281         devpor => devpor,
 282         devclrn => devclrn,
 283         datab => VCC,
 284         datac => VCC,
 285         datad => VCC,
 286         sload => GND,
 287         ena => VCC,
 288         inverta => GND,
 289         aload => GND);
 290 \TOGGLE_COUNTER_SIG_17_\: stratix_lcell generic map (
 291     operation_mode => "arithmetic",
 292     output_mode => "reg_and_comb",
 293     synch_mode => "on",
 294      sum_lutc_input => "cin",
 295      cin_used => "true",
 296     lut_mask => "6c80")
 297 port map (
 298 regout => TOGGLE_COUNTER_SIG_76,
 299 cout => TOGGLE_COUNTER_SIG_COUT(17),
 300 clk => clk_pin_c,
 301 dataa => TOGGLE_COUNTER_SIG_75,
 302 datab => TOGGLE_COUNTER_SIG_76,
 303 aclr => un6_dly_counter_0_x,
 304 sclr => TOGGLE_SIG_0_0_0_G1_I,
 305 cin => TOGGLE_COUNTER_SIG_COUT(15),
 306         devpor => devpor,
 307         devclrn => devclrn,
 308         datac => VCC,
 309         datad => VCC,
 310         sload => GND,
 311         ena => VCC,
 312         inverta => GND,
 313         aload => GND);
 314 \TOGGLE_COUNTER_SIG_16_\: stratix_lcell generic map (
 315     operation_mode => "arithmetic",
 316     output_mode => "reg_and_comb",
 317     synch_mode => "on",
 318      sum_lutc_input => "cin",
 319      cin_used => "true",
 320     lut_mask => "5a80")
 321 port map (
 322 regout => TOGGLE_COUNTER_SIG_75,
 323 cout => TOGGLE_COUNTER_SIG_COUT(16),
 324 clk => clk_pin_c,
 325 dataa => TOGGLE_COUNTER_SIG_75,
 326 datab => TOGGLE_COUNTER_SIG_76,
 327 aclr => un6_dly_counter_0_x,
 328 sclr => TOGGLE_SIG_0_0_0_G1_I,
 329 cin => TOGGLE_COUNTER_SIG_COUT(14),
 330         devpor => devpor,
 331         devclrn => devclrn,
 332         datac => VCC,
 333         datad => VCC,
 334         sload => GND,
 335         ena => VCC,
 336         inverta => GND,
 337         aload => GND);
 338 \TOGGLE_COUNTER_SIG_15_\: stratix_lcell generic map (
 339     operation_mode => "arithmetic",
 340     output_mode => "reg_and_comb",
 341     synch_mode => "on",
 342      sum_lutc_input => "cin",
 343      cin_used => "true",
 344     lut_mask => "6c80")
 345 port map (
 346 regout => TOGGLE_COUNTER_SIG_74,
 347 cout => TOGGLE_COUNTER_SIG_COUT(15),
 348 clk => clk_pin_c,
 349 dataa => TOGGLE_COUNTER_SIG_73,
 350 datab => TOGGLE_COUNTER_SIG_74,
 351 aclr => un6_dly_counter_0_x,
 352 sclr => TOGGLE_SIG_0_0_0_G1_I,
 353 cin => TOGGLE_COUNTER_SIG_COUT(13),
 354         devpor => devpor,
 355         devclrn => devclrn,
 356         datac => VCC,
 357         datad => VCC,
 358         sload => GND,
 359         ena => VCC,
 360         inverta => GND,
 361         aload => GND);
 362 \TOGGLE_COUNTER_SIG_14_\: stratix_lcell generic map (
 363     operation_mode => "arithmetic",
 364     output_mode => "reg_and_comb",
 365     synch_mode => "on",
 366      sum_lutc_input => "cin",
 367      cin_used => "true",
 368     lut_mask => "5a80")
 369 port map (
 370 regout => TOGGLE_COUNTER_SIG_73,
 371 cout => TOGGLE_COUNTER_SIG_COUT(14),
 372 clk => clk_pin_c,
 373 dataa => TOGGLE_COUNTER_SIG_73,
 374 datab => TOGGLE_COUNTER_SIG_74,
 375 aclr => un6_dly_counter_0_x,
 376 sclr => TOGGLE_SIG_0_0_0_G1_I,
 377 cin => TOGGLE_COUNTER_SIG_COUT(12),
 378         devpor => devpor,
 379         devclrn => devclrn,
 380         datac => VCC,
 381         datad => VCC,
 382         sload => GND,
 383         ena => VCC,
 384         inverta => GND,
 385         aload => GND);
 386 \TOGGLE_COUNTER_SIG_13_\: stratix_lcell generic map (
 387     operation_mode => "arithmetic",
 388     output_mode => "reg_and_comb",
 389     synch_mode => "on",
 390      sum_lutc_input => "cin",
 391      cin_used => "true",
 392     lut_mask => "6c80")
 393 port map (
 394 regout => TOGGLE_COUNTER_SIG_72,
 395 cout => TOGGLE_COUNTER_SIG_COUT(13),
 396 clk => clk_pin_c,
 397 dataa => TOGGLE_COUNTER_SIG_71,
 398 datab => TOGGLE_COUNTER_SIG_72,
 399 aclr => un6_dly_counter_0_x,
 400 sclr => TOGGLE_SIG_0_0_0_G1_I,
 401 cin => TOGGLE_COUNTER_SIG_COUT(11),
 402         devpor => devpor,
 403         devclrn => devclrn,
 404         datac => VCC,
 405         datad => VCC,
 406         sload => GND,
 407         ena => VCC,
 408         inverta => GND,
 409         aload => GND);
 410 \TOGGLE_COUNTER_SIG_12_\: stratix_lcell generic map (
 411     operation_mode => "arithmetic",
 412     output_mode => "reg_and_comb",
 413     synch_mode => "on",
 414      sum_lutc_input => "cin",
 415      cin_used => "true",
 416     lut_mask => "5a80")
 417 port map (
 418 regout => TOGGLE_COUNTER_SIG_71,
 419 cout => TOGGLE_COUNTER_SIG_COUT(12),
 420 clk => clk_pin_c,
 421 dataa => TOGGLE_COUNTER_SIG_71,
 422 datab => TOGGLE_COUNTER_SIG_72,
 423 aclr => un6_dly_counter_0_x,
 424 sclr => TOGGLE_SIG_0_0_0_G1_I,
 425 cin => TOGGLE_COUNTER_SIG_COUT(10),
 426         devpor => devpor,
 427         devclrn => devclrn,
 428         datac => VCC,
 429         datad => VCC,
 430         sload => GND,
 431         ena => VCC,
 432         inverta => GND,
 433         aload => GND);
 434 \TOGGLE_COUNTER_SIG_11_\: stratix_lcell generic map (
 435     operation_mode => "arithmetic",
 436     output_mode => "reg_and_comb",
 437     synch_mode => "on",
 438      sum_lutc_input => "cin",
 439      cin_used => "true",
 440     lut_mask => "6c80")
 441 port map (
 442 regout => TOGGLE_COUNTER_SIG_70,
 443 cout => TOGGLE_COUNTER_SIG_COUT(11),
 444 clk => clk_pin_c,
 445 dataa => TOGGLE_COUNTER_SIG_69,
 446 datab => TOGGLE_COUNTER_SIG_70,
 447 aclr => un6_dly_counter_0_x,
 448 sclr => TOGGLE_SIG_0_0_0_G1_I,
 449 cin => TOGGLE_COUNTER_SIG_COUT(9),
 450         devpor => devpor,
 451         devclrn => devclrn,
 452         datac => VCC,
 453         datad => VCC,
 454         sload => GND,
 455         ena => VCC,
 456         inverta => GND,
 457         aload => GND);
 458 \TOGGLE_COUNTER_SIG_10_\: stratix_lcell generic map (
 459     operation_mode => "arithmetic",
 460     output_mode => "reg_and_comb",
 461     synch_mode => "on",
 462      sum_lutc_input => "cin",
 463      cin_used => "true",
 464     lut_mask => "5a80")
 465 port map (
 466 regout => TOGGLE_COUNTER_SIG_69,
 467 cout => TOGGLE_COUNTER_SIG_COUT(10),
 468 clk => clk_pin_c,
 469 dataa => TOGGLE_COUNTER_SIG_69,
 470 datab => TOGGLE_COUNTER_SIG_70,
 471 aclr => un6_dly_counter_0_x,
 472 sclr => TOGGLE_SIG_0_0_0_G1_I,
 473 cin => TOGGLE_COUNTER_SIG_COUT(8),
 474         devpor => devpor,
 475         devclrn => devclrn,
 476         datac => VCC,
 477         datad => VCC,
 478         sload => GND,
 479         ena => VCC,
 480         inverta => GND,
 481         aload => GND);
 482 \TOGGLE_COUNTER_SIG_9_\: stratix_lcell generic map (
 483     operation_mode => "arithmetic",
 484     output_mode => "reg_and_comb",
 485     synch_mode => "on",
 486      sum_lutc_input => "cin",
 487      cin_used => "true",
 488     lut_mask => "6c80")
 489 port map (
 490 regout => TOGGLE_COUNTER_SIG_68,
 491 cout => TOGGLE_COUNTER_SIG_COUT(9),
 492 clk => clk_pin_c,
 493 dataa => TOGGLE_COUNTER_SIG_67,
 494 datab => TOGGLE_COUNTER_SIG_68,
 495 aclr => un6_dly_counter_0_x,
 496 sclr => TOGGLE_SIG_0_0_0_G1_I,
 497 cin => TOGGLE_COUNTER_SIG_COUT(7),
 498         devpor => devpor,
 499         devclrn => devclrn,
 500         datac => VCC,
 501         datad => VCC,
 502         sload => GND,
 503         ena => VCC,
 504         inverta => GND,
 505         aload => GND);
 506 \TOGGLE_COUNTER_SIG_8_\: stratix_lcell generic map (
 507     operation_mode => "arithmetic",
 508     output_mode => "reg_and_comb",
 509     synch_mode => "on",
 510      sum_lutc_input => "cin",
 511      cin_used => "true",
 512     lut_mask => "5a80")
 513 port map (
 514 regout => TOGGLE_COUNTER_SIG_67,
 515 cout => TOGGLE_COUNTER_SIG_COUT(8),
 516 clk => clk_pin_c,
 517 dataa => TOGGLE_COUNTER_SIG_67,
 518 datab => TOGGLE_COUNTER_SIG_68,
 519 aclr => un6_dly_counter_0_x,
 520 sclr => TOGGLE_SIG_0_0_0_G1_I,
 521 cin => TOGGLE_COUNTER_SIG_COUT(6),
 522         devpor => devpor,
 523         devclrn => devclrn,
 524         datac => VCC,
 525         datad => VCC,
 526         sload => GND,
 527         ena => VCC,
 528         inverta => GND,
 529         aload => GND);
 530 \TOGGLE_COUNTER_SIG_7_\: stratix_lcell generic map (
 531     operation_mode => "arithmetic",
 532     output_mode => "reg_and_comb",
 533     synch_mode => "on",
 534      sum_lutc_input => "cin",
 535      cin_used => "true",
 536     lut_mask => "6c80")
 537 port map (
 538 regout => TOGGLE_COUNTER_SIG_66,
 539 cout => TOGGLE_COUNTER_SIG_COUT(7),
 540 clk => clk_pin_c,
 541 dataa => TOGGLE_COUNTER_SIG_65,
 542 datab => TOGGLE_COUNTER_SIG_66,
 543 aclr => un6_dly_counter_0_x,
 544 sclr => TOGGLE_SIG_0_0_0_G1_I,
 545 cin => TOGGLE_COUNTER_SIG_COUT(5),
 546         devpor => devpor,
 547         devclrn => devclrn,
 548         datac => VCC,
 549         datad => VCC,
 550         sload => GND,
 551         ena => VCC,
 552         inverta => GND,
 553         aload => GND);
 554 \TOGGLE_COUNTER_SIG_6_\: stratix_lcell generic map (
 555     operation_mode => "arithmetic",
 556     output_mode => "reg_and_comb",
 557     synch_mode => "on",
 558      sum_lutc_input => "cin",
 559      cin_used => "true",
 560     lut_mask => "5a80")
 561 port map (
 562 regout => TOGGLE_COUNTER_SIG_65,
 563 cout => TOGGLE_COUNTER_SIG_COUT(6),
 564 clk => clk_pin_c,
 565 dataa => TOGGLE_COUNTER_SIG_65,
 566 datab => TOGGLE_COUNTER_SIG_66,
 567 aclr => un6_dly_counter_0_x,
 568 sclr => TOGGLE_SIG_0_0_0_G1_I,
 569 cin => TOGGLE_COUNTER_SIG_COUT(4),
 570         devpor => devpor,
 571         devclrn => devclrn,
 572         datac => VCC,
 573         datad => VCC,
 574         sload => GND,
 575         ena => VCC,
 576         inverta => GND,
 577         aload => GND);
 578 \TOGGLE_COUNTER_SIG_5_\: stratix_lcell generic map (
 579     operation_mode => "arithmetic",
 580     output_mode => "reg_and_comb",
 581     synch_mode => "on",
 582      sum_lutc_input => "cin",
 583      cin_used => "true",
 584     lut_mask => "6c80")
 585 port map (
 586 regout => TOGGLE_COUNTER_SIG_64,
 587 cout => TOGGLE_COUNTER_SIG_COUT(5),
 588 clk => clk_pin_c,
 589 dataa => TOGGLE_COUNTER_SIG_63,
 590 datab => TOGGLE_COUNTER_SIG_64,
 591 aclr => un6_dly_counter_0_x,
 592 sclr => TOGGLE_SIG_0_0_0_G1_I,
 593 cin => TOGGLE_COUNTER_SIG_COUT(3),
 594         devpor => devpor,
 595         devclrn => devclrn,
 596         datac => VCC,
 597         datad => VCC,
 598         sload => GND,
 599         ena => VCC,
 600         inverta => GND,
 601         aload => GND);
 602 \TOGGLE_COUNTER_SIG_4_\: stratix_lcell generic map (
 603     operation_mode => "arithmetic",
 604     output_mode => "reg_and_comb",
 605     synch_mode => "on",
 606      sum_lutc_input => "cin",
 607      cin_used => "true",
 608     lut_mask => "5a80")
 609 port map (
 610 regout => TOGGLE_COUNTER_SIG_63,
 611 cout => TOGGLE_COUNTER_SIG_COUT(4),
 612 clk => clk_pin_c,
 613 dataa => TOGGLE_COUNTER_SIG_63,
 614 datab => TOGGLE_COUNTER_SIG_64,
 615 aclr => un6_dly_counter_0_x,
 616 sclr => TOGGLE_SIG_0_0_0_G1_I,
 617 cin => TOGGLE_COUNTER_SIG_COUT(2),
 618         devpor => devpor,
 619         devclrn => devclrn,
 620         datac => VCC,
 621         datad => VCC,
 622         sload => GND,
 623         ena => VCC,
 624         inverta => GND,
 625         aload => GND);
 626 \TOGGLE_COUNTER_SIG_3_\: stratix_lcell generic map (
 627     operation_mode => "arithmetic",
 628     output_mode => "reg_and_comb",
 629     synch_mode => "on",
 630      sum_lutc_input => "cin",
 631      cin_used => "true",
 632     lut_mask => "6c80")
 633 port map (
 634 regout => TOGGLE_COUNTER_SIG_62,
 635 cout => TOGGLE_COUNTER_SIG_COUT(3),
 636 clk => clk_pin_c,
 637 dataa => TOGGLE_COUNTER_SIG_61,
 638 datab => TOGGLE_COUNTER_SIG_62,
 639 aclr => un6_dly_counter_0_x,
 640 sclr => TOGGLE_SIG_0_0_0_G1_I,
 641 cin => TOGGLE_COUNTER_SIG_COUT(1),
 642         devpor => devpor,
 643         devclrn => devclrn,
 644         datac => VCC,
 645         datad => VCC,
 646         sload => GND,
 647         ena => VCC,
 648         inverta => GND,
 649         aload => GND);
 650 \TOGGLE_COUNTER_SIG_2_\: stratix_lcell generic map (
 651     operation_mode => "arithmetic",
 652     output_mode => "reg_and_comb",
 653     synch_mode => "on",
 654      sum_lutc_input => "cin",
 655      cin_used => "true",
 656     lut_mask => "5a80")
 657 port map (
 658 regout => TOGGLE_COUNTER_SIG_61,
 659 cout => TOGGLE_COUNTER_SIG_COUT(2),
 660 clk => clk_pin_c,
 661 dataa => TOGGLE_COUNTER_SIG_61,
 662 datab => TOGGLE_COUNTER_SIG_62,
 663 aclr => un6_dly_counter_0_x,
 664 sclr => TOGGLE_SIG_0_0_0_G1_I,
 665 cin => UN2_TOGGLE_COUNTER_NEXT_COUT(0),
 666         devpor => devpor,
 667         devclrn => devclrn,
 668         datac => VCC,
 669         datad => VCC,
 670         sload => GND,
 671         ena => VCC,
 672         inverta => GND,
 673         aload => GND);
 674 \TOGGLE_COUNTER_SIG_1_\: stratix_lcell generic map (
 675     operation_mode => "arithmetic",
 676     output_mode => "reg_and_comb",
 677     synch_mode => "on",
 678      sum_lutc_input => "datac",
 679     lut_mask => "6688")
 680 port map (
 681 regout => TOGGLE_COUNTER_SIG_60,
 682 cout => TOGGLE_COUNTER_SIG_COUT(1),
 683 clk => clk_pin_c,
 684 dataa => TOGGLE_COUNTER_SIG_59,
 685 datab => TOGGLE_COUNTER_SIG_60,
 686 aclr => un6_dly_counter_0_x,
 687 sclr => TOGGLE_SIG_0_0_0_G1_I,
 688         devpor => devpor,
 689         devclrn => devclrn,
 690         datac => VCC,
 691         datad => VCC,
 692         sload => GND,
 693         ena => VCC,
 694         cin => GND,
 695         inverta => GND,
 696         aload => GND);
 697 \TOGGLE_COUNTER_SIG_0_\: stratix_lcell generic map (
 698     operation_mode => "normal",
 699     output_mode => "reg_only",
 700     synch_mode => "on",
 701      sum_lutc_input => "datac",
 702     lut_mask => "5555")
 703 port map (
 704 regout => TOGGLE_COUNTER_SIG_59,
 705 clk => clk_pin_c,
 706 dataa => TOGGLE_COUNTER_SIG_59,
 707 aclr => un6_dly_counter_0_x,
 708 sclr => TOGGLE_SIG_0_0_0_G1_I,
 709         devpor => devpor,
 710         devclrn => devclrn,
 711         datab => VCC,
 712         datac => VCC,
 713         datad => VCC,
 714         sload => GND,
 715         ena => VCC,
 716         cin => GND,
 717         inverta => GND,
 718         aload => GND);
 719 TOGGLE_SIG_Z147: stratix_lcell generic map (
 720     operation_mode => "normal",
 721     output_mode => "reg_only",
 722     synch_mode => "off",
 723      sum_lutc_input => "datac",
 724     lut_mask => "9999")
 725 port map (
 726 regout => TOGGLE_SIG_84,
 727 clk => clk_pin_c,
 728 dataa => TOGGLE_SIG_84,
 729 datab => TOGGLE_SIG_0_0_0_G1,
 730 aclr => un6_dly_counter_0_x,
 731         devpor => devpor,
 732         devclrn => devclrn,
 733         datac => VCC,
 734         datad => VCC,
 735         sclr => GND,
 736         sload => GND,
 737         ena => VCC,
 738         cin => GND,
 739         inverta => GND,
 740         aload => GND);
 741 B_Z148: stratix_lcell generic map (
 742     operation_mode => "normal",
 743     output_mode => "reg_only",
 744     synch_mode => "off",
 745      sum_lutc_input => "datac",
 746     lut_mask => "0100")
 747 port map (
 748 regout => b,
 749 clk => clk_pin_c,
 750 dataa => UN13_V_ENABLELTO8,
 751 datab => UN5_V_ENABLELTO7,
 752 datac => UN17_V_ENABLELTO7,
 753 datad => B_NEXT_0_G0_5,
 754 aclr => un6_dly_counter_0_x,
 755         devpor => devpor,
 756         devclrn => devclrn,
 757         sclr => GND,
 758         sload => GND,
 759         ena => VCC,
 760         cin => GND,
 761         inverta => GND,
 762         aload => GND);
 763 R_Z149: stratix_lcell generic map (
 764     operation_mode => "normal",
 765     output_mode => "reg_only",
 766     synch_mode => "off",
 767      sum_lutc_input => "datac",
 768     lut_mask => "ff00")
 769 port map (
 770 regout => r,
 771 clk => clk_pin_c,
 772 datad => GND,
 773 aclr => un6_dly_counter_0_x,
 774         devpor => devpor,
 775         devclrn => devclrn,
 776         dataa => VCC,
 777         datab => VCC,
 778         datac => VCC,
 779         sclr => GND,
 780         sload => GND,
 781         ena => VCC,
 782         cin => GND,
 783         inverta => GND,
 784         aload => GND);
 785 G_Z150: stratix_lcell generic map (
 786     operation_mode => "normal",
 787     output_mode => "reg_only",
 788     synch_mode => "off",
 789      sum_lutc_input => "datac",
 790     lut_mask => "ff00")
 791 port map (
 792 regout => g,
 793 clk => clk_pin_c,
 794 datad => GND,
 795 aclr => un6_dly_counter_0_x,
 796         devpor => devpor,
 797         devclrn => devclrn,
 798         dataa => VCC,
 799         datab => VCC,
 800         datac => VCC,
 801         sclr => GND,
 802         sload => GND,
 803         ena => VCC,
 804         cin => GND,
 805         inverta => GND,
 806         aload => GND);
 807 TOGGLE_SIG_0_0_0_G1_Z151: stratix_lcell generic map (
 808     operation_mode => "normal",
 809     output_mode => "comb_only",
 810     synch_mode => "off",
 811      sum_lutc_input => "datac",
 812     lut_mask => "0100")
 813 port map (
 814 combout => TOGGLE_SIG_0_0_0_G1,
 815 dataa => TOGGLE_COUNTER_SIG_79,
 816 datab => TOGGLE_COUNTER_SIG_80,
 817 datac => TOGGLE_SIG_0_0_0_G1_2,
 818 datad => UN1_TOGGLE_COUNTER_SIGLTO19,
 819         devpor => devpor,
 820         devclrn => devclrn,
 821         clk => GND,
 822         aclr => GND,
 823         sclr => GND,
 824         sload => GND,
 825         ena => VCC,
 826         cin => GND,
 827         inverta => GND,
 828         aload => GND);
 829 BLINKER_NEXT_UN1_TOGGLE_COUNTER_SIGLTO19: stratix_lcell generic map (
 830     operation_mode => "normal",
 831     output_mode => "comb_only",
 832     synch_mode => "off",
 833      sum_lutc_input => "datac",
 834     lut_mask => "f1f0")
 835 port map (
 836 combout => UN1_TOGGLE_COUNTER_SIGLTO19,
 837 dataa => TOGGLE_COUNTER_SIG_70,
 838 datab => TOGGLE_COUNTER_SIG_71,
 839 datac => UN1_TOGGLE_COUNTER_SIGLTO19_5,
 840 datad => UN1_TOGGLE_COUNTER_SIGLTO10,
 841         devpor => devpor,
 842         devclrn => devclrn,
 843         clk => GND,
 844         aclr => GND,
 845         sclr => GND,
 846         sload => GND,
 847         ena => VCC,
 848         cin => GND,
 849         inverta => GND,
 850         aload => GND);
 851 BLINKER_NEXT_UN1_TOGGLE_COUNTER_SIGLTO10: stratix_lcell generic map (
 852     operation_mode => "normal",
 853     output_mode => "comb_only",
 854     synch_mode => "off",
 855      sum_lutc_input => "datac",
 856     lut_mask => "3f1f")
 857 port map (
 858 combout => UN1_TOGGLE_COUNTER_SIGLTO10,
 859 dataa => TOGGLE_COUNTER_SIG_67,
 860 datab => TOGGLE_COUNTER_SIG_68,
 861 datac => TOGGLE_COUNTER_SIG_69,
 862 datad => UN1_TOGGLE_COUNTER_SIGLTO7,
 863         devpor => devpor,
 864         devclrn => devclrn,
 865         clk => GND,
 866         aclr => GND,
 867         sclr => GND,
 868         sload => GND,
 869         ena => VCC,
 870         cin => GND,
 871         inverta => GND,
 872         aload => GND);
 873 B_NEXT_0_G0_5_Z154: stratix_lcell generic map (
 874     operation_mode => "normal",
 875     output_mode => "comb_only",
 876     synch_mode => "off",
 877      sum_lutc_input => "datac",
 878     lut_mask => "0080")
 879 port map (
 880 combout => B_NEXT_0_G0_5,
 881 dataa => h_enable_sig,
 882 datab => TOGGLE_SIG_84,
 883 datac => B_NEXT_0_G0_3,
 884 datad => UN9_V_ENABLELTO9,
 885         devpor => devpor,
 886         devclrn => devclrn,
 887         clk => GND,
 888         aclr => GND,
 889         sclr => GND,
 890         sload => GND,
 891         ena => VCC,
 892         cin => GND,
 893         inverta => GND,
 894         aload => GND);
 895 DRAW_SQUARE_NEXT_UN17_V_ENABLELTO7: stratix_lcell generic map (
 896     operation_mode => "normal",
 897     output_mode => "comb_only",
 898     synch_mode => "off",
 899      sum_lutc_input => "datac",
 900     lut_mask => "8080")
 901 port map (
 902 combout => UN17_V_ENABLELTO7,
 903 dataa => line_counter_sig_6,
 904 datab => line_counter_sig_7,
 905 datac => UN17_V_ENABLELTO5,
 906         devpor => devpor,
 907         devclrn => devclrn,
 908         clk => GND,
 909         datad => VCC,
 910         aclr => GND,
 911         sclr => GND,
 912         sload => GND,
 913         ena => VCC,
 914         cin => GND,
 915         inverta => GND,
 916         aload => GND);
 917 DRAW_SQUARE_NEXT_UN5_V_ENABLELTO7: stratix_lcell generic map (
 918     operation_mode => "normal",
 919     output_mode => "comb_only",
 920     synch_mode => "off",
 921      sum_lutc_input => "datac",
 922     lut_mask => "8880")
 923 port map (
 924 combout => UN5_V_ENABLELTO7,
 925 dataa => column_counter_sig_6,
 926 datab => column_counter_sig_7,
 927 datac => UN5_V_ENABLELTO5_0,
 928 datad => UN5_V_ENABLELTO3,
 929         devpor => devpor,
 930         devclrn => devclrn,
 931         clk => GND,
 932         aclr => GND,
 933         sclr => GND,
 934         sload => GND,
 935         ena => VCC,
 936         cin => GND,
 937         inverta => GND,
 938         aload => GND);
 939 DRAW_SQUARE_NEXT_UN17_V_ENABLELTO5: stratix_lcell generic map (
 940     operation_mode => "normal",
 941     output_mode => "comb_only",
 942     synch_mode => "off",
 943      sum_lutc_input => "datac",
 944     lut_mask => "feee")
 945 port map (
 946 combout => UN17_V_ENABLELTO5,
 947 dataa => line_counter_sig_4,
 948 datab => line_counter_sig_5,
 949 datac => line_counter_sig_3,
 950 datad => UN17_V_ENABLELT2,
 951         devpor => devpor,
 952         devclrn => devclrn,
 953         clk => GND,
 954         aclr => GND,
 955         sclr => GND,
 956         sload => GND,
 957         ena => VCC,
 958         cin => GND,
 959         inverta => GND,
 960         aload => GND);
 961 DRAW_SQUARE_NEXT_UN13_V_ENABLELTO8: stratix_lcell generic map (
 962     operation_mode => "normal",
 963     output_mode => "comb_only",
 964     synch_mode => "off",
 965      sum_lutc_input => "datac",
 966     lut_mask => "1101")
 967 port map (
 968 combout => UN13_V_ENABLELTO8,
 969 dataa => line_counter_sig_8,
 970 datab => line_counter_sig_7,
 971 datac => line_counter_sig_6,
 972 datad => UN13_V_ENABLELTO8_A,
 973         devpor => devpor,
 974         devclrn => devclrn,
 975         clk => GND,
 976         aclr => GND,
 977         sclr => GND,
 978         sload => GND,
 979         ena => VCC,
 980         cin => GND,
 981         inverta => GND,
 982         aload => GND);
 983 DRAW_SQUARE_NEXT_UN13_V_ENABLELTO8_A: stratix_lcell generic map (
 984     operation_mode => "normal",
 985     output_mode => "comb_only",
 986     synch_mode => "off",
 987      sum_lutc_input => "datac",
 988     lut_mask => "01ff")
 989 port map (
 990 combout => UN13_V_ENABLELTO8_A,
 991 dataa => line_counter_sig_2,
 992 datab => line_counter_sig_4,
 993 datac => line_counter_sig_3,
 994 datad => line_counter_sig_5,
 995         devpor => devpor,
 996         devclrn => devclrn,
 997         clk => GND,
 998         aclr => GND,
 999         sclr => GND,
1000         sload => GND,
1001         ena => VCC,
1002         cin => GND,
1003         inverta => GND,
1004         aload => GND);
1005 DRAW_SQUARE_NEXT_UN9_V_ENABLELTO9: stratix_lcell generic map (
1006     operation_mode => "normal",
1007     output_mode => "comb_only",
1008     synch_mode => "off",
1009      sum_lutc_input => "datac",
1010     lut_mask => "0100")
1011 port map (
1012 combout => UN9_V_ENABLELTO9,
1013 dataa => column_counter_sig_7,
1014 datab => column_counter_sig_8,
1015 datac => column_counter_sig_9,
1016 datad => UN9_V_ENABLELTO6,
1017         devpor => devpor,
1018         devclrn => devclrn,
1019         clk => GND,
1020         aclr => GND,
1021         sclr => GND,
1022         sload => GND,
1023         ena => VCC,
1024         cin => GND,
1025         inverta => GND,
1026         aload => GND);
1027 BLINKER_NEXT_UN1_TOGGLE_COUNTER_SIGLTO19_5: stratix_lcell generic map (
1028     operation_mode => "normal",
1029     output_mode => "comb_only",
1030     synch_mode => "off",
1031      sum_lutc_input => "datac",
1032     lut_mask => "ff7f")
1033 port map (
1034 combout => UN1_TOGGLE_COUNTER_SIGLTO19_5,
1035 dataa => TOGGLE_COUNTER_SIG_72,
1036 datab => TOGGLE_COUNTER_SIG_73,
1037 datac => TOGGLE_COUNTER_SIG_74,
1038 datad => UN1_TOGGLE_COUNTER_SIGLTO19_4,
1039         devpor => devpor,
1040         devclrn => devclrn,
1041         clk => GND,
1042         aclr => GND,
1043         sclr => GND,
1044         sload => GND,
1045         ena => VCC,
1046         cin => GND,
1047         inverta => GND,
1048         aload => GND);
1049 BLINKER_NEXT_UN1_TOGGLE_COUNTER_SIGLTO7: stratix_lcell generic map (
1050     operation_mode => "normal",
1051     output_mode => "comb_only",
1052     synch_mode => "off",
1053      sum_lutc_input => "datac",
1054     lut_mask => "0100")
1055 port map (
1056 combout => UN1_TOGGLE_COUNTER_SIGLTO7,
1057 dataa => TOGGLE_COUNTER_SIG_61,
1058 datab => TOGGLE_COUNTER_SIG_62,
1059 datac => TOGGLE_COUNTER_SIG_63,
1060 datad => UN1_TOGGLE_COUNTER_SIGLTO7_4,
1061         devpor => devpor,
1062         devclrn => devclrn,
1063         clk => GND,
1064         aclr => GND,
1065         sclr => GND,
1066         sload => GND,
1067         ena => VCC,
1068         cin => GND,
1069         inverta => GND,
1070         aload => GND);
1071 DRAW_SQUARE_NEXT_UN9_V_ENABLELTO6: stratix_lcell generic map (
1072     operation_mode => "normal",
1073     output_mode => "comb_only",
1074     synch_mode => "off",
1075      sum_lutc_input => "datac",
1076     lut_mask => "ff01")
1077 port map (
1078 combout => UN9_V_ENABLELTO6,
1079 dataa => column_counter_sig_2,
1080 datab => column_counter_sig_4,
1081 datac => column_counter_sig_3,
1082 datad => un10_column_counter_siglt6_1,
1083         devpor => devpor,
1084         devclrn => devclrn,
1085         clk => GND,
1086         aclr => GND,
1087         sclr => GND,
1088         sload => GND,
1089         ena => VCC,
1090         cin => GND,
1091         inverta => GND,
1092         aload => GND);
1093 DRAW_SQUARE_NEXT_UN5_V_ENABLELTO3: stratix_lcell generic map (
1094     operation_mode => "normal",
1095     output_mode => "comb_only",
1096     synch_mode => "off",
1097      sum_lutc_input => "datac",
1098     lut_mask => "fe00")
1099 port map (
1100 combout => UN5_V_ENABLELTO3,
1101 dataa => column_counter_sig_1,
1102 datab => column_counter_sig_2,
1103 datac => column_counter_sig_0,
1104 datad => column_counter_sig_3,
1105         devpor => devpor,
1106         devclrn => devclrn,
1107         clk => GND,
1108         aclr => GND,
1109         sclr => GND,
1110         sload => GND,
1111         ena => VCC,
1112         cin => GND,
1113         inverta => GND,
1114         aload => GND);
1115 TOGGLE_SIG_0_0_0_G1_2_Z165: stratix_lcell generic map (
1116     operation_mode => "normal",
1117     output_mode => "comb_only",
1118     synch_mode => "off",
1119      sum_lutc_input => "datac",
1120     lut_mask => "fefe")
1121 port map (
1122 combout => TOGGLE_SIG_0_0_0_G1_2,
1123 dataa => TOGGLE_COUNTER_SIG_81,
1124 datab => TOGGLE_COUNTER_SIG_82,
1125 datac => TOGGLE_COUNTER_SIG_83,
1126         devpor => devpor,
1127         devclrn => devclrn,
1128         clk => GND,
1129         datad => VCC,
1130         aclr => GND,
1131         sclr => GND,
1132         sload => GND,
1133         ena => VCC,
1134         cin => GND,
1135         inverta => GND,
1136         aload => GND);
1137 BLINKER_NEXT_UN1_TOGGLE_COUNTER_SIGLTO19_4: stratix_lcell generic map (
1138     operation_mode => "normal",
1139     output_mode => "comb_only",
1140     synch_mode => "off",
1141      sum_lutc_input => "datac",
1142     lut_mask => "7fff")
1143 port map (
1144 combout => UN1_TOGGLE_COUNTER_SIGLTO19_4,
1145 dataa => TOGGLE_COUNTER_SIG_75,
1146 datab => TOGGLE_COUNTER_SIG_76,
1147 datac => TOGGLE_COUNTER_SIG_77,
1148 datad => TOGGLE_COUNTER_SIG_78,
1149         devpor => devpor,
1150         devclrn => devclrn,
1151         clk => GND,
1152         aclr => GND,
1153         sclr => GND,
1154         sload => GND,
1155         ena => VCC,
1156         cin => GND,
1157         inverta => GND,
1158         aload => GND);
1159 B_NEXT_0_G0_3_Z167: stratix_lcell generic map (
1160     operation_mode => "normal",
1161     output_mode => "comb_only",
1162     synch_mode => "off",
1163      sum_lutc_input => "datac",
1164     lut_mask => "0004")
1165 port map (
1166 combout => B_NEXT_0_G0_3,
1167 dataa => line_counter_sig_8,
1168 datab => v_enable_sig,
1169 datac => column_counter_sig_8,
1170 datad => column_counter_sig_9,
1171         devpor => devpor,
1172         devclrn => devclrn,
1173         clk => GND,
1174         aclr => GND,
1175         sclr => GND,
1176         sload => GND,
1177         ena => VCC,
1178         cin => GND,
1179         inverta => GND,
1180         aload => GND);
1181 BLINKER_NEXT_UN1_TOGGLE_COUNTER_SIGLTO7_4: stratix_lcell generic map (
1182     operation_mode => "normal",
1183     output_mode => "comb_only",
1184     synch_mode => "off",
1185      sum_lutc_input => "datac",
1186     lut_mask => "0001")
1187 port map (
1188 combout => UN1_TOGGLE_COUNTER_SIGLTO7_4,
1189 dataa => TOGGLE_COUNTER_SIG_60,
1190 datab => TOGGLE_COUNTER_SIG_64,
1191 datac => TOGGLE_COUNTER_SIG_65,
1192 datad => TOGGLE_COUNTER_SIG_66,
1193         devpor => devpor,
1194         devclrn => devclrn,
1195         clk => GND,
1196         aclr => GND,
1197         sclr => GND,
1198         sload => GND,
1199         ena => VCC,
1200         cin => GND,
1201         inverta => GND,
1202         aload => GND);
1203 DRAW_SQUARE_NEXT_UN17_V_ENABLELT2: stratix_lcell generic map (
1204     operation_mode => "normal",
1205     output_mode => "comb_only",
1206     synch_mode => "off",
1207      sum_lutc_input => "datac",
1208     lut_mask => "fefe")
1209 port map (
1210 combout => UN17_V_ENABLELT2,
1211 dataa => line_counter_sig_1,
1212 datab => line_counter_sig_2,
1213 datac => line_counter_sig_0,
1214         devpor => devpor,
1215         devclrn => devclrn,
1216         clk => GND,
1217         datad => VCC,
1218         aclr => GND,
1219         sclr => GND,
1220         sload => GND,
1221         ena => VCC,
1222         cin => GND,
1223         inverta => GND,
1224         aload => GND);
1225 DRAW_SQUARE_NEXT_UN5_V_ENABLELTO5_0: stratix_lcell generic map (
1226     operation_mode => "normal",
1227     output_mode => "comb_only",
1228     synch_mode => "off",
1229      sum_lutc_input => "datac",
1230     lut_mask => "eeee")
1231 port map (
1232 combout => UN5_V_ENABLELTO5_0,
1233 dataa => column_counter_sig_5,
1234 datab => column_counter_sig_4,
1235         devpor => devpor,
1236         devclrn => devclrn,
1237         clk => GND,
1238         datac => VCC,
1239         datad => VCC,
1240         aclr => GND,
1241         sclr => GND,
1242         sload => GND,
1243         ena => VCC,
1244         cin => GND,
1245         inverta => GND,
1246         aload => GND);
1247 \UN2_TOGGLE_COUNTER_NEXT_0_\: stratix_lcell generic map (
1248     operation_mode => "arithmetic",
1249     output_mode => "comb_only",
1250     synch_mode => "off",
1251      sum_lutc_input => "datac",
1252     lut_mask => "5588")
1253 port map (
1254 cout => UN2_TOGGLE_COUNTER_NEXT_COUT(0),
1255 dataa => TOGGLE_COUNTER_SIG_59,
1256 datab => TOGGLE_COUNTER_SIG_60,
1257         devpor => devpor,
1258         devclrn => devclrn,
1259         clk => GND,
1260         datac => VCC,
1261         datad => VCC,
1262         aclr => GND,
1263         sclr => GND,
1264         sload => GND,
1265         ena => VCC,
1266         cin => GND,
1267         inverta => GND,
1268         aload => GND);
1269 GND <= '0';
1270 VCC <= '1';
1271 TOGGLE_SIG_0_0_0_G1_I <= not TOGGLE_SIG_0_0_0_G1;
1272 toggle_counter_sig_0 <= TOGGLE_COUNTER_SIG_59;
1273 toggle_counter_sig_1 <= TOGGLE_COUNTER_SIG_60;
1274 toggle_counter_sig_2 <= TOGGLE_COUNTER_SIG_61;
1275 toggle_counter_sig_3 <= TOGGLE_COUNTER_SIG_62;
1276 toggle_counter_sig_4 <= TOGGLE_COUNTER_SIG_63;
1277 toggle_counter_sig_5 <= TOGGLE_COUNTER_SIG_64;
1278 toggle_counter_sig_6 <= TOGGLE_COUNTER_SIG_65;
1279 toggle_counter_sig_7 <= TOGGLE_COUNTER_SIG_66;
1280 toggle_counter_sig_8 <= TOGGLE_COUNTER_SIG_67;
1281 toggle_counter_sig_9 <= TOGGLE_COUNTER_SIG_68;
1282 toggle_counter_sig_10 <= TOGGLE_COUNTER_SIG_69;
1283 toggle_counter_sig_11 <= TOGGLE_COUNTER_SIG_70;
1284 toggle_counter_sig_12 <= TOGGLE_COUNTER_SIG_71;
1285 toggle_counter_sig_13 <= TOGGLE_COUNTER_SIG_72;
1286 toggle_counter_sig_14 <= TOGGLE_COUNTER_SIG_73;
1287 toggle_counter_sig_15 <= TOGGLE_COUNTER_SIG_74;
1288 toggle_counter_sig_16 <= TOGGLE_COUNTER_SIG_75;
1289 toggle_counter_sig_17 <= TOGGLE_COUNTER_SIG_76;
1290 toggle_counter_sig_18 <= TOGGLE_COUNTER_SIG_77;
1291 toggle_counter_sig_19 <= TOGGLE_COUNTER_SIG_78;
1292 toggle_counter_sig_20 <= TOGGLE_COUNTER_SIG_79;
1293 toggle_counter_sig_21 <= TOGGLE_COUNTER_SIG_80;
1294 toggle_counter_sig_22 <= TOGGLE_COUNTER_SIG_81;
1295 toggle_counter_sig_23 <= TOGGLE_COUNTER_SIG_82;
1296 toggle_counter_sig_24 <= TOGGLE_COUNTER_SIG_83;
1297 toggle_sig <= TOGGLE_SIG_84;
1298 end beh;
1299
1300 --
1301 library ieee, stratix;
1302 use ieee.std_logic_1164.all;
1303 use ieee.numeric_std.all;
1304 library synplify;
1305 use synplify.components.all;
1306 use stratix.stratix_components.all;
1307
1308 entity vga_driver is
1309 port(
1310 line_counter_sig_0 :  out std_logic;
1311 line_counter_sig_1 :  out std_logic;
1312 line_counter_sig_2 :  out std_logic;
1313 line_counter_sig_3 :  out std_logic;
1314 line_counter_sig_4 :  out std_logic;
1315 line_counter_sig_5 :  out std_logic;
1316 line_counter_sig_6 :  out std_logic;
1317 line_counter_sig_7 :  out std_logic;
1318 line_counter_sig_8 :  out std_logic;
1319 dly_counter_1 :  in std_logic;
1320 dly_counter_0 :  in std_logic;
1321 vsync_state_2 :  out std_logic;
1322 vsync_state_5 :  out std_logic;
1323 vsync_state_3 :  out std_logic;
1324 vsync_state_6 :  out std_logic;
1325 vsync_state_4 :  out std_logic;
1326 vsync_state_1 :  out std_logic;
1327 vsync_state_0 :  out std_logic;
1328 hsync_state_2 :  out std_logic;
1329 hsync_state_4 :  out std_logic;
1330 hsync_state_0 :  out std_logic;
1331 hsync_state_5 :  out std_logic;
1332 hsync_state_1 :  out std_logic;
1333 hsync_state_3 :  out std_logic;
1334 hsync_state_6 :  out std_logic;
1335 column_counter_sig_0 :  out std_logic;
1336 column_counter_sig_1 :  out std_logic;
1337 column_counter_sig_2 :  out std_logic;
1338 column_counter_sig_3 :  out std_logic;
1339 column_counter_sig_4 :  out std_logic;
1340 column_counter_sig_5 :  out std_logic;
1341 column_counter_sig_6 :  out std_logic;
1342 column_counter_sig_7 :  out std_logic;
1343 column_counter_sig_8 :  out std_logic;
1344 column_counter_sig_9 :  out std_logic;
1345 vsync_counter_9 :  out std_logic;
1346 vsync_counter_8 :  out std_logic;
1347 vsync_counter_7 :  out std_logic;
1348 vsync_counter_6 :  out std_logic;
1349 vsync_counter_5 :  out std_logic;
1350 vsync_counter_4 :  out std_logic;
1351 vsync_counter_3 :  out std_logic;
1352 vsync_counter_2 :  out std_logic;
1353 vsync_counter_1 :  out std_logic;
1354 vsync_counter_0 :  out std_logic;
1355 hsync_counter_9 :  out std_logic;
1356 hsync_counter_8 :  out std_logic;
1357 hsync_counter_7 :  out std_logic;
1358 hsync_counter_6 :  out std_logic;
1359 hsync_counter_5 :  out std_logic;
1360 hsync_counter_4 :  out std_logic;
1361 hsync_counter_3 :  out std_logic;
1362 hsync_counter_2 :  out std_logic;
1363 hsync_counter_1 :  out std_logic;
1364 hsync_counter_0 :  out std_logic;
1365 d_set_vsync_counter :  out std_logic;
1366 un10_column_counter_siglt6_1 :  out std_logic;
1367 v_sync :  out std_logic;
1368 h_sync :  out std_logic;
1369 h_enable_sig :  out std_logic;
1370 v_enable_sig :  out std_logic;
1371 reset_pin_c :  in std_logic;
1372 un6_dly_counter_0_x :  out std_logic;
1373 d_set_hsync_counter :  out std_logic;
1374 clk_pin_c :  in std_logic);
1375 end vga_driver;
1376
1377 architecture beh of vga_driver is
1378 signal devclrn : std_logic := '1';
1379 signal devpor : std_logic := '1';
1380 signal devoe : std_logic := '0';
1381 signal HSYNC_COUNTER_COUT : std_logic_vector(8 downto 0);
1382 signal VSYNC_COUNTER_COUT : std_logic_vector(8 downto 0);
1383 signal UN2_COLUMN_COUNTER_NEXT_COMBOUT : std_logic_vector(9 downto 1);
1384 signal UN1_LINE_COUNTER_SIG_COMBOUT : std_logic_vector(9 downto 1);
1385 signal UN1_LINE_COUNTER_SIG_COUT : std_logic_vector(7 downto 1);
1386 signal UN1_LINE_COUNTER_SIG_A_COUT : std_logic_vector(1 to 1);
1387 signal UN2_COLUMN_COUNTER_NEXT_COUT : std_logic_vector(7 downto 0);
1388 signal HSYNC_COUNTER_NEXT_1_SQMUXA : std_logic ;
1389 signal G_2_I : std_logic ;
1390 signal UN9_HSYNC_COUNTERLT9 : std_logic ;
1391 signal VSYNC_COUNTER_NEXT_1_SQMUXA : std_logic ;
1392 signal G_16_I : std_logic ;
1393 signal UN9_VSYNC_COUNTERLT9 : std_logic ;
1394 signal UN10_COLUMN_COUNTER_SIGLTO9 : std_logic ;
1395 signal COLUMN_COUNTER_NEXT_0_SQMUXA_1_1 : std_logic ;
1396 signal \VSYNC_STATE_3_IV_0_0__G0_0_A3_0\ : std_logic ;
1397 signal UN6_DLY_COUNTER_0_X_57 : std_logic ;
1398 signal VSYNC_STATE_NEXT_2_SQMUXA : std_logic ;
1399 signal UN12_VSYNC_COUNTER_7 : std_logic ;
1400 signal UN13_VSYNC_COUNTER_4 : std_logic ;
1401 signal UN10_LINE_COUNTER_SIGLTO8 : std_logic ;
1402 signal LINE_COUNTER_NEXT_0_SQMUXA_1_1 : std_logic ;
1403 signal V_ENABLE_SIG_1_0_0_0_G0_I_O4 : std_logic ;
1404 signal H_ENABLE_SIG_1_0_0_0_G0_I_O4 : std_logic ;
1405 signal H_SYNC_1_0_0_0_G1 : std_logic ;
1406 signal V_SYNC_1_0_0_0_G1 : std_logic ;
1407 signal UN14_VSYNC_COUNTER_8 : std_logic ;
1408 signal \HSYNC_STATE_3_0_0_0__G0_0\ : std_logic ;
1409 signal UN10_HSYNC_COUNTER_3 : std_logic ;
1410 signal UN10_HSYNC_COUNTER_1 : std_logic ;
1411 signal UN10_HSYNC_COUNTER_4 : std_logic ;
1412 signal UN12_HSYNC_COUNTER : std_logic ;
1413 signal UN11_HSYNC_COUNTER_2 : std_logic ;
1414 signal UN11_HSYNC_COUNTER_3 : std_logic ;
1415 signal UN13_HSYNC_COUNTER : std_logic ;
1416 signal VSYNC_STATE_NEXT_1_SQMUXA_1 : std_logic ;
1417 signal VSYNC_STATE_NEXT_1_SQMUXA_3 : std_logic ;
1418 signal UN1_VSYNC_STATE_NEXT_1_SQMUXA_0 : std_logic ;
1419 signal HSYNC_STATE_NEXT_1_SQMUXA_1 : std_logic ;
1420 signal HSYNC_STATE_NEXT_1_SQMUXA_2 : std_logic ;
1421 signal UN1_HSYNC_STATE_NEXT_1_SQMUXA_0 : std_logic ;
1422 signal UN12_VSYNC_COUNTER_6 : std_logic ;
1423 signal UN15_VSYNC_COUNTER_4 : std_logic ;
1424 signal VSYNC_STATE_NEXT_1_SQMUXA_2 : std_logic ;
1425 signal UN10_LINE_COUNTER_SIGLTO5 : std_logic ;
1426 signal UN10_COLUMN_COUNTER_SIGLT6 : std_logic ;
1427 signal UN12_HSYNC_COUNTER_3 : std_logic ;
1428 signal UN12_HSYNC_COUNTER_4 : std_logic ;
1429 signal UN13_HSYNC_COUNTER_2 : std_logic ;
1430 signal UN13_HSYNC_COUNTER_7 : std_logic ;
1431 signal UN9_HSYNC_COUNTERLT9_3 : std_logic ;
1432 signal UN9_VSYNC_COUNTERLT9_5 : std_logic ;
1433 signal UN9_VSYNC_COUNTERLT9_6 : std_logic ;
1434 signal UN10_LINE_COUNTER_SIGLT4_2 : std_logic ;
1435 signal UN13_VSYNC_COUNTER_3 : std_logic ;
1436 signal UN15_VSYNC_COUNTER_3 : std_logic ;
1437 signal UN10_COLUMN_COUNTER_SIGLT6_2 : std_logic ;
1438 signal D_SET_HSYNC_COUNTER_58 : std_logic ;
1439 signal H_SYNC_56 : std_logic ;
1440 signal UN1_HSYNC_STATE_3_0 : std_logic ;
1441 signal V_SYNC_55 : std_logic ;
1442 signal UN1_VSYNC_STATE_2_0 : std_logic ;
1443 signal UN10_COLUMN_COUNTER_SIGLT6_54 : std_logic ;
1444 signal D_SET_VSYNC_COUNTER_53 : std_logic ;
1445 signal VCC : std_logic ;
1446 signal LINE_COUNTER_SIG_0_0 : std_logic ;
1447 signal LINE_COUNTER_SIG_1_0 : std_logic ;
1448 signal LINE_COUNTER_SIG_2_0 : std_logic ;
1449 signal LINE_COUNTER_SIG_3_0 : std_logic ;
1450 signal LINE_COUNTER_SIG_4_0 : std_logic ;
1451 signal LINE_COUNTER_SIG_5_0 : std_logic ;
1452 signal LINE_COUNTER_SIG_6_0 : std_logic ;
1453 signal LINE_COUNTER_SIG_7_0 : std_logic ;
1454 signal LINE_COUNTER_SIG_8_0 : std_logic ;
1455 signal VSYNC_STATE_9 : std_logic ;
1456 signal VSYNC_STATE_10 : std_logic ;
1457 signal VSYNC_STATE_11 : std_logic ;
1458 signal VSYNC_STATE_12 : std_logic ;
1459 signal VSYNC_STATE_13 : std_logic ;
1460 signal VSYNC_STATE_14 : std_logic ;
1461 signal VSYNC_STATE_15 : std_logic ;
1462 signal HSYNC_STATE_16 : std_logic ;
1463 signal HSYNC_STATE_17 : std_logic ;
1464 signal HSYNC_STATE_18 : std_logic ;
1465 signal HSYNC_STATE_19 : std_logic ;
1466 signal HSYNC_STATE_20 : std_logic ;
1467 signal HSYNC_STATE_21 : std_logic ;
1468 signal HSYNC_STATE_22 : std_logic ;
1469 signal COLUMN_COUNTER_SIG_23 : std_logic ;
1470 signal COLUMN_COUNTER_SIG_24 : std_logic ;
1471 signal COLUMN_COUNTER_SIG_25 : std_logic ;
1472 signal COLUMN_COUNTER_SIG_26 : std_logic ;
1473 signal COLUMN_COUNTER_SIG_27 : std_logic ;
1474 signal COLUMN_COUNTER_SIG_28 : std_logic ;
1475 signal COLUMN_COUNTER_SIG_29 : std_logic ;
1476 signal COLUMN_COUNTER_SIG_30 : std_logic ;
1477 signal COLUMN_COUNTER_SIG_31 : std_logic ;
1478 signal COLUMN_COUNTER_SIG_32 : std_logic ;
1479 signal VSYNC_COUNTER_33 : std_logic ;
1480 signal VSYNC_COUNTER_34 : std_logic ;
1481 signal VSYNC_COUNTER_35 : std_logic ;
1482 signal VSYNC_COUNTER_36 : std_logic ;
1483 signal VSYNC_COUNTER_37 : std_logic ;
1484 signal VSYNC_COUNTER_38 : std_logic ;
1485 signal VSYNC_COUNTER_39 : std_logic ;
1486 signal VSYNC_COUNTER_40 : std_logic ;
1487 signal VSYNC_COUNTER_41 : std_logic ;
1488 signal VSYNC_COUNTER_42 : std_logic ;
1489 signal HSYNC_COUNTER_43 : std_logic ;
1490 signal HSYNC_COUNTER_44 : std_logic ;
1491 signal HSYNC_COUNTER_45 : std_logic ;
1492 signal HSYNC_COUNTER_46 : std_logic ;
1493 signal HSYNC_COUNTER_47 : std_logic ;
1494 signal HSYNC_COUNTER_48 : std_logic ;
1495 signal HSYNC_COUNTER_49 : std_logic ;
1496 signal HSYNC_COUNTER_50 : std_logic ;
1497 signal HSYNC_COUNTER_51 : std_logic ;
1498 signal HSYNC_COUNTER_52 : std_logic ;
1499 signal GND : std_logic ;
1500 signal LINE_COUNTER_NEXT_0_SQMUXA_1_1_I : std_logic ;
1501 signal COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I : std_logic ;
1502 signal G_16_I_I : std_logic ;
1503 signal UN9_VSYNC_COUNTERLT9_I : std_logic ;
1504 signal G_2_I_I : std_logic ;
1505 signal UN9_HSYNC_COUNTERLT9_I : std_logic ;
1506 begin
1507 \HSYNC_COUNTER_0_\: stratix_lcell generic map (
1508     operation_mode => "arithmetic",
1509     output_mode => "reg_and_comb",
1510     synch_mode => "on",
1511      sum_lutc_input => "datac",
1512     lut_mask => "55aa")
1513 port map (
1514 regout => HSYNC_COUNTER_52,
1515 cout => HSYNC_COUNTER_COUT(0),
1516 clk => clk_pin_c,
1517 dataa => HSYNC_COUNTER_52,
1518 datab => VCC,
1519 datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
1520 sclr => G_2_I_I,
1521 sload => UN9_HSYNC_COUNTERLT9_I,
1522         devpor => devpor,
1523         devclrn => devclrn,
1524         datad => VCC,
1525         aclr => GND,
1526         ena => VCC,
1527         cin => GND,
1528         inverta => GND,
1529         aload => GND);
1530 \HSYNC_COUNTER_1_\: stratix_lcell generic map (
1531     operation_mode => "arithmetic",
1532     output_mode => "reg_and_comb",
1533     synch_mode => "on",
1534      sum_lutc_input => "cin",
1535      cin_used => "true",
1536     lut_mask => "5aa0")
1537 port map (
1538 regout => HSYNC_COUNTER_51,
1539 cout => HSYNC_COUNTER_COUT(1),
1540 clk => clk_pin_c,
1541 dataa => HSYNC_COUNTER_51,
1542 datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
1543 sclr => G_2_I_I,
1544 sload => UN9_HSYNC_COUNTERLT9_I,
1545 cin => HSYNC_COUNTER_COUT(0),
1546         devpor => devpor,
1547         devclrn => devclrn,
1548         datab => VCC,
1549         datad => VCC,
1550         aclr => GND,
1551         ena => VCC,
1552         inverta => GND,
1553         aload => GND);
1554 \HSYNC_COUNTER_2_\: stratix_lcell generic map (
1555     operation_mode => "arithmetic",
1556     output_mode => "reg_and_comb",
1557     synch_mode => "on",
1558      sum_lutc_input => "cin",
1559      cin_used => "true",
1560     lut_mask => "5aa0")
1561 port map (
1562 regout => HSYNC_COUNTER_50,
1563 cout => HSYNC_COUNTER_COUT(2),
1564 clk => clk_pin_c,
1565 dataa => HSYNC_COUNTER_50,
1566 datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
1567 sclr => G_2_I_I,
1568 sload => UN9_HSYNC_COUNTERLT9_I,
1569 cin => HSYNC_COUNTER_COUT(1),
1570         devpor => devpor,
1571         devclrn => devclrn,
1572         datab => VCC,
1573         datad => VCC,
1574         aclr => GND,
1575         ena => VCC,
1576         inverta => GND,
1577         aload => GND);
1578 \HSYNC_COUNTER_3_\: stratix_lcell generic map (
1579     operation_mode => "arithmetic",
1580     output_mode => "reg_and_comb",
1581     synch_mode => "on",
1582      sum_lutc_input => "cin",
1583      cin_used => "true",
1584     lut_mask => "5aa0")
1585 port map (
1586 regout => HSYNC_COUNTER_49,
1587 cout => HSYNC_COUNTER_COUT(3),
1588 clk => clk_pin_c,
1589 dataa => HSYNC_COUNTER_49,
1590 datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
1591 sclr => G_2_I_I,
1592 sload => UN9_HSYNC_COUNTERLT9_I,
1593 cin => HSYNC_COUNTER_COUT(2),
1594         devpor => devpor,
1595         devclrn => devclrn,
1596         datab => VCC,
1597         datad => VCC,
1598         aclr => GND,
1599         ena => VCC,
1600         inverta => GND,
1601         aload => GND);
1602 \HSYNC_COUNTER_4_\: stratix_lcell generic map (
1603     operation_mode => "arithmetic",
1604     output_mode => "reg_and_comb",
1605     synch_mode => "on",
1606      sum_lutc_input => "cin",
1607      cin_used => "true",
1608     lut_mask => "5aa0")
1609 port map (
1610 regout => HSYNC_COUNTER_48,
1611 cout => HSYNC_COUNTER_COUT(4),
1612 clk => clk_pin_c,
1613 dataa => HSYNC_COUNTER_48,
1614 datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
1615 sclr => G_2_I_I,
1616 sload => UN9_HSYNC_COUNTERLT9_I,
1617 cin => HSYNC_COUNTER_COUT(3),
1618         devpor => devpor,
1619         devclrn => devclrn,
1620         datab => VCC,
1621         datad => VCC,
1622         aclr => GND,
1623         ena => VCC,
1624         inverta => GND,
1625         aload => GND);
1626 \HSYNC_COUNTER_5_\: stratix_lcell generic map (
1627     operation_mode => "arithmetic",
1628     output_mode => "reg_and_comb",
1629     synch_mode => "on",
1630      sum_lutc_input => "cin",
1631      cin_used => "true",
1632     lut_mask => "5aa0")
1633 port map (
1634 regout => HSYNC_COUNTER_47,
1635 cout => HSYNC_COUNTER_COUT(5),
1636 clk => clk_pin_c,
1637 dataa => HSYNC_COUNTER_47,
1638 datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
1639 sclr => G_2_I_I,
1640 sload => UN9_HSYNC_COUNTERLT9_I,
1641 cin => HSYNC_COUNTER_COUT(4),
1642         devpor => devpor,
1643         devclrn => devclrn,
1644         datab => VCC,
1645         datad => VCC,
1646         aclr => GND,
1647         ena => VCC,
1648         inverta => GND,
1649         aload => GND);
1650 \HSYNC_COUNTER_6_\: stratix_lcell generic map (
1651     operation_mode => "arithmetic",
1652     output_mode => "reg_and_comb",
1653     synch_mode => "on",
1654      sum_lutc_input => "cin",
1655      cin_used => "true",
1656     lut_mask => "5aa0")
1657 port map (
1658 regout => HSYNC_COUNTER_46,
1659 cout => HSYNC_COUNTER_COUT(6),
1660 clk => clk_pin_c,
1661 dataa => HSYNC_COUNTER_46,
1662 datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
1663 sclr => G_2_I_I,
1664 sload => UN9_HSYNC_COUNTERLT9_I,
1665 cin => HSYNC_COUNTER_COUT(5),
1666         devpor => devpor,
1667         devclrn => devclrn,
1668         datab => VCC,
1669         datad => VCC,
1670         aclr => GND,
1671         ena => VCC,
1672         inverta => GND,
1673         aload => GND);
1674 \HSYNC_COUNTER_7_\: stratix_lcell generic map (
1675     operation_mode => "arithmetic",
1676     output_mode => "reg_and_comb",
1677     synch_mode => "on",
1678      sum_lutc_input => "cin",
1679      cin_used => "true",
1680     lut_mask => "5aa0")
1681 port map (
1682 regout => HSYNC_COUNTER_45,
1683 cout => HSYNC_COUNTER_COUT(7),
1684 clk => clk_pin_c,
1685 dataa => HSYNC_COUNTER_45,
1686 datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
1687 sclr => G_2_I_I,
1688 sload => UN9_HSYNC_COUNTERLT9_I,
1689 cin => HSYNC_COUNTER_COUT(6),
1690         devpor => devpor,
1691         devclrn => devclrn,
1692         datab => VCC,
1693         datad => VCC,
1694         aclr => GND,
1695         ena => VCC,
1696         inverta => GND,
1697         aload => GND);
1698 \HSYNC_COUNTER_8_\: stratix_lcell generic map (
1699     operation_mode => "arithmetic",
1700     output_mode => "reg_and_comb",
1701     synch_mode => "on",
1702      sum_lutc_input => "cin",
1703      cin_used => "true",
1704     lut_mask => "5aa0")
1705 port map (
1706 regout => HSYNC_COUNTER_44,
1707 cout => HSYNC_COUNTER_COUT(8),
1708 clk => clk_pin_c,
1709 dataa => HSYNC_COUNTER_44,
1710 datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
1711 sclr => G_2_I_I,
1712 sload => UN9_HSYNC_COUNTERLT9_I,
1713 cin => HSYNC_COUNTER_COUT(7),
1714         devpor => devpor,
1715         devclrn => devclrn,
1716         datab => VCC,
1717         datad => VCC,
1718         aclr => GND,
1719         ena => VCC,
1720         inverta => GND,
1721         aload => GND);
1722 \HSYNC_COUNTER_9_\: stratix_lcell generic map (
1723     operation_mode => "normal",
1724     output_mode => "reg_only",
1725     synch_mode => "on",
1726      sum_lutc_input => "cin",
1727      cin_used => "true",
1728     lut_mask => "5a5a")
1729 port map (
1730 regout => HSYNC_COUNTER_43,
1731 clk => clk_pin_c,
1732 dataa => HSYNC_COUNTER_43,
1733 datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
1734 sclr => G_2_I_I,
1735 sload => UN9_HSYNC_COUNTERLT9_I,
1736 cin => HSYNC_COUNTER_COUT(8),
1737         devpor => devpor,
1738         devclrn => devclrn,
1739         datab => VCC,
1740         datad => VCC,
1741         aclr => GND,
1742         ena => VCC,
1743         inverta => GND,
1744         aload => GND);
1745 \VSYNC_COUNTER_0_\: stratix_lcell generic map (
1746     operation_mode => "arithmetic",
1747     output_mode => "reg_and_comb",
1748     synch_mode => "on",
1749      sum_lutc_input => "datac",
1750     lut_mask => "6688")
1751 port map (
1752 regout => VSYNC_COUNTER_42,
1753 cout => VSYNC_COUNTER_COUT(0),
1754 clk => clk_pin_c,
1755 dataa => VSYNC_COUNTER_42,
1756 datab => D_SET_HSYNC_COUNTER_58,
1757 datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
1758 sclr => G_16_I_I,
1759 sload => UN9_VSYNC_COUNTERLT9_I,
1760         devpor => devpor,
1761         devclrn => devclrn,
1762         datad => VCC,
1763         aclr => GND,
1764         ena => VCC,
1765         cin => GND,
1766         inverta => GND,
1767         aload => GND);
1768 \VSYNC_COUNTER_1_\: stratix_lcell generic map (
1769     operation_mode => "arithmetic",
1770     output_mode => "reg_and_comb",
1771     synch_mode => "on",
1772      sum_lutc_input => "cin",
1773      cin_used => "true",
1774     lut_mask => "5aa0")
1775 port map (
1776 regout => VSYNC_COUNTER_41,
1777 cout => VSYNC_COUNTER_COUT(1),
1778 clk => clk_pin_c,
1779 dataa => VSYNC_COUNTER_41,
1780 datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
1781 sclr => G_16_I_I,
1782 sload => UN9_VSYNC_COUNTERLT9_I,
1783 cin => VSYNC_COUNTER_COUT(0),
1784         devpor => devpor,
1785         devclrn => devclrn,
1786         datab => VCC,
1787         datad => VCC,
1788         aclr => GND,
1789         ena => VCC,
1790         inverta => GND,
1791         aload => GND);
1792 \VSYNC_COUNTER_2_\: stratix_lcell generic map (
1793     operation_mode => "arithmetic",
1794     output_mode => "reg_and_comb",
1795     synch_mode => "on",
1796      sum_lutc_input => "cin",
1797      cin_used => "true",
1798     lut_mask => "5aa0")
1799 port map (
1800 regout => VSYNC_COUNTER_40,
1801 cout => VSYNC_COUNTER_COUT(2),
1802 clk => clk_pin_c,
1803 dataa => VSYNC_COUNTER_40,
1804 datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
1805 sclr => G_16_I_I,
1806 sload => UN9_VSYNC_COUNTERLT9_I,
1807 cin => VSYNC_COUNTER_COUT(1),
1808         devpor => devpor,
1809         devclrn => devclrn,
1810         datab => VCC,
1811         datad => VCC,
1812         aclr => GND,
1813         ena => VCC,
1814         inverta => GND,
1815         aload => GND);
1816 \VSYNC_COUNTER_3_\: stratix_lcell generic map (
1817     operation_mode => "arithmetic",
1818     output_mode => "reg_and_comb",
1819     synch_mode => "on",
1820      sum_lutc_input => "cin",
1821      cin_used => "true",
1822     lut_mask => "5aa0")
1823 port map (
1824 regout => VSYNC_COUNTER_39,
1825 cout => VSYNC_COUNTER_COUT(3),
1826 clk => clk_pin_c,
1827 dataa => VSYNC_COUNTER_39,
1828 datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
1829 sclr => G_16_I_I,
1830 sload => UN9_VSYNC_COUNTERLT9_I,
1831 cin => VSYNC_COUNTER_COUT(2),
1832         devpor => devpor,
1833         devclrn => devclrn,
1834         datab => VCC,
1835         datad => VCC,
1836         aclr => GND,
1837         ena => VCC,
1838         inverta => GND,
1839         aload => GND);
1840 \VSYNC_COUNTER_4_\: stratix_lcell generic map (
1841     operation_mode => "arithmetic",
1842     output_mode => "reg_and_comb",
1843     synch_mode => "on",
1844      sum_lutc_input => "cin",
1845      cin_used => "true",
1846     lut_mask => "5aa0")
1847 port map (
1848 regout => VSYNC_COUNTER_38,
1849 cout => VSYNC_COUNTER_COUT(4),
1850 clk => clk_pin_c,
1851 dataa => VSYNC_COUNTER_38,
1852 datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
1853 sclr => G_16_I_I,
1854 sload => UN9_VSYNC_COUNTERLT9_I,
1855 cin => VSYNC_COUNTER_COUT(3),
1856         devpor => devpor,
1857         devclrn => devclrn,
1858         datab => VCC,
1859         datad => VCC,
1860         aclr => GND,
1861         ena => VCC,
1862         inverta => GND,
1863         aload => GND);
1864 \VSYNC_COUNTER_5_\: stratix_lcell generic map (
1865     operation_mode => "arithmetic",
1866     output_mode => "reg_and_comb",
1867     synch_mode => "on",
1868      sum_lutc_input => "cin",
1869      cin_used => "true",
1870     lut_mask => "5aa0")
1871 port map (
1872 regout => VSYNC_COUNTER_37,
1873 cout => VSYNC_COUNTER_COUT(5),
1874 clk => clk_pin_c,
1875 dataa => VSYNC_COUNTER_37,
1876 datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
1877 sclr => G_16_I_I,
1878 sload => UN9_VSYNC_COUNTERLT9_I,
1879 cin => VSYNC_COUNTER_COUT(4),
1880         devpor => devpor,
1881         devclrn => devclrn,
1882         datab => VCC,
1883         datad => VCC,
1884         aclr => GND,
1885         ena => VCC,
1886         inverta => GND,
1887         aload => GND);
1888 \VSYNC_COUNTER_6_\: stratix_lcell generic map (
1889     operation_mode => "arithmetic",
1890     output_mode => "reg_and_comb",
1891     synch_mode => "on",
1892      sum_lutc_input => "cin",
1893      cin_used => "true",
1894     lut_mask => "5aa0")
1895 port map (
1896 regout => VSYNC_COUNTER_36,
1897 cout => VSYNC_COUNTER_COUT(6),
1898 clk => clk_pin_c,
1899 dataa => VSYNC_COUNTER_36,
1900 datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
1901 sclr => G_16_I_I,
1902 sload => UN9_VSYNC_COUNTERLT9_I,
1903 cin => VSYNC_COUNTER_COUT(5),
1904         devpor => devpor,
1905         devclrn => devclrn,
1906         datab => VCC,
1907         datad => VCC,
1908         aclr => GND,
1909         ena => VCC,
1910         inverta => GND,
1911         aload => GND);
1912 \VSYNC_COUNTER_7_\: stratix_lcell generic map (
1913     operation_mode => "arithmetic",
1914     output_mode => "reg_and_comb",
1915     synch_mode => "on",
1916      sum_lutc_input => "cin",
1917      cin_used => "true",
1918     lut_mask => "5aa0")
1919 port map (
1920 regout => VSYNC_COUNTER_35,
1921 cout => VSYNC_COUNTER_COUT(7),
1922 clk => clk_pin_c,
1923 dataa => VSYNC_COUNTER_35,
1924 datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
1925 sclr => G_16_I_I,
1926 sload => UN9_VSYNC_COUNTERLT9_I,
1927 cin => VSYNC_COUNTER_COUT(6),
1928         devpor => devpor,
1929         devclrn => devclrn,
1930         datab => VCC,
1931         datad => VCC,
1932         aclr => GND,
1933         ena => VCC,
1934         inverta => GND,
1935         aload => GND);
1936 \VSYNC_COUNTER_8_\: stratix_lcell generic map (
1937     operation_mode => "arithmetic",
1938     output_mode => "reg_and_comb",
1939     synch_mode => "on",
1940      sum_lutc_input => "cin",
1941      cin_used => "true",
1942     lut_mask => "5aa0")
1943 port map (
1944 regout => VSYNC_COUNTER_34,
1945 cout => VSYNC_COUNTER_COUT(8),
1946 clk => clk_pin_c,
1947 dataa => VSYNC_COUNTER_34,
1948 datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
1949 sclr => G_16_I_I,
1950 sload => UN9_VSYNC_COUNTERLT9_I,
1951 cin => VSYNC_COUNTER_COUT(7),
1952         devpor => devpor,
1953         devclrn => devclrn,
1954         datab => VCC,
1955         datad => VCC,
1956         aclr => GND,
1957         ena => VCC,
1958         inverta => GND,
1959         aload => GND);
1960 \VSYNC_COUNTER_9_\: stratix_lcell generic map (
1961     operation_mode => "normal",
1962     output_mode => "reg_only",
1963     synch_mode => "on",
1964      sum_lutc_input => "cin",
1965      cin_used => "true",
1966     lut_mask => "5a5a")
1967 port map (
1968 regout => VSYNC_COUNTER_33,
1969 clk => clk_pin_c,
1970 dataa => VSYNC_COUNTER_33,
1971 datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
1972 sclr => G_16_I_I,
1973 sload => UN9_VSYNC_COUNTERLT9_I,
1974 cin => VSYNC_COUNTER_COUT(8),
1975         devpor => devpor,
1976         devclrn => devclrn,
1977         datab => VCC,
1978         datad => VCC,
1979         aclr => GND,
1980         ena => VCC,
1981         inverta => GND,
1982         aload => GND);
1983 \COLUMN_COUNTER_SIG_9_\: stratix_lcell generic map (
1984     operation_mode => "normal",
1985     output_mode => "reg_only",
1986     synch_mode => "on",
1987      sum_lutc_input => "datac",
1988     lut_mask => "bbbb")
1989 port map (
1990 regout => COLUMN_COUNTER_SIG_32,
1991 clk => clk_pin_c,
1992 dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(9),
1993 datab => UN10_COLUMN_COUNTER_SIGLTO9,
1994 sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
1995         devpor => devpor,
1996         devclrn => devclrn,
1997         datac => VCC,
1998         datad => VCC,
1999         aclr => GND,
2000         sload => GND,
2001         ena => VCC,
2002         cin => GND,
2003         inverta => GND,
2004         aload => GND);
2005 \COLUMN_COUNTER_SIG_8_\: stratix_lcell generic map (
2006     operation_mode => "normal",
2007     output_mode => "reg_only",
2008     synch_mode => "off",
2009      sum_lutc_input => "datac",
2010     lut_mask => "8080")
2011 port map (
2012 regout => COLUMN_COUNTER_SIG_31,
2013 clk => clk_pin_c,
2014 dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(8),
2015 datab => UN10_COLUMN_COUNTER_SIGLTO9,
2016 datac => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1,
2017         devpor => devpor,
2018         devclrn => devclrn,
2019         datad => VCC,
2020         aclr => GND,
2021         sclr => GND,
2022         sload => GND,
2023         ena => VCC,
2024         cin => GND,
2025         inverta => GND,
2026         aload => GND);
2027 \COLUMN_COUNTER_SIG_7_\: stratix_lcell generic map (
2028     operation_mode => "normal",
2029     output_mode => "reg_only",
2030     synch_mode => "off",
2031      sum_lutc_input => "datac",
2032     lut_mask => "8080")
2033 port map (
2034 regout => COLUMN_COUNTER_SIG_30,
2035 clk => clk_pin_c,
2036 dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(7),
2037 datab => UN10_COLUMN_COUNTER_SIGLTO9,
2038 datac => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1,
2039         devpor => devpor,
2040         devclrn => devclrn,
2041         datad => VCC,
2042         aclr => GND,
2043         sclr => GND,
2044         sload => GND,
2045         ena => VCC,
2046         cin => GND,
2047         inverta => GND,
2048         aload => GND);
2049 \COLUMN_COUNTER_SIG_6_\: stratix_lcell generic map (
2050     operation_mode => "normal",
2051     output_mode => "reg_only",
2052     synch_mode => "on",
2053      sum_lutc_input => "datac",
2054     lut_mask => "bbbb")
2055 port map (
2056 regout => COLUMN_COUNTER_SIG_29,
2057 clk => clk_pin_c,
2058 dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(6),
2059 datab => UN10_COLUMN_COUNTER_SIGLTO9,
2060 sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
2061         devpor => devpor,
2062         devclrn => devclrn,
2063         datac => VCC,
2064         datad => VCC,
2065         aclr => GND,
2066         sload => GND,
2067         ena => VCC,
2068         cin => GND,
2069         inverta => GND,
2070         aload => GND);
2071 \COLUMN_COUNTER_SIG_5_\: stratix_lcell generic map (
2072     operation_mode => "normal",
2073     output_mode => "reg_only",
2074     synch_mode => "on",
2075      sum_lutc_input => "datac",
2076     lut_mask => "bbbb")
2077 port map (
2078 regout => COLUMN_COUNTER_SIG_28,
2079 clk => clk_pin_c,
2080 dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(5),
2081 datab => UN10_COLUMN_COUNTER_SIGLTO9,
2082 sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
2083         devpor => devpor,
2084         devclrn => devclrn,
2085         datac => VCC,
2086         datad => VCC,
2087         aclr => GND,
2088         sload => GND,
2089         ena => VCC,
2090         cin => GND,
2091         inverta => GND,
2092         aload => GND);
2093 \COLUMN_COUNTER_SIG_4_\: stratix_lcell generic map (
2094     operation_mode => "normal",
2095     output_mode => "reg_only",
2096     synch_mode => "on",
2097      sum_lutc_input => "datac",
2098     lut_mask => "bbbb")
2099 port map (
2100 regout => COLUMN_COUNTER_SIG_27,
2101 clk => clk_pin_c,
2102 dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(4),
2103 datab => UN10_COLUMN_COUNTER_SIGLTO9,
2104 sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
2105         devpor => devpor,
2106         devclrn => devclrn,
2107         datac => VCC,
2108         datad => VCC,
2109         aclr => GND,
2110         sload => GND,
2111         ena => VCC,
2112         cin => GND,
2113         inverta => GND,
2114         aload => GND);
2115 \COLUMN_COUNTER_SIG_3_\: stratix_lcell generic map (
2116     operation_mode => "normal",
2117     output_mode => "reg_only",
2118     synch_mode => "on",
2119      sum_lutc_input => "datac",
2120     lut_mask => "bbbb")
2121 port map (
2122 regout => COLUMN_COUNTER_SIG_26,
2123 clk => clk_pin_c,
2124 dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(3),
2125 datab => UN10_COLUMN_COUNTER_SIGLTO9,
2126 sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
2127         devpor => devpor,
2128         devclrn => devclrn,
2129         datac => VCC,
2130         datad => VCC,
2131         aclr => GND,
2132         sload => GND,
2133         ena => VCC,
2134         cin => GND,
2135         inverta => GND,
2136         aload => GND);
2137 \COLUMN_COUNTER_SIG_2_\: stratix_lcell generic map (
2138     operation_mode => "normal",
2139     output_mode => "reg_only",
2140     synch_mode => "on",
2141      sum_lutc_input => "datac",
2142     lut_mask => "bbbb")
2143 port map (
2144 regout => COLUMN_COUNTER_SIG_25,
2145 clk => clk_pin_c,
2146 dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(2),
2147 datab => UN10_COLUMN_COUNTER_SIGLTO9,
2148 sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
2149         devpor => devpor,
2150         devclrn => devclrn,
2151         datac => VCC,
2152         datad => VCC,
2153         aclr => GND,
2154         sload => GND,
2155         ena => VCC,
2156         cin => GND,
2157         inverta => GND,
2158         aload => GND);
2159 \COLUMN_COUNTER_SIG_1_\: stratix_lcell generic map (
2160     operation_mode => "normal",
2161     output_mode => "reg_only",
2162     synch_mode => "on",
2163      sum_lutc_input => "datac",
2164     lut_mask => "bbbb")
2165 port map (
2166 regout => COLUMN_COUNTER_SIG_24,
2167 clk => clk_pin_c,
2168 dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(1),
2169 datab => UN10_COLUMN_COUNTER_SIGLTO9,
2170 sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
2171         devpor => devpor,
2172         devclrn => devclrn,
2173         datac => VCC,
2174         datad => VCC,
2175         aclr => GND,
2176         sload => GND,
2177         ena => VCC,
2178         cin => GND,
2179         inverta => GND,
2180         aload => GND);
2181 \COLUMN_COUNTER_SIG_0_\: stratix_lcell generic map (
2182     operation_mode => "normal",
2183     output_mode => "reg_only",
2184     synch_mode => "on",
2185      sum_lutc_input => "datac",
2186     lut_mask => "7777")
2187 port map (
2188 regout => COLUMN_COUNTER_SIG_23,
2189 clk => clk_pin_c,
2190 dataa => COLUMN_COUNTER_SIG_23,
2191 datab => UN10_COLUMN_COUNTER_SIGLTO9,
2192 sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
2193         devpor => devpor,
2194         devclrn => devclrn,
2195         datac => VCC,
2196         datad => VCC,
2197         aclr => GND,
2198         sload => GND,
2199         ena => VCC,
2200         cin => GND,
2201         inverta => GND,
2202         aload => GND);
2203 \HSYNC_STATE_6_\: stratix_lcell generic map (
2204     operation_mode => "normal",
2205     output_mode => "reg_only",
2206     synch_mode => "off",
2207      sum_lutc_input => "datac",
2208     lut_mask => "ff00")
2209 port map (
2210 regout => HSYNC_STATE_22,
2211 clk => clk_pin_c,
2212 datad => UN6_DLY_COUNTER_0_X_57,
2213         devpor => devpor,
2214         devclrn => devclrn,
2215         dataa => VCC,
2216         datab => VCC,
2217         datac => VCC,
2218         aclr => GND,
2219         sclr => GND,
2220         sload => GND,
2221         ena => VCC,
2222         cin => GND,
2223         inverta => GND,
2224         aload => GND);
2225 \VSYNC_STATE_0_\: stratix_lcell generic map (
2226     operation_mode => "normal",
2227     output_mode => "reg_only",
2228     synch_mode => "off",
2229      sum_lutc_input => "datac",
2230     lut_mask => "0cae")
2231 port map (
2232 regout => VSYNC_STATE_15,
2233 clk => clk_pin_c,
2234 dataa => VSYNC_STATE_15,
2235 datab => \VSYNC_STATE_3_IV_0_0__G0_0_A3_0\,
2236 datac => UN6_DLY_COUNTER_0_X_57,
2237 datad => VSYNC_STATE_NEXT_2_SQMUXA,
2238         devpor => devpor,
2239         devclrn => devclrn,
2240         aclr => GND,
2241         sclr => GND,
2242         sload => GND,
2243         ena => VCC,
2244         cin => GND,
2245         inverta => GND,
2246         aload => GND);
2247 \VSYNC_STATE_1_\: stratix_lcell generic map (
2248     operation_mode => "normal",
2249     output_mode => "reg_only",
2250     synch_mode => "off",
2251      sum_lutc_input => "datac",
2252     lut_mask => "0080")
2253 port map (
2254 regout => VSYNC_STATE_14,
2255 clk => clk_pin_c,
2256 dataa => VSYNC_STATE_13,
2257 datab => UN12_VSYNC_COUNTER_7,
2258 datac => UN13_VSYNC_COUNTER_4,
2259 datad => UN6_DLY_COUNTER_0_X_57,
2260         devpor => devpor,
2261         devclrn => devclrn,
2262         aclr => GND,
2263         sclr => GND,
2264         sload => GND,
2265         ena => VCC,
2266         cin => GND,
2267         inverta => GND,
2268         aload => GND);
2269 \VSYNC_STATE_6_\: stratix_lcell generic map (
2270     operation_mode => "normal",
2271     output_mode => "reg_and_comb",
2272     synch_mode => "off",
2273      sum_lutc_input => "datac",
2274     lut_mask => "7f7f")
2275 port map (
2276 combout => UN6_DLY_COUNTER_0_X_57,
2277 regout => VSYNC_STATE_12,
2278 clk => clk_pin_c,
2279 dataa => reset_pin_c,
2280 datab => dly_counter_0,
2281 datac => dly_counter_1,
2282         devpor => devpor,
2283         devclrn => devclrn,
2284         datad => VCC,
2285         aclr => GND,
2286         sclr => GND,
2287         sload => GND,
2288         ena => VCC,
2289         cin => GND,
2290         inverta => GND,
2291         aload => GND);
2292 \LINE_COUNTER_SIG_8_\: stratix_lcell generic map (
2293     operation_mode => "normal",
2294     output_mode => "reg_only",
2295     synch_mode => "on",
2296      sum_lutc_input => "datac",
2297     lut_mask => "dddd")
2298 port map (
2299 regout => LINE_COUNTER_SIG_8_0,
2300 clk => clk_pin_c,
2301 dataa => UN10_LINE_COUNTER_SIGLTO8,
2302 datab => UN1_LINE_COUNTER_SIG_COMBOUT(9),
2303 sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
2304         devpor => devpor,
2305         devclrn => devclrn,
2306         datac => VCC,
2307         datad => VCC,
2308         aclr => GND,
2309         sload => GND,
2310         ena => VCC,
2311         cin => GND,
2312         inverta => GND,
2313         aload => GND);
2314 \LINE_COUNTER_SIG_7_\: stratix_lcell generic map (
2315     operation_mode => "normal",
2316     output_mode => "reg_only",
2317     synch_mode => "on",
2318      sum_lutc_input => "datac",
2319     lut_mask => "dddd")
2320 port map (
2321 regout => LINE_COUNTER_SIG_7_0,
2322 clk => clk_pin_c,
2323 dataa => UN10_LINE_COUNTER_SIGLTO8,
2324 datab => UN1_LINE_COUNTER_SIG_COMBOUT(8),
2325 sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
2326         devpor => devpor,
2327         devclrn => devclrn,
2328         datac => VCC,
2329         datad => VCC,
2330         aclr => GND,
2331         sload => GND,
2332         ena => VCC,
2333         cin => GND,
2334         inverta => GND,
2335         aload => GND);
2336 \LINE_COUNTER_SIG_6_\: stratix_lcell generic map (
2337     operation_mode => "normal",
2338     output_mode => "reg_only",
2339     synch_mode => "on",
2340      sum_lutc_input => "datac",
2341     lut_mask => "dddd")
2342 port map (
2343 regout => LINE_COUNTER_SIG_6_0,
2344 clk => clk_pin_c,
2345 dataa => UN10_LINE_COUNTER_SIGLTO8,
2346 datab => UN1_LINE_COUNTER_SIG_COMBOUT(7),
2347 sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
2348         devpor => devpor,
2349         devclrn => devclrn,
2350         datac => VCC,
2351         datad => VCC,
2352         aclr => GND,
2353         sload => GND,
2354         ena => VCC,
2355         cin => GND,
2356         inverta => GND,
2357         aload => GND);
2358 \LINE_COUNTER_SIG_5_\: stratix_lcell generic map (
2359     operation_mode => "normal",
2360     output_mode => "reg_only",
2361     synch_mode => "off",
2362      sum_lutc_input => "datac",
2363     lut_mask => "8080")
2364 port map (
2365 regout => LINE_COUNTER_SIG_5_0,
2366 clk => clk_pin_c,
2367 dataa => UN10_LINE_COUNTER_SIGLTO8,
2368 datab => UN1_LINE_COUNTER_SIG_COMBOUT(6),
2369 datac => LINE_COUNTER_NEXT_0_SQMUXA_1_1,
2370         devpor => devpor,
2371         devclrn => devclrn,
2372         datad => VCC,
2373         aclr => GND,
2374         sclr => GND,
2375         sload => GND,
2376         ena => VCC,
2377         cin => GND,
2378         inverta => GND,
2379         aload => GND);
2380 \LINE_COUNTER_SIG_4_\: stratix_lcell generic map (
2381     operation_mode => "normal",
2382     output_mode => "reg_only",
2383     synch_mode => "on",
2384      sum_lutc_input => "datac",
2385     lut_mask => "dddd")
2386 port map (
2387 regout => LINE_COUNTER_SIG_4_0,
2388 clk => clk_pin_c,
2389 dataa => UN10_LINE_COUNTER_SIGLTO8,
2390 datab => UN1_LINE_COUNTER_SIG_COMBOUT(5),
2391 sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
2392         devpor => devpor,
2393         devclrn => devclrn,
2394         datac => VCC,
2395         datad => VCC,
2396         aclr => GND,
2397         sload => GND,
2398         ena => VCC,
2399         cin => GND,
2400         inverta => GND,
2401         aload => GND);
2402 \LINE_COUNTER_SIG_3_\: stratix_lcell generic map (
2403     operation_mode => "normal",
2404     output_mode => "reg_only",
2405     synch_mode => "on",
2406      sum_lutc_input => "datac",
2407     lut_mask => "dddd")
2408 port map (
2409 regout => LINE_COUNTER_SIG_3_0,
2410 clk => clk_pin_c,
2411 dataa => UN10_LINE_COUNTER_SIGLTO8,
2412 datab => UN1_LINE_COUNTER_SIG_COMBOUT(4),
2413 sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
2414         devpor => devpor,
2415         devclrn => devclrn,
2416         datac => VCC,
2417         datad => VCC,
2418         aclr => GND,
2419         sload => GND,
2420         ena => VCC,
2421         cin => GND,
2422         inverta => GND,
2423         aload => GND);
2424 \LINE_COUNTER_SIG_2_\: stratix_lcell generic map (
2425     operation_mode => "normal",
2426     output_mode => "reg_only",
2427     synch_mode => "on",
2428      sum_lutc_input => "datac",
2429     lut_mask => "dddd")
2430 port map (
2431 regout => LINE_COUNTER_SIG_2_0,
2432 clk => clk_pin_c,
2433 dataa => UN10_LINE_COUNTER_SIGLTO8,
2434 datab => UN1_LINE_COUNTER_SIG_COMBOUT(3),
2435 sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
2436         devpor => devpor,
2437         devclrn => devclrn,
2438         datac => VCC,
2439         datad => VCC,
2440         aclr => GND,
2441         sload => GND,
2442         ena => VCC,
2443         cin => GND,
2444         inverta => GND,
2445         aload => GND);
2446 \LINE_COUNTER_SIG_1_\: stratix_lcell generic map (
2447     operation_mode => "normal",
2448     output_mode => "reg_only",
2449     synch_mode => "on",
2450      sum_lutc_input => "datac",
2451     lut_mask => "dddd")
2452 port map (
2453 regout => LINE_COUNTER_SIG_1_0,
2454 clk => clk_pin_c,
2455 dataa => UN10_LINE_COUNTER_SIGLTO8,
2456 datab => UN1_LINE_COUNTER_SIG_COMBOUT(2),
2457 sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
2458         devpor => devpor,
2459         devclrn => devclrn,
2460         datac => VCC,
2461         datad => VCC,
2462         aclr => GND,
2463         sload => GND,
2464         ena => VCC,
2465         cin => GND,
2466         inverta => GND,
2467         aload => GND);
2468 \LINE_COUNTER_SIG_0_\: stratix_lcell generic map (
2469     operation_mode => "normal",
2470     output_mode => "reg_only",
2471     synch_mode => "on",
2472      sum_lutc_input => "datac",
2473     lut_mask => "bbbb")
2474 port map (
2475 regout => LINE_COUNTER_SIG_0_0,
2476 clk => clk_pin_c,
2477 dataa => UN1_LINE_COUNTER_SIG_COMBOUT(1),
2478 datab => UN10_LINE_COUNTER_SIGLTO8,
2479 sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
2480         devpor => devpor,
2481         devclrn => devclrn,
2482         datac => VCC,
2483         datad => VCC,
2484         aclr => GND,
2485         sload => GND,
2486         ena => VCC,
2487         cin => GND,
2488         inverta => GND,
2489         aload => GND);
2490 V_ENABLE_SIG_Z285: stratix_lcell generic map (
2491     operation_mode => "normal",
2492     output_mode => "reg_only",
2493     synch_mode => "on",
2494      sum_lutc_input => "datac",
2495     lut_mask => "eeee")
2496 port map (
2497 regout => v_enable_sig,
2498 clk => clk_pin_c,
2499 dataa => HSYNC_STATE_21,
2500 datab => HSYNC_STATE_20,
2501 sclr => UN6_DLY_COUNTER_0_X_57,
2502 ena => V_ENABLE_SIG_1_0_0_0_G0_I_O4,
2503         devpor => devpor,
2504         devclrn => devclrn,
2505         datac => VCC,
2506         datad => VCC,
2507         aclr => GND,
2508         sload => GND,
2509         cin => GND,
2510         inverta => GND,
2511         aload => GND);
2512 H_ENABLE_SIG_Z286: stratix_lcell generic map (
2513     operation_mode => "normal",
2514     output_mode => "reg_only",
2515     synch_mode => "on",
2516      sum_lutc_input => "datac",
2517     lut_mask => "eeee")
2518 port map (
2519 regout => h_enable_sig,
2520 clk => clk_pin_c,
2521 dataa => VSYNC_STATE_11,
2522 datab => VSYNC_STATE_14,
2523 sclr => UN6_DLY_COUNTER_0_X_57,
2524 ena => H_ENABLE_SIG_1_0_0_0_G0_I_O4,
2525         devpor => devpor,
2526         devclrn => devclrn,
2527         datac => VCC,
2528         datad => VCC,
2529         aclr => GND,
2530         sload => GND,
2531         cin => GND,
2532         inverta => GND,
2533         aload => GND);
2534 H_SYNC_Z287: stratix_lcell generic map (
2535     operation_mode => "normal",
2536     output_mode => "reg_only",
2537     synch_mode => "off",
2538      sum_lutc_input => "datac",
2539     lut_mask => "ff7f")
2540 port map (
2541 regout => H_SYNC_56,
2542 clk => clk_pin_c,
2543 dataa => reset_pin_c,
2544 datab => dly_counter_0,
2545 datac => dly_counter_1,
2546 datad => H_SYNC_1_0_0_0_G1,
2547         devpor => devpor,
2548         devclrn => devclrn,
2549         aclr => GND,
2550         sclr => GND,
2551         sload => GND,
2552         ena => VCC,
2553         cin => GND,
2554         inverta => GND,
2555         aload => GND);
2556 V_SYNC_Z288: stratix_lcell generic map (
2557     operation_mode => "normal",
2558     output_mode => "reg_only",
2559     synch_mode => "off",
2560      sum_lutc_input => "datac",
2561     lut_mask => "ff7f")
2562 port map (
2563 regout => V_SYNC_55,
2564 clk => clk_pin_c,
2565 dataa => reset_pin_c,
2566 datab => dly_counter_0,
2567 datac => dly_counter_1,
2568 datad => V_SYNC_1_0_0_0_G1,
2569         devpor => devpor,
2570         devclrn => devclrn,
2571         aclr => GND,
2572         sclr => GND,
2573         sload => GND,
2574         ena => VCC,
2575         cin => GND,
2576         inverta => GND,
2577         aload => GND);
2578 \VSYNC_STATE_5_\: stratix_lcell generic map (
2579     operation_mode => "normal",
2580     output_mode => "reg_only",
2581     synch_mode => "on",
2582      sum_lutc_input => "datac",
2583     lut_mask => "eeee")
2584 port map (
2585 regout => VSYNC_STATE_10,
2586 clk => clk_pin_c,
2587 dataa => VSYNC_STATE_12,
2588 datab => VSYNC_STATE_15,
2589 sclr => UN6_DLY_COUNTER_0_X_57,
2590 ena => VSYNC_STATE_NEXT_2_SQMUXA,
2591         devpor => devpor,
2592         devclrn => devclrn,
2593         datac => VCC,
2594         datad => VCC,
2595         aclr => GND,
2596         sload => GND,
2597         cin => GND,
2598         inverta => GND,
2599         aload => GND);
2600 \VSYNC_STATE_4_\: stratix_lcell generic map (
2601     operation_mode => "normal",
2602     output_mode => "reg_only",
2603     synch_mode => "on",
2604      sum_lutc_input => "datac",
2605     lut_mask => "2000")
2606 port map (
2607 regout => VSYNC_STATE_13,
2608 clk => clk_pin_c,
2609 dataa => VSYNC_COUNTER_42,
2610 datab => VSYNC_COUNTER_33,
2611 datac => VSYNC_STATE_10,
2612 datad => UN14_VSYNC_COUNTER_8,
2613 sclr => UN6_DLY_COUNTER_0_X_57,
2614 ena => VSYNC_STATE_NEXT_2_SQMUXA,
2615         devpor => devpor,
2616         devclrn => devclrn,
2617         aclr => GND,
2618         sload => GND,
2619         cin => GND,
2620         inverta => GND,
2621         aload => GND);
2622 \VSYNC_STATE_3_\: stratix_lcell generic map (
2623     operation_mode => "normal",
2624     output_mode => "reg_only",
2625     synch_mode => "on",
2626      sum_lutc_input => "datac",
2627     lut_mask => "aaaa")
2628 port map (
2629 regout => VSYNC_STATE_11,
2630 clk => clk_pin_c,
2631 dataa => VSYNC_STATE_14,
2632 sclr => UN6_DLY_COUNTER_0_X_57,
2633 ena => VSYNC_STATE_NEXT_2_SQMUXA,
2634         devpor => devpor,
2635         devclrn => devclrn,
2636         datab => VCC,
2637         datac => VCC,
2638         datad => VCC,
2639         aclr => GND,
2640         sload => GND,
2641         cin => GND,
2642         inverta => GND,
2643         aload => GND);
2644 \VSYNC_STATE_2_\: stratix_lcell generic map (
2645     operation_mode => "normal",
2646     output_mode => "reg_only",
2647     synch_mode => "on",
2648      sum_lutc_input => "datac",
2649     lut_mask => "8000")
2650 port map (
2651 regout => VSYNC_STATE_9,
2652 clk => clk_pin_c,
2653 dataa => VSYNC_COUNTER_42,
2654 datab => VSYNC_COUNTER_33,
2655 datac => VSYNC_STATE_11,
2656 datad => UN14_VSYNC_COUNTER_8,
2657 sclr => UN6_DLY_COUNTER_0_X_57,
2658 ena => VSYNC_STATE_NEXT_2_SQMUXA,
2659         devpor => devpor,
2660         devclrn => devclrn,
2661         aclr => GND,
2662         sload => GND,
2663         cin => GND,
2664         inverta => GND,
2665         aload => GND);
2666 \HSYNC_STATE_5_\: stratix_lcell generic map (
2667     operation_mode => "normal",
2668     output_mode => "reg_only",
2669     synch_mode => "on",
2670      sum_lutc_input => "datac",
2671     lut_mask => "eeee")
2672 port map (
2673 regout => HSYNC_STATE_19,
2674 clk => clk_pin_c,
2675 dataa => HSYNC_STATE_22,
2676 datab => HSYNC_STATE_18,
2677 sclr => UN6_DLY_COUNTER_0_X_57,
2678 ena => \HSYNC_STATE_3_0_0_0__G0_0\,
2679         devpor => devpor,
2680         devclrn => devclrn,
2681         datac => VCC,
2682         datad => VCC,
2683         aclr => GND,
2684         sload => GND,
2685         cin => GND,
2686         inverta => GND,
2687         aload => GND);
2688 \HSYNC_STATE_4_\: stratix_lcell generic map (
2689     operation_mode => "normal",
2690     output_mode => "reg_only",
2691     synch_mode => "on",
2692      sum_lutc_input => "datac",
2693     lut_mask => "8000")
2694 port map (
2695 regout => HSYNC_STATE_17,
2696 clk => clk_pin_c,
2697 dataa => HSYNC_STATE_19,
2698 datab => UN10_HSYNC_COUNTER_3,
2699 datac => UN10_HSYNC_COUNTER_1,
2700 datad => UN10_HSYNC_COUNTER_4,
2701 sclr => UN6_DLY_COUNTER_0_X_57,
2702 ena => \HSYNC_STATE_3_0_0_0__G0_0\,
2703         devpor => devpor,
2704         devclrn => devclrn,
2705         aclr => GND,
2706         sload => GND,
2707         cin => GND,
2708         inverta => GND,
2709         aload => GND);
2710 \HSYNC_STATE_3_\: stratix_lcell generic map (
2711     operation_mode => "normal",
2712     output_mode => "reg_only",
2713     synch_mode => "on",
2714      sum_lutc_input => "datac",
2715     lut_mask => "aaaa")
2716 port map (
2717 regout => HSYNC_STATE_21,
2718 clk => clk_pin_c,
2719 dataa => HSYNC_STATE_20,
2720 sclr => UN6_DLY_COUNTER_0_X_57,
2721 ena => \HSYNC_STATE_3_0_0_0__G0_0\,
2722         devpor => devpor,
2723         devclrn => devclrn,
2724         datab => VCC,
2725         datac => VCC,
2726         datad => VCC,
2727         aclr => GND,
2728         sload => GND,
2729         cin => GND,
2730         inverta => GND,
2731         aload => GND);
2732 \HSYNC_STATE_2_\: stratix_lcell generic map (
2733     operation_mode => "normal",
2734     output_mode => "reg_only",
2735     synch_mode => "on",
2736      sum_lutc_input => "datac",
2737     lut_mask => "8888")
2738 port map (
2739 regout => HSYNC_STATE_16,
2740 clk => clk_pin_c,
2741 dataa => HSYNC_STATE_21,
2742 datab => UN12_HSYNC_COUNTER,
2743 sclr => UN6_DLY_COUNTER_0_X_57,
2744 ena => \HSYNC_STATE_3_0_0_0__G0_0\,
2745         devpor => devpor,
2746         devclrn => devclrn,
2747         datac => VCC,
2748         datad => VCC,
2749         aclr => GND,
2750         sload => GND,
2751         cin => GND,
2752         inverta => GND,
2753         aload => GND);
2754 \HSYNC_STATE_1_\: stratix_lcell generic map (
2755     operation_mode => "normal",
2756     output_mode => "reg_only",
2757     synch_mode => "on",
2758      sum_lutc_input => "datac",
2759     lut_mask => "8000")
2760 port map (
2761 regout => HSYNC_STATE_20,
2762 clk => clk_pin_c,
2763 dataa => HSYNC_STATE_17,
2764 datab => UN11_HSYNC_COUNTER_2,
2765 datac => UN10_HSYNC_COUNTER_1,
2766 datad => UN11_HSYNC_COUNTER_3,
2767 sclr => UN6_DLY_COUNTER_0_X_57,
2768 ena => \HSYNC_STATE_3_0_0_0__G0_0\,
2769         devpor => devpor,
2770         devclrn => devclrn,
2771         aclr => GND,
2772         sload => GND,
2773         cin => GND,
2774         inverta => GND,
2775         aload => GND);
2776 \HSYNC_STATE_0_\: stratix_lcell generic map (
2777     operation_mode => "normal",
2778     output_mode => "reg_only",
2779     synch_mode => "on",
2780      sum_lutc_input => "datac",
2781     lut_mask => "8888")
2782 port map (
2783 regout => HSYNC_STATE_18,
2784 clk => clk_pin_c,
2785 dataa => HSYNC_STATE_16,
2786 datab => UN13_HSYNC_COUNTER,
2787 sclr => UN6_DLY_COUNTER_0_X_57,
2788 ena => \HSYNC_STATE_3_0_0_0__G0_0\,
2789         devpor => devpor,
2790         devclrn => devclrn,
2791         datac => VCC,
2792         datad => VCC,
2793         aclr => GND,
2794         sload => GND,
2795         cin => GND,
2796         inverta => GND,
2797         aload => GND);
2798 VSYNC_STATE_NEXT_2_SQMUXA_Z299: stratix_lcell generic map (
2799     operation_mode => "normal",
2800     output_mode => "comb_only",
2801     synch_mode => "off",
2802      sum_lutc_input => "datac",
2803     lut_mask => "aaab")
2804 port map (
2805 combout => VSYNC_STATE_NEXT_2_SQMUXA,
2806 dataa => UN6_DLY_COUNTER_0_X_57,
2807 datab => VSYNC_STATE_NEXT_1_SQMUXA_1,
2808 datac => VSYNC_STATE_NEXT_1_SQMUXA_3,
2809 datad => UN1_VSYNC_STATE_NEXT_1_SQMUXA_0,
2810         devpor => devpor,
2811         devclrn => devclrn,
2812         clk => GND,
2813         aclr => GND,
2814         sclr => GND,
2815         sload => GND,
2816         ena => VCC,
2817         cin => GND,
2818         inverta => GND,
2819         aload => GND);
2820 \HSYNC_STATE_3_0_0_0__G0_0_Z300\: stratix_lcell generic map (
2821     operation_mode => "normal",
2822     output_mode => "comb_only",
2823     synch_mode => "off",
2824      sum_lutc_input => "datac",
2825     lut_mask => "f0f1")
2826 port map (
2827 combout => \HSYNC_STATE_3_0_0_0__G0_0\,
2828 dataa => HSYNC_STATE_NEXT_1_SQMUXA_1,
2829 datab => HSYNC_STATE_NEXT_1_SQMUXA_2,
2830 datac => UN6_DLY_COUNTER_0_X_57,
2831 datad => UN1_HSYNC_STATE_NEXT_1_SQMUXA_0,
2832         devpor => devpor,
2833         devclrn => devclrn,
2834         clk => GND,
2835         aclr => GND,
2836         sclr => GND,
2837         sload => GND,
2838         ena => VCC,
2839         cin => GND,
2840         inverta => GND,
2841         aload => GND);
2842 UN1_HSYNC_STATE_NEXT_1_SQMUXA_0_Z301: stratix_lcell generic map (
2843     operation_mode => "normal",
2844     output_mode => "comb_only",
2845     synch_mode => "off",
2846      sum_lutc_input => "datac",
2847     lut_mask => "0ace")
2848 port map (
2849 combout => UN1_HSYNC_STATE_NEXT_1_SQMUXA_0,
2850 dataa => HSYNC_STATE_16,
2851 datab => HSYNC_STATE_21,
2852 datac => UN13_HSYNC_COUNTER,
2853 datad => UN12_HSYNC_COUNTER,
2854         devpor => devpor,
2855         devclrn => devclrn,
2856         clk => GND,
2857         aclr => GND,
2858         sclr => GND,
2859         sload => GND,
2860         ena => VCC,
2861         cin => GND,
2862         inverta => GND,
2863         aload => GND);
2864 UN1_VSYNC_STATE_NEXT_1_SQMUXA_0_Z302: stratix_lcell generic map (
2865     operation_mode => "normal",
2866     output_mode => "comb_only",
2867     synch_mode => "off",
2868      sum_lutc_input => "datac",
2869     lut_mask => "ff2a")
2870 port map (
2871 combout => UN1_VSYNC_STATE_NEXT_1_SQMUXA_0,
2872 dataa => VSYNC_STATE_9,
2873 datab => UN12_VSYNC_COUNTER_6,
2874 datac => UN15_VSYNC_COUNTER_4,
2875 datad => VSYNC_STATE_NEXT_1_SQMUXA_2,
2876         devpor => devpor,
2877         devclrn => devclrn,
2878         clk => GND,
2879         aclr => GND,
2880         sclr => GND,
2881         sload => GND,
2882         ena => VCC,
2883         cin => GND,
2884         inverta => GND,
2885         aload => GND);
2886 \VSYNC_STATE_3_IV_0_0__G0_0_A3_0_Z303\: stratix_lcell generic map (
2887     operation_mode => "normal",
2888     output_mode => "comb_only",
2889     synch_mode => "off",
2890      sum_lutc_input => "datac",
2891     lut_mask => "8080")
2892 port map (
2893 combout => \VSYNC_STATE_3_IV_0_0__G0_0_A3_0\,
2894 dataa => VSYNC_STATE_9,
2895 datab => UN12_VSYNC_COUNTER_6,
2896 datac => UN15_VSYNC_COUNTER_4,
2897         devpor => devpor,
2898         devclrn => devclrn,
2899         clk => GND,
2900         datad => VCC,
2901         aclr => GND,
2902         sclr => GND,
2903         sload => GND,
2904         ena => VCC,
2905         cin => GND,
2906         inverta => GND,
2907         aload => GND);
2908 LINE_COUNT_NEXT_UN10_LINE_COUNTER_SIGLTO8: stratix_lcell generic map (
2909     operation_mode => "normal",
2910     output_mode => "comb_only",
2911     synch_mode => "off",
2912      sum_lutc_input => "datac",
2913     lut_mask => "ff7f")
2914 port map (
2915 combout => UN10_LINE_COUNTER_SIGLTO8,
2916 dataa => LINE_COUNTER_SIG_7_0,
2917 datab => LINE_COUNTER_SIG_8_0,
2918 datac => LINE_COUNTER_SIG_6_0,
2919 datad => UN10_LINE_COUNTER_SIGLTO5,
2920         devpor => devpor,
2921         devclrn => devclrn,
2922         clk => GND,
2923         aclr => GND,
2924         sclr => GND,
2925         sload => GND,
2926         ena => VCC,
2927         cin => GND,
2928         inverta => GND,
2929         aload => GND);
2930 G_2: stratix_lcell generic map (
2931     operation_mode => "normal",
2932     output_mode => "comb_only",
2933     synch_mode => "off",
2934      sum_lutc_input => "datac",
2935     lut_mask => "0f1f")
2936 port map (
2937 combout => G_2_I,
2938 dataa => HSYNC_STATE_18,
2939 datab => HSYNC_STATE_22,
2940 datac => UN9_HSYNC_COUNTERLT9,
2941 datad => UN6_DLY_COUNTER_0_X_57,
2942         devpor => devpor,
2943         devclrn => devclrn,
2944         clk => GND,
2945         aclr => GND,
2946         sclr => GND,
2947         sload => GND,
2948         ena => VCC,
2949         cin => GND,
2950         inverta => GND,
2951         aload => GND);
2952 VSYNC_STATE_NEXT_1_SQMUXA_1_Z306: stratix_lcell generic map (
2953     operation_mode => "normal",
2954     output_mode => "comb_only",
2955     synch_mode => "off",
2956      sum_lutc_input => "datac",
2957     lut_mask => "d0f0")
2958 port map (
2959 combout => VSYNC_STATE_NEXT_1_SQMUXA_1,
2960 dataa => VSYNC_COUNTER_42,
2961 datab => VSYNC_COUNTER_33,
2962 datac => VSYNC_STATE_10,
2963 datad => UN14_VSYNC_COUNTER_8,
2964         devpor => devpor,
2965         devclrn => devclrn,
2966         clk => GND,
2967         aclr => GND,
2968         sclr => GND,
2969         sload => GND,
2970         ena => VCC,
2971         cin => GND,
2972         inverta => GND,
2973         aload => GND);
2974 VSYNC_STATE_NEXT_1_SQMUXA_2_Z307: stratix_lcell generic map (
2975     operation_mode => "normal",
2976     output_mode => "comb_only",
2977     synch_mode => "off",
2978      sum_lutc_input => "datac",
2979     lut_mask => "2a2a")
2980 port map (
2981 combout => VSYNC_STATE_NEXT_1_SQMUXA_2,
2982 dataa => VSYNC_STATE_13,
2983 datab => UN12_VSYNC_COUNTER_7,
2984 datac => UN13_VSYNC_COUNTER_4,
2985         devpor => devpor,
2986         devclrn => devclrn,
2987         clk => GND,
2988         datad => VCC,
2989         aclr => GND,
2990         sclr => GND,
2991         sload => GND,
2992         ena => VCC,
2993         cin => GND,
2994         inverta => GND,
2995         aload => GND);
2996 VSYNC_STATE_NEXT_1_SQMUXA_3_Z308: stratix_lcell generic map (
2997     operation_mode => "normal",
2998     output_mode => "comb_only",
2999     synch_mode => "off",
3000      sum_lutc_input => "datac",
3001     lut_mask => "70f0")
3002 port map (
3003 combout => VSYNC_STATE_NEXT_1_SQMUXA_3,
3004 dataa => VSYNC_COUNTER_42,
3005 datab => VSYNC_COUNTER_33,
3006 datac => VSYNC_STATE_11,
3007 datad => UN14_VSYNC_COUNTER_8,
3008         devpor => devpor,
3009         devclrn => devclrn,
3010         clk => GND,
3011         aclr => GND,
3012         sclr => GND,
3013         sload => GND,
3014         ena => VCC,
3015         cin => GND,
3016         inverta => GND,
3017         aload => GND);
3018 G_16: stratix_lcell generic map (
3019     operation_mode => "normal",
3020     output_mode => "comb_only",
3021     synch_mode => "off",
3022      sum_lutc_input => "datac",
3023     lut_mask => "0f1f")
3024 port map (
3025 combout => G_16_I,
3026 dataa => VSYNC_STATE_15,
3027 datab => VSYNC_STATE_12,
3028 datac => UN9_VSYNC_COUNTERLT9,
3029 datad => UN6_DLY_COUNTER_0_X_57,
3030         devpor => devpor,
3031         devclrn => devclrn,
3032         clk => GND,
3033         aclr => GND,
3034         sclr => GND,
3035         sload => GND,
3036         ena => VCC,
3037         cin => GND,
3038         inverta => GND,
3039         aload => GND);
3040 HSYNC_STATE_NEXT_1_SQMUXA_2_Z310: stratix_lcell generic map (
3041     operation_mode => "normal",
3042     output_mode => "comb_only",
3043     synch_mode => "off",
3044      sum_lutc_input => "datac",
3045     lut_mask => "2aaa")
3046 port map (
3047 combout => HSYNC_STATE_NEXT_1_SQMUXA_2,
3048 dataa => HSYNC_STATE_17,
3049 datab => UN11_HSYNC_COUNTER_2,
3050 datac => UN10_HSYNC_COUNTER_1,
3051 datad => UN11_HSYNC_COUNTER_3,
3052         devpor => devpor,
3053         devclrn => devclrn,
3054         clk => GND,
3055         aclr => GND,
3056         sclr => GND,
3057         sload => GND,
3058         ena => VCC,
3059         cin => GND,
3060         inverta => GND,
3061         aload => GND);
3062 HSYNC_STATE_NEXT_1_SQMUXA_1_Z311: stratix_lcell generic map (
3063     operation_mode => "normal",
3064     output_mode => "comb_only",
3065     synch_mode => "off",
3066      sum_lutc_input => "datac",
3067     lut_mask => "2aaa")
3068 port map (
3069 combout => HSYNC_STATE_NEXT_1_SQMUXA_1,
3070 dataa => HSYNC_STATE_19,
3071 datab => UN10_HSYNC_COUNTER_3,
3072 datac => UN10_HSYNC_COUNTER_1,
3073 datad => UN10_HSYNC_COUNTER_4,
3074         devpor => devpor,
3075         devclrn => devclrn,
3076         clk => GND,
3077         aclr => GND,
3078         sclr => GND,
3079         sload => GND,
3080         ena => VCC,
3081         cin => GND,
3082         inverta => GND,
3083         aload => GND);
3084 COLUMN_COUNT_NEXT_UN10_COLUMN_COUNTER_SIGLTO9: stratix_lcell generic map (
3085     operation_mode => "normal",
3086     output_mode => "comb_only",
3087     synch_mode => "off",
3088      sum_lutc_input => "datac",
3089     lut_mask => "1f0f")
3090 port map (
3091 combout => UN10_COLUMN_COUNTER_SIGLTO9,
3092 dataa => COLUMN_COUNTER_SIG_30,
3093 datab => COLUMN_COUNTER_SIG_31,
3094 datac => COLUMN_COUNTER_SIG_32,
3095 datad => UN10_COLUMN_COUNTER_SIGLT6,
3096         devpor => devpor,
3097         devclrn => devclrn,
3098         clk => GND,
3099         aclr => GND,
3100         sclr => GND,
3101         sload => GND,
3102         ena => VCC,
3103         cin => GND,
3104         inverta => GND,
3105         aload => GND);
3106 HSYNC_FSM_NEXT_UN12_HSYNC_COUNTER: stratix_lcell generic map (
3107     operation_mode => "normal",
3108     output_mode => "comb_only",
3109     synch_mode => "off",
3110      sum_lutc_input => "datac",
3111     lut_mask => "8000")
3112 port map (
3113 combout => UN12_HSYNC_COUNTER,
3114 dataa => HSYNC_COUNTER_52,
3115 datab => HSYNC_COUNTER_51,
3116 datac => UN12_HSYNC_COUNTER_3,
3117 datad => UN12_HSYNC_COUNTER_4,
3118         devpor => devpor,
3119         devclrn => devclrn,
3120         clk => GND,
3121         aclr => GND,
3122         sclr => GND,
3123         sload => GND,
3124         ena => VCC,
3125         cin => GND,
3126         inverta => GND,
3127         aload => GND);
3128 HSYNC_FSM_NEXT_UN13_HSYNC_COUNTER: stratix_lcell generic map (
3129     operation_mode => "normal",
3130     output_mode => "comb_only",
3131     synch_mode => "off",
3132      sum_lutc_input => "datac",
3133     lut_mask => "1000")
3134 port map (
3135 combout => UN13_HSYNC_COUNTER,
3136 dataa => HSYNC_COUNTER_46,
3137 datab => HSYNC_COUNTER_45,
3138 datac => UN13_HSYNC_COUNTER_2,
3139 datad => UN13_HSYNC_COUNTER_7,
3140         devpor => devpor,
3141         devclrn => devclrn,
3142         clk => GND,
3143         aclr => GND,
3144         sclr => GND,
3145         sload => GND,
3146         ena => VCC,
3147         cin => GND,
3148         inverta => GND,
3149         aload => GND);
3150 HSYNC_COUNT_NEXT_UN9_HSYNC_COUNTERLT9: stratix_lcell generic map (
3151     operation_mode => "normal",
3152     output_mode => "comb_only",
3153     synch_mode => "off",
3154      sum_lutc_input => "datac",
3155     lut_mask => "f7ff")
3156 port map (
3157 combout => UN9_HSYNC_COUNTERLT9,
3158 dataa => HSYNC_COUNTER_44,
3159 datab => HSYNC_COUNTER_43,
3160 datac => UN9_HSYNC_COUNTERLT9_3,
3161 datad => UN13_HSYNC_COUNTER_7,
3162         devpor => devpor,
3163         devclrn => devclrn,
3164         clk => GND,
3165         aclr => GND,
3166         sclr => GND,
3167         sload => GND,
3168         ena => VCC,
3169         cin => GND,
3170         inverta => GND,
3171         aload => GND);
3172 VSYNC_COUNT_NEXT_UN9_VSYNC_COUNTERLT9: stratix_lcell generic map (
3173     operation_mode => "normal",
3174     output_mode => "comb_only",
3175     synch_mode => "off",
3176      sum_lutc_input => "datac",
3177     lut_mask => "fff7")
3178 port map (
3179 combout => UN9_VSYNC_COUNTERLT9,
3180 dataa => VSYNC_COUNTER_38,
3181 datab => VSYNC_COUNTER_37,
3182 datac => UN9_VSYNC_COUNTERLT9_5,
3183 datad => UN9_VSYNC_COUNTERLT9_6,
3184         devpor => devpor,
3185         devclrn => devclrn,
3186         clk => GND,
3187         aclr => GND,
3188         sclr => GND,
3189         sload => GND,
3190         ena => VCC,
3191         cin => GND,
3192         inverta => GND,
3193         aload => GND);
3194 LINE_COUNT_NEXT_UN10_LINE_COUNTER_SIGLTO5: stratix_lcell generic map (
3195     operation_mode => "normal",
3196     output_mode => "comb_only",
3197     synch_mode => "off",
3198      sum_lutc_input => "datac",
3199     lut_mask => "0f07")
3200 port map (
3201 combout => UN10_LINE_COUNTER_SIGLTO5,
3202 dataa => LINE_COUNTER_SIG_1_0,
3203 datab => LINE_COUNTER_SIG_2_0,
3204 datac => LINE_COUNTER_SIG_5_0,
3205 datad => UN10_LINE_COUNTER_SIGLT4_2,
3206         devpor => devpor,
3207         devclrn => devclrn,
3208         clk => GND,
3209         aclr => GND,
3210         sclr => GND,
3211         sload => GND,
3212         ena => VCC,
3213         cin => GND,
3214         inverta => GND,
3215         aload => GND);
3216 VSYNC_FSM_NEXT_UN13_VSYNC_COUNTER_4: stratix_lcell generic map (
3217     operation_mode => "normal",
3218     output_mode => "comb_only",
3219     synch_mode => "off",
3220      sum_lutc_input => "datac",
3221     lut_mask => "8080")
3222 port map (
3223 combout => UN13_VSYNC_COUNTER_4,
3224 dataa => VSYNC_COUNTER_42,
3225 datab => VSYNC_COUNTER_37,
3226 datac => UN13_VSYNC_COUNTER_3,
3227         devpor => devpor,
3228         devclrn => devclrn,
3229         clk => GND,
3230         datad => VCC,
3231         aclr => GND,
3232         sclr => GND,
3233         sload => GND,
3234         ena => VCC,
3235         cin => GND,
3236         inverta => GND,
3237         aload => GND);
3238 VSYNC_FSM_NEXT_UN15_VSYNC_COUNTER_4: stratix_lcell generic map (
3239     operation_mode => "normal",
3240     output_mode => "comb_only",
3241     synch_mode => "off",
3242      sum_lutc_input => "datac",
3243     lut_mask => "1010")
3244 port map (
3245 combout => UN15_VSYNC_COUNTER_4,
3246 dataa => VSYNC_COUNTER_41,
3247 datab => VSYNC_COUNTER_38,
3248 datac => UN15_VSYNC_COUNTER_3,
3249         devpor => devpor,
3250         devclrn => devclrn,
3251         clk => GND,
3252         datad => VCC,
3253         aclr => GND,
3254         sclr => GND,
3255         sload => GND,
3256         ena => VCC,
3257         cin => GND,
3258         inverta => GND,
3259         aload => GND);
3260 COLUMN_COUNT_NEXT_UN10_COLUMN_COUNTER_SIGLT6: stratix_lcell generic map (
3261     operation_mode => "normal",
3262     output_mode => "comb_only",
3263     synch_mode => "off",
3264      sum_lutc_input => "datac",
3265     lut_mask => "fff7")
3266 port map (
3267 combout => UN10_COLUMN_COUNTER_SIGLT6,
3268 dataa => COLUMN_COUNTER_SIG_23,
3269 datab => COLUMN_COUNTER_SIG_24,
3270 datac => UN10_COLUMN_COUNTER_SIGLT6_54,
3271 datad => UN10_COLUMN_COUNTER_SIGLT6_2,
3272         devpor => devpor,
3273         devclrn => devclrn,
3274         clk => GND,
3275         aclr => GND,
3276         sclr => GND,
3277         sload => GND,
3278         ena => VCC,
3279         cin => GND,
3280         inverta => GND,
3281         aload => GND);
3282 HSYNC_COUNTER_NEXT_1_SQMUXA_Z321: stratix_lcell generic map (
3283     operation_mode => "normal",
3284     output_mode => "comb_only",
3285     synch_mode => "off",
3286      sum_lutc_input => "datac",
3287     lut_mask => "0080")
3288 port map (
3289 combout => HSYNC_COUNTER_NEXT_1_SQMUXA,
3290 dataa => reset_pin_c,
3291 datab => dly_counter_0,
3292 datac => dly_counter_1,
3293 datad => D_SET_HSYNC_COUNTER_58,
3294         devpor => devpor,
3295         devclrn => devclrn,
3296         clk => GND,
3297         aclr => GND,
3298         sclr => GND,
3299         sload => GND,
3300         ena => VCC,
3301         cin => GND,
3302         inverta => GND,
3303         aload => GND);
3304 COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_Z322: stratix_lcell generic map (
3305     operation_mode => "normal",
3306     output_mode => "comb_only",
3307     synch_mode => "off",
3308      sum_lutc_input => "datac",
3309     lut_mask => "0080")
3310 port map (
3311 combout => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1,
3312 dataa => reset_pin_c,
3313 datab => dly_counter_0,
3314 datac => dly_counter_1,
3315 datad => HSYNC_STATE_20,
3316         devpor => devpor,
3317         devclrn => devclrn,
3318         clk => GND,
3319         aclr => GND,
3320         sclr => GND,
3321         sload => GND,
3322         ena => VCC,
3323         cin => GND,
3324         inverta => GND,
3325         aload => GND);
3326 H_SYNC_1_0_0_0_G1_Z323: stratix_lcell generic map (
3327     operation_mode => "normal",
3328     output_mode => "comb_only",
3329     synch_mode => "off",
3330      sum_lutc_input => "datac",
3331     lut_mask => "ccd8")
3332 port map (
3333 combout => H_SYNC_1_0_0_0_G1,
3334 dataa => HSYNC_STATE_16,
3335 datab => H_SYNC_56,
3336 datac => HSYNC_STATE_17,
3337 datad => UN1_HSYNC_STATE_3_0,
3338         devpor => devpor,
3339         devclrn => devclrn,
3340         clk => GND,
3341         aclr => GND,
3342         sclr => GND,
3343         sload => GND,
3344         ena => VCC,
3345         cin => GND,
3346         inverta => GND,
3347         aload => GND);
3348 LINE_COUNTER_NEXT_0_SQMUXA_1_1_Z324: stratix_lcell generic map (
3349     operation_mode => "normal",
3350     output_mode => "comb_only",
3351     synch_mode => "off",
3352      sum_lutc_input => "datac",
3353     lut_mask => "0080")
3354 port map (
3355 combout => LINE_COUNTER_NEXT_0_SQMUXA_1_1,
3356 dataa => reset_pin_c,
3357 datab => dly_counter_0,
3358 datac => dly_counter_1,
3359 datad => VSYNC_STATE_14,
3360         devpor => devpor,
3361         devclrn => devclrn,
3362         clk => GND,
3363         aclr => GND,
3364         sclr => GND,
3365         sload => GND,
3366         ena => VCC,
3367         cin => GND,
3368         inverta => GND,
3369         aload => GND);
3370 V_SYNC_1_0_0_0_G1_Z325: stratix_lcell generic map (
3371     operation_mode => "normal",
3372     output_mode => "comb_only",
3373     synch_mode => "off",
3374      sum_lutc_input => "datac",
3375     lut_mask => "ccd8")
3376 port map (
3377 combout => V_SYNC_1_0_0_0_G1,
3378 dataa => VSYNC_STATE_9,
3379 datab => V_SYNC_55,
3380 datac => VSYNC_STATE_13,
3381 datad => UN1_VSYNC_STATE_2_0,
3382         devpor => devpor,
3383         devclrn => devclrn,
3384         clk => GND,
3385         aclr => GND,
3386         sclr => GND,
3387         sload => GND,
3388         ena => VCC,
3389         cin => GND,
3390         inverta => GND,
3391         aload => GND);
3392 H_ENABLE_SIG_1_0_0_0_G0_I_O4_Z326: stratix_lcell generic map (
3393     operation_mode => "normal",
3394     output_mode => "comb_only",
3395     synch_mode => "off",
3396      sum_lutc_input => "datac",
3397     lut_mask => "f1f1")
3398 port map (
3399 combout => H_ENABLE_SIG_1_0_0_0_G0_I_O4,
3400 dataa => VSYNC_STATE_13,
3401 datab => VSYNC_STATE_10,
3402 datac => UN6_DLY_COUNTER_0_X_57,
3403         devpor => devpor,
3404         devclrn => devclrn,
3405         clk => GND,
3406         datad => VCC,
3407         aclr => GND,
3408         sclr => GND,
3409         sload => GND,
3410         ena => VCC,
3411         cin => GND,
3412         inverta => GND,
3413         aload => GND);
3414 VSYNC_COUNTER_NEXT_1_SQMUXA_Z327: stratix_lcell generic map (
3415     operation_mode => "normal",
3416     output_mode => "comb_only",
3417     synch_mode => "off",
3418      sum_lutc_input => "datac",
3419     lut_mask => "0080")
3420 port map (
3421 combout => VSYNC_COUNTER_NEXT_1_SQMUXA,
3422 dataa => reset_pin_c,
3423 datab => dly_counter_0,
3424 datac => dly_counter_1,
3425 datad => D_SET_VSYNC_COUNTER_53,
3426         devpor => devpor,
3427         devclrn => devclrn,
3428         clk => GND,
3429         aclr => GND,
3430         sclr => GND,
3431         sload => GND,
3432         ena => VCC,
3433         cin => GND,
3434         inverta => GND,
3435         aload => GND);
3436 VSYNC_FSM_NEXT_UN14_VSYNC_COUNTER_8: stratix_lcell generic map (
3437     operation_mode => "normal",
3438     output_mode => "comb_only",
3439     synch_mode => "off",
3440      sum_lutc_input => "datac",
3441     lut_mask => "8888")
3442 port map (
3443 combout => UN14_VSYNC_COUNTER_8,
3444 dataa => UN12_VSYNC_COUNTER_6,
3445 datab => UN12_VSYNC_COUNTER_7,
3446         devpor => devpor,
3447         devclrn => devclrn,
3448         clk => GND,
3449         datac => VCC,
3450         datad => VCC,
3451         aclr => GND,
3452         sclr => GND,
3453         sload => GND,
3454         ena => VCC,
3455         cin => GND,
3456         inverta => GND,
3457         aload => GND);
3458 V_ENABLE_SIG_1_0_0_0_G0_I_O4_Z329: stratix_lcell generic map (
3459     operation_mode => "normal",
3460     output_mode => "comb_only",
3461     synch_mode => "off",
3462      sum_lutc_input => "datac",
3463     lut_mask => "f1f1")
3464 port map (
3465 combout => V_ENABLE_SIG_1_0_0_0_G0_I_O4,
3466 dataa => HSYNC_STATE_17,
3467 datab => HSYNC_STATE_19,
3468 datac => UN6_DLY_COUNTER_0_X_57,
3469         devpor => devpor,
3470         devclrn => devclrn,
3471         clk => GND,
3472         datad => VCC,
3473         aclr => GND,
3474         sclr => GND,
3475         sload => GND,
3476         ena => VCC,
3477         cin => GND,
3478         inverta => GND,
3479         aload => GND);
3480 HSYNC_FSM_NEXT_UN11_HSYNC_COUNTER_3: stratix_lcell generic map (
3481     operation_mode => "normal",
3482     output_mode => "comb_only",
3483     synch_mode => "off",
3484      sum_lutc_input => "datac",
3485     lut_mask => "0008")
3486 port map (
3487 combout => UN11_HSYNC_COUNTER_3,
3488 dataa => HSYNC_COUNTER_52,
3489 datab => HSYNC_COUNTER_51,
3490 datac => HSYNC_COUNTER_49,
3491 datad => HSYNC_COUNTER_48,
3492         devpor => devpor,
3493         devclrn => devclrn,
3494         clk => GND,
3495         aclr => GND,
3496         sclr => GND,
3497         sload => GND,
3498         ena => VCC,
3499         cin => GND,
3500         inverta => GND,
3501         aload => GND);
3502 HSYNC_FSM_NEXT_UN11_HSYNC_COUNTER_2: stratix_lcell generic map (
3503     operation_mode => "normal",
3504     output_mode => "comb_only",
3505     synch_mode => "off",
3506      sum_lutc_input => "datac",
3507     lut_mask => "0808")
3508 port map (
3509 combout => UN11_HSYNC_COUNTER_2,
3510 dataa => HSYNC_COUNTER_50,
3511 datab => HSYNC_COUNTER_45,
3512 datac => HSYNC_COUNTER_46,
3513         devpor => devpor,
3514         devclrn => devclrn,
3515         clk => GND,
3516         datad => VCC,
3517         aclr => GND,
3518         sclr => GND,
3519         sload => GND,
3520         ena => VCC,
3521         cin => GND,
3522         inverta => GND,
3523         aload => GND);
3524 HSYNC_FSM_NEXT_UN12_HSYNC_COUNTER_4: stratix_lcell generic map (
3525     operation_mode => "normal",
3526     output_mode => "comb_only",
3527     synch_mode => "off",
3528      sum_lutc_input => "datac",
3529     lut_mask => "0010")
3530 port map (
3531 combout => UN12_HSYNC_COUNTER_4,
3532 dataa => HSYNC_COUNTER_46,
3533 datab => HSYNC_COUNTER_45,
3534 datac => HSYNC_COUNTER_50,
3535 datad => HSYNC_COUNTER_48,
3536         devpor => devpor,
3537         devclrn => devclrn,
3538         clk => GND,
3539         aclr => GND,
3540         sclr => GND,
3541         sload => GND,
3542         ena => VCC,
3543         cin => GND,
3544         inverta => GND,
3545         aload => GND);
3546 HSYNC_FSM_NEXT_UN12_HSYNC_COUNTER_3: stratix_lcell generic map (
3547     operation_mode => "normal",
3548     output_mode => "comb_only",
3549     synch_mode => "off",
3550      sum_lutc_input => "datac",
3551     lut_mask => "0020")
3552 port map (
3553 combout => UN12_HSYNC_COUNTER_3,
3554 dataa => HSYNC_COUNTER_43,
3555 datab => HSYNC_COUNTER_47,
3556 datac => HSYNC_COUNTER_44,
3557 datad => HSYNC_COUNTER_49,
3558         devpor => devpor,
3559         devclrn => devclrn,
3560         clk => GND,
3561         aclr => GND,
3562         sclr => GND,
3563         sload => GND,
3564         ena => VCC,
3565         cin => GND,
3566         inverta => GND,
3567         aload => GND);
3568 HSYNC_COUNT_NEXT_UN9_HSYNC_COUNTERLT9_3: stratix_lcell generic map (
3569     operation_mode => "normal",
3570     output_mode => "comb_only",
3571     synch_mode => "off",
3572      sum_lutc_input => "datac",
3573     lut_mask => "7fff")
3574 port map (
3575 combout => UN9_HSYNC_COUNTERLT9_3,
3576 dataa => HSYNC_COUNTER_46,
3577 datab => HSYNC_COUNTER_45,
3578 datac => HSYNC_COUNTER_48,
3579 datad => HSYNC_COUNTER_47,
3580         devpor => devpor,
3581         devclrn => devclrn,
3582         clk => GND,
3583         aclr => GND,
3584         sclr => GND,
3585         sload => GND,
3586         ena => VCC,
3587         cin => GND,
3588         inverta => GND,
3589         aload => GND);
3590 HSYNC_FSM_NEXT_UN13_HSYNC_COUNTER_2: stratix_lcell generic map (
3591     operation_mode => "normal",
3592     output_mode => "comb_only",
3593     synch_mode => "off",
3594      sum_lutc_input => "datac",
3595     lut_mask => "0080")
3596 port map (
3597 combout => UN13_HSYNC_COUNTER_2,
3598 dataa => HSYNC_COUNTER_44,
3599 datab => HSYNC_COUNTER_43,
3600 datac => HSYNC_COUNTER_48,
3601 datad => HSYNC_COUNTER_47,
3602         devpor => devpor,
3603         devclrn => devclrn,
3604         clk => GND,
3605         aclr => GND,
3606         sclr => GND,
3607         sload => GND,
3608         ena => VCC,
3609         cin => GND,
3610         inverta => GND,
3611         aload => GND);
3612 VSYNC_COUNT_NEXT_UN9_VSYNC_COUNTERLT9_6: stratix_lcell generic map (
3613     operation_mode => "normal",
3614     output_mode => "comb_only",
3615     synch_mode => "off",
3616      sum_lutc_input => "datac",
3617     lut_mask => "7fff")
3618 port map (
3619 combout => UN9_VSYNC_COUNTERLT9_6,
3620 dataa => VSYNC_COUNTER_40,
3621 datab => VSYNC_COUNTER_39,
3622 datac => VSYNC_COUNTER_42,
3623 datad => VSYNC_COUNTER_41,
3624         devpor => devpor,
3625         devclrn => devclrn,
3626         clk => GND,
3627         aclr => GND,
3628         sclr => GND,
3629         sload => GND,
3630         ena => VCC,
3631         cin => GND,
3632         inverta => GND,
3633         aload => GND);
3634 VSYNC_COUNT_NEXT_UN9_VSYNC_COUNTERLT9_5: stratix_lcell generic map (
3635     operation_mode => "normal",
3636     output_mode => "comb_only",
3637     synch_mode => "off",
3638      sum_lutc_input => "datac",
3639     lut_mask => "7fff")
3640 port map (
3641 combout => UN9_VSYNC_COUNTERLT9_5,
3642 dataa => VSYNC_COUNTER_34,
3643 datab => VSYNC_COUNTER_33,
3644 datac => VSYNC_COUNTER_36,
3645 datad => VSYNC_COUNTER_35,
3646         devpor => devpor,
3647         devclrn => devclrn,
3648         clk => GND,
3649         aclr => GND,
3650         sclr => GND,
3651         sload => GND,
3652         ena => VCC,
3653         cin => GND,
3654         inverta => GND,
3655         aload => GND);
3656 VSYNC_FSM_NEXT_UN13_VSYNC_COUNTER_3: stratix_lcell generic map (
3657     operation_mode => "normal",
3658     output_mode => "comb_only",
3659     synch_mode => "off",
3660      sum_lutc_input => "datac",
3661     lut_mask => "0001")
3662 port map (
3663 combout => UN13_VSYNC_COUNTER_3,
3664 dataa => VSYNC_COUNTER_36,
3665 datab => VSYNC_COUNTER_35,
3666 datac => VSYNC_COUNTER_34,
3667 datad => VSYNC_COUNTER_33,
3668         devpor => devpor,
3669         devclrn => devclrn,
3670         clk => GND,
3671         aclr => GND,
3672         sclr => GND,
3673         sload => GND,
3674         ena => VCC,
3675         cin => GND,
3676         inverta => GND,
3677         aload => GND);
3678 HSYNC_FSM_NEXT_UN10_HSYNC_COUNTER_4: stratix_lcell generic map (
3679     operation_mode => "normal",
3680     output_mode => "comb_only",
3681     synch_mode => "off",
3682      sum_lutc_input => "datac",
3683     lut_mask => "8000")
3684 port map (
3685 combout => UN10_HSYNC_COUNTER_4,
3686 dataa => HSYNC_COUNTER_48,
3687 datab => HSYNC_COUNTER_46,
3688 datac => HSYNC_COUNTER_51,
3689 datad => HSYNC_COUNTER_49,
3690         devpor => devpor,
3691         devclrn => devclrn,
3692         clk => GND,
3693         aclr => GND,
3694         sclr => GND,
3695         sload => GND,
3696         ena => VCC,
3697         cin => GND,
3698         inverta => GND,
3699         aload => GND);
3700 HSYNC_FSM_NEXT_UN10_HSYNC_COUNTER_3: stratix_lcell generic map (
3701     operation_mode => "normal",
3702     output_mode => "comb_only",
3703     synch_mode => "off",
3704      sum_lutc_input => "datac",
3705     lut_mask => "0101")
3706 port map (
3707 combout => UN10_HSYNC_COUNTER_3,
3708 dataa => HSYNC_COUNTER_52,
3709 datab => HSYNC_COUNTER_45,
3710 datac => HSYNC_COUNTER_50,
3711         devpor => devpor,
3712         devclrn => devclrn,
3713         clk => GND,
3714         datad => VCC,
3715         aclr => GND,
3716         sclr => GND,
3717         sload => GND,
3718         ena => VCC,
3719         cin => GND,
3720         inverta => GND,
3721         aload => GND);
3722 VSYNC_FSM_NEXT_UN15_VSYNC_COUNTER_3: stratix_lcell generic map (
3723     operation_mode => "normal",
3724     output_mode => "comb_only",
3725     synch_mode => "off",
3726      sum_lutc_input => "datac",
3727     lut_mask => "0020")
3728 port map (
3729 combout => UN15_VSYNC_COUNTER_3,
3730 dataa => VSYNC_COUNTER_33,
3731 datab => VSYNC_COUNTER_40,
3732 datac => VSYNC_COUNTER_39,
3733 datad => VSYNC_COUNTER_42,
3734         devpor => devpor,
3735         devclrn => devclrn,
3736         clk => GND,
3737         aclr => GND,
3738         sclr => GND,
3739         sload => GND,
3740         ena => VCC,
3741         cin => GND,
3742         inverta => GND,
3743         aload => GND);
3744 COLUMN_COUNT_NEXT_UN10_COLUMN_COUNTER_SIGLT6_2: stratix_lcell generic map (
3745     operation_mode => "normal",
3746     output_mode => "comb_only",
3747     synch_mode => "off",
3748      sum_lutc_input => "datac",
3749     lut_mask => "7f7f")
3750 port map (
3751 combout => UN10_COLUMN_COUNTER_SIGLT6_2,
3752 dataa => COLUMN_COUNTER_SIG_25,
3753 datab => COLUMN_COUNTER_SIG_26,
3754 datac => COLUMN_COUNTER_SIG_27,
3755         devpor => devpor,
3756         devclrn => devclrn,
3757         clk => GND,
3758         datad => VCC,
3759         aclr => GND,
3760         sclr => GND,
3761         sload => GND,
3762         ena => VCC,
3763         cin => GND,
3764         inverta => GND,
3765         aload => GND);
3766 LINE_COUNT_NEXT_UN10_LINE_COUNTER_SIGLT4_2: stratix_lcell generic map (
3767     operation_mode => "normal",
3768     output_mode => "comb_only",
3769     synch_mode => "off",
3770      sum_lutc_input => "datac",
3771     lut_mask => "7f7f")
3772 port map (
3773 combout => UN10_LINE_COUNTER_SIGLT4_2,
3774 dataa => LINE_COUNTER_SIG_0_0,
3775 datab => LINE_COUNTER_SIG_4_0,
3776 datac => LINE_COUNTER_SIG_3_0,
3777         devpor => devpor,
3778         devclrn => devclrn,
3779         clk => GND,
3780         datad => VCC,
3781         aclr => GND,
3782         sclr => GND,
3783         sload => GND,
3784         ena => VCC,
3785         cin => GND,
3786         inverta => GND,
3787         aload => GND);
3788 HSYNC_FSM_NEXT_UN10_HSYNC_COUNTER_1: stratix_lcell generic map (
3789     operation_mode => "normal",
3790     output_mode => "comb_only",
3791     synch_mode => "off",
3792      sum_lutc_input => "datac",
3793     lut_mask => "0101")
3794 port map (
3795 combout => UN10_HSYNC_COUNTER_1,
3796 dataa => HSYNC_COUNTER_47,
3797 datab => HSYNC_COUNTER_44,
3798 datac => HSYNC_COUNTER_43,
3799         devpor => devpor,
3800         devclrn => devclrn,
3801         clk => GND,
3802         datad => VCC,
3803         aclr => GND,
3804         sclr => GND,
3805         sload => GND,
3806         ena => VCC,
3807         cin => GND,
3808         inverta => GND,
3809         aload => GND);
3810 HSYNC_FSM_NEXT_UN13_HSYNC_COUNTER_7: stratix_lcell generic map (
3811     operation_mode => "normal",
3812     output_mode => "comb_only",
3813     synch_mode => "off",
3814      sum_lutc_input => "datac",
3815     lut_mask => "8000")
3816 port map (
3817 combout => UN13_HSYNC_COUNTER_7,
3818 dataa => HSYNC_COUNTER_50,
3819 datab => HSYNC_COUNTER_49,
3820 datac => HSYNC_COUNTER_52,
3821 datad => HSYNC_COUNTER_51,
3822         devpor => devpor,
3823         devclrn => devclrn,
3824         clk => GND,
3825         aclr => GND,
3826         sclr => GND,
3827         sload => GND,
3828         ena => VCC,
3829         cin => GND,
3830         inverta => GND,
3831         aload => GND);
3832 VSYNC_FSM_NEXT_UN12_VSYNC_COUNTER_6: stratix_lcell generic map (
3833     operation_mode => "normal",
3834     output_mode => "comb_only",
3835     synch_mode => "off",
3836      sum_lutc_input => "datac",
3837     lut_mask => "0001")
3838 port map (
3839 combout => UN12_VSYNC_COUNTER_6,
3840 dataa => VSYNC_COUNTER_35,
3841 datab => VSYNC_COUNTER_34,
3842 datac => VSYNC_COUNTER_37,
3843 datad => VSYNC_COUNTER_36,
3844         devpor => devpor,
3845         devclrn => devclrn,
3846         clk => GND,
3847         aclr => GND,
3848         sclr => GND,
3849         sload => GND,
3850         ena => VCC,
3851         cin => GND,
3852         inverta => GND,
3853         aload => GND);
3854 VSYNC_FSM_NEXT_UN12_VSYNC_COUNTER_7: stratix_lcell generic map (
3855     operation_mode => "normal",
3856     output_mode => "comb_only",
3857     synch_mode => "off",
3858      sum_lutc_input => "datac",
3859     lut_mask => "0001")
3860 port map (
3861 combout => UN12_VSYNC_COUNTER_7,
3862 dataa => VSYNC_COUNTER_39,
3863 datab => VSYNC_COUNTER_38,
3864 datac => VSYNC_COUNTER_41,
3865 datad => VSYNC_COUNTER_40,
3866         devpor => devpor,
3867         devclrn => devclrn,
3868         clk => GND,
3869         aclr => GND,
3870         sclr => GND,
3871         sload => GND,
3872         ena => VCC,
3873         cin => GND,
3874         inverta => GND,
3875         aload => GND);
3876 UN1_HSYNC_STATE_3_0_Z348: stratix_lcell generic map (
3877     operation_mode => "normal",
3878     output_mode => "comb_only",
3879     synch_mode => "off",
3880      sum_lutc_input => "datac",
3881     lut_mask => "eeee")
3882 port map (
3883 combout => UN1_HSYNC_STATE_3_0,
3884 dataa => HSYNC_STATE_21,
3885 datab => HSYNC_STATE_20,
3886         devpor => devpor,
3887         devclrn => devclrn,
3888         clk => GND,
3889         datac => VCC,
3890         datad => VCC,
3891         aclr => GND,
3892         sclr => GND,
3893         sload => GND,
3894         ena => VCC,
3895         cin => GND,
3896         inverta => GND,
3897         aload => GND);
3898 COLUMN_COUNT_NEXT_UN10_COLUMN_COUNTER_SIGLT6_1: stratix_lcell generic map (
3899     operation_mode => "normal",
3900     output_mode => "comb_only",
3901     synch_mode => "off",
3902      sum_lutc_input => "datac",
3903     lut_mask => "7777")
3904 port map (
3905 combout => UN10_COLUMN_COUNTER_SIGLT6_54,
3906 dataa => COLUMN_COUNTER_SIG_29,
3907 datab => COLUMN_COUNTER_SIG_28,
3908         devpor => devpor,
3909         devclrn => devclrn,
3910         clk => GND,
3911         datac => VCC,
3912         datad => VCC,
3913         aclr => GND,
3914         sclr => GND,
3915         sload => GND,
3916         ena => VCC,
3917         cin => GND,
3918         inverta => GND,
3919         aload => GND);
3920 UN1_VSYNC_STATE_2_0_Z350: stratix_lcell generic map (
3921     operation_mode => "normal",
3922     output_mode => "comb_only",
3923     synch_mode => "off",
3924      sum_lutc_input => "datac",
3925     lut_mask => "eeee")
3926 port map (
3927 combout => UN1_VSYNC_STATE_2_0,
3928 dataa => VSYNC_STATE_11,
3929 datab => VSYNC_STATE_14,
3930         devpor => devpor,
3931         devclrn => devclrn,
3932         clk => GND,
3933         datac => VCC,
3934         datad => VCC,
3935         aclr => GND,
3936         sclr => GND,
3937         sload => GND,
3938         ena => VCC,
3939         cin => GND,
3940         inverta => GND,
3941         aload => GND);
3942 D_SET_HSYNC_COUNTER_Z351: stratix_lcell generic map (
3943     operation_mode => "normal",
3944     output_mode => "comb_only",
3945     synch_mode => "off",
3946      sum_lutc_input => "datac",
3947     lut_mask => "eeee")
3948 port map (
3949 combout => D_SET_HSYNC_COUNTER_58,
3950 dataa => HSYNC_STATE_22,
3951 datab => HSYNC_STATE_18,
3952         devpor => devpor,
3953         devclrn => devclrn,
3954         clk => GND,
3955         datac => VCC,
3956         datad => VCC,
3957         aclr => GND,
3958         sclr => GND,
3959         sload => GND,
3960         ena => VCC,
3961         cin => GND,
3962         inverta => GND,
3963         aload => GND);
3964 D_SET_VSYNC_COUNTER_Z352: stratix_lcell generic map (
3965     operation_mode => "normal",
3966     output_mode => "comb_only",
3967     synch_mode => "off",
3968      sum_lutc_input => "datac",
3969     lut_mask => "eeee")
3970 port map (
3971 combout => D_SET_VSYNC_COUNTER_53,
3972 dataa => VSYNC_STATE_12,
3973 datab => VSYNC_STATE_15,
3974         devpor => devpor,
3975         devclrn => devclrn,
3976         clk => GND,
3977         datac => VCC,
3978         datad => VCC,
3979         aclr => GND,
3980         sclr => GND,
3981         sload => GND,
3982         ena => VCC,
3983         cin => GND,
3984         inverta => GND,
3985         aload => GND);
3986 \UN1_LINE_COUNTER_SIG_9_\: stratix_lcell generic map (
3987     operation_mode => "normal",
3988     output_mode => "comb_only",
3989     synch_mode => "off",
3990      sum_lutc_input => "cin",
3991      cin_used => "true",
3992     lut_mask => "6c6c")
3993 port map (
3994 combout => UN1_LINE_COUNTER_SIG_COMBOUT(9),
3995 dataa => LINE_COUNTER_SIG_7_0,
3996 datab => LINE_COUNTER_SIG_8_0,
3997 cin => UN1_LINE_COUNTER_SIG_COUT(7),
3998         devpor => devpor,
3999         devclrn => devclrn,
4000         clk => GND,
4001         datac => VCC,
4002         datad => VCC,
4003         aclr => GND,
4004         sclr => GND,
4005         sload => GND,
4006         ena => VCC,
4007         inverta => GND,
4008         aload => GND);
4009 \UN1_LINE_COUNTER_SIG_8_\: stratix_lcell generic map (
4010     operation_mode => "normal",
4011     output_mode => "comb_only",
4012     synch_mode => "off",
4013      sum_lutc_input => "cin",
4014      cin_used => "true",
4015     lut_mask => "5a5a")
4016 port map (
4017 combout => UN1_LINE_COUNTER_SIG_COMBOUT(8),
4018 dataa => LINE_COUNTER_SIG_7_0,
4019 cin => UN1_LINE_COUNTER_SIG_COUT(6),
4020         devpor => devpor,
4021         devclrn => devclrn,
4022         clk => GND,
4023         datab => VCC,
4024         datac => VCC,
4025         datad => VCC,
4026         aclr => GND,
4027         sclr => GND,
4028         sload => GND,
4029         ena => VCC,
4030         inverta => GND,
4031         aload => GND);
4032 \UN1_LINE_COUNTER_SIG_7_\: stratix_lcell generic map (
4033     operation_mode => "arithmetic",
4034     output_mode => "comb_only",
4035     synch_mode => "off",
4036      sum_lutc_input => "cin",
4037      cin_used => "true",
4038     lut_mask => "6c80")
4039 port map (
4040 combout => UN1_LINE_COUNTER_SIG_COMBOUT(7),
4041 cout => UN1_LINE_COUNTER_SIG_COUT(7),
4042 dataa => LINE_COUNTER_SIG_5_0,
4043 datab => LINE_COUNTER_SIG_6_0,
4044 cin => UN1_LINE_COUNTER_SIG_COUT(5),
4045         devpor => devpor,
4046         devclrn => devclrn,
4047         clk => GND,
4048         datac => VCC,
4049         datad => VCC,
4050         aclr => GND,
4051         sclr => GND,
4052         sload => GND,
4053         ena => VCC,
4054         inverta => GND,
4055         aload => GND);
4056 \UN1_LINE_COUNTER_SIG_6_\: stratix_lcell generic map (
4057     operation_mode => "arithmetic",
4058     output_mode => "comb_only",
4059     synch_mode => "off",
4060      sum_lutc_input => "cin",
4061      cin_used => "true",
4062     lut_mask => "5a80")
4063 port map (
4064 combout => UN1_LINE_COUNTER_SIG_COMBOUT(6),
4065 cout => UN1_LINE_COUNTER_SIG_COUT(6),
4066 dataa => LINE_COUNTER_SIG_5_0,
4067 datab => LINE_COUNTER_SIG_6_0,
4068 cin => UN1_LINE_COUNTER_SIG_COUT(4),
4069         devpor => devpor,
4070         devclrn => devclrn,
4071         clk => GND,
4072         datac => VCC,
4073         datad => VCC,
4074         aclr => GND,
4075         sclr => GND,
4076         sload => GND,
4077         ena => VCC,
4078         inverta => GND,
4079         aload => GND);
4080 \UN1_LINE_COUNTER_SIG_5_\: stratix_lcell generic map (
4081     operation_mode => "arithmetic",
4082     output_mode => "comb_only",
4083     synch_mode => "off",
4084      sum_lutc_input => "cin",
4085      cin_used => "true",
4086     lut_mask => "6c80")
4087 port map (
4088 combout => UN1_LINE_COUNTER_SIG_COMBOUT(5),
4089 cout => UN1_LINE_COUNTER_SIG_COUT(5),
4090 dataa => LINE_COUNTER_SIG_3_0,
4091 datab => LINE_COUNTER_SIG_4_0,
4092 cin => UN1_LINE_COUNTER_SIG_COUT(3),
4093         devpor => devpor,
4094         devclrn => devclrn,
4095         clk => GND,
4096         datac => VCC,
4097         datad => VCC,
4098         aclr => GND,
4099         sclr => GND,
4100         sload => GND,
4101         ena => VCC,
4102         inverta => GND,
4103         aload => GND);
4104 \UN1_LINE_COUNTER_SIG_4_\: stratix_lcell generic map (
4105     operation_mode => "arithmetic",
4106     output_mode => "comb_only",
4107     synch_mode => "off",
4108      sum_lutc_input => "cin",
4109      cin_used => "true",
4110     lut_mask => "5a80")
4111 port map (
4112 combout => UN1_LINE_COUNTER_SIG_COMBOUT(4),
4113 cout => UN1_LINE_COUNTER_SIG_COUT(4),
4114 dataa => LINE_COUNTER_SIG_3_0,
4115 datab => LINE_COUNTER_SIG_4_0,
4116 cin => UN1_LINE_COUNTER_SIG_COUT(2),
4117         devpor => devpor,
4118         devclrn => devclrn,
4119         clk => GND,
4120         datac => VCC,
4121         datad => VCC,
4122         aclr => GND,
4123         sclr => GND,
4124         sload => GND,
4125         ena => VCC,
4126         inverta => GND,
4127         aload => GND);
4128 \UN1_LINE_COUNTER_SIG_3_\: stratix_lcell generic map (
4129     operation_mode => "arithmetic",
4130     output_mode => "comb_only",
4131     synch_mode => "off",
4132      sum_lutc_input => "cin",
4133      cin_used => "true",
4134     lut_mask => "6c80")
4135 port map (
4136 combout => UN1_LINE_COUNTER_SIG_COMBOUT(3),
4137 cout => UN1_LINE_COUNTER_SIG_COUT(3),
4138 dataa => LINE_COUNTER_SIG_1_0,
4139 datab => LINE_COUNTER_SIG_2_0,
4140 cin => UN1_LINE_COUNTER_SIG_COUT(1),
4141         devpor => devpor,
4142         devclrn => devclrn,
4143         clk => GND,
4144         datac => VCC,
4145         datad => VCC,
4146         aclr => GND,
4147         sclr => GND,
4148         sload => GND,
4149         ena => VCC,
4150         inverta => GND,
4151         aload => GND);
4152 \UN1_LINE_COUNTER_SIG_2_\: stratix_lcell generic map (
4153     operation_mode => "arithmetic",
4154     output_mode => "comb_only",
4155     synch_mode => "off",
4156      sum_lutc_input => "cin",
4157      cin_used => "true",
4158     lut_mask => "5a80")
4159 port map (
4160 combout => UN1_LINE_COUNTER_SIG_COMBOUT(2),
4161 cout => UN1_LINE_COUNTER_SIG_COUT(2),
4162 dataa => LINE_COUNTER_SIG_1_0,
4163 datab => LINE_COUNTER_SIG_2_0,
4164 cin => UN1_LINE_COUNTER_SIG_A_COUT(1),
4165         devpor => devpor,
4166         devclrn => devclrn,
4167         clk => GND,
4168         datac => VCC,
4169         datad => VCC,
4170         aclr => GND,
4171         sclr => GND,
4172         sload => GND,
4173         ena => VCC,
4174         inverta => GND,
4175         aload => GND);
4176 \UN1_LINE_COUNTER_SIG_A_1_\: stratix_lcell generic map (
4177     operation_mode => "arithmetic",
4178     output_mode => "comb_only",
4179     synch_mode => "off",
4180      sum_lutc_input => "datac",
4181     lut_mask => "0088")
4182 port map (
4183 cout => UN1_LINE_COUNTER_SIG_A_COUT(1),
4184 dataa => D_SET_HSYNC_COUNTER_58,
4185 datab => LINE_COUNTER_SIG_0_0,
4186         devpor => devpor,
4187         devclrn => devclrn,
4188         clk => GND,
4189         datac => VCC,
4190         datad => VCC,
4191         aclr => GND,
4192         sclr => GND,
4193         sload => GND,
4194         ena => VCC,
4195         cin => GND,
4196         inverta => GND,
4197         aload => GND);
4198 \UN1_LINE_COUNTER_SIG_1_\: stratix_lcell generic map (
4199     operation_mode => "arithmetic",
4200     output_mode => "comb_only",
4201     synch_mode => "off",
4202      sum_lutc_input => "datac",
4203     lut_mask => "6688")
4204 port map (
4205 combout => UN1_LINE_COUNTER_SIG_COMBOUT(1),
4206 cout => UN1_LINE_COUNTER_SIG_COUT(1),
4207 dataa => D_SET_HSYNC_COUNTER_58,
4208 datab => LINE_COUNTER_SIG_0_0,
4209         devpor => devpor,
4210         devclrn => devclrn,
4211         clk => GND,
4212         datac => VCC,
4213         datad => VCC,
4214         aclr => GND,
4215         sclr => GND,
4216         sload => GND,
4217         ena => VCC,
4218         cin => GND,
4219         inverta => GND,
4220         aload => GND);
4221 \UN2_COLUMN_COUNTER_NEXT_9_\: stratix_lcell generic map (
4222     operation_mode => "normal",
4223     output_mode => "comb_only",
4224     synch_mode => "off",
4225      sum_lutc_input => "cin",
4226      cin_used => "true",
4227     lut_mask => "6c6c")
4228 port map (
4229 combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(9),
4230 dataa => COLUMN_COUNTER_SIG_31,
4231 datab => COLUMN_COUNTER_SIG_32,
4232 cin => UN2_COLUMN_COUNTER_NEXT_COUT(7),
4233         devpor => devpor,
4234         devclrn => devclrn,
4235         clk => GND,
4236         datac => VCC,
4237         datad => VCC,
4238         aclr => GND,
4239         sclr => GND,
4240         sload => GND,
4241         ena => VCC,
4242         inverta => GND,
4243         aload => GND);
4244 \UN2_COLUMN_COUNTER_NEXT_8_\: stratix_lcell generic map (
4245     operation_mode => "normal",
4246     output_mode => "comb_only",
4247     synch_mode => "off",
4248      sum_lutc_input => "cin",
4249      cin_used => "true",
4250     lut_mask => "5a5a")
4251 port map (
4252 combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(8),
4253 dataa => COLUMN_COUNTER_SIG_31,
4254 cin => UN2_COLUMN_COUNTER_NEXT_COUT(6),
4255         devpor => devpor,
4256         devclrn => devclrn,
4257         clk => GND,
4258         datab => VCC,
4259         datac => VCC,
4260         datad => VCC,
4261         aclr => GND,
4262         sclr => GND,
4263         sload => GND,
4264         ena => VCC,
4265         inverta => GND,
4266         aload => GND);
4267 \UN2_COLUMN_COUNTER_NEXT_7_\: stratix_lcell generic map (
4268     operation_mode => "arithmetic",
4269     output_mode => "comb_only",
4270     synch_mode => "off",
4271      sum_lutc_input => "cin",
4272      cin_used => "true",
4273     lut_mask => "6c80")
4274 port map (
4275 combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(7),
4276 cout => UN2_COLUMN_COUNTER_NEXT_COUT(7),
4277 dataa => COLUMN_COUNTER_SIG_29,
4278 datab => COLUMN_COUNTER_SIG_30,
4279 cin => UN2_COLUMN_COUNTER_NEXT_COUT(5),
4280         devpor => devpor,
4281         devclrn => devclrn,
4282         clk => GND,
4283         datac => VCC,
4284         datad => VCC,
4285         aclr => GND,
4286         sclr => GND,
4287         sload => GND,
4288         ena => VCC,
4289         inverta => GND,
4290         aload => GND);
4291 \UN2_COLUMN_COUNTER_NEXT_6_\: stratix_lcell generic map (
4292     operation_mode => "arithmetic",
4293     output_mode => "comb_only",
4294     synch_mode => "off",
4295      sum_lutc_input => "cin",
4296      cin_used => "true",
4297     lut_mask => "5a80")
4298 port map (
4299 combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(6),
4300 cout => UN2_COLUMN_COUNTER_NEXT_COUT(6),
4301 dataa => COLUMN_COUNTER_SIG_29,
4302 datab => COLUMN_COUNTER_SIG_30,
4303 cin => UN2_COLUMN_COUNTER_NEXT_COUT(4),
4304         devpor => devpor,
4305         devclrn => devclrn,
4306         clk => GND,
4307         datac => VCC,
4308         datad => VCC,
4309         aclr => GND,
4310         sclr => GND,
4311         sload => GND,
4312         ena => VCC,
4313         inverta => GND,
4314         aload => GND);
4315 \UN2_COLUMN_COUNTER_NEXT_5_\: stratix_lcell generic map (
4316     operation_mode => "arithmetic",
4317     output_mode => "comb_only",
4318     synch_mode => "off",
4319      sum_lutc_input => "cin",
4320      cin_used => "true",
4321     lut_mask => "6c80")
4322 port map (
4323 combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(5),
4324 cout => UN2_COLUMN_COUNTER_NEXT_COUT(5),
4325 dataa => COLUMN_COUNTER_SIG_27,
4326 datab => COLUMN_COUNTER_SIG_28,
4327 cin => UN2_COLUMN_COUNTER_NEXT_COUT(3),
4328         devpor => devpor,
4329         devclrn => devclrn,
4330         clk => GND,
4331         datac => VCC,
4332         datad => VCC,
4333         aclr => GND,
4334         sclr => GND,
4335         sload => GND,
4336         ena => VCC,
4337         inverta => GND,
4338         aload => GND);
4339 \UN2_COLUMN_COUNTER_NEXT_4_\: stratix_lcell generic map (
4340     operation_mode => "arithmetic",
4341     output_mode => "comb_only",
4342     synch_mode => "off",
4343      sum_lutc_input => "cin",
4344      cin_used => "true",
4345     lut_mask => "5a80")
4346 port map (
4347 combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(4),
4348 cout => UN2_COLUMN_COUNTER_NEXT_COUT(4),
4349 dataa => COLUMN_COUNTER_SIG_27,
4350 datab => COLUMN_COUNTER_SIG_28,
4351 cin => UN2_COLUMN_COUNTER_NEXT_COUT(2),
4352         devpor => devpor,
4353         devclrn => devclrn,
4354         clk => GND,
4355         datac => VCC,
4356         datad => VCC,
4357         aclr => GND,
4358         sclr => GND,
4359         sload => GND,
4360         ena => VCC,
4361         inverta => GND,
4362         aload => GND);
4363 \UN2_COLUMN_COUNTER_NEXT_3_\: stratix_lcell generic map (
4364     operation_mode => "arithmetic",
4365     output_mode => "comb_only",
4366     synch_mode => "off",
4367      sum_lutc_input => "cin",
4368      cin_used => "true",
4369     lut_mask => "6c80")
4370 port map (
4371 combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(3),
4372 cout => UN2_COLUMN_COUNTER_NEXT_COUT(3),
4373 dataa => COLUMN_COUNTER_SIG_25,
4374 datab => COLUMN_COUNTER_SIG_26,
4375 cin => UN2_COLUMN_COUNTER_NEXT_COUT(1),
4376         devpor => devpor,
4377         devclrn => devclrn,
4378         clk => GND,
4379         datac => VCC,
4380         datad => VCC,
4381         aclr => GND,
4382         sclr => GND,
4383         sload => GND,
4384         ena => VCC,
4385         inverta => GND,
4386         aload => GND);
4387 \UN2_COLUMN_COUNTER_NEXT_2_\: stratix_lcell generic map (
4388     operation_mode => "arithmetic",
4389     output_mode => "comb_only",
4390     synch_mode => "off",
4391      sum_lutc_input => "cin",
4392      cin_used => "true",
4393     lut_mask => "5a80")
4394 port map (
4395 combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(2),
4396 cout => UN2_COLUMN_COUNTER_NEXT_COUT(2),
4397 dataa => COLUMN_COUNTER_SIG_25,
4398 datab => COLUMN_COUNTER_SIG_26,
4399 cin => UN2_COLUMN_COUNTER_NEXT_COUT(0),
4400         devpor => devpor,
4401         devclrn => devclrn,
4402         clk => GND,
4403         datac => VCC,
4404         datad => VCC,
4405         aclr => GND,
4406         sclr => GND,
4407         sload => GND,
4408         ena => VCC,
4409         inverta => GND,
4410         aload => GND);
4411 \UN2_COLUMN_COUNTER_NEXT_1_\: stratix_lcell generic map (
4412     operation_mode => "arithmetic",
4413     output_mode => "comb_only",
4414     synch_mode => "off",
4415      sum_lutc_input => "datac",
4416     lut_mask => "6688")
4417 port map (
4418 combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(1),
4419 cout => UN2_COLUMN_COUNTER_NEXT_COUT(1),
4420 dataa => COLUMN_COUNTER_SIG_23,
4421 datab => COLUMN_COUNTER_SIG_24,
4422         devpor => devpor,
4423         devclrn => devclrn,
4424         clk => GND,
4425         datac => VCC,
4426         datad => VCC,
4427         aclr => GND,
4428         sclr => GND,
4429         sload => GND,
4430         ena => VCC,
4431         cin => GND,
4432         inverta => GND,
4433         aload => GND);
4434 \UN2_COLUMN_COUNTER_NEXT_0_\: stratix_lcell generic map (
4435     operation_mode => "arithmetic",
4436     output_mode => "comb_only",
4437     synch_mode => "off",
4438      sum_lutc_input => "datac",
4439     lut_mask => "5588")
4440 port map (
4441 cout => UN2_COLUMN_COUNTER_NEXT_COUT(0),
4442 dataa => COLUMN_COUNTER_SIG_23,
4443 datab => COLUMN_COUNTER_SIG_24,
4444         devpor => devpor,
4445         devclrn => devclrn,
4446         clk => GND,
4447         datac => VCC,
4448         datad => VCC,
4449         aclr => GND,
4450         sclr => GND,
4451         sload => GND,
4452         ena => VCC,
4453         cin => GND,
4454         inverta => GND,
4455         aload => GND);
4456 VCC <= '1';
4457 GND <= '0';
4458 LINE_COUNTER_NEXT_0_SQMUXA_1_1_I <= not LINE_COUNTER_NEXT_0_SQMUXA_1_1;
4459 COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I <= not COLUMN_COUNTER_NEXT_0_SQMUXA_1_1;
4460 G_16_I_I <= not G_16_I;
4461 UN9_VSYNC_COUNTERLT9_I <= not UN9_VSYNC_COUNTERLT9;
4462 G_2_I_I <= not G_2_I;
4463 UN9_HSYNC_COUNTERLT9_I <= not UN9_HSYNC_COUNTERLT9;
4464 line_counter_sig_0 <= LINE_COUNTER_SIG_0_0;
4465 line_counter_sig_1 <= LINE_COUNTER_SIG_1_0;
4466 line_counter_sig_2 <= LINE_COUNTER_SIG_2_0;
4467 line_counter_sig_3 <= LINE_COUNTER_SIG_3_0;
4468 line_counter_sig_4 <= LINE_COUNTER_SIG_4_0;
4469 line_counter_sig_5 <= LINE_COUNTER_SIG_5_0;
4470 line_counter_sig_6 <= LINE_COUNTER_SIG_6_0;
4471 line_counter_sig_7 <= LINE_COUNTER_SIG_7_0;
4472 line_counter_sig_8 <= LINE_COUNTER_SIG_8_0;
4473 vsync_state_2 <= VSYNC_STATE_9;
4474 vsync_state_5 <= VSYNC_STATE_10;
4475 vsync_state_3 <= VSYNC_STATE_11;
4476 vsync_state_6 <= VSYNC_STATE_12;
4477 vsync_state_4 <= VSYNC_STATE_13;
4478 vsync_state_1 <= VSYNC_STATE_14;
4479 vsync_state_0 <= VSYNC_STATE_15;
4480 hsync_state_2 <= HSYNC_STATE_16;
4481 hsync_state_4 <= HSYNC_STATE_17;
4482 hsync_state_0 <= HSYNC_STATE_18;
4483 hsync_state_5 <= HSYNC_STATE_19;
4484 hsync_state_1 <= HSYNC_STATE_20;
4485 hsync_state_3 <= HSYNC_STATE_21;
4486 hsync_state_6 <= HSYNC_STATE_22;
4487 column_counter_sig_0 <= COLUMN_COUNTER_SIG_23;
4488 column_counter_sig_1 <= COLUMN_COUNTER_SIG_24;
4489 column_counter_sig_2 <= COLUMN_COUNTER_SIG_25;
4490 column_counter_sig_3 <= COLUMN_COUNTER_SIG_26;
4491 column_counter_sig_4 <= COLUMN_COUNTER_SIG_27;
4492 column_counter_sig_5 <= COLUMN_COUNTER_SIG_28;
4493 column_counter_sig_6 <= COLUMN_COUNTER_SIG_29;
4494 column_counter_sig_7 <= COLUMN_COUNTER_SIG_30;
4495 column_counter_sig_8 <= COLUMN_COUNTER_SIG_31;
4496 column_counter_sig_9 <= COLUMN_COUNTER_SIG_32;
4497 vsync_counter_9 <= VSYNC_COUNTER_33;
4498 vsync_counter_8 <= VSYNC_COUNTER_34;
4499 vsync_counter_7 <= VSYNC_COUNTER_35;
4500 vsync_counter_6 <= VSYNC_COUNTER_36;
4501 vsync_counter_5 <= VSYNC_COUNTER_37;
4502 vsync_counter_4 <= VSYNC_COUNTER_38;
4503 vsync_counter_3 <= VSYNC_COUNTER_39;
4504 vsync_counter_2 <= VSYNC_COUNTER_40;
4505 vsync_counter_1 <= VSYNC_COUNTER_41;
4506 vsync_counter_0 <= VSYNC_COUNTER_42;
4507 hsync_counter_9 <= HSYNC_COUNTER_43;
4508 hsync_counter_8 <= HSYNC_COUNTER_44;
4509 hsync_counter_7 <= HSYNC_COUNTER_45;
4510 hsync_counter_6 <= HSYNC_COUNTER_46;
4511 hsync_counter_5 <= HSYNC_COUNTER_47;
4512 hsync_counter_4 <= HSYNC_COUNTER_48;
4513 hsync_counter_3 <= HSYNC_COUNTER_49;
4514 hsync_counter_2 <= HSYNC_COUNTER_50;
4515 hsync_counter_1 <= HSYNC_COUNTER_51;
4516 hsync_counter_0 <= HSYNC_COUNTER_52;
4517 d_set_vsync_counter <= D_SET_VSYNC_COUNTER_53;
4518 un10_column_counter_siglt6_1 <= UN10_COLUMN_COUNTER_SIGLT6_54;
4519 v_sync <= V_SYNC_55;
4520 h_sync <= H_SYNC_56;
4521 un6_dly_counter_0_x <= UN6_DLY_COUNTER_0_X_57;
4522 d_set_hsync_counter <= D_SET_HSYNC_COUNTER_58;
4523 end beh;
4524
4525 --
4526 library ieee, stratix;
4527 use ieee.std_logic_1164.all;
4528 use ieee.numeric_std.all;
4529 library synplify;
4530 use synplify.components.all;
4531 use stratix.stratix_components.all;
4532
4533 entity vga is
4534 port(
4535 clk_pin :  in std_logic;
4536 reset_pin :  in std_logic;
4537 r0_pin :  out std_logic;
4538 r1_pin :  out std_logic;
4539 r2_pin :  out std_logic;
4540 g0_pin :  out std_logic;
4541 g1_pin :  out std_logic;
4542 g2_pin :  out std_logic;
4543 b0_pin :  out std_logic;
4544 b1_pin :  out std_logic;
4545 hsync_pin :  out std_logic;
4546 vsync_pin :  out std_logic;
4547 seven_seg_pin : out std_logic_vector(13 downto 0);
4548 d_hsync :  out std_logic;
4549 d_vsync :  out std_logic;
4550 d_column_counter : out std_logic_vector(9 downto 0);
4551 d_line_counter : out std_logic_vector(8 downto 0);
4552 d_set_column_counter :  out std_logic;
4553 d_set_line_counter :  out std_logic;
4554 d_hsync_counter : out std_logic_vector(9 downto 0);
4555 d_vsync_counter : out std_logic_vector(9 downto 0);
4556 d_set_hsync_counter :  out std_logic;
4557 d_set_vsync_counter :  out std_logic;
4558 d_h_enable :  out std_logic;
4559 d_v_enable :  out std_logic;
4560 d_r :  out std_logic;
4561 d_g :  out std_logic;
4562 d_b :  out std_logic;
4563 d_hsync_state : out std_logic_vector(0 to 6);
4564 d_vsync_state : out std_logic_vector(0 to 6);
4565 d_state_clk :  out std_logic;
4566 d_toggle :  out std_logic;
4567 d_toggle_counter : out std_logic_vector(24 downto 0));
4568 end vga;
4569
4570 architecture beh of vga is
4571 signal devclrn : std_logic := '1';
4572 signal devpor : std_logic := '1';
4573 signal devoe : std_logic := '0';
4574 signal DLY_COUNTER : std_logic_vector(1 downto 0);
4575 signal \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\ : std_logic_vector(9 downto 0);
4576 signal \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\ : std_logic_vector(8 downto 0);
4577 signal \VGA_DRIVER_UNIT.HSYNC_COUNTER\ : std_logic_vector(9 downto 0);
4578 signal \VGA_DRIVER_UNIT.VSYNC_COUNTER\ : std_logic_vector(9 downto 0);
4579 signal \VGA_DRIVER_UNIT.HSYNC_STATE\ : std_logic_vector(6 downto 0);
4580 signal \VGA_DRIVER_UNIT.VSYNC_STATE\ : std_logic_vector(6 downto 0);
4581 signal \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\ : std_logic_vector(24 downto 0);
4582 signal SEVEN_SEG_PINZ : std_logic_vector(13 downto 0);
4583 signal D_COLUMN_COUNTERZ : std_logic_vector(9 downto 0);
4584 signal D_LINE_COUNTERZ : std_logic_vector(8 downto 0);
4585 signal D_HSYNC_COUNTERZ : std_logic_vector(9 downto 0);
4586 signal D_VSYNC_COUNTERZ : std_logic_vector(9 downto 0);
4587 signal D_HSYNC_STATEZ : std_logic_vector(6 downto 0);
4588 signal D_VSYNC_STATEZ : std_logic_vector(6 downto 0);
4589 signal D_TOGGLE_COUNTERZ : std_logic_vector(24 downto 0);
4590 signal VCC : std_logic ;
4591 signal GND : std_logic ;
4592 signal \VGA_DRIVER_UNIT.COLUMN_COUNT_NEXT.UN10_COLUMN_COUNTER_SIGLT6_1\ : std_logic ;
4593 signal \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\ : std_logic ;
4594 signal \VGA_DRIVER_UNIT.H_SYNC\ : std_logic ;
4595 signal \VGA_DRIVER_UNIT.V_SYNC\ : std_logic ;
4596 signal \VGA_DRIVER_UNIT.D_SET_HSYNC_COUNTER\ : std_logic ;
4597 signal \VGA_DRIVER_UNIT.D_SET_VSYNC_COUNTER\ : std_logic ;
4598 signal \VGA_DRIVER_UNIT.H_ENABLE_SIG\ : std_logic ;
4599 signal \VGA_DRIVER_UNIT.V_ENABLE_SIG\ : std_logic ;
4600 signal \VGA_CONTROL_UNIT.R\ : std_logic ;
4601 signal \VGA_CONTROL_UNIT.G\ : std_logic ;
4602 signal \VGA_CONTROL_UNIT.B\ : std_logic ;
4603 signal G_33 : std_logic ;
4604 signal \VGA_CONTROL_UNIT.TOGGLE_SIG\ : std_logic ;
4605 signal CLK_PIN_C : std_logic ;
4606 signal RESET_PIN_C : std_logic ;
4607 signal CLK_PIN_INTERNAL : std_logic ;
4608 signal RESET_PIN_INTERNAL : std_logic ;
4609 signal N_1 : std_logic ;
4610 signal N_2 : std_logic ;
4611 signal N_85_0 : std_logic ;
4612 signal N_86_0 : std_logic ;
4613 signal N_87_0 : std_logic ;
4614 signal N_88_0 : std_logic ;
4615 signal N_89_0 : std_logic ;
4616 signal N_90_0 : std_logic ;
4617 signal N_91_0 : std_logic ;
4618 signal N_92_0 : std_logic ;
4619 signal N_93_0 : std_logic ;
4620 signal N_94_0 : std_logic ;
4621 signal N_95_0 : std_logic ;
4622 signal N_96_0 : std_logic ;
4623 signal N_97_0 : std_logic ;
4624 signal N_98_0 : std_logic ;
4625 signal N_99_0 : std_logic ;
4626 signal N_100_0 : std_logic ;
4627 signal N_101_0 : std_logic ;
4628 signal N_102_0 : std_logic ;
4629 signal N_103_0 : std_logic ;
4630 signal N_104_0 : std_logic ;
4631 signal N_105_0 : std_logic ;
4632 signal N_106_0 : std_logic ;
4633 signal N_107_0 : std_logic ;
4634 signal N_108_0 : std_logic ;
4635 signal N_109_0 : std_logic ;
4636 signal N_110_0 : std_logic ;
4637 signal N_111_0 : std_logic ;
4638 signal N_112_0 : std_logic ;
4639 signal N_113_0 : std_logic ;
4640 signal N_114_0 : std_logic ;
4641 signal N_115_0 : std_logic ;
4642 signal N_116_0 : std_logic ;
4643 signal N_117_0 : std_logic ;
4644 signal N_118 : std_logic ;
4645 signal N_119 : std_logic ;
4646 signal N_120 : std_logic ;
4647 signal N_121 : std_logic ;
4648 signal N_122 : std_logic ;
4649 signal N_123 : std_logic ;
4650 signal N_124 : std_logic ;
4651 signal N_125 : std_logic ;
4652 signal N_126 : std_logic ;
4653 signal N_127 : std_logic ;
4654 signal N_128 : std_logic ;
4655 signal N_129 : std_logic ;
4656 signal N_130 : std_logic ;
4657 signal N_131 : std_logic ;
4658 signal N_132 : std_logic ;
4659 signal N_133 : std_logic ;
4660 signal N_134 : std_logic ;
4661 signal N_135 : std_logic ;
4662 signal N_136 : std_logic ;
4663 signal N_137 : std_logic ;
4664 signal N_138 : std_logic ;
4665 signal N_139 : std_logic ;
4666 signal N_140 : std_logic ;
4667 signal N_141 : std_logic ;
4668 signal N_142 : std_logic ;
4669 signal N_143 : std_logic ;
4670 signal N_144 : std_logic ;
4671 signal N_145 : std_logic ;
4672 signal N_146 : std_logic ;
4673 signal N_147 : std_logic ;
4674 signal N_148 : std_logic ;
4675 signal N_149 : std_logic ;
4676 signal N_150 : std_logic ;
4677 signal N_151 : std_logic ;
4678 signal N_152 : std_logic ;
4679 signal N_153 : std_logic ;
4680 signal N_154 : std_logic ;
4681 signal N_155 : std_logic ;
4682 signal N_156 : std_logic ;
4683 signal N_157 : std_logic ;
4684 signal N_158 : std_logic ;
4685 signal N_159 : std_logic ;
4686 signal N_160 : std_logic ;
4687 signal N_161 : std_logic ;
4688 signal N_162 : std_logic ;
4689 signal N_163 : std_logic ;
4690 signal N_164 : std_logic ;
4691 signal N_165 : std_logic ;
4692 signal N_166 : std_logic ;
4693 signal N_167 : std_logic ;
4694 signal N_168 : std_logic ;
4695 signal N_169 : std_logic ;
4696 signal N_170 : std_logic ;
4697 signal N_171 : std_logic ;
4698 signal N_172 : std_logic ;
4699 signal N_173 : std_logic ;
4700 signal N_174 : std_logic ;
4701 signal N_175 : std_logic ;
4702 signal N_176 : std_logic ;
4703 signal N_177 : std_logic ;
4704 signal N_178 : std_logic ;
4705 signal N_179 : std_logic ;
4706 signal N_180 : std_logic ;
4707 signal N_181 : std_logic ;
4708 signal N_182 : std_logic ;
4709 signal N_183 : std_logic ;
4710 signal N_184 : std_logic ;
4711 signal N_185 : std_logic ;
4712 signal N_186 : std_logic ;
4713 signal N_187 : std_logic ;
4714 signal N_188 : std_logic ;
4715 signal N_189 : std_logic ;
4716 signal N_190 : std_logic ;
4717 signal N_191 : std_logic ;
4718 signal N_192 : std_logic ;
4719 signal N_193 : std_logic ;
4720 signal N_194 : std_logic ;
4721 signal N_195 : std_logic ;
4722 signal N_196 : std_logic ;
4723 signal N_197 : std_logic ;
4724 signal N_198 : std_logic ;
4725 signal N_199 : std_logic ;
4726 signal R0_PINZ : std_logic ;
4727 signal R1_PINZ : std_logic ;
4728 signal R2_PINZ : std_logic ;
4729 signal G0_PINZ : std_logic ;
4730 signal G1_PINZ : std_logic ;
4731 signal G2_PINZ : std_logic ;
4732 signal B0_PINZ : std_logic ;
4733 signal B1_PINZ : std_logic ;
4734 signal HSYNC_PINZ : std_logic ;
4735 signal VSYNC_PINZ : std_logic ;
4736 signal D_HSYNCZ : std_logic ;
4737 signal D_VSYNCZ : std_logic ;
4738 signal D_SET_COLUMN_COUNTERZ : std_logic ;
4739 signal D_SET_LINE_COUNTERZ : std_logic ;
4740 signal D_SET_HSYNC_COUNTERZ : std_logic ;
4741 signal D_SET_VSYNC_COUNTERZ : std_logic ;
4742 signal D_H_ENABLEZ : std_logic ;
4743 signal D_V_ENABLEZ : std_logic ;
4744 signal D_RZ : std_logic ;
4745 signal D_GZ : std_logic ;
4746 signal D_BZ : std_logic ;
4747 signal D_STATE_CLKZ : std_logic ;
4748 signal D_TOGGLEZ : std_logic ;
4749 component vga_driver
4750 port(
4751   line_counter_sig_0 :  out std_logic;
4752   line_counter_sig_1 :  out std_logic;
4753   line_counter_sig_2 :  out std_logic;
4754   line_counter_sig_3 :  out std_logic;
4755   line_counter_sig_4 :  out std_logic;
4756   line_counter_sig_5 :  out std_logic;
4757   line_counter_sig_6 :  out std_logic;
4758   line_counter_sig_7 :  out std_logic;
4759   line_counter_sig_8 :  out std_logic;
4760   dly_counter_1 :  in std_logic;
4761   dly_counter_0 :  in std_logic;
4762   vsync_state_2 :  out std_logic;
4763   vsync_state_5 :  out std_logic;
4764   vsync_state_3 :  out std_logic;
4765   vsync_state_6 :  out std_logic;
4766   vsync_state_4 :  out std_logic;
4767   vsync_state_1 :  out std_logic;
4768   vsync_state_0 :  out std_logic;
4769   hsync_state_2 :  out std_logic;
4770   hsync_state_4 :  out std_logic;
4771   hsync_state_0 :  out std_logic;
4772   hsync_state_5 :  out std_logic;
4773   hsync_state_1 :  out std_logic;
4774   hsync_state_3 :  out std_logic;
4775   hsync_state_6 :  out std_logic;
4776   column_counter_sig_0 :  out std_logic;
4777   column_counter_sig_1 :  out std_logic;
4778   column_counter_sig_2 :  out std_logic;
4779   column_counter_sig_3 :  out std_logic;
4780   column_counter_sig_4 :  out std_logic;
4781   column_counter_sig_5 :  out std_logic;
4782   column_counter_sig_6 :  out std_logic;
4783   column_counter_sig_7 :  out std_logic;
4784   column_counter_sig_8 :  out std_logic;
4785   column_counter_sig_9 :  out std_logic;
4786   vsync_counter_9 :  out std_logic;
4787   vsync_counter_8 :  out std_logic;
4788   vsync_counter_7 :  out std_logic;
4789   vsync_counter_6 :  out std_logic;
4790   vsync_counter_5 :  out std_logic;
4791   vsync_counter_4 :  out std_logic;
4792   vsync_counter_3 :  out std_logic;
4793   vsync_counter_2 :  out std_logic;
4794   vsync_counter_1 :  out std_logic;
4795   vsync_counter_0 :  out std_logic;
4796   hsync_counter_9 :  out std_logic;
4797   hsync_counter_8 :  out std_logic;
4798   hsync_counter_7 :  out std_logic;
4799   hsync_counter_6 :  out std_logic;
4800   hsync_counter_5 :  out std_logic;
4801   hsync_counter_4 :  out std_logic;
4802   hsync_counter_3 :  out std_logic;
4803   hsync_counter_2 :  out std_logic;
4804   hsync_counter_1 :  out std_logic;
4805   hsync_counter_0 :  out std_logic;
4806   d_set_vsync_counter :  out std_logic;
4807   un10_column_counter_siglt6_1 :  out std_logic;
4808   v_sync :  out std_logic;
4809   h_sync :  out std_logic;
4810   h_enable_sig :  out std_logic;
4811   v_enable_sig :  out std_logic;
4812   reset_pin_c :  in std_logic;
4813   un6_dly_counter_0_x :  out std_logic;
4814   d_set_hsync_counter :  out std_logic;
4815   clk_pin_c :  in std_logic  );
4816 end component;
4817 component vga_control
4818 port(
4819   column_counter_sig_5 :  in std_logic;
4820   column_counter_sig_0 :  in std_logic;
4821   column_counter_sig_1 :  in std_logic;
4822   column_counter_sig_3 :  in std_logic;
4823   column_counter_sig_4 :  in std_logic;
4824   column_counter_sig_2 :  in std_logic;
4825   column_counter_sig_9 :  in std_logic;
4826   column_counter_sig_8 :  in std_logic;
4827   column_counter_sig_7 :  in std_logic;
4828   column_counter_sig_6 :  in std_logic;
4829   line_counter_sig_0 :  in std_logic;
4830   line_counter_sig_1 :  in std_logic;
4831   line_counter_sig_2 :  in std_logic;
4832   line_counter_sig_8 :  in std_logic;
4833   line_counter_sig_3 :  in std_logic;
4834   line_counter_sig_5 :  in std_logic;
4835   line_counter_sig_4 :  in std_logic;
4836   line_counter_sig_7 :  in std_logic;
4837   line_counter_sig_6 :  in std_logic;
4838   toggle_counter_sig_0 :  out std_logic;
4839   toggle_counter_sig_1 :  out std_logic;
4840   toggle_counter_sig_2 :  out std_logic;
4841   toggle_counter_sig_3 :  out std_logic;
4842   toggle_counter_sig_4 :  out std_logic;
4843   toggle_counter_sig_5 :  out std_logic;
4844   toggle_counter_sig_6 :  out std_logic;
4845   toggle_counter_sig_7 :  out std_logic;
4846   toggle_counter_sig_8 :  out std_logic;
4847   toggle_counter_sig_9 :  out std_logic;
4848   toggle_counter_sig_10 :  out std_logic;
4849   toggle_counter_sig_11 :  out std_logic;
4850   toggle_counter_sig_12 :  out std_logic;
4851   toggle_counter_sig_13 :  out std_logic;
4852   toggle_counter_sig_14 :  out std_logic;
4853   toggle_counter_sig_15 :  out std_logic;
4854   toggle_counter_sig_16 :  out std_logic;
4855   toggle_counter_sig_17 :  out std_logic;
4856   toggle_counter_sig_18 :  out std_logic;
4857   toggle_counter_sig_19 :  out std_logic;
4858   toggle_counter_sig_20 :  out std_logic;
4859   toggle_counter_sig_21 :  out std_logic;
4860   toggle_counter_sig_22 :  out std_logic;
4861   toggle_counter_sig_23 :  out std_logic;
4862   toggle_counter_sig_24 :  out std_logic;
4863   v_enable_sig :  in std_logic;
4864   un10_column_counter_siglt6_1 :  in std_logic;
4865   h_enable_sig :  in std_logic;
4866   g :  out std_logic;
4867   r :  out std_logic;
4868   b :  out std_logic;
4869   toggle_sig :  out std_logic;
4870   un6_dly_counter_0_x :  in std_logic;
4871   clk_pin_c :  in std_logic  );
4872 end component;
4873 begin
4874 VCC <= '1';
4875 GND <= '0';
4876 \DLY_COUNTER_1_\: stratix_lcell generic map (
4877     operation_mode => "normal",
4878     output_mode => "reg_only",
4879     synch_mode => "off",
4880      sum_lutc_input => "datac",
4881     lut_mask => "a8a8")
4882 port map (
4883 regout => DLY_COUNTER(1),
4884 clk => CLK_PIN_C,
4885 dataa => RESET_PIN_C,
4886 datab => DLY_COUNTER(0),
4887 datac => DLY_COUNTER(1),
4888         devpor => devpor,
4889         devclrn => devclrn,
4890         datad => VCC,
4891         aclr => GND,
4892         sclr => GND,
4893         sload => GND,
4894         ena => VCC,
4895         cin => GND,
4896         inverta => GND,
4897         aload => GND);
4898 \DLY_COUNTER_0_\: stratix_lcell generic map (
4899     operation_mode => "normal",
4900     output_mode => "reg_only",
4901     synch_mode => "off",
4902      sum_lutc_input => "datac",
4903     lut_mask => "a2a2")
4904 port map (
4905 regout => DLY_COUNTER(0),
4906 clk => CLK_PIN_C,
4907 dataa => RESET_PIN_C,
4908 datab => DLY_COUNTER(0),
4909 datac => DLY_COUNTER(1),
4910         devpor => devpor,
4911         devclrn => devclrn,
4912         datad => VCC,
4913         aclr => GND,
4914         sclr => GND,
4915         sload => GND,
4916         ena => VCC,
4917         cin => GND,
4918         inverta => GND,
4919         aload => GND);
4920 RESET_PIN_IN: stratix_io generic map (
4921     operation_mode => "input"
4922     )
4923 port map (
4924 padio => N_2,
4925 combout => RESET_PIN_C,
4926 oe => GND,
4927         devpor => devpor,
4928         devclrn => devclrn,
4929         devoe => devoe,
4930         outclkena => VCC,
4931         inclkena => VCC,
4932         areset => GND,
4933         sreset => GND);
4934 CLK_PIN_IN: stratix_io generic map (
4935     operation_mode => "input"
4936     )
4937 port map (
4938 padio => N_1,
4939 combout => CLK_PIN_C,
4940 oe => GND,
4941         devpor => devpor,
4942         devclrn => devclrn,
4943         devoe => devoe,
4944         outclkena => VCC,
4945         inclkena => VCC,
4946         areset => GND,
4947         sreset => GND);
4948 \D_TOGGLE_COUNTER_OUT_24_\: stratix_io generic map (
4949     operation_mode => "output"
4950     )
4951 port map (
4952 padio => D_TOGGLE_COUNTERZ(24),
4953 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(24),
4954 oe => VCC,
4955         devpor => devpor,
4956         devclrn => devclrn,
4957         devoe => devoe,
4958         outclkena => VCC,
4959         inclkena => VCC,
4960         areset => GND,
4961         sreset => GND);
4962 \D_TOGGLE_COUNTER_OUT_23_\: stratix_io generic map (
4963     operation_mode => "output"
4964     )
4965 port map (
4966 padio => D_TOGGLE_COUNTERZ(23),
4967 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(23),
4968 oe => VCC,
4969         devpor => devpor,
4970         devclrn => devclrn,
4971         devoe => devoe,
4972         outclkena => VCC,
4973         inclkena => VCC,
4974         areset => GND,
4975         sreset => GND);
4976 \D_TOGGLE_COUNTER_OUT_22_\: stratix_io generic map (
4977     operation_mode => "output"
4978     )
4979 port map (
4980 padio => D_TOGGLE_COUNTERZ(22),
4981 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(22),
4982 oe => VCC,
4983         devpor => devpor,
4984         devclrn => devclrn,
4985         devoe => devoe,
4986         outclkena => VCC,
4987         inclkena => VCC,
4988         areset => GND,
4989         sreset => GND);
4990 \D_TOGGLE_COUNTER_OUT_21_\: stratix_io generic map (
4991     operation_mode => "output"
4992     )
4993 port map (
4994 padio => D_TOGGLE_COUNTERZ(21),
4995 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(21),
4996 oe => VCC,
4997         devpor => devpor,
4998         devclrn => devclrn,
4999         devoe => devoe,
5000         outclkena => VCC,
5001         inclkena => VCC,
5002         areset => GND,
5003         sreset => GND);
5004 \D_TOGGLE_COUNTER_OUT_20_\: stratix_io generic map (
5005     operation_mode => "output"
5006     )
5007 port map (
5008 padio => D_TOGGLE_COUNTERZ(20),
5009 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(20),
5010 oe => VCC,
5011         devpor => devpor,
5012         devclrn => devclrn,
5013         devoe => devoe,
5014         outclkena => VCC,
5015         inclkena => VCC,
5016         areset => GND,
5017         sreset => GND);
5018 \D_TOGGLE_COUNTER_OUT_19_\: stratix_io generic map (
5019     operation_mode => "output"
5020     )
5021 port map (
5022 padio => D_TOGGLE_COUNTERZ(19),
5023 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(19),
5024 oe => VCC,
5025         devpor => devpor,
5026         devclrn => devclrn,
5027         devoe => devoe,
5028         outclkena => VCC,
5029         inclkena => VCC,
5030         areset => GND,
5031         sreset => GND);
5032 \D_TOGGLE_COUNTER_OUT_18_\: stratix_io generic map (
5033     operation_mode => "output"
5034     )
5035 port map (
5036 padio => D_TOGGLE_COUNTERZ(18),
5037 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(18),
5038 oe => VCC,
5039         devpor => devpor,
5040         devclrn => devclrn,
5041         devoe => devoe,
5042         outclkena => VCC,
5043         inclkena => VCC,
5044         areset => GND,
5045         sreset => GND);
5046 \D_TOGGLE_COUNTER_OUT_17_\: stratix_io generic map (
5047     operation_mode => "output"
5048     )
5049 port map (
5050 padio => D_TOGGLE_COUNTERZ(17),
5051 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(17),
5052 oe => VCC,
5053         devpor => devpor,
5054         devclrn => devclrn,
5055         devoe => devoe,
5056         outclkena => VCC,
5057         inclkena => VCC,
5058         areset => GND,
5059         sreset => GND);
5060 \D_TOGGLE_COUNTER_OUT_16_\: stratix_io generic map (
5061     operation_mode => "output"
5062     )
5063 port map (
5064 padio => D_TOGGLE_COUNTERZ(16),
5065 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(16),
5066 oe => VCC,
5067         devpor => devpor,
5068         devclrn => devclrn,
5069         devoe => devoe,
5070         outclkena => VCC,
5071         inclkena => VCC,
5072         areset => GND,
5073         sreset => GND);
5074 \D_TOGGLE_COUNTER_OUT_15_\: stratix_io generic map (
5075     operation_mode => "output"
5076     )
5077 port map (
5078 padio => D_TOGGLE_COUNTERZ(15),
5079 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(15),
5080 oe => VCC,
5081         devpor => devpor,
5082         devclrn => devclrn,
5083         devoe => devoe,
5084         outclkena => VCC,
5085         inclkena => VCC,
5086         areset => GND,
5087         sreset => GND);
5088 \D_TOGGLE_COUNTER_OUT_14_\: stratix_io generic map (
5089     operation_mode => "output"
5090     )
5091 port map (
5092 padio => D_TOGGLE_COUNTERZ(14),
5093 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(14),
5094 oe => VCC,
5095         devpor => devpor,
5096         devclrn => devclrn,
5097         devoe => devoe,
5098         outclkena => VCC,
5099         inclkena => VCC,
5100         areset => GND,
5101         sreset => GND);
5102 \D_TOGGLE_COUNTER_OUT_13_\: stratix_io generic map (
5103     operation_mode => "output"
5104     )
5105 port map (
5106 padio => D_TOGGLE_COUNTERZ(13),
5107 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(13),
5108 oe => VCC,
5109         devpor => devpor,
5110         devclrn => devclrn,
5111         devoe => devoe,
5112         outclkena => VCC,
5113         inclkena => VCC,
5114         areset => GND,
5115         sreset => GND);
5116 \D_TOGGLE_COUNTER_OUT_12_\: stratix_io generic map (
5117     operation_mode => "output"
5118     )
5119 port map (
5120 padio => D_TOGGLE_COUNTERZ(12),
5121 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(12),
5122 oe => VCC,
5123         devpor => devpor,
5124         devclrn => devclrn,
5125         devoe => devoe,
5126         outclkena => VCC,
5127         inclkena => VCC,
5128         areset => GND,
5129         sreset => GND);
5130 \D_TOGGLE_COUNTER_OUT_11_\: stratix_io generic map (
5131     operation_mode => "output"
5132     )
5133 port map (
5134 padio => D_TOGGLE_COUNTERZ(11),
5135 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(11),
5136 oe => VCC,
5137         devpor => devpor,
5138         devclrn => devclrn,
5139         devoe => devoe,
5140         outclkena => VCC,
5141         inclkena => VCC,
5142         areset => GND,
5143         sreset => GND);
5144 \D_TOGGLE_COUNTER_OUT_10_\: stratix_io generic map (
5145     operation_mode => "output"
5146     )
5147 port map (
5148 padio => D_TOGGLE_COUNTERZ(10),
5149 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(10),
5150 oe => VCC,
5151         devpor => devpor,
5152         devclrn => devclrn,
5153         devoe => devoe,
5154         outclkena => VCC,
5155         inclkena => VCC,
5156         areset => GND,
5157         sreset => GND);
5158 \D_TOGGLE_COUNTER_OUT_9_\: stratix_io generic map (
5159     operation_mode => "output"
5160     )
5161 port map (
5162 padio => D_TOGGLE_COUNTERZ(9),
5163 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(9),
5164 oe => VCC,
5165         devpor => devpor,
5166         devclrn => devclrn,
5167         devoe => devoe,
5168         outclkena => VCC,
5169         inclkena => VCC,
5170         areset => GND,
5171         sreset => GND);
5172 \D_TOGGLE_COUNTER_OUT_8_\: stratix_io generic map (
5173     operation_mode => "output"
5174     )
5175 port map (
5176 padio => D_TOGGLE_COUNTERZ(8),
5177 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(8),
5178 oe => VCC,
5179         devpor => devpor,
5180         devclrn => devclrn,
5181         devoe => devoe,
5182         outclkena => VCC,
5183         inclkena => VCC,
5184         areset => GND,
5185         sreset => GND);
5186 \D_TOGGLE_COUNTER_OUT_7_\: stratix_io generic map (
5187     operation_mode => "output"
5188     )
5189 port map (
5190 padio => D_TOGGLE_COUNTERZ(7),
5191 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(7),
5192 oe => VCC,
5193         devpor => devpor,
5194         devclrn => devclrn,
5195         devoe => devoe,
5196         outclkena => VCC,
5197         inclkena => VCC,
5198         areset => GND,
5199         sreset => GND);
5200 \D_TOGGLE_COUNTER_OUT_6_\: stratix_io generic map (
5201     operation_mode => "output"
5202     )
5203 port map (
5204 padio => D_TOGGLE_COUNTERZ(6),
5205 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(6),
5206 oe => VCC,
5207         devpor => devpor,
5208         devclrn => devclrn,
5209         devoe => devoe,
5210         outclkena => VCC,
5211         inclkena => VCC,
5212         areset => GND,
5213         sreset => GND);
5214 \D_TOGGLE_COUNTER_OUT_5_\: stratix_io generic map (
5215     operation_mode => "output"
5216     )
5217 port map (
5218 padio => D_TOGGLE_COUNTERZ(5),
5219 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(5),
5220 oe => VCC,
5221         devpor => devpor,
5222         devclrn => devclrn,
5223         devoe => devoe,
5224         outclkena => VCC,
5225         inclkena => VCC,
5226         areset => GND,
5227         sreset => GND);
5228 \D_TOGGLE_COUNTER_OUT_4_\: stratix_io generic map (
5229     operation_mode => "output"
5230     )
5231 port map (
5232 padio => D_TOGGLE_COUNTERZ(4),
5233 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(4),
5234 oe => VCC,
5235         devpor => devpor,
5236         devclrn => devclrn,
5237         devoe => devoe,
5238         outclkena => VCC,
5239         inclkena => VCC,
5240         areset => GND,
5241         sreset => GND);
5242 \D_TOGGLE_COUNTER_OUT_3_\: stratix_io generic map (
5243     operation_mode => "output"
5244     )
5245 port map (
5246 padio => D_TOGGLE_COUNTERZ(3),
5247 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(3),
5248 oe => VCC,
5249         devpor => devpor,
5250         devclrn => devclrn,
5251         devoe => devoe,
5252         outclkena => VCC,
5253         inclkena => VCC,
5254         areset => GND,
5255         sreset => GND);
5256 \D_TOGGLE_COUNTER_OUT_2_\: stratix_io generic map (
5257     operation_mode => "output"
5258     )
5259 port map (
5260 padio => D_TOGGLE_COUNTERZ(2),
5261 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(2),
5262 oe => VCC,
5263         devpor => devpor,
5264         devclrn => devclrn,
5265         devoe => devoe,
5266         outclkena => VCC,
5267         inclkena => VCC,
5268         areset => GND,
5269         sreset => GND);
5270 \D_TOGGLE_COUNTER_OUT_1_\: stratix_io generic map (
5271     operation_mode => "output"
5272     )
5273 port map (
5274 padio => D_TOGGLE_COUNTERZ(1),
5275 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(1),
5276 oe => VCC,
5277         devpor => devpor,
5278         devclrn => devclrn,
5279         devoe => devoe,
5280         outclkena => VCC,
5281         inclkena => VCC,
5282         areset => GND,
5283         sreset => GND);
5284 \D_TOGGLE_COUNTER_OUT_0_\: stratix_io generic map (
5285     operation_mode => "output"
5286     )
5287 port map (
5288 padio => D_TOGGLE_COUNTERZ(0),
5289 datain => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(0),
5290 oe => VCC,
5291         devpor => devpor,
5292         devclrn => devclrn,
5293         devoe => devoe,
5294         outclkena => VCC,
5295         inclkena => VCC,
5296         areset => GND,
5297         sreset => GND);
5298 D_TOGGLE_OUT: stratix_io generic map (
5299     operation_mode => "output"
5300     )
5301 port map (
5302 padio => D_TOGGLEZ,
5303 datain => \VGA_CONTROL_UNIT.TOGGLE_SIG\,
5304 oe => VCC,
5305         devpor => devpor,
5306         devclrn => devclrn,
5307         devoe => devoe,
5308         outclkena => VCC,
5309         inclkena => VCC,
5310         areset => GND,
5311         sreset => GND);
5312 D_STATE_CLK_OUT: stratix_io generic map (
5313     operation_mode => "output"
5314     )
5315 port map (
5316 padio => D_STATE_CLKZ,
5317 datain => G_33,
5318 oe => VCC,
5319         devpor => devpor,
5320         devclrn => devclrn,
5321         devoe => devoe,
5322         outclkena => VCC,
5323         inclkena => VCC,
5324         areset => GND,
5325         sreset => GND);
5326 \D_VSYNC_STATE_OUT_0_\: stratix_io generic map (
5327     operation_mode => "output"
5328     )
5329 port map (
5330 padio => D_VSYNC_STATEZ(0),
5331 datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(0),
5332 oe => VCC,
5333         devpor => devpor,
5334         devclrn => devclrn,
5335         devoe => devoe,
5336         outclkena => VCC,
5337         inclkena => VCC,
5338         areset => GND,
5339         sreset => GND);
5340 \D_VSYNC_STATE_OUT_1_\: stratix_io generic map (
5341     operation_mode => "output"
5342     )
5343 port map (
5344 padio => D_VSYNC_STATEZ(1),
5345 datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(1),
5346 oe => VCC,
5347         devpor => devpor,
5348         devclrn => devclrn,
5349         devoe => devoe,
5350         outclkena => VCC,
5351         inclkena => VCC,
5352         areset => GND,
5353         sreset => GND);
5354 \D_VSYNC_STATE_OUT_2_\: stratix_io generic map (
5355     operation_mode => "output"
5356     )
5357 port map (
5358 padio => D_VSYNC_STATEZ(2),
5359 datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(2),
5360 oe => VCC,
5361         devpor => devpor,
5362         devclrn => devclrn,
5363         devoe => devoe,
5364         outclkena => VCC,
5365         inclkena => VCC,
5366         areset => GND,
5367         sreset => GND);
5368 \D_VSYNC_STATE_OUT_3_\: stratix_io generic map (
5369     operation_mode => "output"
5370     )
5371 port map (
5372 padio => D_VSYNC_STATEZ(3),
5373 datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(3),
5374 oe => VCC,
5375         devpor => devpor,
5376         devclrn => devclrn,
5377         devoe => devoe,
5378         outclkena => VCC,
5379         inclkena => VCC,
5380         areset => GND,
5381         sreset => GND);
5382 \D_VSYNC_STATE_OUT_4_\: stratix_io generic map (
5383     operation_mode => "output"
5384     )
5385 port map (
5386 padio => D_VSYNC_STATEZ(4),
5387 datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(4),
5388 oe => VCC,
5389         devpor => devpor,
5390         devclrn => devclrn,
5391         devoe => devoe,
5392         outclkena => VCC,
5393         inclkena => VCC,
5394         areset => GND,
5395         sreset => GND);
5396 \D_VSYNC_STATE_OUT_5_\: stratix_io generic map (
5397     operation_mode => "output"
5398     )
5399 port map (
5400 padio => D_VSYNC_STATEZ(5),
5401 datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(5),
5402 oe => VCC,
5403         devpor => devpor,
5404         devclrn => devclrn,
5405         devoe => devoe,
5406         outclkena => VCC,
5407         inclkena => VCC,
5408         areset => GND,
5409         sreset => GND);
5410 \D_VSYNC_STATE_OUT_6_\: stratix_io generic map (
5411     operation_mode => "output"
5412     )
5413 port map (
5414 padio => D_VSYNC_STATEZ(6),
5415 datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(6),
5416 oe => VCC,
5417         devpor => devpor,
5418         devclrn => devclrn,
5419         devoe => devoe,
5420         outclkena => VCC,
5421         inclkena => VCC,
5422         areset => GND,
5423         sreset => GND);
5424 \D_HSYNC_STATE_OUT_0_\: stratix_io generic map (
5425     operation_mode => "output"
5426     )
5427 port map (
5428 padio => D_HSYNC_STATEZ(0),
5429 datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(0),
5430 oe => VCC,
5431         devpor => devpor,
5432         devclrn => devclrn,
5433         devoe => devoe,
5434         outclkena => VCC,
5435         inclkena => VCC,
5436         areset => GND,
5437         sreset => GND);
5438 \D_HSYNC_STATE_OUT_1_\: stratix_io generic map (
5439     operation_mode => "output"
5440     )
5441 port map (
5442 padio => D_HSYNC_STATEZ(1),
5443 datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(1),
5444 oe => VCC,
5445         devpor => devpor,
5446         devclrn => devclrn,
5447         devoe => devoe,
5448         outclkena => VCC,
5449         inclkena => VCC,
5450         areset => GND,
5451         sreset => GND);
5452 \D_HSYNC_STATE_OUT_2_\: stratix_io generic map (
5453     operation_mode => "output"
5454     )
5455 port map (
5456 padio => D_HSYNC_STATEZ(2),
5457 datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(2),
5458 oe => VCC,
5459         devpor => devpor,
5460         devclrn => devclrn,
5461         devoe => devoe,
5462         outclkena => VCC,
5463         inclkena => VCC,
5464         areset => GND,
5465         sreset => GND);
5466 \D_HSYNC_STATE_OUT_3_\: stratix_io generic map (
5467     operation_mode => "output"
5468     )
5469 port map (
5470 padio => D_HSYNC_STATEZ(3),
5471 datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(3),
5472 oe => VCC,
5473         devpor => devpor,
5474         devclrn => devclrn,
5475         devoe => devoe,
5476         outclkena => VCC,
5477         inclkena => VCC,
5478         areset => GND,
5479         sreset => GND);
5480 \D_HSYNC_STATE_OUT_4_\: stratix_io generic map (
5481     operation_mode => "output"
5482     )
5483 port map (
5484 padio => D_HSYNC_STATEZ(4),
5485 datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(4),
5486 oe => VCC,
5487         devpor => devpor,
5488         devclrn => devclrn,
5489         devoe => devoe,
5490         outclkena => VCC,
5491         inclkena => VCC,
5492         areset => GND,
5493         sreset => GND);
5494 \D_HSYNC_STATE_OUT_5_\: stratix_io generic map (
5495     operation_mode => "output"
5496     )
5497 port map (
5498 padio => D_HSYNC_STATEZ(5),
5499 datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(5),
5500 oe => VCC,
5501         devpor => devpor,
5502         devclrn => devclrn,
5503         devoe => devoe,
5504         outclkena => VCC,
5505         inclkena => VCC,
5506         areset => GND,
5507         sreset => GND);
5508 \D_HSYNC_STATE_OUT_6_\: stratix_io generic map (
5509     operation_mode => "output"
5510     )
5511 port map (
5512 padio => D_HSYNC_STATEZ(6),
5513 datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(6),
5514 oe => VCC,
5515         devpor => devpor,
5516         devclrn => devclrn,
5517         devoe => devoe,
5518         outclkena => VCC,
5519         inclkena => VCC,
5520         areset => GND,
5521         sreset => GND);
5522 D_B_OUT: stratix_io generic map (
5523     operation_mode => "output"
5524     )
5525 port map (
5526 padio => D_BZ,
5527 datain => \VGA_CONTROL_UNIT.B\,
5528 oe => VCC,
5529         devpor => devpor,
5530         devclrn => devclrn,
5531         devoe => devoe,
5532         outclkena => VCC,
5533         inclkena => VCC,
5534         areset => GND,
5535         sreset => GND);
5536 D_G_OUT: stratix_io generic map (
5537     operation_mode => "output"
5538     )
5539 port map (
5540 padio => D_GZ,
5541 datain => \VGA_CONTROL_UNIT.G\,
5542 oe => VCC,
5543         devpor => devpor,
5544         devclrn => devclrn,
5545         devoe => devoe,
5546         outclkena => VCC,
5547         inclkena => VCC,
5548         areset => GND,
5549         sreset => GND);
5550 D_R_OUT: stratix_io generic map (
5551     operation_mode => "output"
5552     )
5553 port map (
5554 padio => D_RZ,
5555 datain => \VGA_CONTROL_UNIT.R\,
5556 oe => VCC,
5557         devpor => devpor,
5558         devclrn => devclrn,
5559         devoe => devoe,
5560         outclkena => VCC,
5561         inclkena => VCC,
5562         areset => GND,
5563         sreset => GND);
5564 D_V_ENABLE_OUT: stratix_io generic map (
5565     operation_mode => "output"
5566     )
5567 port map (
5568 padio => D_V_ENABLEZ,
5569 datain => \VGA_DRIVER_UNIT.V_ENABLE_SIG\,
5570 oe => VCC,
5571         devpor => devpor,
5572         devclrn => devclrn,
5573         devoe => devoe,
5574         outclkena => VCC,
5575         inclkena => VCC,
5576         areset => GND,
5577         sreset => GND);
5578 D_H_ENABLE_OUT: stratix_io generic map (
5579     operation_mode => "output"
5580     )
5581 port map (
5582 padio => D_H_ENABLEZ,
5583 datain => \VGA_DRIVER_UNIT.H_ENABLE_SIG\,
5584 oe => VCC,
5585         devpor => devpor,
5586         devclrn => devclrn,
5587         devoe => devoe,
5588         outclkena => VCC,
5589         inclkena => VCC,
5590         areset => GND,
5591         sreset => GND);
5592 D_SET_VSYNC_COUNTER_OUT: stratix_io generic map (
5593     operation_mode => "output"
5594     )
5595 port map (
5596 padio => D_SET_VSYNC_COUNTERZ,
5597 datain => \VGA_DRIVER_UNIT.D_SET_VSYNC_COUNTER\,
5598 oe => VCC,
5599         devpor => devpor,
5600         devclrn => devclrn,
5601         devoe => devoe,
5602         outclkena => VCC,
5603         inclkena => VCC,
5604         areset => GND,
5605         sreset => GND);
5606 D_SET_HSYNC_COUNTER_OUT: stratix_io generic map (
5607     operation_mode => "output"
5608     )
5609 port map (
5610 padio => D_SET_HSYNC_COUNTERZ,
5611 datain => \VGA_DRIVER_UNIT.D_SET_HSYNC_COUNTER\,
5612 oe => VCC,
5613         devpor => devpor,
5614         devclrn => devclrn,
5615         devoe => devoe,
5616         outclkena => VCC,
5617         inclkena => VCC,
5618         areset => GND,
5619         sreset => GND);
5620 \D_VSYNC_COUNTER_OUT_9_\: stratix_io generic map (
5621     operation_mode => "output"
5622     )
5623 port map (
5624 padio => D_VSYNC_COUNTERZ(9),
5625 datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(9),
5626 oe => VCC,
5627         devpor => devpor,
5628         devclrn => devclrn,
5629         devoe => devoe,
5630         outclkena => VCC,
5631         inclkena => VCC,
5632         areset => GND,
5633         sreset => GND);
5634 \D_VSYNC_COUNTER_OUT_8_\: stratix_io generic map (
5635     operation_mode => "output"
5636     )
5637 port map (
5638 padio => D_VSYNC_COUNTERZ(8),
5639 datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(8),
5640 oe => VCC,
5641         devpor => devpor,
5642         devclrn => devclrn,
5643         devoe => devoe,
5644         outclkena => VCC,
5645         inclkena => VCC,
5646         areset => GND,
5647         sreset => GND);
5648 \D_VSYNC_COUNTER_OUT_7_\: stratix_io generic map (
5649     operation_mode => "output"
5650     )
5651 port map (
5652 padio => D_VSYNC_COUNTERZ(7),
5653 datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(7),
5654 oe => VCC,
5655         devpor => devpor,
5656         devclrn => devclrn,
5657         devoe => devoe,
5658         outclkena => VCC,
5659         inclkena => VCC,
5660         areset => GND,
5661         sreset => GND);
5662 \D_VSYNC_COUNTER_OUT_6_\: stratix_io generic map (
5663     operation_mode => "output"
5664     )
5665 port map (
5666 padio => D_VSYNC_COUNTERZ(6),
5667 datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(6),
5668 oe => VCC,
5669         devpor => devpor,
5670         devclrn => devclrn,
5671         devoe => devoe,
5672         outclkena => VCC,
5673         inclkena => VCC,
5674         areset => GND,
5675         sreset => GND);
5676 \D_VSYNC_COUNTER_OUT_5_\: stratix_io generic map (
5677     operation_mode => "output"
5678     )
5679 port map (
5680 padio => D_VSYNC_COUNTERZ(5),
5681 datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(5),
5682 oe => VCC,
5683         devpor => devpor,
5684         devclrn => devclrn,
5685         devoe => devoe,
5686         outclkena => VCC,
5687         inclkena => VCC,
5688         areset => GND,
5689         sreset => GND);
5690 \D_VSYNC_COUNTER_OUT_4_\: stratix_io generic map (
5691     operation_mode => "output"
5692     )
5693 port map (
5694 padio => D_VSYNC_COUNTERZ(4),
5695 datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(4),
5696 oe => VCC,
5697         devpor => devpor,
5698         devclrn => devclrn,
5699         devoe => devoe,
5700         outclkena => VCC,
5701         inclkena => VCC,
5702         areset => GND,
5703         sreset => GND);
5704 \D_VSYNC_COUNTER_OUT_3_\: stratix_io generic map (
5705     operation_mode => "output"
5706     )
5707 port map (
5708 padio => D_VSYNC_COUNTERZ(3),
5709 datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(3),
5710 oe => VCC,
5711         devpor => devpor,
5712         devclrn => devclrn,
5713         devoe => devoe,
5714         outclkena => VCC,
5715         inclkena => VCC,
5716         areset => GND,
5717         sreset => GND);
5718 \D_VSYNC_COUNTER_OUT_2_\: stratix_io generic map (
5719     operation_mode => "output"
5720     )
5721 port map (
5722 padio => D_VSYNC_COUNTERZ(2),
5723 datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(2),
5724 oe => VCC,
5725         devpor => devpor,
5726         devclrn => devclrn,
5727         devoe => devoe,
5728         outclkena => VCC,
5729         inclkena => VCC,
5730         areset => GND,
5731         sreset => GND);
5732 \D_VSYNC_COUNTER_OUT_1_\: stratix_io generic map (
5733     operation_mode => "output"
5734     )
5735 port map (
5736 padio => D_VSYNC_COUNTERZ(1),
5737 datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(1),
5738 oe => VCC,
5739         devpor => devpor,
5740         devclrn => devclrn,
5741         devoe => devoe,
5742         outclkena => VCC,
5743         inclkena => VCC,
5744         areset => GND,
5745         sreset => GND);
5746 \D_VSYNC_COUNTER_OUT_0_\: stratix_io generic map (
5747     operation_mode => "output"
5748     )
5749 port map (
5750 padio => D_VSYNC_COUNTERZ(0),
5751 datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(0),
5752 oe => VCC,
5753         devpor => devpor,
5754         devclrn => devclrn,
5755         devoe => devoe,
5756         outclkena => VCC,
5757         inclkena => VCC,
5758         areset => GND,
5759         sreset => GND);
5760 \D_HSYNC_COUNTER_OUT_9_\: stratix_io generic map (
5761     operation_mode => "output"
5762     )
5763 port map (
5764 padio => D_HSYNC_COUNTERZ(9),
5765 datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(9),
5766 oe => VCC,
5767         devpor => devpor,
5768         devclrn => devclrn,
5769         devoe => devoe,
5770         outclkena => VCC,
5771         inclkena => VCC,
5772         areset => GND,
5773         sreset => GND);
5774 \D_HSYNC_COUNTER_OUT_8_\: stratix_io generic map (
5775     operation_mode => "output"
5776     )
5777 port map (
5778 padio => D_HSYNC_COUNTERZ(8),
5779 datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(8),
5780 oe => VCC,
5781         devpor => devpor,
5782         devclrn => devclrn,
5783         devoe => devoe,
5784         outclkena => VCC,
5785         inclkena => VCC,
5786         areset => GND,
5787         sreset => GND);
5788 \D_HSYNC_COUNTER_OUT_7_\: stratix_io generic map (
5789     operation_mode => "output"
5790     )
5791 port map (
5792 padio => D_HSYNC_COUNTERZ(7),
5793 datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(7),
5794 oe => VCC,
5795         devpor => devpor,
5796         devclrn => devclrn,
5797         devoe => devoe,
5798         outclkena => VCC,
5799         inclkena => VCC,
5800         areset => GND,
5801         sreset => GND);
5802 \D_HSYNC_COUNTER_OUT_6_\: stratix_io generic map (
5803     operation_mode => "output"
5804     )
5805 port map (
5806 padio => D_HSYNC_COUNTERZ(6),
5807 datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(6),
5808 oe => VCC,
5809         devpor => devpor,
5810         devclrn => devclrn,
5811         devoe => devoe,
5812         outclkena => VCC,
5813         inclkena => VCC,
5814         areset => GND,
5815         sreset => GND);
5816 \D_HSYNC_COUNTER_OUT_5_\: stratix_io generic map (
5817     operation_mode => "output"
5818     )
5819 port map (
5820 padio => D_HSYNC_COUNTERZ(5),
5821 datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(5),
5822 oe => VCC,
5823         devpor => devpor,
5824         devclrn => devclrn,
5825         devoe => devoe,
5826         outclkena => VCC,
5827         inclkena => VCC,
5828         areset => GND,
5829         sreset => GND);
5830 \D_HSYNC_COUNTER_OUT_4_\: stratix_io generic map (
5831     operation_mode => "output"
5832     )
5833 port map (
5834 padio => D_HSYNC_COUNTERZ(4),
5835 datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(4),
5836 oe => VCC,
5837         devpor => devpor,
5838         devclrn => devclrn,
5839         devoe => devoe,
5840         outclkena => VCC,
5841         inclkena => VCC,
5842         areset => GND,
5843         sreset => GND);
5844 \D_HSYNC_COUNTER_OUT_3_\: stratix_io generic map (
5845     operation_mode => "output"
5846     )
5847 port map (
5848 padio => D_HSYNC_COUNTERZ(3),
5849 datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(3),
5850 oe => VCC,
5851         devpor => devpor,
5852         devclrn => devclrn,
5853         devoe => devoe,
5854         outclkena => VCC,
5855         inclkena => VCC,
5856         areset => GND,
5857         sreset => GND);
5858 \D_HSYNC_COUNTER_OUT_2_\: stratix_io generic map (
5859     operation_mode => "output"
5860     )
5861 port map (
5862 padio => D_HSYNC_COUNTERZ(2),
5863 datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(2),
5864 oe => VCC,
5865         devpor => devpor,
5866         devclrn => devclrn,
5867         devoe => devoe,
5868         outclkena => VCC,
5869         inclkena => VCC,
5870         areset => GND,
5871         sreset => GND);
5872 \D_HSYNC_COUNTER_OUT_1_\: stratix_io generic map (
5873     operation_mode => "output"
5874     )
5875 port map (
5876 padio => D_HSYNC_COUNTERZ(1),
5877 datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(1),
5878 oe => VCC,
5879         devpor => devpor,
5880         devclrn => devclrn,
5881         devoe => devoe,
5882         outclkena => VCC,
5883         inclkena => VCC,
5884         areset => GND,
5885         sreset => GND);
5886 \D_HSYNC_COUNTER_OUT_0_\: stratix_io generic map (
5887     operation_mode => "output"
5888     )
5889 port map (
5890 padio => D_HSYNC_COUNTERZ(0),
5891 datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(0),
5892 oe => VCC,
5893         devpor => devpor,
5894         devclrn => devclrn,
5895         devoe => devoe,
5896         outclkena => VCC,
5897         inclkena => VCC,
5898         areset => GND,
5899         sreset => GND);
5900 D_SET_LINE_COUNTER_OUT: stratix_io generic map (
5901     operation_mode => "output"
5902     )
5903 port map (
5904 padio => D_SET_LINE_COUNTERZ,
5905 datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(1),
5906 oe => VCC,
5907         devpor => devpor,
5908         devclrn => devclrn,
5909         devoe => devoe,
5910         outclkena => VCC,
5911         inclkena => VCC,
5912         areset => GND,
5913         sreset => GND);
5914 D_SET_COLUMN_COUNTER_OUT: stratix_io generic map (
5915     operation_mode => "output"
5916     )
5917 port map (
5918 padio => D_SET_COLUMN_COUNTERZ,
5919 datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(1),
5920 oe => VCC,
5921         devpor => devpor,
5922         devclrn => devclrn,
5923         devoe => devoe,
5924         outclkena => VCC,
5925         inclkena => VCC,
5926         areset => GND,
5927         sreset => GND);
5928 \D_LINE_COUNTER_OUT_8_\: stratix_io generic map (
5929     operation_mode => "output"
5930     )
5931 port map (
5932 padio => D_LINE_COUNTERZ(8),
5933 datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(8),
5934 oe => VCC,
5935         devpor => devpor,
5936         devclrn => devclrn,
5937         devoe => devoe,
5938         outclkena => VCC,
5939         inclkena => VCC,
5940         areset => GND,
5941         sreset => GND);
5942 \D_LINE_COUNTER_OUT_7_\: stratix_io generic map (
5943     operation_mode => "output"
5944     )
5945 port map (
5946 padio => D_LINE_COUNTERZ(7),
5947 datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(7),
5948 oe => VCC,
5949         devpor => devpor,
5950         devclrn => devclrn,
5951         devoe => devoe,
5952         outclkena => VCC,
5953         inclkena => VCC,
5954         areset => GND,
5955         sreset => GND);
5956 \D_LINE_COUNTER_OUT_6_\: stratix_io generic map (
5957     operation_mode => "output"
5958     )
5959 port map (
5960 padio => D_LINE_COUNTERZ(6),
5961 datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(6),
5962 oe => VCC,
5963         devpor => devpor,
5964         devclrn => devclrn,
5965         devoe => devoe,
5966         outclkena => VCC,
5967         inclkena => VCC,
5968         areset => GND,
5969         sreset => GND);
5970 \D_LINE_COUNTER_OUT_5_\: stratix_io generic map (
5971     operation_mode => "output"
5972     )
5973 port map (
5974 padio => D_LINE_COUNTERZ(5),
5975 datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(5),
5976 oe => VCC,
5977         devpor => devpor,
5978         devclrn => devclrn,
5979         devoe => devoe,
5980         outclkena => VCC,
5981         inclkena => VCC,
5982         areset => GND,
5983         sreset => GND);
5984 \D_LINE_COUNTER_OUT_4_\: stratix_io generic map (
5985     operation_mode => "output"
5986     )
5987 port map (
5988 padio => D_LINE_COUNTERZ(4),
5989 datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(4),
5990 oe => VCC,
5991         devpor => devpor,
5992         devclrn => devclrn,
5993         devoe => devoe,
5994         outclkena => VCC,
5995         inclkena => VCC,
5996         areset => GND,
5997         sreset => GND);
5998 \D_LINE_COUNTER_OUT_3_\: stratix_io generic map (
5999     operation_mode => "output"
6000     )
6001 port map (
6002 padio => D_LINE_COUNTERZ(3),
6003 datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(3),
6004 oe => VCC,
6005         devpor => devpor,
6006         devclrn => devclrn,
6007         devoe => devoe,
6008         outclkena => VCC,
6009         inclkena => VCC,
6010         areset => GND,
6011         sreset => GND);
6012 \D_LINE_COUNTER_OUT_2_\: stratix_io generic map (
6013     operation_mode => "output"
6014     )
6015 port map (
6016 padio => D_LINE_COUNTERZ(2),
6017 datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(2),
6018 oe => VCC,
6019         devpor => devpor,
6020         devclrn => devclrn,
6021         devoe => devoe,
6022         outclkena => VCC,
6023         inclkena => VCC,
6024         areset => GND,
6025         sreset => GND);
6026 \D_LINE_COUNTER_OUT_1_\: stratix_io generic map (
6027     operation_mode => "output"
6028     )
6029 port map (
6030 padio => D_LINE_COUNTERZ(1),
6031 datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(1),
6032 oe => VCC,
6033         devpor => devpor,
6034         devclrn => devclrn,
6035         devoe => devoe,
6036         outclkena => VCC,
6037         inclkena => VCC,
6038         areset => GND,
6039         sreset => GND);
6040 \D_LINE_COUNTER_OUT_0_\: stratix_io generic map (
6041     operation_mode => "output"
6042     )
6043 port map (
6044 padio => D_LINE_COUNTERZ(0),
6045 datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(0),
6046 oe => VCC,
6047         devpor => devpor,
6048         devclrn => devclrn,
6049         devoe => devoe,
6050         outclkena => VCC,
6051         inclkena => VCC,
6052         areset => GND,
6053         sreset => GND);
6054 \D_COLUMN_COUNTER_OUT_9_\: stratix_io generic map (
6055     operation_mode => "output"
6056     )
6057 port map (
6058 padio => D_COLUMN_COUNTERZ(9),
6059 datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(9),
6060 oe => VCC,
6061         devpor => devpor,
6062         devclrn => devclrn,
6063         devoe => devoe,
6064         outclkena => VCC,
6065         inclkena => VCC,
6066         areset => GND,
6067         sreset => GND);
6068 \D_COLUMN_COUNTER_OUT_8_\: stratix_io generic map (
6069     operation_mode => "output"
6070     )
6071 port map (
6072 padio => D_COLUMN_COUNTERZ(8),
6073 datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(8),
6074 oe => VCC,
6075         devpor => devpor,
6076         devclrn => devclrn,
6077         devoe => devoe,
6078         outclkena => VCC,
6079         inclkena => VCC,
6080         areset => GND,
6081         sreset => GND);
6082 \D_COLUMN_COUNTER_OUT_7_\: stratix_io generic map (
6083     operation_mode => "output"
6084     )
6085 port map (
6086 padio => D_COLUMN_COUNTERZ(7),
6087 datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(7),
6088 oe => VCC,
6089         devpor => devpor,
6090         devclrn => devclrn,
6091         devoe => devoe,
6092         outclkena => VCC,
6093         inclkena => VCC,
6094         areset => GND,
6095         sreset => GND);
6096 \D_COLUMN_COUNTER_OUT_6_\: stratix_io generic map (
6097     operation_mode => "output"
6098     )
6099 port map (
6100 padio => D_COLUMN_COUNTERZ(6),
6101 datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(6),
6102 oe => VCC,
6103         devpor => devpor,
6104         devclrn => devclrn,
6105         devoe => devoe,
6106         outclkena => VCC,
6107         inclkena => VCC,
6108         areset => GND,
6109         sreset => GND);
6110 \D_COLUMN_COUNTER_OUT_5_\: stratix_io generic map (
6111     operation_mode => "output"
6112     )
6113 port map (
6114 padio => D_COLUMN_COUNTERZ(5),
6115 datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(5),
6116 oe => VCC,
6117         devpor => devpor,
6118         devclrn => devclrn,
6119         devoe => devoe,
6120         outclkena => VCC,
6121         inclkena => VCC,
6122         areset => GND,
6123         sreset => GND);
6124 \D_COLUMN_COUNTER_OUT_4_\: stratix_io generic map (
6125     operation_mode => "output"
6126     )
6127 port map (
6128 padio => D_COLUMN_COUNTERZ(4),
6129 datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(4),
6130 oe => VCC,
6131         devpor => devpor,
6132         devclrn => devclrn,
6133         devoe => devoe,
6134         outclkena => VCC,
6135         inclkena => VCC,
6136         areset => GND,
6137         sreset => GND);
6138 \D_COLUMN_COUNTER_OUT_3_\: stratix_io generic map (
6139     operation_mode => "output"
6140     )
6141 port map (
6142 padio => D_COLUMN_COUNTERZ(3),
6143 datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(3),
6144 oe => VCC,
6145         devpor => devpor,
6146         devclrn => devclrn,
6147         devoe => devoe,
6148         outclkena => VCC,
6149         inclkena => VCC,
6150         areset => GND,
6151         sreset => GND);
6152 \D_COLUMN_COUNTER_OUT_2_\: stratix_io generic map (
6153     operation_mode => "output"
6154     )
6155 port map (
6156 padio => D_COLUMN_COUNTERZ(2),
6157 datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(2),
6158 oe => VCC,
6159         devpor => devpor,
6160         devclrn => devclrn,
6161         devoe => devoe,
6162         outclkena => VCC,
6163         inclkena => VCC,
6164         areset => GND,
6165         sreset => GND);
6166 \D_COLUMN_COUNTER_OUT_1_\: stratix_io generic map (
6167     operation_mode => "output"
6168     )
6169 port map (
6170 padio => D_COLUMN_COUNTERZ(1),
6171 datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(1),
6172 oe => VCC,
6173         devpor => devpor,
6174         devclrn => devclrn,
6175         devoe => devoe,
6176         outclkena => VCC,
6177         inclkena => VCC,
6178         areset => GND,
6179         sreset => GND);
6180 \D_COLUMN_COUNTER_OUT_0_\: stratix_io generic map (
6181     operation_mode => "output"
6182     )
6183 port map (
6184 padio => D_COLUMN_COUNTERZ(0),
6185 datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(0),
6186 oe => VCC,
6187         devpor => devpor,
6188         devclrn => devclrn,
6189         devoe => devoe,
6190         outclkena => VCC,
6191         inclkena => VCC,
6192         areset => GND,
6193         sreset => GND);
6194 D_VSYNC_OUT: stratix_io generic map (
6195     operation_mode => "output"
6196     )
6197 port map (
6198 padio => D_VSYNCZ,
6199 datain => \VGA_DRIVER_UNIT.V_SYNC\,
6200 oe => VCC,
6201         devpor => devpor,
6202         devclrn => devclrn,
6203         devoe => devoe,
6204         outclkena => VCC,
6205         inclkena => VCC,
6206         areset => GND,
6207         sreset => GND);
6208 D_HSYNC_OUT: stratix_io generic map (
6209     operation_mode => "output"
6210     )
6211 port map (
6212 padio => D_HSYNCZ,
6213 datain => \VGA_DRIVER_UNIT.H_SYNC\,
6214 oe => VCC,
6215         devpor => devpor,
6216         devclrn => devclrn,
6217         devoe => devoe,
6218         outclkena => VCC,
6219         inclkena => VCC,
6220         areset => GND,
6221         sreset => GND);
6222 \SEVEN_SEG_PIN_TRI_13_\: stratix_io generic map (
6223     operation_mode => "output"
6224     )
6225 port map (
6226 padio => SEVEN_SEG_PINZ(13),
6227 datain => VCC,
6228 oe => VCC,
6229         devpor => devpor,
6230         devclrn => devclrn,
6231         devoe => devoe,
6232         outclkena => VCC,
6233         inclkena => VCC,
6234         areset => GND,
6235         sreset => GND);
6236 \SEVEN_SEG_PIN_OUT_12_\: stratix_io generic map (
6237     operation_mode => "output"
6238     )
6239 port map (
6240 padio => SEVEN_SEG_PINZ(12),
6241 datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
6242 oe => VCC,
6243         devpor => devpor,
6244         devclrn => devclrn,
6245         devoe => devoe,
6246         outclkena => VCC,
6247         inclkena => VCC,
6248         areset => GND,
6249         sreset => GND);
6250 \SEVEN_SEG_PIN_OUT_11_\: stratix_io generic map (
6251     operation_mode => "output"
6252     )
6253 port map (
6254 padio => SEVEN_SEG_PINZ(11),
6255 datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
6256 oe => VCC,
6257         devpor => devpor,
6258         devclrn => devclrn,
6259         devoe => devoe,
6260         outclkena => VCC,
6261         inclkena => VCC,
6262         areset => GND,
6263         sreset => GND);
6264 \SEVEN_SEG_PIN_OUT_10_\: stratix_io generic map (
6265     operation_mode => "output"
6266     )
6267 port map (
6268 padio => SEVEN_SEG_PINZ(10),
6269 datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
6270 oe => VCC,
6271         devpor => devpor,
6272         devclrn => devclrn,
6273         devoe => devoe,
6274         outclkena => VCC,
6275         inclkena => VCC,
6276         areset => GND,
6277         sreset => GND);
6278 \SEVEN_SEG_PIN_OUT_9_\: stratix_io generic map (
6279     operation_mode => "output"
6280     )
6281 port map (
6282 padio => SEVEN_SEG_PINZ(9),
6283 datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
6284 oe => VCC,
6285         devpor => devpor,
6286         devclrn => devclrn,
6287         devoe => devoe,
6288         outclkena => VCC,
6289         inclkena => VCC,
6290         areset => GND,
6291         sreset => GND);
6292 \SEVEN_SEG_PIN_OUT_8_\: stratix_io generic map (
6293     operation_mode => "output"
6294     )
6295 port map (
6296 padio => SEVEN_SEG_PINZ(8),
6297 datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
6298 oe => VCC,
6299         devpor => devpor,
6300         devclrn => devclrn,
6301         devoe => devoe,
6302         outclkena => VCC,
6303         inclkena => VCC,
6304         areset => GND,
6305         sreset => GND);
6306 \SEVEN_SEG_PIN_OUT_7_\: stratix_io generic map (
6307     operation_mode => "output"
6308     )
6309 port map (
6310 padio => SEVEN_SEG_PINZ(7),
6311 datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
6312 oe => VCC,
6313         devpor => devpor,
6314         devclrn => devclrn,
6315         devoe => devoe,
6316         outclkena => VCC,
6317         inclkena => VCC,
6318         areset => GND,
6319         sreset => GND);
6320 \SEVEN_SEG_PIN_TRI_6_\: stratix_io generic map (
6321     operation_mode => "output"
6322     )
6323 port map (
6324 padio => SEVEN_SEG_PINZ(6),
6325 datain => VCC,
6326 oe => VCC,
6327         devpor => devpor,
6328         devclrn => devclrn,
6329         devoe => devoe,
6330         outclkena => VCC,
6331         inclkena => VCC,
6332         areset => GND,
6333         sreset => GND);
6334 \SEVEN_SEG_PIN_TRI_5_\: stratix_io generic map (
6335     operation_mode => "output"
6336     )
6337 port map (
6338 padio => SEVEN_SEG_PINZ(5),
6339 datain => VCC,
6340 oe => VCC,
6341         devpor => devpor,
6342         devclrn => devclrn,
6343         devoe => devoe,
6344         outclkena => VCC,
6345         inclkena => VCC,
6346         areset => GND,
6347         sreset => GND);
6348 \SEVEN_SEG_PIN_TRI_4_\: stratix_io generic map (
6349     operation_mode => "output"
6350     )
6351 port map (
6352 padio => SEVEN_SEG_PINZ(4),
6353 datain => VCC,
6354 oe => VCC,
6355         devpor => devpor,
6356         devclrn => devclrn,
6357         devoe => devoe,
6358         outclkena => VCC,
6359         inclkena => VCC,
6360         areset => GND,
6361         sreset => GND);
6362 \SEVEN_SEG_PIN_TRI_3_\: stratix_io generic map (
6363     operation_mode => "output"
6364     )
6365 port map (
6366 padio => SEVEN_SEG_PINZ(3),
6367 datain => VCC,
6368 oe => VCC,
6369         devpor => devpor,
6370         devclrn => devclrn,
6371         devoe => devoe,
6372         outclkena => VCC,
6373         inclkena => VCC,
6374         areset => GND,
6375         sreset => GND);
6376 \SEVEN_SEG_PIN_OUT_2_\: stratix_io generic map (
6377     operation_mode => "output"
6378     )
6379 port map (
6380 padio => SEVEN_SEG_PINZ(2),
6381 datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
6382 oe => VCC,
6383         devpor => devpor,
6384         devclrn => devclrn,
6385         devoe => devoe,
6386         outclkena => VCC,
6387         inclkena => VCC,
6388         areset => GND,
6389         sreset => GND);
6390 \SEVEN_SEG_PIN_OUT_1_\: stratix_io generic map (
6391     operation_mode => "output"
6392     )
6393 port map (
6394 padio => SEVEN_SEG_PINZ(1),
6395 datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
6396 oe => VCC,
6397         devpor => devpor,
6398         devclrn => devclrn,
6399         devoe => devoe,
6400         outclkena => VCC,
6401         inclkena => VCC,
6402         areset => GND,
6403         sreset => GND);
6404 \SEVEN_SEG_PIN_TRI_0_\: stratix_io generic map (
6405     operation_mode => "output"
6406     )
6407 port map (
6408 padio => SEVEN_SEG_PINZ(0),
6409 datain => VCC,
6410 oe => VCC,
6411         devpor => devpor,
6412         devclrn => devclrn,
6413         devoe => devoe,
6414         outclkena => VCC,
6415         inclkena => VCC,
6416         areset => GND,
6417         sreset => GND);
6418 VSYNC_PIN_OUT: stratix_io generic map (
6419     operation_mode => "output"
6420     )
6421 port map (
6422 padio => VSYNC_PINZ,
6423 datain => \VGA_DRIVER_UNIT.V_SYNC\,
6424 oe => VCC,
6425         devpor => devpor,
6426         devclrn => devclrn,
6427         devoe => devoe,
6428         outclkena => VCC,
6429         inclkena => VCC,
6430         areset => GND,
6431         sreset => GND);
6432 HSYNC_PIN_OUT: stratix_io generic map (
6433     operation_mode => "output"
6434     )
6435 port map (
6436 padio => HSYNC_PINZ,
6437 datain => \VGA_DRIVER_UNIT.H_SYNC\,
6438 oe => VCC,
6439         devpor => devpor,
6440         devclrn => devclrn,
6441         devoe => devoe,
6442         outclkena => VCC,
6443         inclkena => VCC,
6444         areset => GND,
6445         sreset => GND);
6446 B1_PIN_OUT: stratix_io generic map (
6447     operation_mode => "output"
6448     )
6449 port map (
6450 padio => B1_PINZ,
6451 datain => \VGA_CONTROL_UNIT.B\,
6452 oe => VCC,
6453         devpor => devpor,
6454         devclrn => devclrn,
6455         devoe => devoe,
6456         outclkena => VCC,
6457         inclkena => VCC,
6458         areset => GND,
6459         sreset => GND);
6460 B0_PIN_OUT: stratix_io generic map (
6461     operation_mode => "output"
6462     )
6463 port map (
6464 padio => B0_PINZ,
6465 datain => \VGA_CONTROL_UNIT.B\,
6466 oe => VCC,
6467         devpor => devpor,
6468         devclrn => devclrn,
6469         devoe => devoe,
6470         outclkena => VCC,
6471         inclkena => VCC,
6472         areset => GND,
6473         sreset => GND);
6474 G2_PIN_OUT: stratix_io generic map (
6475     operation_mode => "output"
6476     )
6477 port map (
6478 padio => G2_PINZ,
6479 datain => \VGA_CONTROL_UNIT.G\,
6480 oe => VCC,
6481         devpor => devpor,
6482         devclrn => devclrn,
6483         devoe => devoe,
6484         outclkena => VCC,
6485         inclkena => VCC,
6486         areset => GND,
6487         sreset => GND);
6488 G1_PIN_OUT: stratix_io generic map (
6489     operation_mode => "output"
6490     )
6491 port map (
6492 padio => G1_PINZ,
6493 datain => \VGA_CONTROL_UNIT.G\,
6494 oe => VCC,
6495         devpor => devpor,
6496         devclrn => devclrn,
6497         devoe => devoe,
6498         outclkena => VCC,
6499         inclkena => VCC,
6500         areset => GND,
6501         sreset => GND);
6502 G0_PIN_OUT: stratix_io generic map (
6503     operation_mode => "output"
6504     )
6505 port map (
6506 padio => G0_PINZ,
6507 datain => \VGA_CONTROL_UNIT.G\,
6508 oe => VCC,
6509         devpor => devpor,
6510         devclrn => devclrn,
6511         devoe => devoe,
6512         outclkena => VCC,
6513         inclkena => VCC,
6514         areset => GND,
6515         sreset => GND);
6516 R2_PIN_OUT: stratix_io generic map (
6517     operation_mode => "output"
6518     )
6519 port map (
6520 padio => R2_PINZ,
6521 datain => \VGA_CONTROL_UNIT.R\,
6522 oe => VCC,
6523         devpor => devpor,
6524         devclrn => devclrn,
6525         devoe => devoe,
6526         outclkena => VCC,
6527         inclkena => VCC,
6528         areset => GND,
6529         sreset => GND);
6530 R1_PIN_OUT: stratix_io generic map (
6531     operation_mode => "output"
6532     )
6533 port map (
6534 padio => R1_PINZ,
6535 datain => \VGA_CONTROL_UNIT.R\,
6536 oe => VCC,
6537         devpor => devpor,
6538         devclrn => devclrn,
6539         devoe => devoe,
6540         outclkena => VCC,
6541         inclkena => VCC,
6542         areset => GND,
6543         sreset => GND);
6544 R0_PIN_OUT: stratix_io generic map (
6545     operation_mode => "output"
6546     )
6547 port map (
6548 padio => R0_PINZ,
6549 datain => \VGA_CONTROL_UNIT.R\,
6550 oe => VCC,
6551         devpor => devpor,
6552         devclrn => devclrn,
6553         devoe => devoe,
6554         outclkena => VCC,
6555         inclkena => VCC,
6556         areset => GND,
6557         sreset => GND);
6558 G_33 <= CLK_PIN_C;
6559 VGA_DRIVER_UNIT: vga_driver port map (
6560 line_counter_sig_0 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(0),
6561 line_counter_sig_1 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(1),
6562 line_counter_sig_2 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(2),
6563 line_counter_sig_3 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(3),
6564 line_counter_sig_4 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(4),
6565 line_counter_sig_5 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(5),
6566 line_counter_sig_6 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(6),
6567 line_counter_sig_7 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(7),
6568 line_counter_sig_8 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(8),
6569 dly_counter_1 => DLY_COUNTER(1),
6570 dly_counter_0 => DLY_COUNTER(0),
6571 vsync_state_2 => \VGA_DRIVER_UNIT.VSYNC_STATE\(2),
6572 vsync_state_5 => \VGA_DRIVER_UNIT.VSYNC_STATE\(5),
6573 vsync_state_3 => \VGA_DRIVER_UNIT.VSYNC_STATE\(3),
6574 vsync_state_6 => \VGA_DRIVER_UNIT.VSYNC_STATE\(6),
6575 vsync_state_4 => \VGA_DRIVER_UNIT.VSYNC_STATE\(4),
6576 vsync_state_1 => \VGA_DRIVER_UNIT.VSYNC_STATE\(1),
6577 vsync_state_0 => \VGA_DRIVER_UNIT.VSYNC_STATE\(0),
6578 hsync_state_2 => \VGA_DRIVER_UNIT.HSYNC_STATE\(2),
6579 hsync_state_4 => \VGA_DRIVER_UNIT.HSYNC_STATE\(4),
6580 hsync_state_0 => \VGA_DRIVER_UNIT.HSYNC_STATE\(0),
6581 hsync_state_5 => \VGA_DRIVER_UNIT.HSYNC_STATE\(5),
6582 hsync_state_1 => \VGA_DRIVER_UNIT.HSYNC_STATE\(1),
6583 hsync_state_3 => \VGA_DRIVER_UNIT.HSYNC_STATE\(3),
6584 hsync_state_6 => \VGA_DRIVER_UNIT.HSYNC_STATE\(6),
6585 column_counter_sig_0 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(0),
6586 column_counter_sig_1 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(1),
6587 column_counter_sig_2 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(2),
6588 column_counter_sig_3 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(3),
6589 column_counter_sig_4 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(4),
6590 column_counter_sig_5 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(5),
6591 column_counter_sig_6 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(6),
6592 column_counter_sig_7 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(7),
6593 column_counter_sig_8 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(8),
6594 column_counter_sig_9 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(9),
6595 vsync_counter_9 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(9),
6596 vsync_counter_8 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(8),
6597 vsync_counter_7 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(7),
6598 vsync_counter_6 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(6),
6599 vsync_counter_5 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(5),
6600 vsync_counter_4 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(4),
6601 vsync_counter_3 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(3),
6602 vsync_counter_2 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(2),
6603 vsync_counter_1 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(1),
6604 vsync_counter_0 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(0),
6605 hsync_counter_9 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(9),
6606 hsync_counter_8 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(8),
6607 hsync_counter_7 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(7),
6608 hsync_counter_6 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(6),
6609 hsync_counter_5 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(5),
6610 hsync_counter_4 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(4),
6611 hsync_counter_3 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(3),
6612 hsync_counter_2 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(2),
6613 hsync_counter_1 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(1),
6614 hsync_counter_0 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(0),
6615 d_set_vsync_counter => \VGA_DRIVER_UNIT.D_SET_VSYNC_COUNTER\,
6616 un10_column_counter_siglt6_1 => \VGA_DRIVER_UNIT.COLUMN_COUNT_NEXT.UN10_COLUMN_COUNTER_SIGLT6_1\,
6617 v_sync => \VGA_DRIVER_UNIT.V_SYNC\,
6618 h_sync => \VGA_DRIVER_UNIT.H_SYNC\,
6619 h_enable_sig => \VGA_DRIVER_UNIT.H_ENABLE_SIG\,
6620 v_enable_sig => \VGA_DRIVER_UNIT.V_ENABLE_SIG\,
6621 reset_pin_c => RESET_PIN_C,
6622 un6_dly_counter_0_x => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
6623 d_set_hsync_counter => \VGA_DRIVER_UNIT.D_SET_HSYNC_COUNTER\,
6624 clk_pin_c => CLK_PIN_C);
6625 VGA_CONTROL_UNIT: vga_control port map (
6626 column_counter_sig_5 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(5),
6627 column_counter_sig_0 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(0),
6628 column_counter_sig_1 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(1),
6629 column_counter_sig_3 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(3),
6630 column_counter_sig_4 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(4),
6631 column_counter_sig_2 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(2),
6632 column_counter_sig_9 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(9),
6633 column_counter_sig_8 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(8),
6634 column_counter_sig_7 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(7),
6635 column_counter_sig_6 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(6),
6636 line_counter_sig_0 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(0),
6637 line_counter_sig_1 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(1),
6638 line_counter_sig_2 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(2),
6639 line_counter_sig_8 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(8),
6640 line_counter_sig_3 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(3),
6641 line_counter_sig_5 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(5),
6642 line_counter_sig_4 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(4),
6643 line_counter_sig_7 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(7),
6644 line_counter_sig_6 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(6),
6645 toggle_counter_sig_0 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(0),
6646 toggle_counter_sig_1 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(1),
6647 toggle_counter_sig_2 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(2),
6648 toggle_counter_sig_3 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(3),
6649 toggle_counter_sig_4 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(4),
6650 toggle_counter_sig_5 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(5),
6651 toggle_counter_sig_6 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(6),
6652 toggle_counter_sig_7 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(7),
6653 toggle_counter_sig_8 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(8),
6654 toggle_counter_sig_9 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(9),
6655 toggle_counter_sig_10 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(10),
6656 toggle_counter_sig_11 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(11),
6657 toggle_counter_sig_12 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(12),
6658 toggle_counter_sig_13 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(13),
6659 toggle_counter_sig_14 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(14),
6660 toggle_counter_sig_15 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(15),
6661 toggle_counter_sig_16 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(16),
6662 toggle_counter_sig_17 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(17),
6663 toggle_counter_sig_18 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(18),
6664 toggle_counter_sig_19 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(19),
6665 toggle_counter_sig_20 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(20),
6666 toggle_counter_sig_21 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(21),
6667 toggle_counter_sig_22 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(22),
6668 toggle_counter_sig_23 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(23),
6669 toggle_counter_sig_24 => \VGA_CONTROL_UNIT.TOGGLE_COUNTER_SIG\(24),
6670 v_enable_sig => \VGA_DRIVER_UNIT.V_ENABLE_SIG\,
6671 un10_column_counter_siglt6_1 => \VGA_DRIVER_UNIT.COLUMN_COUNT_NEXT.UN10_COLUMN_COUNTER_SIGLT6_1\,
6672 h_enable_sig => \VGA_DRIVER_UNIT.H_ENABLE_SIG\,
6673 g => \VGA_CONTROL_UNIT.G\,
6674 r => \VGA_CONTROL_UNIT.R\,
6675 b => \VGA_CONTROL_UNIT.B\,
6676 toggle_sig => \VGA_CONTROL_UNIT.TOGGLE_SIG\,
6677 un6_dly_counter_0_x => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
6678 clk_pin_c => CLK_PIN_C);
6679 N_1 <= CLK_PIN_INTERNAL;
6680 N_2 <= RESET_PIN_INTERNAL;
6681 N_85_0 <= R0_PINZ;
6682 N_86_0 <= R1_PINZ;
6683 N_87_0 <= R2_PINZ;
6684 N_88_0 <= G0_PINZ;
6685 N_89_0 <= G1_PINZ;
6686 N_90_0 <= G2_PINZ;
6687 N_91_0 <= B0_PINZ;
6688 N_92_0 <= B1_PINZ;
6689 N_93_0 <= HSYNC_PINZ;
6690 N_94_0 <= VSYNC_PINZ;
6691 N_95_0 <= SEVEN_SEG_PINZ(0);
6692 N_96_0 <= SEVEN_SEG_PINZ(1);
6693 N_97_0 <= SEVEN_SEG_PINZ(2);
6694 N_98_0 <= SEVEN_SEG_PINZ(3);
6695 N_99_0 <= SEVEN_SEG_PINZ(4);
6696 N_100_0 <= SEVEN_SEG_PINZ(5);
6697 N_101_0 <= SEVEN_SEG_PINZ(6);
6698 N_102_0 <= SEVEN_SEG_PINZ(7);
6699 N_103_0 <= SEVEN_SEG_PINZ(8);
6700 N_104_0 <= SEVEN_SEG_PINZ(9);
6701 N_105_0 <= SEVEN_SEG_PINZ(10);
6702 N_106_0 <= SEVEN_SEG_PINZ(11);
6703 N_107_0 <= SEVEN_SEG_PINZ(12);
6704 N_108_0 <= SEVEN_SEG_PINZ(13);
6705 N_109_0 <= D_HSYNCZ;
6706 N_110_0 <= D_VSYNCZ;
6707 N_111_0 <= D_COLUMN_COUNTERZ(0);
6708 N_112_0 <= D_COLUMN_COUNTERZ(1);
6709 N_113_0 <= D_COLUMN_COUNTERZ(2);
6710 N_114_0 <= D_COLUMN_COUNTERZ(3);
6711 N_115_0 <= D_COLUMN_COUNTERZ(4);
6712 N_116_0 <= D_COLUMN_COUNTERZ(5);
6713 N_117_0 <= D_COLUMN_COUNTERZ(6);
6714 N_118 <= D_COLUMN_COUNTERZ(7);
6715 N_119 <= D_COLUMN_COUNTERZ(8);
6716 N_120 <= D_COLUMN_COUNTERZ(9);
6717 N_121 <= D_LINE_COUNTERZ(0);
6718 N_122 <= D_LINE_COUNTERZ(1);
6719 N_123 <= D_LINE_COUNTERZ(2);
6720 N_124 <= D_LINE_COUNTERZ(3);
6721 N_125 <= D_LINE_COUNTERZ(4);
6722 N_126 <= D_LINE_COUNTERZ(5);
6723 N_127 <= D_LINE_COUNTERZ(6);
6724 N_128 <= D_LINE_COUNTERZ(7);
6725 N_129 <= D_LINE_COUNTERZ(8);
6726 N_130 <= D_SET_COLUMN_COUNTERZ;
6727 N_131 <= D_SET_LINE_COUNTERZ;
6728 N_132 <= D_HSYNC_COUNTERZ(0);
6729 N_133 <= D_HSYNC_COUNTERZ(1);
6730 N_134 <= D_HSYNC_COUNTERZ(2);
6731 N_135 <= D_HSYNC_COUNTERZ(3);
6732 N_136 <= D_HSYNC_COUNTERZ(4);
6733 N_137 <= D_HSYNC_COUNTERZ(5);
6734 N_138 <= D_HSYNC_COUNTERZ(6);
6735 N_139 <= D_HSYNC_COUNTERZ(7);
6736 N_140 <= D_HSYNC_COUNTERZ(8);
6737 N_141 <= D_HSYNC_COUNTERZ(9);
6738 N_142 <= D_VSYNC_COUNTERZ(0);
6739 N_143 <= D_VSYNC_COUNTERZ(1);
6740 N_144 <= D_VSYNC_COUNTERZ(2);
6741 N_145 <= D_VSYNC_COUNTERZ(3);
6742 N_146 <= D_VSYNC_COUNTERZ(4);
6743 N_147 <= D_VSYNC_COUNTERZ(5);
6744 N_148 <= D_VSYNC_COUNTERZ(6);
6745 N_149 <= D_VSYNC_COUNTERZ(7);
6746 N_150 <= D_VSYNC_COUNTERZ(8);
6747 N_151 <= D_VSYNC_COUNTERZ(9);
6748 N_152 <= D_SET_HSYNC_COUNTERZ;
6749 N_153 <= D_SET_VSYNC_COUNTERZ;
6750 N_154 <= D_H_ENABLEZ;
6751 N_155 <= D_V_ENABLEZ;
6752 N_156 <= D_RZ;
6753 N_157 <= D_GZ;
6754 N_158 <= D_BZ;
6755 N_159 <= D_HSYNC_STATEZ(6);
6756 N_160 <= D_HSYNC_STATEZ(5);
6757 N_161 <= D_HSYNC_STATEZ(4);
6758 N_162 <= D_HSYNC_STATEZ(3);
6759 N_163 <= D_HSYNC_STATEZ(2);
6760 N_164 <= D_HSYNC_STATEZ(1);
6761 N_165 <= D_HSYNC_STATEZ(0);
6762 N_166 <= D_VSYNC_STATEZ(6);
6763 N_167 <= D_VSYNC_STATEZ(5);
6764 N_168 <= D_VSYNC_STATEZ(4);
6765 N_169 <= D_VSYNC_STATEZ(3);
6766 N_170 <= D_VSYNC_STATEZ(2);
6767 N_171 <= D_VSYNC_STATEZ(1);
6768 N_172 <= D_VSYNC_STATEZ(0);
6769 N_173 <= D_STATE_CLKZ;
6770 N_174 <= D_TOGGLEZ;
6771 N_175 <= D_TOGGLE_COUNTERZ(0);
6772 N_176 <= D_TOGGLE_COUNTERZ(1);
6773 N_177 <= D_TOGGLE_COUNTERZ(2);
6774 N_178 <= D_TOGGLE_COUNTERZ(3);
6775 N_179 <= D_TOGGLE_COUNTERZ(4);
6776 N_180 <= D_TOGGLE_COUNTERZ(5);
6777 N_181 <= D_TOGGLE_COUNTERZ(6);
6778 N_182 <= D_TOGGLE_COUNTERZ(7);
6779 N_183 <= D_TOGGLE_COUNTERZ(8);
6780 N_184 <= D_TOGGLE_COUNTERZ(9);
6781 N_185 <= D_TOGGLE_COUNTERZ(10);
6782 N_186 <= D_TOGGLE_COUNTERZ(11);
6783 N_187 <= D_TOGGLE_COUNTERZ(12);
6784 N_188 <= D_TOGGLE_COUNTERZ(13);
6785 N_189 <= D_TOGGLE_COUNTERZ(14);
6786 N_190 <= D_TOGGLE_COUNTERZ(15);
6787 N_191 <= D_TOGGLE_COUNTERZ(16);
6788 N_192 <= D_TOGGLE_COUNTERZ(17);
6789 N_193 <= D_TOGGLE_COUNTERZ(18);
6790 N_194 <= D_TOGGLE_COUNTERZ(19);
6791 N_195 <= D_TOGGLE_COUNTERZ(20);
6792 N_196 <= D_TOGGLE_COUNTERZ(21);
6793 N_197 <= D_TOGGLE_COUNTERZ(22);
6794 N_198 <= D_TOGGLE_COUNTERZ(23);
6795 N_199 <= D_TOGGLE_COUNTERZ(24);
6796 r0_pin <= N_85_0;
6797 r1_pin <= N_86_0;
6798 r2_pin <= N_87_0;
6799 g0_pin <= N_88_0;
6800 g1_pin <= N_89_0;
6801 g2_pin <= N_90_0;
6802 b0_pin <= N_91_0;
6803 b1_pin <= N_92_0;
6804 hsync_pin <= N_93_0;
6805 vsync_pin <= N_94_0;
6806 seven_seg_pin(0) <= N_95_0;
6807 seven_seg_pin(1) <= N_96_0;
6808 seven_seg_pin(2) <= N_97_0;
6809 seven_seg_pin(3) <= N_98_0;
6810 seven_seg_pin(4) <= N_99_0;
6811 seven_seg_pin(5) <= N_100_0;
6812 seven_seg_pin(6) <= N_101_0;
6813 seven_seg_pin(7) <= N_102_0;
6814 seven_seg_pin(8) <= N_103_0;
6815 seven_seg_pin(9) <= N_104_0;
6816 seven_seg_pin(10) <= N_105_0;
6817 seven_seg_pin(11) <= N_106_0;
6818 seven_seg_pin(12) <= N_107_0;
6819 seven_seg_pin(13) <= N_108_0;
6820 d_hsync <= N_109_0;
6821 d_vsync <= N_110_0;
6822 d_column_counter(0) <= N_111_0;
6823 d_column_counter(1) <= N_112_0;
6824 d_column_counter(2) <= N_113_0;
6825 d_column_counter(3) <= N_114_0;
6826 d_column_counter(4) <= N_115_0;
6827 d_column_counter(5) <= N_116_0;
6828 d_column_counter(6) <= N_117_0;
6829 d_column_counter(7) <= N_118;
6830 d_column_counter(8) <= N_119;
6831 d_column_counter(9) <= N_120;
6832 d_line_counter(0) <= N_121;
6833 d_line_counter(1) <= N_122;
6834 d_line_counter(2) <= N_123;
6835 d_line_counter(3) <= N_124;
6836 d_line_counter(4) <= N_125;
6837 d_line_counter(5) <= N_126;
6838 d_line_counter(6) <= N_127;
6839 d_line_counter(7) <= N_128;
6840 d_line_counter(8) <= N_129;
6841 d_set_column_counter <= N_130;
6842 d_set_line_counter <= N_131;
6843 d_hsync_counter(0) <= N_132;
6844 d_hsync_counter(1) <= N_133;
6845 d_hsync_counter(2) <= N_134;
6846 d_hsync_counter(3) <= N_135;
6847 d_hsync_counter(4) <= N_136;
6848 d_hsync_counter(5) <= N_137;
6849 d_hsync_counter(6) <= N_138;
6850 d_hsync_counter(7) <= N_139;
6851 d_hsync_counter(8) <= N_140;
6852 d_hsync_counter(9) <= N_141;
6853 d_vsync_counter(0) <= N_142;
6854 d_vsync_counter(1) <= N_143;
6855 d_vsync_counter(2) <= N_144;
6856 d_vsync_counter(3) <= N_145;
6857 d_vsync_counter(4) <= N_146;
6858 d_vsync_counter(5) <= N_147;
6859 d_vsync_counter(6) <= N_148;
6860 d_vsync_counter(7) <= N_149;
6861 d_vsync_counter(8) <= N_150;
6862 d_vsync_counter(9) <= N_151;
6863 d_set_hsync_counter <= N_152;
6864 d_set_vsync_counter <= N_153;
6865 d_h_enable <= N_154;
6866 d_v_enable <= N_155;
6867 d_r <= N_156;
6868 d_g <= N_157;
6869 d_b <= N_158;
6870 d_hsync_state(6) <= N_159;
6871 d_hsync_state(5) <= N_160;
6872 d_hsync_state(4) <= N_161;
6873 d_hsync_state(3) <= N_162;
6874 d_hsync_state(2) <= N_163;
6875 d_hsync_state(1) <= N_164;
6876 d_hsync_state(0) <= N_165;
6877 d_vsync_state(6) <= N_166;
6878 d_vsync_state(5) <= N_167;
6879 d_vsync_state(4) <= N_168;
6880 d_vsync_state(3) <= N_169;
6881 d_vsync_state(2) <= N_170;
6882 d_vsync_state(1) <= N_171;
6883 d_vsync_state(0) <= N_172;
6884 d_state_clk <= N_173;
6885 d_toggle <= N_174;
6886 d_toggle_counter(0) <= N_175;
6887 d_toggle_counter(1) <= N_176;
6888 d_toggle_counter(2) <= N_177;
6889 d_toggle_counter(3) <= N_178;
6890 d_toggle_counter(4) <= N_179;
6891 d_toggle_counter(5) <= N_180;
6892 d_toggle_counter(6) <= N_181;
6893 d_toggle_counter(7) <= N_182;
6894 d_toggle_counter(8) <= N_183;
6895 d_toggle_counter(9) <= N_184;
6896 d_toggle_counter(10) <= N_185;
6897 d_toggle_counter(11) <= N_186;
6898 d_toggle_counter(12) <= N_187;
6899 d_toggle_counter(13) <= N_188;
6900 d_toggle_counter(14) <= N_189;
6901 d_toggle_counter(15) <= N_190;
6902 d_toggle_counter(16) <= N_191;
6903 d_toggle_counter(17) <= N_192;
6904 d_toggle_counter(18) <= N_193;
6905 d_toggle_counter(19) <= N_194;
6906 d_toggle_counter(20) <= N_195;
6907 d_toggle_counter(21) <= N_196;
6908 d_toggle_counter(22) <= N_197;
6909 d_toggle_counter(23) <= N_198;
6910 d_toggle_counter(24) <= N_199;
6911 CLK_PIN_INTERNAL <= clk_pin;
6912 RESET_PIN_INTERNAL <= reset_pin;
6913 end beh;
6914