bsp4/Designflow/syn/rev_1/vga.srr

   1 #Build: Synplify Pro C-2009.06, Build 063R, May 19 2009
   2 #install: /opt/synplify/fpga_c200906
   3 #OS: Linux
   4 #Hostname: ti14
   5
   6 #Implementation: rev_1
   7
   8 #Tue Nov  3 17:21:38 2009
   9
  10 $ Start of Compile
  11 #Tue Nov  3 17:21:38 2009
  12
  13 Synopsys VHDL Compiler, version comp400rc, Build 020R, built May 20 2009
  14 Copyright (C) 1994-2009, Synopsys Inc.  All Rights Reserved
  15
  16 @N: CD720 :"/opt/synplify/fpga_c200906/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ns
  17 @N:"/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_ent.vhd":38:7:38:9|Top entity is set to vga.
  18 VHDL syntax check successful!
  19 @N: CD630 :"/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_ent.vhd":38:7:38:9|Synthesizing work.vga.behav
  20 @N: CD231 :"/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_pak.vhd":60:24:60:25|Using onehot encoding for type hsync_state_type (reset_state="1000000")
  21 @N: CD231 :"/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_pak.vhd":62:24:62:25|Using onehot encoding for type vsync_state_type (reset_state="1000000")
  22 @N: CD630 :"/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_control_ent.vhd":37:7:37:17|Synthesizing work.vga_control.behav
  23 Post processing for work.vga_control.behav
  24 @N: CD630 :"/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_driver_ent.vhd":37:7:37:16|Synthesizing work.vga_driver.behav
  25 @N: CD231 :"/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_pak.vhd":60:24:60:25|Using onehot encoding for type hsync_state_type (reset_state="1000000")
  26 @N: CD231 :"/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_pak.vhd":62:24:62:25|Using onehot encoding for type vsync_state_type (reset_state="1000000")
  27 Post processing for work.vga_driver.behav
  28 @N: CD630 :"/homes/burban/didelu/dide_16/bsp4/Designflow/src/board_driver_ent.vhd":36:7:36:18|Synthesizing work.board_driver.behav
  29 Post processing for work.board_driver.behav
  30 Post processing for work.vga.behav
  31 @END
  32 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
  33 # Tue Nov  3 17:21:39 2009
  34
  35 ###########################################################]
  36 Synopsys Altera Technology Mapper, Version map450rc, Build 029R, Built May 22 2009 13:59:53
  37 Copyright (C) 1994-2009, Synopsys Inc.  All Rights Reserved
  38 Product Version C-2009.06
  39 @N: MF249 |Running in 32-bit mode.
  40 @N: MF257 |Gated clock conversion enabled
  41 @N|Running in logic synthesis mode without enhanced optimization
  42
  43 Automatic dissolve during optimization of view:work.vga(behav) of board_driver_unit(board_driver)
  44 Automatic dissolve at startup in view:work.vga(behav) of vga_control_unit(vga_control)
  45
  46 Available hyper_sources - for debug and ip models
  47         None Found
  48
  49 Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 55MB)
  50
  51 @N:"/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_driver_arc.vhd":267:4:267:5|Found counter in view:work.vga_driver(behav) inst vsync_counter[9:0]
  52 @N:"/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_driver_arc.vhd":158:4:158:5|Found counter in view:work.vga_driver(behav) inst hsync_counter[9:0]
  53 Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 55MB)
  54
  55 Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 55MB)
  56
  57 Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 55MB)
  58
  59
  60
  61 #################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[
  62
  63 ======================================================================================
  64                                 Instance:Pin        Generated Clock Optimization Status
  65 ======================================================================================
  66
  67
  68 ##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################]
  69
  70 Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 56MB)
  71
  72 Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 56MB)
  73
  74 Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 56MB)
  75
  76 Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 56MB)
  77
  78 Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
  79
  80 Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
  81
  82 Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
  83
  84 Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
  85
  86 Finished technology mapping (Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 67MB)
  87
  88 Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:04s; Memory used current: 66MB peak: 67MB)
  89
  90 Finished restoring hierarchy (Time elapsed 0h:00m:04s; Memory used current: 66MB peak: 69MB)
  91
  92
  93 Writing Analyst data base /homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.srm
  94 Finished Writing Netlist Databases (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 69MB)
  95
  96 Writing Verilog Netlist and constraint files
  97 Writing .vqm output for Quartus
  98 Writing Cross reference file for Quartus to /homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.xrf
  99 Finished Writing Verilog Netlist and constraint files (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 69MB)
 100
 101 Writing VHDL Simulation files
 102 Finished Writing VHDL Simulation files (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 69MB)
 103
 104 Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 69MB)
 105
 106 @N: MF276 |Gated clock conversion enabled, but no gated clocks found in design
 107 Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 69MB)
 108
 109 Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 69MB)
 110
 111 @N: MF333 |Generated clock conversion enabled, but no generated clocks found in design
 112 Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 69MB)
 113
 114 Found clock vga|clk_pin with period 39.72ns
 115
 116
 117 ##### START OF TIMING REPORT #####[
 118 # Timing Report written on Tue Nov  3 17:21:46 2009
 119 #
 120
 121
 122 Top view:               vga
 123 Requested Frequency:    25.2 MHz
 124 Wire load mode:         top
 125 Paths requested:        5
 126 Constraint File(s):
 127 @N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..
 128
 129 @N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock..
 130
 131
 132
 133 Performance Summary
 134 *******************
 135
 136
 137 Worst slack in design: 34.465
 138
 139                    Requested     Estimated     Requested     Estimated                Clock        Clock
 140 Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group
 141 ----------------------------------------------------------------------------------------------------------------------
 142 vga|clk_pin        25.2 MHz      190.2 MHz     39.722        5.257         34.465     inferred     Inferred_clkgroup_0
 143 ======================================================================================================================
 144
 145
 146
 147
 148
 149 Clock Relationships
 150 *******************
 151
 152 Clocks                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
 153 -----------------------------------------------------------------------------------------------------------------
 154 Starting     Ending       |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
 155 -----------------------------------------------------------------------------------------------------------------
 156 vga|clk_pin  vga|clk_pin  |  39.722      34.465  |  No paths    -      |  No paths    -      |  No paths    -
 157 =================================================================================================================
 158  Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
 159        'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 160
 161
 162
 163 Interface Information
 164 *********************
 165
 166                 No IO constraint found
 167
 168
 169
 170 ====================================
 171 Detailed Report for Clock: vga|clk_pin
 172 ====================================
 173
 174
 175
 176 Starting Points with Worst Slack
 177 ********************************
 178
 179                                            Starting                                                                 Arrival
 180 Instance                                   Reference       Type                 Pin        Net                      Time        Slack
 181                                            Clock
 182 --------------------------------------------------------------------------------------------------------------------------------------
 183 dly_counter[0]                             vga|clk_pin     stratix_lcell_ff     regout     dly_counter[0]           0.176       34.465
 184 dly_counter[1]                             vga|clk_pin     stratix_lcell_ff     regout     dly_counter[1]           0.176       34.584
 185 vga_driver_unit.vsync_counter[6]           vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_6          0.176       34.836
 186 vga_driver_unit.vsync_counter[7]           vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_7          0.176       34.865
 187 vga_control_unit.toggle_counter_sig[1]     vga|clk_pin     stratix_lcell_ff     regout     toggle_counter_sig_1     0.176       34.968
 188 vga_driver_unit.vsync_counter[3]           vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_3          0.176       34.992
 189 vga_driver_unit.vsync_counter[8]           vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_8          0.176       34.992
 190 vga_control_unit.toggle_counter_sig[5]     vga|clk_pin     stratix_lcell_ff     regout     toggle_counter_sig_5     0.176       35.095
 191 vga_driver_unit.vsync_counter[5]           vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_5          0.176       35.111
 192 vga_driver_unit.vsync_counter[4]           vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_4          0.176       35.119
 193 ======================================================================================================================================
 194
 195
 196 Ending Points with Worst Slack
 197 ******************************
 198
 199                                    Starting                                                                     Required
 200 Instance                           Reference       Type                 Pin       Net                           Time         Slack
 201                                    Clock
 202 -----------------------------------------------------------------------------------------------------------------------------------
 203 vga_driver_unit.vsync_state[2]     vga|clk_pin     stratix_lcell_ff     ena       vsync_state_next_2_sqmuxa     38.986       34.465
 204 vga_driver_unit.vsync_state[3]     vga|clk_pin     stratix_lcell_ff     ena       vsync_state_next_2_sqmuxa     38.986       34.465
 205 vga_driver_unit.vsync_state[4]     vga|clk_pin     stratix_lcell_ff     ena       vsync_state_next_2_sqmuxa     38.986       34.465
 206 vga_driver_unit.vsync_state[5]     vga|clk_pin     stratix_lcell_ff     ena       vsync_state_next_2_sqmuxa     38.986       34.465
 207 vga_driver_unit.vsync_state[6]     vga|clk_pin     stratix_lcell_ff     datab     dly_counter_0                 35.641       34.465
 208 vga_driver_unit.vsync_state[6]     vga|clk_pin     stratix_lcell_ff     datac     dly_counter_1                 35.760       34.584
 209 vga_driver_unit.hsync_state[0]     vga|clk_pin     stratix_lcell_ff     ena       hsync_state_3_0_0_0__g0_0     38.986       34.711
 210 vga_driver_unit.hsync_state[1]     vga|clk_pin     stratix_lcell_ff     ena       hsync_state_3_0_0_0__g0_0     38.986       34.711
 211 vga_driver_unit.hsync_state[2]     vga|clk_pin     stratix_lcell_ff     ena       hsync_state_3_0_0_0__g0_0     38.986       34.711
 212 vga_driver_unit.hsync_state[3]     vga|clk_pin     stratix_lcell_ff     ena       hsync_state_3_0_0_0__g0_0     38.986       34.711
 213 ===================================================================================================================================
 214
 215
 216
 217 Worst Path Information
 218 ***********************
 219
 220
 221 Path information for path number 1:
 222     Requested Period:                        39.722
 223     - Setup time:                            0.736
 224     + Clock delay at ending point:           0.000 (ideal)
 225     = Required time:                         38.986
 226
 227     - Propagation time:                      4.521
 228     - Clock delay at starting point:         0.000 (ideal)
 229     = Slack (critical) :                     34.465
 230
 231     Number of logic level(s):                2
 232     Starting point:                          dly_counter[0] / regout
 233     Ending point:                            vga_driver_unit.vsync_state[2] / ena
 234     The start point is clocked by            vga|clk_pin [rising] on pin clk
 235     The end   point is clocked by            vga|clk_pin [rising] on pin clk
 236
 237 Instance / Net                                                     Pin         Pin               Arrival     No. of
 238 Name                                          Type                 Name        Dir     Delay     Time        Fan Out(s)
 239 -----------------------------------------------------------------------------------------------------------------------
 240 dly_counter[0]                                stratix_lcell_ff     regout      Out     0.176     0.176       -
 241 dly_counter[0]                                Net                  -           -       1.000     -           9
 242 vga_driver_unit.vsync_state[6]                stratix_lcell_ff     datab       In      -         1.176       -
 243 vga_driver_unit.vsync_state[6]                stratix_lcell_ff     combout     Out     0.332     1.508       -
 244 un6_dly_counter_0_x                           Net                  -           -       2.160     -           58(49)
 245 vga_driver_unit.vsync_state_next_2_sqmuxa     stratix_lcell        dataa       In      -         3.668       -
 246 vga_driver_unit.vsync_state_next_2_sqmuxa     stratix_lcell        combout     Out     0.459     4.127       -
 247 vsync_state_next_2_sqmuxa                     Net                  -           -       0.393     -           5(2)
 248 vga_driver_unit.vsync_state[2]                stratix_lcell_ff     ena         In      -         4.521       -
 249 =======================================================================================================================
 250 Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 5.257 is 1.703(32.4%) logic and 3.554(67.6%) route.
 251 Fanout format: logic fanout (physical fanout)
 252 Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
 253 *Arrival time includes intrinsic clock delay at start point and clock delay at startpoint
 254
 255
 256
 257 ##### END OF TIMING REPORT #####]
 258
 259 ##### START OF AREA REPORT #####[
 260 Design view:work.vga(behav)
 261 Selecting part EP1S25F672C6
 262 @N: FA174 |The following device usage report estimates place and route data. Please look at the place and route report for final resource usage..
 263
 264 I/O ATOMs:       117
 265
 266 Total LUTs:  181 of 25660 ( 0%)
 267 Logic resources:  183 ATOMs of 25660 ( 0%)
 268
 269 Number of I/O registers
 270                         Output DDRs   :0
 271
 272 ATOM count by mode:
 273   normal:       131
 274   arithmetic:   52
 275
 276 DSP Blocks:     0  (0 nine-bit DSP elements).
 277 DSP Utilization: 0.00% of available 10 blocks (80 nine-bit).
 278 ShiftTap:       0  (0 registers)
 279 MRAM:           0  (0% of 2)
 280 M4Ks:           0  (0% of 138)
 281 M512s:          0  (0% of 224)
 282 Total ESB:      0 bits
 283
 284 ATOMs using regout pin: 88
 285   also using enable pin: 12
 286   also using combout pin: 1
 287 ATOMs using combout pin: 93
 288 Number of Inputs on ATOMs: 759
 289 Number of Nets:   55530
 290
 291 ##### END OF AREA REPORT #####]
 292
 293 Mapper successful!
 294 Process took 0h:00m:05s realtime, 0h:00m:04s cputime
 295 # Tue Nov  3 17:21:46 2009
 296
 297 ###########################################################]