1 <html><body><samp><pre>
3 #Build: Synplify Pro C-2009.06, Build 063R, May 19 2009
4 #install: /opt/synplify/fpga_c200906
10 #Tue Nov 3 17:21:38 2009
12 <a name=compilerReport1>$ Start of Compile</a>
13 #Tue Nov 3 17:21:38 2009
15 Synopsys VHDL Compiler, version comp400rc, Build 020R, built May 20 2009
16 Copyright (C) 1994-2009, Synopsys Inc. All Rights Reserved
18 @N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="/opt/synplify/fpga_c200906/lib/vhd/std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1257265299> | Setting time resolution to ns
19 @N: : <a href="/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_ent.vhd:38:7:38:10:@N::@XP_MSG">vga_ent.vhd(38)</a><!@TM:1257265299> | Top entity is set to vga.
20 VHDL syntax check successful!
21 @N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_ent.vhd:38:7:38:10:@N:CD630:@XP_MSG">vga_ent.vhd(38)</a><!@TM:1257265299> | Synthesizing work.vga.behav
22 @N:<a href="@N:CD231:@XP_HELP">CD231</a> : <a href="/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_pak.vhd:60:24:60:26:@N:CD231:@XP_MSG">vga_pak.vhd(60)</a><!@TM:1257265299> | Using onehot encoding for type hsync_state_type (reset_state="1000000")
23 @N:<a href="@N:CD231:@XP_HELP">CD231</a> : <a href="/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_pak.vhd:62:24:62:26:@N:CD231:@XP_MSG">vga_pak.vhd(62)</a><!@TM:1257265299> | Using onehot encoding for type vsync_state_type (reset_state="1000000")
24 @N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_control_ent.vhd:37:7:37:18:@N:CD630:@XP_MSG">vga_control_ent.vhd(37)</a><!@TM:1257265299> | Synthesizing work.vga_control.behav
25 Post processing for work.vga_control.behav
26 @N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_driver_ent.vhd:37:7:37:17:@N:CD630:@XP_MSG">vga_driver_ent.vhd(37)</a><!@TM:1257265299> | Synthesizing work.vga_driver.behav
27 @N:<a href="@N:CD231:@XP_HELP">CD231</a> : <a href="/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_pak.vhd:60:24:60:26:@N:CD231:@XP_MSG">vga_pak.vhd(60)</a><!@TM:1257265299> | Using onehot encoding for type hsync_state_type (reset_state="1000000")
28 @N:<a href="@N:CD231:@XP_HELP">CD231</a> : <a href="/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_pak.vhd:62:24:62:26:@N:CD231:@XP_MSG">vga_pak.vhd(62)</a><!@TM:1257265299> | Using onehot encoding for type vsync_state_type (reset_state="1000000")
29 Post processing for work.vga_driver.behav
30 @N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/homes/burban/didelu/dide_16/bsp4/Designflow/src/board_driver_ent.vhd:36:7:36:19:@N:CD630:@XP_MSG">board_driver_ent.vhd(36)</a><!@TM:1257265299> | Synthesizing work.board_driver.behav
31 Post processing for work.board_driver.behav
32 Post processing for work.vga.behav
34 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
35 # Tue Nov 3 17:21:39 2009
37 ###########################################################]
38 <a name=mapperReport2>Synopsys Altera Technology Mapper, Version map450rc, Build 029R, Built May 22 2009 13:59:53</a>
39 Copyright (C) 1994-2009, Synopsys Inc. All Rights Reserved
40 Product Version C-2009.06
41 @N:<a href="@N:MF249:@XP_HELP">MF249</a> : <!@TM:1257265306> | Running in 32-bit mode.
42 @N:<a href="@N:MF257:@XP_HELP">MF257</a> : <!@TM:1257265306> | Gated clock conversion enabled
43 @N: : <!@TM:1257265306> | Running in logic synthesis mode without enhanced optimization
45 Automatic dissolve during optimization of view:work.vga(behav) of board_driver_unit(board_driver)
46 Automatic dissolve at startup in view:work.vga(behav) of vga_control_unit(vga_control)
48 Available hyper_sources - for debug and ip models
51 Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 55MB)
53 @N: : <a href="/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_driver_arc.vhd:267:4:267:6:@N::@XP_MSG">vga_driver_arc.vhd(267)</a><!@TM:1257265306> | Found counter in view:work.vga_driver(behav) inst vsync_counter[9:0]
54 @N: : <a href="/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_driver_arc.vhd:158:4:158:6:@N::@XP_MSG">vga_driver_arc.vhd(158)</a><!@TM:1257265306> | Found counter in view:work.vga_driver(behav) inst hsync_counter[9:0]
55 Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 55MB)
57 Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 55MB)
59 Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 55MB)
63 #################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[
65 ======================================================================================
66 Instance:Pin Generated Clock Optimization Status
67 ======================================================================================
70 ##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################]
72 Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 56MB)
74 Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 56MB)
76 Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 56MB)
78 Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 56MB)
80 Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
82 Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
84 Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
86 Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 56MB)
88 Finished technology mapping (Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 67MB)
90 Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:04s; Memory used current: 66MB peak: 67MB)
92 Finished restoring hierarchy (Time elapsed 0h:00m:04s; Memory used current: 66MB peak: 69MB)
95 Writing Analyst data base /homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.srm
96 Finished Writing Netlist Databases (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 69MB)
98 Writing Verilog Netlist and constraint files
99 Writing .vqm output for Quartus
100 Writing Cross reference file for Quartus to /homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.xrf
101 Finished Writing Verilog Netlist and constraint files (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 69MB)
103 Writing VHDL Simulation files
104 Finished Writing VHDL Simulation files (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 69MB)
106 Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 69MB)
108 @N:<a href="@N:MF276:@XP_HELP">MF276</a> : <!@TM:1257265306> | Gated clock conversion enabled, but no gated clocks found in design
109 Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 69MB)
111 Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 69MB)
113 @N:<a href="@N:MF333:@XP_HELP">MF333</a> : <!@TM:1257265306> | Generated clock conversion enabled, but no generated clocks found in design
114 Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 69MB)
116 Found clock vga|clk_pin with period 39.72ns
119 <a name=timingReport3>##### START OF TIMING REPORT #####[</a>
120 # Timing Report written on Tue Nov 3 17:21:46 2009
125 Requested Frequency: 25.2 MHz
129 @N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1257265306> | This timing report estimates place and route data. Please look at the place and route timing report for final timing..
131 @N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1257265306> | Clock constraints cover only FF-to-FF paths associated with the clock..
135 <a name=performanceSummary4>Performance Summary </a>
139 Worst slack in design: 34.465
141 Requested Estimated Requested Estimated Clock Clock
142 Starting Clock Frequency Frequency Period Period Slack Type Group
143 ----------------------------------------------------------------------------------------------------------------------
144 vga|clk_pin 25.2 MHz 190.2 MHz 39.722 5.257 34.465 inferred Inferred_clkgroup_0
145 ======================================================================================================================
151 <a name=clockRelationships5>Clock Relationships</a>
154 Clocks | rise to rise | fall to fall | rise to fall | fall to rise
155 -----------------------------------------------------------------------------------------------------------------
156 Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
157 -----------------------------------------------------------------------------------------------------------------
158 vga|clk_pin vga|clk_pin | 39.722 34.465 | No paths - | No paths - | No paths -
159 =================================================================================================================
160 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
161 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
165 <a name=interfaceInfo6>Interface Information </a>
166 *********************
168 No IO constraint found
172 ====================================
173 <a name=clockReport7>Detailed Report for Clock: vga|clk_pin</a>
174 ====================================
178 <a name=startingSlack8>Starting Points with Worst Slack</a>
179 ********************************
182 Instance Reference Type Pin Net Time Slack
184 --------------------------------------------------------------------------------------------------------------------------------------
185 dly_counter[0] vga|clk_pin stratix_lcell_ff regout dly_counter[0] 0.176 34.465
186 dly_counter[1] vga|clk_pin stratix_lcell_ff regout dly_counter[1] 0.176 34.584
187 vga_driver_unit.vsync_counter[6] vga|clk_pin stratix_lcell_ff regout vsync_counter_6 0.176 34.836
188 vga_driver_unit.vsync_counter[7] vga|clk_pin stratix_lcell_ff regout vsync_counter_7 0.176 34.865
189 vga_control_unit.toggle_counter_sig[1] vga|clk_pin stratix_lcell_ff regout toggle_counter_sig_1 0.176 34.968
190 vga_driver_unit.vsync_counter[3] vga|clk_pin stratix_lcell_ff regout vsync_counter_3 0.176 34.992
191 vga_driver_unit.vsync_counter[8] vga|clk_pin stratix_lcell_ff regout vsync_counter_8 0.176 34.992
192 vga_control_unit.toggle_counter_sig[5] vga|clk_pin stratix_lcell_ff regout toggle_counter_sig_5 0.176 35.095
193 vga_driver_unit.vsync_counter[5] vga|clk_pin stratix_lcell_ff regout vsync_counter_5 0.176 35.111
194 vga_driver_unit.vsync_counter[4] vga|clk_pin stratix_lcell_ff regout vsync_counter_4 0.176 35.119
195 ======================================================================================================================================
198 <a name=endingSlack9>Ending Points with Worst Slack</a>
199 ******************************
202 Instance Reference Type Pin Net Time Slack
204 -----------------------------------------------------------------------------------------------------------------------------------
205 vga_driver_unit.vsync_state[2] vga|clk_pin stratix_lcell_ff ena vsync_state_next_2_sqmuxa 38.986 34.465
206 vga_driver_unit.vsync_state[3] vga|clk_pin stratix_lcell_ff ena vsync_state_next_2_sqmuxa 38.986 34.465
207 vga_driver_unit.vsync_state[4] vga|clk_pin stratix_lcell_ff ena vsync_state_next_2_sqmuxa 38.986 34.465
208 vga_driver_unit.vsync_state[5] vga|clk_pin stratix_lcell_ff ena vsync_state_next_2_sqmuxa 38.986 34.465
209 vga_driver_unit.vsync_state[6] vga|clk_pin stratix_lcell_ff datab dly_counter_0 35.641 34.465
210 vga_driver_unit.vsync_state[6] vga|clk_pin stratix_lcell_ff datac dly_counter_1 35.760 34.584
211 vga_driver_unit.hsync_state[0] vga|clk_pin stratix_lcell_ff ena hsync_state_3_0_0_0__g0_0 38.986 34.711
212 vga_driver_unit.hsync_state[1] vga|clk_pin stratix_lcell_ff ena hsync_state_3_0_0_0__g0_0 38.986 34.711
213 vga_driver_unit.hsync_state[2] vga|clk_pin stratix_lcell_ff ena hsync_state_3_0_0_0__g0_0 38.986 34.711
214 vga_driver_unit.hsync_state[3] vga|clk_pin stratix_lcell_ff ena hsync_state_3_0_0_0__g0_0 38.986 34.711
215 ===================================================================================================================================
219 <a name=worstPaths10>Worst Path Information</a>
220 <a href="/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.srr:fp:13748:14828:@XP_NAMES_GATE">View Worst Path in Analyst</a>
221 ***********************
224 Path information for path number 1:
225 Requested Period: 39.722
227 + Clock delay at ending point: 0.000 (ideal)
228 = Required time: 38.986
230 - Propagation time: 4.521
231 - Clock delay at starting point: 0.000 (ideal)
232 = Slack (critical) : 34.465
234 Number of logic level(s): 2
235 Starting point: dly_counter[0] / regout
236 Ending point: vga_driver_unit.vsync_state[2] / ena
237 The start point is clocked by vga|clk_pin [rising] on pin clk
238 The end point is clocked by vga|clk_pin [rising] on pin clk
240 Instance / Net Pin Pin Arrival No. of
241 Name Type Name Dir Delay Time Fan Out(s)
242 -----------------------------------------------------------------------------------------------------------------------
243 dly_counter[0] stratix_lcell_ff regout Out 0.176 0.176 -
244 dly_counter[0] Net - - 1.000 - 9
245 vga_driver_unit.vsync_state[6] stratix_lcell_ff datab In - 1.176 -
246 vga_driver_unit.vsync_state[6] stratix_lcell_ff combout Out 0.332 1.508 -
247 un6_dly_counter_0_x Net - - 2.160 - 58(49)
248 vga_driver_unit.vsync_state_next_2_sqmuxa stratix_lcell dataa In - 3.668 -
249 vga_driver_unit.vsync_state_next_2_sqmuxa stratix_lcell combout Out 0.459 4.127 -
250 vsync_state_next_2_sqmuxa Net - - 0.393 - 5(2)
251 vga_driver_unit.vsync_state[2] stratix_lcell_ff ena In - 4.521 -
252 =======================================================================================================================
253 Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 5.257 is 1.703(32.4%) logic and 3.554(67.6%) route.
254 Fanout format: logic fanout (physical fanout)
255 Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
256 *Arrival time includes intrinsic clock delay at start point and clock delay at startpoint
260 ##### END OF TIMING REPORT #####]
262 <a name=areaReport11>##### START OF AREA REPORT #####[</a>
263 Design view:work.vga(behav)
264 Selecting part EP1S25F672C6
265 @N:<a href="@N:FA174:@XP_HELP">FA174</a> : <!@TM:1257265306> | The following device usage report estimates place and route data. Please look at the place and route report for final resource usage..
269 Total LUTs: 181 of 25660 ( 0%)
270 Logic resources: 183 ATOMs of 25660 ( 0%)
272 Number of I/O registers
279 DSP Blocks: 0 (0 nine-bit DSP elements).
280 DSP Utilization: 0.00% of available 10 blocks (80 nine-bit).
281 ShiftTap: 0 (0 registers)
287 ATOMs using regout pin: 88
288 also using enable pin: 12
289 also using combout pin: 1
290 ATOMs using combout pin: 93
291 Number of Inputs on ATOMs: 759
292 Number of Nets: 55530
294 ##### END OF AREA REPORT #####]
297 Process took 0h:00m:05s realtime, 0h:00m:04s cputime
298 # Tue Nov 3 17:21:46 2009
300 ###########################################################]