after slot5
[dide_16.git] / bsp4 / Designflow / sim / pre / work / @_opt / voptve8zdn
1 m255
2 K3
3 13
4 cModel Technology
5 Z0 d/homes/burban/didelu/dide_16/bsp4/Designflow/sim/pre
6 T_opt
7 Z1 V9ZLk`O78oFgz7?3D`AM6m3
8 Z2 04 12 0 work vga_conf_pre 1
9 Z3 =1-0015609ed0a8-4af058ea-7c4d1-790d
10 Z4 o-quiet -auto_acc_if_foreign -work work
11 Z5 n@_opt
12 Z6 OE;O;6.5b;42
13 Evga
14 Z7 w1257265305
15 Z8 DPx17 __model_tech/ieee 16 vital_primitives 0 22 E9g6AWKAc2T]enMfl94If3
16 Z9 DPx20 __model_tech/stratix 17 stratix_atom_pack 0 22 4LU4R]0>3N6GcAdgd1O1R2
17 Z10 DPx17 __model_tech/ieee 12 vital_timing 0 22 OBWK>;kUYmkG<OChK2lhV1
18 Z11 DPx20 __model_tech/stratix 18 stratix_components 0 22 ETJi=`V@8?ceQEj0KODmn3
19 Z12 DPx21 __model_tech/synplify 10 components 0 22 @=LFfPB8UiBPm8Y3jZ0Dj3
20 Z13 DPx17 __model_tech/ieee 11 numeric_std 0 22 =NSdli^?T5OD8;4F<blj<3
21 Z14 DPx17 __model_tech/ieee 14 std_logic_1164 0 22 GH1=`jDDBJ=`LM;:Ak`kf2
22 32
23 Z15 8/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vhm
24 Z16 F/homes/burban/didelu/dide_16/bsp4/Designflow/syn/rev_1/vga.vhm
25 l0
26 L4533
27 Z17 V_AKaP>g_z3;H?[j4SIkEJ3
28 Z18 OE;C;6.5b;42
29 Z19 o-work work
30 Z20 tExplicit 1
31 Z21 !s100 GLiW2HX1d;F:740SRcE`T1
32 Abeh
33 Z22 DEx57 /homes/burban/didelu/dide_16/bsp4/Designflow/sim/pre/work 11 vga_control 0 22 c[8UcKzm1=5YbM[1P_A8V0
34 Z23 DEx57 /homes/burban/didelu/dide_16/bsp4/Designflow/sim/pre/work 10 vga_driver 0 22 ][gj?A8M9aEN4T?IfB[nn2
35 Z24 DEx20 __model_tech/stratix 10 stratix_io 0 22 8g8W4@DX]PW8dgJFjd5lT1
36 Z25 DEx20 __model_tech/stratix 13 stratix_lcell 0 22 aWl_l1>i5>lzY<SO57h5o1
37 R8
38 R9
39 R10
40 R11
41 R12
42 R13
43 R14
44 Z26 DEx57 /homes/burban/didelu/dide_16/bsp4/Designflow/sim/pre/work 3 vga 0 22 _AKaP>g_z3;H?[j4SIkEJ3
45 32
46 Z27 Mx8 17 __model_tech/ieee 14 std_logic_1164
47 Z28 Mx7 17 __model_tech/ieee 11 numeric_std
48 Z29 Mx6 21 __model_tech/synplify 10 components
49 Z30 Mx5 20 __model_tech/stratix 18 stratix_components
50 Z31 Mx4 17 __model_tech/ieee 12 vital_timing
51 Z32 Mx3 16 __model_tech/std 6 textio
52 Z33 Mx2 20 __model_tech/stratix 17 stratix_atom_pack
53 Z34 Mx1 17 __model_tech/ieee 16 vital_primitives
54 l4873
55 L4570
56 Z35 V4MkFMEzoaBO_>SXMeUCLU0
57 R18
58 R19
59 R20
60 Z36 !s100 IFXRAMl`fOYGC@`o>zE=S3
61 Cvga_conf_pre
62 R8
63 R9
64 R10
65 R11
66 R12
67 R13
68 R26
69 DAx57 /homes/burban/didelu/dide_16/bsp4/Designflow/sim/pre/work 10 vga_pre_tb 9 structure 22 JFe?g0DaUzZBYk[>IoSWP0
70 Z37 DPx57 /homes/burban/didelu/dide_16/bsp4/Designflow/sim/pre/work 7 vga_pak 0 22 HkmzP=gd;mD@MOhh4AYKl3
71 Z38 DPx17 __model_tech/ieee 15 std_logic_arith 0 22 GJbAT?7@hRQU9IQ702DT]2
72 Z39 DPx17 __model_tech/ieee 18 std_logic_unsigned 0 22 hEMVMlaNCR^<OOoVNV;m90
73 R14
74 Z40 DEx57 /homes/burban/didelu/dide_16/bsp4/Designflow/sim/pre/work 10 vga_pre_tb 0 22 lBieNQVlYd]7:AWzH`k4l2
75 32
76 Z41 Mx11 17 __model_tech/ieee 14 std_logic_1164
77 Z42 Mx10 17 __model_tech/ieee 18 std_logic_unsigned
78 Z43 Mx9 17 __model_tech/ieee 15 std_logic_arith
79 Z44 Mx8 57 /homes/burban/didelu/dide_16/bsp4/Designflow/sim/pre/work 7 vga_pak
80 R28
81 R29
82 R30
83 R31
84 R32
85 R33
86 R34
87 Z45 astructure
88 Z46 evga_pre_tb
89 Z47 w1257262050
90 Z48 8/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_pre_tb.vhd
91 Z49 F/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_pre_tb.vhd
92 l0
93 L189
94 Z50 VaNjILBk^@SVk6Z1ONfaFf3
95 R18
96 R19
97 R20
98 Z51 !s100 VZQjaChjIO3TWTR03Wl1B1
99 Evga_control
100 R7
101 R8
102 R9
103 R10
104 R11
105 R12
106 R13
107 R14
108 32
109 R15
110 R16
111 l0
112 L21
113 Z52 Vc[8UcKzm1=5YbM[1P_A8V0
114 R18
115 R19
116 R20
117 Z53 !s100 QQaQ1z6<=O3a[ZeJl5eU?2
118 Abeh
119 Z54 DEx20 __model_tech/stratix 22 stratix_lcell_register 0 22 CWH?gQ078^87jkOg?o7Z63
120 Z55 DEx20 __model_tech/stratix 20 stratix_asynch_lcell 0 22 8j4Kk3oSOGiVF;kHH9H=I1
121 R25
122 R8
123 R9
124 R10
125 R11
126 R12
127 R13
128 R14
129 R22
130 32
131 R27
132 R28
133 R29
134 R30
135 R31
136 R32
137 R33
138 R34
139 l133
140 L78
141 Z56 VM2^VYFBjUfEgbCAe?[1`a0
142 R18
143 R19
144 R20
145 Z57 !s100 RC]fSSYMGlQdlomZHN6N81
146 Evga_driver
147 R7
148 R8
149 R9
150 R10
151 R11
152 R12
153 R13
154 R14
155 32
156 R15
157 R16
158 l0
159 L1308
160 Z58 V][gj?A8M9aEN4T?IfB[nn2
161 R18
162 R19
163 R20
164 Z59 !s100 c<J3@6GSPO89]PVD@Ao@@0
165 Abeh
166 R54
167 R55
168 R25
169 R8
170 R9
171 R10
172 R11
173 R12
174 R13
175 R14
176 R23
177 32
178 R27
179 R28
180 R29
181 R30
182 R31
183 R32
184 R33
185 R34
186 l1506
187 L1377
188 Z60 VeB^:=KgUKlJ:>DP5D^=MT3
189 R18
190 R19
191 R20
192 Z61 !s100 ShYcRb34UG[M_Lj;KLTFh0
193 Pvga_pak
194 R38
195 R39
196 R14
197 32
198 Z62 Mx3 17 __model_tech/ieee 14 std_logic_1164
199 Mx2 17 __model_tech/ieee 18 std_logic_unsigned
200 Z63 Mx1 17 __model_tech/ieee 15 std_logic_arith
201 Z64 w1257265128
202 Z65 8/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_pak.vhd
203 Z66 F/homes/burban/didelu/dide_16/bsp4/Designflow/src/vga_pak.vhd
204 l0
205 L35
206 Z67 VHkmzP=gd;mD@MOhh4AYKl3
207 R18
208 R19
209 R20
210 Z68 !s100 VL:Z2?FJISz9N5>XaK:5k0
211 Evga_pre_tb
212 R47
213 R37
214 R38
215 R39
216 R14
217 32
218 R48
219 R49
220 l0
221 L37
222 Z69 VlBieNQVlYd]7:AWzH`k4l2
223 R18
224 R19
225 R20
226 Z70 !s100 E`OC=4TKQQZR9AW6:_aWL3
227 Astructure
228 R8
229 R9
230 R10
231 R11
232 R12
233 R13
234 R26
235 R37
236 R38
237 R39
238 R14
239 R40
240 32
241 R41
242 R42
243 R43
244 R44
245 R28
246 R29
247 R30
248 R31
249 R32
250 R33
251 R34
252 l101
253 L45
254 Z71 VJFe?g0DaUzZBYk[>IoSWP0
255 R18
256 R19
257 R20
258 Z72 !s100 mXQY>;W35^hoSE<0NCLIV3