7 Z1 DPx17 __model_tech/ieee 14 std_logic_1164 0 22 GH1=`jDDBJ=`LM;:Ak`kf2
10 Z3 Mx1 17 __model_tech/ieee 14 std_logic_1164
12 Z5 FC:/Programme/Synplicity/fpga_81/lib/vhdl_sim/synplify.vhd
15 Z6 V@=LFfPB8UiBPm8Y3jZ0Dj3
18 Z9 tExplicit 1 GenerateLoopIterationMax 100000
21 Z10 DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
25 Z11 VcQCCenBd1lX<X2e`IDo]j0
32 Z12 DE work prim_counter cQCCenBd1lX<X2e`IDo]j0
35 Z13 VoLVi?g_jUJ43C[<A]FZ_@3
38 Z14 M1 ieee std_logic_1164
47 Z15 VS5Io]C1B4zYM>Wm_j9FUd2
54 Z16 DE work prim_dff S5Io]C1B4zYM>Wm_j9FUd2
57 Z17 VT[KO?W>VV?5LNHP^g`R[_1
69 Z18 VmR@CKl<SfVQ2Dg<2oc`ZI1
76 Z19 DE work prim_latch mR@CKl<SfVQ2Dg<2oc`ZI1
79 Z20 VSjC?ZATX9ZbnGVb2fU>Rn3
87 Z21 DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
88 Z22 DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
93 Z23 Vg`]Yh^7Wk:d6^Jda_dECB1
102 Z24 DE work prim_ramd g`]Yh^7Wk:d6^Jda_dECB1
105 Z25 V>^iBn8PBXdNVQ^KnC[EQ`0
108 Z26 M3 ieee std_logic_1164
109 Z27 M2 ieee std_logic_unsigned
110 Z28 M1 ieee std_logic_arith
119 Z29 VHZDBHc7EHMMlKLZ:7l2?P1
126 Z30 DE work prim_sdff HZDBHc7EHMMlKLZ:7l2?P1
129 Z31 V@KF;3mY=J>QVDOIl9k?c51
141 Z32 VaajiH=affEnY`VBgj=VoV2
148 Z33 DE work zeroohm1 aajiH=affEnY`VBgj=VoV2
151 Z34 V1g5GS;_H4iKP[SR00lVV73