bsp4/Designflow/ppr/sim/simulation/modelsim/vga.vho

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   2 -- Your use of Altera Corporation's design tools, logic functions
   3 -- and other software and tools, and its AMPP partner logic
   4 -- functions, and any output files from any of the foregoing
   5 -- (including device programming or simulation files), and any
   6 -- associated documentation or information are expressly subject
   7 -- to the terms and conditions of the Altera Program License
   8 -- Subscription Agreement, Altera MegaCore Function License
   9 -- Agreement, or other applicable license agreement, including,
  10 -- without limitation, that your use is for the sole purpose of
  11 -- programming logic devices manufactured by Altera and sold by
  12 -- Altera or its authorized distributors.  Please refer to the
  13 -- applicable agreement for further details.
  14
  15 -- VENDOR "Altera"
  16 -- PROGRAM "Quartus II"
  17 -- VERSION "Version 9.0 Build 132 02/25/2009 SJ Full Version"
  18
  19 -- DATE "11/03/2009 17:31:40"
  20
  21 --
  22 -- Device: Altera EP1S25F672C6 Package FBGA672
  23 --
  24
  25 --
  26 -- This VHDL file should be used for ModelSim (VHDL) only
  27 --
  28
  29 LIBRARY IEEE, stratix;
  30 USE IEEE.std_logic_1164.all;
  31 USE stratix.stratix_components.all;
  32
  33 ENTITY  vga IS
  34     PORT (
  35         clk_pin : IN std_logic;
  36         reset_pin : IN std_logic;
  37         r0_pin : OUT std_logic;
  38         r1_pin : OUT std_logic;
  39         r2_pin : OUT std_logic;
  40         g0_pin : OUT std_logic;
  41         g1_pin : OUT std_logic;
  42         g2_pin : OUT std_logic;
  43         b0_pin : OUT std_logic;
  44         b1_pin : OUT std_logic;
  45         hsync_pin : OUT std_logic;
  46         vsync_pin : OUT std_logic;
  47         seven_seg_pin : OUT std_logic_vector(13 DOWNTO 0);
  48         d_hsync : OUT std_logic;
  49         d_vsync : OUT std_logic;
  50         d_column_counter : OUT std_logic_vector(9 DOWNTO 0);
  51         d_line_counter : OUT std_logic_vector(8 DOWNTO 0);
  52         d_set_column_counter : OUT std_logic;
  53         d_set_line_counter : OUT std_logic;
  54         d_hsync_counter : OUT std_logic_vector(9 DOWNTO 0);
  55         d_vsync_counter : OUT std_logic_vector(9 DOWNTO 0);
  56         d_set_hsync_counter : OUT std_logic;
  57         d_set_vsync_counter : OUT std_logic;
  58         d_h_enable : OUT std_logic;
  59         d_v_enable : OUT std_logic;
  60         d_r : OUT std_logic;
  61         d_g : OUT std_logic;
  62         d_b : OUT std_logic;
  63         d_hsync_state : OUT std_logic_vector(0 TO 6);
  64         d_vsync_state : OUT std_logic_vector(0 TO 6);
  65         d_state_clk : OUT std_logic;
  66         d_toggle : OUT std_logic;
  67         d_toggle_counter : OUT std_logic_vector(24 DOWNTO 0)
  68         );
  69 END vga;
  70
  71 ARCHITECTURE structure OF vga IS
  72 SIGNAL gnd : std_logic := '0';
  73 SIGNAL vcc : std_logic := '1';
  74 SIGNAL devoe : std_logic := '1';
  75 SIGNAL devclrn : std_logic := '1';
  76 SIGNAL devpor : std_logic := '1';
  77 SIGNAL ww_devoe : std_logic;
  78 SIGNAL ww_devclrn : std_logic;
  79 SIGNAL ww_devpor : std_logic;
  80 SIGNAL ww_clk_pin : std_logic;
  81 SIGNAL ww_reset_pin : std_logic;
  82 SIGNAL ww_r0_pin : std_logic;
  83 SIGNAL ww_r1_pin : std_logic;
  84 SIGNAL ww_r2_pin : std_logic;
  85 SIGNAL ww_g0_pin : std_logic;
  86 SIGNAL ww_g1_pin : std_logic;
  87 SIGNAL ww_g2_pin : std_logic;
  88 SIGNAL ww_b0_pin : std_logic;
  89 SIGNAL ww_b1_pin : std_logic;
  90 SIGNAL ww_hsync_pin : std_logic;
  91 SIGNAL ww_vsync_pin : std_logic;
  92 SIGNAL ww_seven_seg_pin : std_logic_vector(13 DOWNTO 0);
  93 SIGNAL ww_d_hsync : std_logic;
  94 SIGNAL ww_d_vsync : std_logic;
  95 SIGNAL ww_d_column_counter : std_logic_vector(9 DOWNTO 0);
  96 SIGNAL ww_d_line_counter : std_logic_vector(8 DOWNTO 0);
  97 SIGNAL ww_d_set_column_counter : std_logic;
  98 SIGNAL ww_d_set_line_counter : std_logic;
  99 SIGNAL ww_d_hsync_counter : std_logic_vector(9 DOWNTO 0);
 100 SIGNAL ww_d_vsync_counter : std_logic_vector(9 DOWNTO 0);
 101 SIGNAL ww_d_set_hsync_counter : std_logic;
 102 SIGNAL ww_d_set_vsync_counter : std_logic;
 103 SIGNAL ww_d_h_enable : std_logic;
 104 SIGNAL ww_d_v_enable : std_logic;
 105 SIGNAL ww_d_r : std_logic;
 106 SIGNAL ww_d_g : std_logic;
 107 SIGNAL ww_d_b : std_logic;
 108 SIGNAL ww_d_hsync_state : std_logic_vector(0 TO 6);
 109 SIGNAL ww_d_vsync_state : std_logic_vector(0 TO 6);
 110 SIGNAL ww_d_state_clk : std_logic;
 111 SIGNAL ww_d_toggle : std_logic;
 112 SIGNAL ww_d_toggle_counter : std_logic_vector(24 DOWNTO 0);
 113 SIGNAL \vga_control_unit|un2_toggle_counter_next_0_~COMBOUT\ : std_logic;
 114 SIGNAL \vga_driver_unit|un2_column_counter_next_0_~COMBOUT\ : std_logic;
 115 SIGNAL \vga_driver_unit|un1_line_counter_sig_a_1_~COMBOUT\ : std_logic;
 116 SIGNAL \~STRATIX_FITTER_CREATED_GND~I_combout\ : std_logic;
 117 SIGNAL \clk_pin~combout\ : std_logic;
 118 SIGNAL \reset_pin~combout\ : std_logic;
 119 SIGNAL \vga_driver_unit|un6_dly_counter_0_x\ : std_logic;
 120 SIGNAL \vga_driver_unit|hsync_state_6\ : std_logic;
 121 SIGNAL \vga_driver_unit|hsync_counter_0\ : std_logic;
 122 SIGNAL \vga_driver_unit|hsync_counter_cout[0]~COUT1_10\ : std_logic;
 123 SIGNAL \vga_driver_unit|hsync_counter_cout[1]~COUT1_12\ : std_logic;
 124 SIGNAL \vga_driver_unit|hsync_counter_2\ : std_logic;
 125 SIGNAL \vga_driver_unit|hsync_counter_cout[2]~COUT1_14\ : std_logic;
 126 SIGNAL \vga_driver_unit|hsync_counter_3\ : std_logic;
 127 SIGNAL \vga_driver_unit|hsync_counter_cout[3]~COUT1_16\ : std_logic;
 128 SIGNAL \vga_driver_unit|hsync_counter_4\ : std_logic;
 129 SIGNAL \vga_driver_unit|hsync_counter_5\ : std_logic;
 130 SIGNAL \vga_driver_unit|hsync_counter_cout[5]~COUT1_18\ : std_logic;
 131 SIGNAL \vga_driver_unit|hsync_counter_6\ : std_logic;
 132 SIGNAL \vga_driver_unit|hsync_counter_cout[6]~COUT1_20\ : std_logic;
 133 SIGNAL \vga_driver_unit|hsync_counter_cout[7]~COUT1_22\ : std_logic;
 134 SIGNAL \vga_driver_unit|hsync_counter_8\ : std_logic;
 135 SIGNAL \vga_driver_unit|hsync_counter_cout[8]~COUT1_24\ : std_logic;
 136 SIGNAL \vga_driver_unit|hsync_counter_9\ : std_logic;
 137 SIGNAL \vga_driver_unit|un9_hsync_counterlt9_3\ : std_logic;
 138 SIGNAL \vga_driver_unit|un9_hsync_counterlt9\ : std_logic;
 139 SIGNAL \vga_driver_unit|G_2_i\ : std_logic;
 140 SIGNAL \vga_driver_unit|hsync_counter_1\ : std_logic;
 141 SIGNAL \vga_driver_unit|un13_hsync_counter_7\ : std_logic;
 142 SIGNAL \vga_driver_unit|un13_hsync_counter_2\ : std_logic;
 143 SIGNAL \vga_driver_unit|un13_hsync_counter\ : std_logic;
 144 SIGNAL \vga_driver_unit|un12_hsync_counter_3\ : std_logic;
 145 SIGNAL \vga_driver_unit|un12_hsync_counter_4\ : std_logic;
 146 SIGNAL \vga_driver_unit|un12_hsync_counter\ : std_logic;
 147 SIGNAL \vga_driver_unit|un10_hsync_counter_4\ : std_logic;
 148 SIGNAL \vga_driver_unit|un10_hsync_counter_3\ : std_logic;
 149 SIGNAL \vga_driver_unit|un10_hsync_counter_1\ : std_logic;
 150 SIGNAL \vga_driver_unit|hsync_state_5\ : std_logic;
 151 SIGNAL \vga_driver_unit|hsync_state_4\ : std_logic;
 152 SIGNAL \vga_driver_unit|un11_hsync_counter_3\ : std_logic;
 153 SIGNAL \vga_driver_unit|hsync_state_next_1_sqmuxa_2\ : std_logic;
 154 SIGNAL \vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\ : std_logic;
 155 SIGNAL \vga_driver_unit|hsync_state_next_1_sqmuxa_1\ : std_logic;
 156 SIGNAL \vga_driver_unit|hsync_state_3_0_0_0__g0_0\ : std_logic;
 157 SIGNAL \vga_driver_unit|hsync_state_3\ : std_logic;
 158 SIGNAL \vga_driver_unit|hsync_state_2\ : std_logic;
 159 SIGNAL \vga_driver_unit|hsync_state_0\ : std_logic;
 160 SIGNAL \vga_driver_unit|d_set_hsync_counter\ : std_logic;
 161 SIGNAL \vga_driver_unit|hsync_counter_next_1_sqmuxa\ : std_logic;
 162 SIGNAL \vga_driver_unit|hsync_counter_7\ : std_logic;
 163 SIGNAL \vga_driver_unit|un11_hsync_counter_2\ : std_logic;
 164 SIGNAL \vga_driver_unit|hsync_state_1\ : std_logic;
 165 SIGNAL \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\ : std_logic;
 166 SIGNAL \vga_driver_unit|column_counter_sig_0\ : std_logic;
 167 SIGNAL \vga_driver_unit|column_counter_sig_1\ : std_logic;
 168 SIGNAL \vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18\ : std_logic;
 169 SIGNAL \vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20\ : std_logic;
 170 SIGNAL \vga_driver_unit|column_counter_sig_4\ : std_logic;
 171 SIGNAL \vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10\ : std_logic;
 172 SIGNAL \vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12\ : std_logic;
 173 SIGNAL \vga_driver_unit|column_counter_sig_5\ : std_logic;
 174 SIGNAL \vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14\ : std_logic;
 175 SIGNAL \vga_driver_unit|column_counter_sig_7\ : std_logic;
 176 SIGNAL \vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22\ : std_logic;
 177 SIGNAL \vga_driver_unit|column_counter_sig_6\ : std_logic;
 178 SIGNAL \vga_driver_unit|un10_column_counter_siglt6_1\ : std_logic;
 179 SIGNAL \vga_driver_unit|un10_column_counter_siglt6_2\ : std_logic;
 180 SIGNAL \vga_driver_unit|un10_column_counter_siglt6\ : std_logic;
 181 SIGNAL \vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24\ : std_logic;
 182 SIGNAL \vga_driver_unit|column_counter_sig_8\ : std_logic;
 183 SIGNAL \vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16\ : std_logic;
 184 SIGNAL \vga_driver_unit|column_counter_sig_9\ : std_logic;
 185 SIGNAL \vga_driver_unit|un10_column_counter_siglto9\ : std_logic;
 186 SIGNAL \vga_driver_unit|column_counter_sig_2\ : std_logic;
 187 SIGNAL \vga_driver_unit|column_counter_sig_3\ : std_logic;
 188 SIGNAL \vga_control_unit|un5_v_enablelto3\ : std_logic;
 189 SIGNAL \vga_control_unit|un5_v_enablelto5_0\ : std_logic;
 190 SIGNAL \vga_control_unit|un5_v_enablelto7\ : std_logic;
 191 SIGNAL \vga_driver_unit|vsync_counter_0\ : std_logic;
 192 SIGNAL \vga_driver_unit|vsync_counter_cout[0]~COUT1_10\ : std_logic;
 193 SIGNAL \vga_driver_unit|vsync_counter_cout[1]~COUT1_12\ : std_logic;
 194 SIGNAL \vga_driver_unit|vsync_counter_2\ : std_logic;
 195 SIGNAL \vga_driver_unit|vsync_counter_cout[2]~COUT1_14\ : std_logic;
 196 SIGNAL \vga_driver_unit|vsync_counter_3\ : std_logic;
 197 SIGNAL \vga_driver_unit|vsync_counter_cout[3]~COUT1_16\ : std_logic;
 198 SIGNAL \vga_driver_unit|vsync_counter_4\ : std_logic;
 199 SIGNAL \vga_driver_unit|vsync_counter_5\ : std_logic;
 200 SIGNAL \vga_driver_unit|un9_vsync_counterlt9_6\ : std_logic;
 201 SIGNAL \vga_driver_unit|vsync_counter_cout[5]~COUT1_18\ : std_logic;
 202 SIGNAL \vga_driver_unit|vsync_counter_6\ : std_logic;
 203 SIGNAL \vga_driver_unit|vsync_counter_cout[6]~COUT1_20\ : std_logic;
 204 SIGNAL \vga_driver_unit|vsync_counter_7\ : std_logic;
 205 SIGNAL \vga_driver_unit|vsync_counter_cout[7]~COUT1_22\ : std_logic;
 206 SIGNAL \vga_driver_unit|vsync_counter_8\ : std_logic;
 207 SIGNAL \vga_driver_unit|un9_vsync_counterlt9_5\ : std_logic;
 208 SIGNAL \vga_driver_unit|un9_vsync_counterlt9\ : std_logic;
 209 SIGNAL \vga_driver_unit|vsync_state_6\ : std_logic;
 210 SIGNAL \vga_driver_unit|G_16_i\ : std_logic;
 211 SIGNAL \vga_driver_unit|vsync_counter_1\ : std_logic;
 212 SIGNAL \vga_driver_unit|un12_vsync_counter_7\ : std_logic;
 213 SIGNAL \vga_driver_unit|un12_vsync_counter_6\ : std_logic;
 214 SIGNAL \vga_driver_unit|un14_vsync_counter_8\ : std_logic;
 215 SIGNAL \vga_driver_unit|vsync_state_next_1_sqmuxa_3\ : std_logic;
 216 SIGNAL \vga_driver_unit|vsync_state_5\ : std_logic;
 217 SIGNAL \vga_driver_unit|vsync_state_next_1_sqmuxa_1\ : std_logic;
 218 SIGNAL \vga_driver_unit|un15_vsync_counter_3\ : std_logic;
 219 SIGNAL \vga_driver_unit|un15_vsync_counter_4\ : std_logic;
 220 SIGNAL \vga_driver_unit|un13_vsync_counter_3\ : std_logic;
 221 SIGNAL \vga_driver_unit|un13_vsync_counter_4\ : std_logic;
 222 SIGNAL \vga_driver_unit|vsync_state_next_1_sqmuxa_2\ : std_logic;
 223 SIGNAL \vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0\ : std_logic;
 224 SIGNAL \vga_driver_unit|vsync_state_next_2_sqmuxa\ : std_logic;
 225 SIGNAL \vga_driver_unit|vsync_state_3\ : std_logic;
 226 SIGNAL \vga_driver_unit|vsync_state_2\ : std_logic;
 227 SIGNAL \vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\ : std_logic;
 228 SIGNAL \vga_driver_unit|vsync_state_0\ : std_logic;
 229 SIGNAL \vga_driver_unit|d_set_vsync_counter\ : std_logic;
 230 SIGNAL \vga_driver_unit|vsync_counter_next_1_sqmuxa\ : std_logic;
 231 SIGNAL \vga_driver_unit|vsync_counter_cout[8]~COUT1_24\ : std_logic;
 232 SIGNAL \vga_driver_unit|vsync_counter_9\ : std_logic;
 233 SIGNAL \vga_driver_unit|vsync_state_4\ : std_logic;
 234 SIGNAL \vga_driver_unit|vsync_state_1\ : std_logic;
 235 SIGNAL \vga_driver_unit|line_counter_next_0_sqmuxa_1_1\ : std_logic;
 236 SIGNAL \vga_driver_unit|line_counter_sig_0\ : std_logic;
 237 SIGNAL \vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3\ : std_logic;
 238 SIGNAL \vga_driver_unit|line_counter_sig_1\ : std_logic;
 239 SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9\ : std_logic;
 240 SIGNAL \vga_driver_unit|line_counter_sig_2\ : std_logic;
 241 SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11\ : std_logic;
 242 SIGNAL \vga_driver_unit|line_counter_sig_4\ : std_logic;
 243 SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17\ : std_logic;
 244 SIGNAL \vga_driver_unit|line_counter_sig_3\ : std_logic;
 245 SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13\ : std_logic;
 246 SIGNAL \vga_driver_unit|line_counter_sig_6\ : std_logic;
 247 SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19\ : std_logic;
 248 SIGNAL \vga_driver_unit|line_counter_sig_5\ : std_logic;
 249 SIGNAL \vga_driver_unit|un10_line_counter_siglt4_2\ : std_logic;
 250 SIGNAL \vga_driver_unit|un10_line_counter_siglto5\ : std_logic;
 251 SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15\ : std_logic;
 252 SIGNAL \vga_driver_unit|line_counter_sig_8\ : std_logic;
 253 SIGNAL \vga_driver_unit|un10_line_counter_siglto8\ : std_logic;
 254 SIGNAL \vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21\ : std_logic;
 255 SIGNAL \vga_driver_unit|line_counter_sig_7\ : std_logic;
 256 SIGNAL \vga_control_unit|un17_v_enablelt2\ : std_logic;
 257 SIGNAL \vga_control_unit|un17_v_enablelto5\ : std_logic;
 258 SIGNAL \vga_control_unit|un17_v_enablelto7\ : std_logic;
 259 SIGNAL \vga_control_unit|toggle_counter_sig_0\ : std_logic;
 260 SIGNAL \vga_control_unit|toggle_counter_sig_1\ : std_logic;
 261 SIGNAL \vga_control_unit|toggle_counter_sig_cout[1]~COUT1_17\ : std_logic;
 262 SIGNAL \vga_control_unit|toggle_counter_sig_3\ : std_logic;
 263 SIGNAL \vga_control_unit|un2_toggle_counter_next_cout[0]~COUT1_3\ : std_logic;
 264 SIGNAL \vga_control_unit|toggle_counter_sig_2\ : std_logic;
 265 SIGNAL \vga_control_unit|toggle_counter_sig_cout[3]~COUT1_19\ : std_logic;
 266 SIGNAL \vga_control_unit|toggle_counter_sig_5\ : std_logic;
 267 SIGNAL \vga_control_unit|toggle_counter_sig_cout[2]~COUT1_33\ : std_logic;
 268 SIGNAL \vga_control_unit|toggle_counter_sig_4\ : std_logic;
 269 SIGNAL \vga_control_unit|toggle_counter_sig_cout[4]~COUT1_35\ : std_logic;
 270 SIGNAL \vga_control_unit|toggle_counter_sig_6\ : std_logic;
 271 SIGNAL \vga_control_unit|toggle_counter_sig_cout[5]~COUT1_21\ : std_logic;
 272 SIGNAL \vga_control_unit|toggle_counter_sig_7\ : std_logic;
 273 SIGNAL \vga_control_unit|toggle_counter_sig_cout[7]~COUT1_23\ : std_logic;
 274 SIGNAL \vga_control_unit|toggle_counter_sig_9\ : std_logic;
 275 SIGNAL \vga_control_unit|toggle_counter_sig_cout[6]~COUT1_37\ : std_logic;
 276 SIGNAL \vga_control_unit|toggle_counter_sig_8\ : std_logic;
 277 SIGNAL \vga_control_unit|toggle_counter_sig_10\ : std_logic;
 278 SIGNAL \vga_control_unit|toggle_counter_sig_11\ : std_logic;
 279 SIGNAL \vga_control_unit|toggle_counter_sig_cout[11]~COUT1_25\ : std_logic;
 280 SIGNAL \vga_control_unit|toggle_counter_sig_13\ : std_logic;
 281 SIGNAL \vga_control_unit|toggle_counter_sig_cout[10]~COUT1_39\ : std_logic;
 282 SIGNAL \vga_control_unit|toggle_counter_sig_12\ : std_logic;
 283 SIGNAL \vga_control_unit|toggle_counter_sig_cout[13]~COUT1_27\ : std_logic;
 284 SIGNAL \vga_control_unit|toggle_counter_sig_15\ : std_logic;
 285 SIGNAL \vga_control_unit|toggle_counter_sig_cout[12]~COUT1_41\ : std_logic;
 286 SIGNAL \vga_control_unit|toggle_counter_sig_14\ : std_logic;
 287 SIGNAL \vga_control_unit|toggle_counter_sig_cout[15]~COUT1_29\ : std_logic;
 288 SIGNAL \vga_control_unit|toggle_counter_sig_17\ : std_logic;
 289 SIGNAL \vga_control_unit|toggle_counter_sig_cout[14]~COUT1_43\ : std_logic;
 290 SIGNAL \vga_control_unit|toggle_counter_sig_16\ : std_logic;
 291 SIGNAL \vga_control_unit|toggle_counter_sig_cout[16]~COUT1_45\ : std_logic;
 292 SIGNAL \vga_control_unit|toggle_counter_sig_18\ : std_logic;
 293 SIGNAL \vga_control_unit|toggle_counter_sig_cout[17]~COUT1_31\ : std_logic;
 294 SIGNAL \vga_control_unit|toggle_counter_sig_19\ : std_logic;
 295 SIGNAL \vga_control_unit|un1_toggle_counter_siglto19_4\ : std_logic;
 296 SIGNAL \vga_control_unit|un1_toggle_counter_siglto19_5\ : std_logic;
 297 SIGNAL \vga_control_unit|un1_toggle_counter_siglto7_4\ : std_logic;
 298 SIGNAL \vga_control_unit|un1_toggle_counter_siglto7\ : std_logic;
 299 SIGNAL \vga_control_unit|un1_toggle_counter_siglto10\ : std_logic;
 300 SIGNAL \vga_control_unit|un1_toggle_counter_siglto19\ : std_logic;
 301 SIGNAL \vga_control_unit|toggle_sig_0_0_0_g1\ : std_logic;
 302 SIGNAL \vga_control_unit|toggle_sig\ : std_logic;
 303 SIGNAL \vga_control_unit|un9_v_enablelto6\ : std_logic;
 304 SIGNAL \vga_control_unit|un9_v_enablelto9\ : std_logic;
 305 SIGNAL \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4\ : std_logic;
 306 SIGNAL \vga_driver_unit|h_enable_sig\ : std_logic;
 307 SIGNAL \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4\ : std_logic;
 308 SIGNAL \vga_driver_unit|v_enable_sig\ : std_logic;
 309 SIGNAL \vga_control_unit|b_next_0_g0_3\ : std_logic;
 310 SIGNAL \vga_control_unit|b_next_0_g0_5\ : std_logic;
 311 SIGNAL \vga_control_unit|un13_v_enablelto8_a\ : std_logic;
 312 SIGNAL \vga_control_unit|un13_v_enablelto8\ : std_logic;
 313 SIGNAL \vga_control_unit|b\ : std_logic;
 314 SIGNAL \vga_driver_unit|un1_hsync_state_3_0\ : std_logic;
 315 SIGNAL \vga_driver_unit|h_sync_1_0_0_0_g1\ : std_logic;
 316 SIGNAL \vga_driver_unit|h_sync\ : std_logic;
 317 SIGNAL \vga_driver_unit|un1_vsync_state_2_0\ : std_logic;
 318 SIGNAL \vga_driver_unit|v_sync_1_0_0_0_g1\ : std_logic;
 319 SIGNAL \vga_driver_unit|v_sync\ : std_logic;
 320 SIGNAL dly_counter : std_logic_vector(1 DOWNTO 0);
 321 SIGNAL \vga_control_unit|toggle_counter_sig_cout\ : std_logic_vector(17 DOWNTO 1);
 322 SIGNAL \vga_control_unit|un2_toggle_counter_next_cout\ : std_logic_vector(0 DOWNTO 0);
 323 SIGNAL \vga_driver_unit|hsync_counter_cout\ : std_logic_vector(8 DOWNTO 0);
 324 SIGNAL \vga_driver_unit|un1_line_counter_sig_a_cout\ : std_logic_vector(1 DOWNTO 1);
 325 SIGNAL \vga_driver_unit|un1_line_counter_sig_combout\ : std_logic_vector(9 DOWNTO 1);
 326 SIGNAL \vga_driver_unit|un1_line_counter_sig_cout\ : std_logic_vector(7 DOWNTO 1);
 327 SIGNAL \vga_driver_unit|un2_column_counter_next_combout\ : std_logic_vector(9 DOWNTO 1);
 328 SIGNAL \vga_driver_unit|un2_column_counter_next_cout\ : std_logic_vector(7 DOWNTO 0);
 329 SIGNAL \vga_driver_unit|vsync_counter_cout\ : std_logic_vector(8 DOWNTO 0);
 330 SIGNAL \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\ : std_logic;
 331 SIGNAL \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\ : std_logic;
 332 SIGNAL \vga_driver_unit|ALT_INV_G_2_i\ : std_logic;
 333 SIGNAL \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\ : std_logic;
 334 SIGNAL \vga_driver_unit|ALT_INV_G_16_i\ : std_logic;
 335 SIGNAL \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\ : std_logic;
 336 SIGNAL \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\ : std_logic;
 337 SIGNAL \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\ : std_logic;
 338
 339 BEGIN
 340
 341 ww_clk_pin <= clk_pin;
 342 ww_reset_pin <= reset_pin;
 343 r0_pin <= ww_r0_pin;
 344 r1_pin <= ww_r1_pin;
 345 r2_pin <= ww_r2_pin;
 346 g0_pin <= ww_g0_pin;
 347 g1_pin <= ww_g1_pin;
 348 g2_pin <= ww_g2_pin;
 349 b0_pin <= ww_b0_pin;
 350 b1_pin <= ww_b1_pin;
 351 hsync_pin <= ww_hsync_pin;
 352 vsync_pin <= ww_vsync_pin;
 353 seven_seg_pin <= ww_seven_seg_pin;
 354 d_hsync <= ww_d_hsync;
 355 d_vsync <= ww_d_vsync;
 356 d_column_counter <= ww_d_column_counter;
 357 d_line_counter <= ww_d_line_counter;
 358 d_set_column_counter <= ww_d_set_column_counter;
 359 d_set_line_counter <= ww_d_set_line_counter;
 360 d_hsync_counter <= ww_d_hsync_counter;
 361 d_vsync_counter <= ww_d_vsync_counter;
 362 d_set_hsync_counter <= ww_d_set_hsync_counter;
 363 d_set_vsync_counter <= ww_d_set_vsync_counter;
 364 d_h_enable <= ww_d_h_enable;
 365 d_v_enable <= ww_d_v_enable;
 366 d_r <= ww_d_r;
 367 d_g <= ww_d_g;
 368 d_b <= ww_d_b;
 369 d_hsync_state <= ww_d_hsync_state;
 370 d_vsync_state <= ww_d_vsync_state;
 371 d_state_clk <= ww_d_state_clk;
 372 d_toggle <= ww_d_toggle;
 373 d_toggle_counter <= ww_d_toggle_counter;
 374 ww_devoe <= devoe;
 375 ww_devclrn <= devclrn;
 376 ww_devpor <= devpor;
 377 \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\ <= NOT \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\;
 378 \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\ <= NOT \vga_driver_unit|line_counter_next_0_sqmuxa_1_1\;
 379 \vga_driver_unit|ALT_INV_G_2_i\ <= NOT \vga_driver_unit|G_2_i\;
 380 \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\ <= NOT \vga_driver_unit|un9_hsync_counterlt9\;
 381 \vga_driver_unit|ALT_INV_G_16_i\ <= NOT \vga_driver_unit|G_16_i\;
 382 \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\ <= NOT \vga_driver_unit|un9_vsync_counterlt9\;
 383 \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\ <= NOT \vga_control_unit|toggle_sig_0_0_0_g1\;
 384 \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\ <= NOT \~STRATIX_FITTER_CREATED_GND~I_combout\;
 385
 386 \~STRATIX_FITTER_CREATED_GND~I\ : stratix_lcell
 387 -- Equation(s):
 388 -- \~STRATIX_FITTER_CREATED_GND~I_combout\ = GND
 389
 390 -- pragma translate_off
 391 GENERIC MAP (
 392         lut_mask => "0000",
 393         operation_mode => "normal",
 394         output_mode => "comb_only",
 395         register_cascade_mode => "off",
 396         sum_lutc_input => "datac",
 397         synch_mode => "off")
 398 -- pragma translate_on
 399 PORT MAP (
 400         devclrn => ww_devclrn,
 401         devpor => ww_devpor,
 402         combout => \~STRATIX_FITTER_CREATED_GND~I_combout\);
 403
 404 clk_pin_in : stratix_io
 405 -- pragma translate_off
 406 GENERIC MAP (
 407         ddio_mode => "none",
 408         input_async_reset => "none",
 409         input_power_up => "low",
 410         input_register_mode => "none",
 411         input_sync_reset => "none",
 412         oe_async_reset => "none",
 413         oe_power_up => "low",
 414         oe_register_mode => "none",
 415         oe_sync_reset => "none",
 416         operation_mode => "input",
 417         output_async_reset => "none",
 418         output_power_up => "low",
 419         output_register_mode => "none",
 420         output_sync_reset => "none")
 421 -- pragma translate_on
 422 PORT MAP (
 423         devclrn => ww_devclrn,
 424         devpor => ww_devpor,
 425         devoe => ww_devoe,
 426         oe => GND,
 427         padio => ww_clk_pin,
 428         combout => \clk_pin~combout\);
 429
 430 reset_pin_in : stratix_io
 431 -- pragma translate_off
 432 GENERIC MAP (
 433         ddio_mode => "none",
 434         input_async_reset => "none",
 435         input_power_up => "low",
 436         input_register_mode => "none",
 437         input_sync_reset => "none",
 438         oe_async_reset => "none",
 439         oe_power_up => "low",
 440         oe_register_mode => "none",
 441         oe_sync_reset => "none",
 442         operation_mode => "input",
 443         output_async_reset => "none",
 444         output_power_up => "low",
 445         output_register_mode => "none",
 446         output_sync_reset => "none")
 447 -- pragma translate_on
 448 PORT MAP (
 449         devclrn => ww_devclrn,
 450         devpor => ww_devpor,
 451         devoe => ww_devoe,
 452         oe => GND,
 453         padio => ww_reset_pin,
 454         combout => \reset_pin~combout\);
 455
 456 \dly_counter_1_\ : stratix_lcell
 457 -- Equation(s):
 458 -- dly_counter(1) = DFFEAS(\reset_pin~combout\ & (dly_counter(0) # dly_counter(1)), GLOBAL(\clk_pin~combout\), VCC, , , , , , )
 459
 460 -- pragma translate_off
 461 GENERIC MAP (
 462         lut_mask => "aaa0",
 463         operation_mode => "normal",
 464         output_mode => "reg_only",
 465         register_cascade_mode => "off",
 466         sum_lutc_input => "datac",
 467         synch_mode => "off")
 468 -- pragma translate_on
 469 PORT MAP (
 470         clk => \clk_pin~combout\,
 471         dataa => \reset_pin~combout\,
 472         datac => dly_counter(0),
 473         datad => dly_counter(1),
 474         aclr => GND,
 475         devclrn => ww_devclrn,
 476         devpor => ww_devpor,
 477         regout => dly_counter(1));
 478
 479 \dly_counter_0_\ : stratix_lcell
 480 -- Equation(s):
 481 -- dly_counter(0) = DFFEAS(\reset_pin~combout\ & (dly_counter(1) # !dly_counter(0)), GLOBAL(\clk_pin~combout\), VCC, , , , , , )
 482
 483 -- pragma translate_off
 484 GENERIC MAP (
 485         lut_mask => "f300",
 486         operation_mode => "normal",
 487         output_mode => "reg_only",
 488         register_cascade_mode => "off",
 489         sum_lutc_input => "datac",
 490         synch_mode => "off")
 491 -- pragma translate_on
 492 PORT MAP (
 493         clk => \clk_pin~combout\,
 494         datab => dly_counter(0),
 495         datac => dly_counter(1),
 496         datad => \reset_pin~combout\,
 497         aclr => GND,
 498         devclrn => ww_devclrn,
 499         devpor => ww_devpor,
 500         regout => dly_counter(0));
 501
 502 \vga_driver_unit|vsync_state_6_\ : stratix_lcell
 503 -- Equation(s):
 504 -- \vga_driver_unit|un6_dly_counter_0_x\ = !\reset_pin~combout\ # !dly_counter(1) # !dly_counter(0)
 505 -- \vga_driver_unit|vsync_state_6\ = DFFEAS(\vga_driver_unit|un6_dly_counter_0_x\, GLOBAL(\clk_pin~combout\), VCC, , , , , , )
 506
 507 -- pragma translate_off
 508 GENERIC MAP (
 509         lut_mask => "3fff",
 510         operation_mode => "normal",
 511         output_mode => "reg_and_comb",
 512         register_cascade_mode => "off",
 513         sum_lutc_input => "datac",
 514         synch_mode => "off")
 515 -- pragma translate_on
 516 PORT MAP (
 517         clk => \clk_pin~combout\,
 518         datab => dly_counter(0),
 519         datac => dly_counter(1),
 520         datad => \reset_pin~combout\,
 521         aclr => GND,
 522         devclrn => ww_devclrn,
 523         devpor => ww_devpor,
 524         combout => \vga_driver_unit|un6_dly_counter_0_x\,
 525         regout => \vga_driver_unit|vsync_state_6\);
 526
 527 \vga_driver_unit|hsync_state_6_\ : stratix_lcell
 528 -- Equation(s):
 529 -- \vga_driver_unit|d_set_hsync_counter\ = C1_hsync_state_6 # \vga_driver_unit|hsync_state_0\
 530 -- \vga_driver_unit|hsync_state_6\ = DFFEAS(\vga_driver_unit|d_set_hsync_counter\, GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|un6_dly_counter_0_x\, , , VCC)
 531
 532 -- pragma translate_off
 533 GENERIC MAP (
 534         lut_mask => "fff0",
 535         operation_mode => "normal",
 536         output_mode => "reg_and_comb",
 537         register_cascade_mode => "off",
 538         sum_lutc_input => "qfbk",
 539         synch_mode => "on")
 540 -- pragma translate_on
 541 PORT MAP (
 542         clk => \clk_pin~combout\,
 543         datac => \vga_driver_unit|un6_dly_counter_0_x\,
 544         datad => \vga_driver_unit|hsync_state_0\,
 545         aclr => GND,
 546         sload => VCC,
 547         devclrn => ww_devclrn,
 548         devpor => ww_devpor,
 549         combout => \vga_driver_unit|d_set_hsync_counter\,
 550         regout => \vga_driver_unit|hsync_state_6\);
 551
 552 \vga_driver_unit|hsync_counter_0_\ : stratix_lcell
 553 -- Equation(s):
 554 -- \vga_driver_unit|hsync_counter_0\ = DFFEAS(!\vga_driver_unit|hsync_counter_0\, GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, !\vga_driver_unit|un9_hsync_counterlt9\)
 555 -- \vga_driver_unit|hsync_counter_cout\(0) = CARRY(\vga_driver_unit|hsync_counter_0\)
 556 -- \vga_driver_unit|hsync_counter_cout[0]~COUT1_10\ = CARRY(\vga_driver_unit|hsync_counter_0\)
 557
 558 -- pragma translate_off
 559 GENERIC MAP (
 560         lut_mask => "33cc",
 561         operation_mode => "arithmetic",
 562         output_mode => "reg_only",
 563         register_cascade_mode => "off",
 564         sum_lutc_input => "datac",
 565         synch_mode => "on")
 566 -- pragma translate_on
 567 PORT MAP (
 568         clk => \clk_pin~combout\,
 569         datab => \vga_driver_unit|hsync_counter_0\,
 570         datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
 571         aclr => GND,
 572         sclr => \vga_driver_unit|ALT_INV_G_2_i\,
 573         sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
 574         devclrn => ww_devclrn,
 575         devpor => ww_devpor,
 576         regout => \vga_driver_unit|hsync_counter_0\,
 577         cout0 => \vga_driver_unit|hsync_counter_cout\(0),
 578         cout1 => \vga_driver_unit|hsync_counter_cout[0]~COUT1_10\);
 579
 580 \vga_driver_unit|hsync_counter_1_\ : stratix_lcell
 581 -- Equation(s):
 582 -- \vga_driver_unit|hsync_counter_1\ = DFFEAS(\vga_driver_unit|hsync_counter_1\ $ \vga_driver_unit|hsync_counter_cout\(0), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\,
 583 -- !\vga_driver_unit|un9_hsync_counterlt9\)
 584 -- \vga_driver_unit|hsync_counter_cout\(1) = CARRY(!\vga_driver_unit|hsync_counter_cout\(0) # !\vga_driver_unit|hsync_counter_1\)
 585 -- \vga_driver_unit|hsync_counter_cout[1]~COUT1_12\ = CARRY(!\vga_driver_unit|hsync_counter_cout[0]~COUT1_10\ # !\vga_driver_unit|hsync_counter_1\)
 586
 587 -- pragma translate_off
 588 GENERIC MAP (
 589         cin0_used => "true",
 590         cin1_used => "true",
 591         lut_mask => "3c3f",
 592         operation_mode => "arithmetic",
 593         output_mode => "reg_only",
 594         register_cascade_mode => "off",
 595         sum_lutc_input => "cin",
 596         synch_mode => "on")
 597 -- pragma translate_on
 598 PORT MAP (
 599         clk => \clk_pin~combout\,
 600         datab => \vga_driver_unit|hsync_counter_1\,
 601         datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
 602         aclr => GND,
 603         sclr => \vga_driver_unit|ALT_INV_G_2_i\,
 604         sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
 605         cin0 => \vga_driver_unit|hsync_counter_cout\(0),
 606         cin1 => \vga_driver_unit|hsync_counter_cout[0]~COUT1_10\,
 607         devclrn => ww_devclrn,
 608         devpor => ww_devpor,
 609         regout => \vga_driver_unit|hsync_counter_1\,
 610         cout0 => \vga_driver_unit|hsync_counter_cout\(1),
 611         cout1 => \vga_driver_unit|hsync_counter_cout[1]~COUT1_12\);
 612
 613 \vga_driver_unit|hsync_counter_2_\ : stratix_lcell
 614 -- Equation(s):
 615 -- \vga_driver_unit|hsync_counter_2\ = DFFEAS(\vga_driver_unit|hsync_counter_2\ $ (!\vga_driver_unit|hsync_counter_cout\(1)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\,
 616 -- !\vga_driver_unit|un9_hsync_counterlt9\)
 617 -- \vga_driver_unit|hsync_counter_cout\(2) = CARRY(\vga_driver_unit|hsync_counter_2\ & (!\vga_driver_unit|hsync_counter_cout\(1)))
 618 -- \vga_driver_unit|hsync_counter_cout[2]~COUT1_14\ = CARRY(\vga_driver_unit|hsync_counter_2\ & (!\vga_driver_unit|hsync_counter_cout[1]~COUT1_12\))
 619
 620 -- pragma translate_off
 621 GENERIC MAP (
 622         cin0_used => "true",
 623         cin1_used => "true",
 624         lut_mask => "a50a",
 625         operation_mode => "arithmetic",
 626         output_mode => "reg_only",
 627         register_cascade_mode => "off",
 628         sum_lutc_input => "cin",
 629         synch_mode => "on")
 630 -- pragma translate_on
 631 PORT MAP (
 632         clk => \clk_pin~combout\,
 633         dataa => \vga_driver_unit|hsync_counter_2\,
 634         datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
 635         aclr => GND,
 636         sclr => \vga_driver_unit|ALT_INV_G_2_i\,
 637         sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
 638         cin0 => \vga_driver_unit|hsync_counter_cout\(1),
 639         cin1 => \vga_driver_unit|hsync_counter_cout[1]~COUT1_12\,
 640         devclrn => ww_devclrn,
 641         devpor => ww_devpor,
 642         regout => \vga_driver_unit|hsync_counter_2\,
 643         cout0 => \vga_driver_unit|hsync_counter_cout\(2),
 644         cout1 => \vga_driver_unit|hsync_counter_cout[2]~COUT1_14\);
 645
 646 \vga_driver_unit|hsync_counter_3_\ : stratix_lcell
 647 -- Equation(s):
 648 -- \vga_driver_unit|hsync_counter_3\ = DFFEAS(\vga_driver_unit|hsync_counter_3\ $ (\vga_driver_unit|hsync_counter_cout\(2)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\,
 649 -- !\vga_driver_unit|un9_hsync_counterlt9\)
 650 -- \vga_driver_unit|hsync_counter_cout\(3) = CARRY(!\vga_driver_unit|hsync_counter_cout\(2) # !\vga_driver_unit|hsync_counter_3\)
 651 -- \vga_driver_unit|hsync_counter_cout[3]~COUT1_16\ = CARRY(!\vga_driver_unit|hsync_counter_cout[2]~COUT1_14\ # !\vga_driver_unit|hsync_counter_3\)
 652
 653 -- pragma translate_off
 654 GENERIC MAP (
 655         cin0_used => "true",
 656         cin1_used => "true",
 657         lut_mask => "5a5f",
 658         operation_mode => "arithmetic",
 659         output_mode => "reg_only",
 660         register_cascade_mode => "off",
 661         sum_lutc_input => "cin",
 662         synch_mode => "on")
 663 -- pragma translate_on
 664 PORT MAP (
 665         clk => \clk_pin~combout\,
 666         dataa => \vga_driver_unit|hsync_counter_3\,
 667         datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
 668         aclr => GND,
 669         sclr => \vga_driver_unit|ALT_INV_G_2_i\,
 670         sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
 671         cin0 => \vga_driver_unit|hsync_counter_cout\(2),
 672         cin1 => \vga_driver_unit|hsync_counter_cout[2]~COUT1_14\,
 673         devclrn => ww_devclrn,
 674         devpor => ww_devpor,
 675         regout => \vga_driver_unit|hsync_counter_3\,
 676         cout0 => \vga_driver_unit|hsync_counter_cout\(3),
 677         cout1 => \vga_driver_unit|hsync_counter_cout[3]~COUT1_16\);
 678
 679 \vga_driver_unit|hsync_counter_4_\ : stratix_lcell
 680 -- Equation(s):
 681 -- \vga_driver_unit|hsync_counter_4\ = DFFEAS(\vga_driver_unit|hsync_counter_4\ $ (!\vga_driver_unit|hsync_counter_cout\(3)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\,
 682 -- !\vga_driver_unit|un9_hsync_counterlt9\)
 683 -- \vga_driver_unit|hsync_counter_cout\(4) = CARRY(\vga_driver_unit|hsync_counter_4\ & (!\vga_driver_unit|hsync_counter_cout[3]~COUT1_16\))
 684
 685 -- pragma translate_off
 686 GENERIC MAP (
 687         cin0_used => "true",
 688         cin1_used => "true",
 689         lut_mask => "a50a",
 690         operation_mode => "arithmetic",
 691         output_mode => "reg_only",
 692         register_cascade_mode => "off",
 693         sum_lutc_input => "cin",
 694         synch_mode => "on")
 695 -- pragma translate_on
 696 PORT MAP (
 697         clk => \clk_pin~combout\,
 698         dataa => \vga_driver_unit|hsync_counter_4\,
 699         datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
 700         aclr => GND,
 701         sclr => \vga_driver_unit|ALT_INV_G_2_i\,
 702         sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
 703         cin0 => \vga_driver_unit|hsync_counter_cout\(3),
 704         cin1 => \vga_driver_unit|hsync_counter_cout[3]~COUT1_16\,
 705         devclrn => ww_devclrn,
 706         devpor => ww_devpor,
 707         regout => \vga_driver_unit|hsync_counter_4\,
 708         cout => \vga_driver_unit|hsync_counter_cout\(4));
 709
 710 \vga_driver_unit|hsync_counter_5_\ : stratix_lcell
 711 -- Equation(s):
 712 -- \vga_driver_unit|hsync_counter_5\ = DFFEAS(\vga_driver_unit|hsync_counter_5\ $ \vga_driver_unit|hsync_counter_cout\(4), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\,
 713 -- !\vga_driver_unit|un9_hsync_counterlt9\)
 714 -- \vga_driver_unit|hsync_counter_cout\(5) = CARRY(!\vga_driver_unit|hsync_counter_cout\(4) # !\vga_driver_unit|hsync_counter_5\)
 715 -- \vga_driver_unit|hsync_counter_cout[5]~COUT1_18\ = CARRY(!\vga_driver_unit|hsync_counter_cout\(4) # !\vga_driver_unit|hsync_counter_5\)
 716
 717 -- pragma translate_off
 718 GENERIC MAP (
 719         cin_used => "true",
 720         lut_mask => "3c3f",
 721         operation_mode => "arithmetic",
 722         output_mode => "reg_only",
 723         register_cascade_mode => "off",
 724         sum_lutc_input => "cin",
 725         synch_mode => "on")
 726 -- pragma translate_on
 727 PORT MAP (
 728         clk => \clk_pin~combout\,
 729         datab => \vga_driver_unit|hsync_counter_5\,
 730         datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
 731         aclr => GND,
 732         sclr => \vga_driver_unit|ALT_INV_G_2_i\,
 733         sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
 734         cin => \vga_driver_unit|hsync_counter_cout\(4),
 735         devclrn => ww_devclrn,
 736         devpor => ww_devpor,
 737         regout => \vga_driver_unit|hsync_counter_5\,
 738         cout0 => \vga_driver_unit|hsync_counter_cout\(5),
 739         cout1 => \vga_driver_unit|hsync_counter_cout[5]~COUT1_18\);
 740
 741 \vga_driver_unit|hsync_counter_6_\ : stratix_lcell
 742 -- Equation(s):
 743 -- \vga_driver_unit|hsync_counter_6\ = DFFEAS(\vga_driver_unit|hsync_counter_6\ $ !(!\vga_driver_unit|hsync_counter_cout\(4) & \vga_driver_unit|hsync_counter_cout\(5)) # (\vga_driver_unit|hsync_counter_cout\(4) &
 744 -- \vga_driver_unit|hsync_counter_cout[5]~COUT1_18\), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, !\vga_driver_unit|un9_hsync_counterlt9\)
 745 -- \vga_driver_unit|hsync_counter_cout\(6) = CARRY(\vga_driver_unit|hsync_counter_6\ & !\vga_driver_unit|hsync_counter_cout\(5))
 746 -- \vga_driver_unit|hsync_counter_cout[6]~COUT1_20\ = CARRY(\vga_driver_unit|hsync_counter_6\ & !\vga_driver_unit|hsync_counter_cout[5]~COUT1_18\)
 747
 748 -- pragma translate_off
 749 GENERIC MAP (
 750         cin0_used => "true",
 751         cin1_used => "true",
 752         cin_used => "true",
 753         lut_mask => "c30c",
 754         operation_mode => "arithmetic",
 755         output_mode => "reg_only",
 756         register_cascade_mode => "off",
 757         sum_lutc_input => "cin",
 758         synch_mode => "on")
 759 -- pragma translate_on
 760 PORT MAP (
 761         clk => \clk_pin~combout\,
 762         datab => \vga_driver_unit|hsync_counter_6\,
 763         datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
 764         aclr => GND,
 765         sclr => \vga_driver_unit|ALT_INV_G_2_i\,
 766         sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
 767         cin => \vga_driver_unit|hsync_counter_cout\(4),
 768         cin0 => \vga_driver_unit|hsync_counter_cout\(5),
 769         cin1 => \vga_driver_unit|hsync_counter_cout[5]~COUT1_18\,
 770         devclrn => ww_devclrn,
 771         devpor => ww_devpor,
 772         regout => \vga_driver_unit|hsync_counter_6\,
 773         cout0 => \vga_driver_unit|hsync_counter_cout\(6),
 774         cout1 => \vga_driver_unit|hsync_counter_cout[6]~COUT1_20\);
 775
 776 \vga_driver_unit|hsync_counter_7_\ : stratix_lcell
 777 -- Equation(s):
 778 -- \vga_driver_unit|hsync_counter_7\ = DFFEAS(\vga_driver_unit|hsync_counter_7\ $ ((!\vga_driver_unit|hsync_counter_cout\(4) & \vga_driver_unit|hsync_counter_cout\(6)) # (\vga_driver_unit|hsync_counter_cout\(4) &
 779 -- \vga_driver_unit|hsync_counter_cout[6]~COUT1_20\)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, !\vga_driver_unit|un9_hsync_counterlt9\)
 780 -- \vga_driver_unit|hsync_counter_cout\(7) = CARRY(!\vga_driver_unit|hsync_counter_cout\(6) # !\vga_driver_unit|hsync_counter_7\)
 781 -- \vga_driver_unit|hsync_counter_cout[7]~COUT1_22\ = CARRY(!\vga_driver_unit|hsync_counter_cout[6]~COUT1_20\ # !\vga_driver_unit|hsync_counter_7\)
 782
 783 -- pragma translate_off
 784 GENERIC MAP (
 785         cin0_used => "true",
 786         cin1_used => "true",
 787         cin_used => "true",
 788         lut_mask => "5a5f",
 789         operation_mode => "arithmetic",
 790         output_mode => "reg_only",
 791         register_cascade_mode => "off",
 792         sum_lutc_input => "cin",
 793         synch_mode => "on")
 794 -- pragma translate_on
 795 PORT MAP (
 796         clk => \clk_pin~combout\,
 797         dataa => \vga_driver_unit|hsync_counter_7\,
 798         datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
 799         aclr => GND,
 800         sclr => \vga_driver_unit|ALT_INV_G_2_i\,
 801         sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
 802         cin => \vga_driver_unit|hsync_counter_cout\(4),
 803         cin0 => \vga_driver_unit|hsync_counter_cout\(6),
 804         cin1 => \vga_driver_unit|hsync_counter_cout[6]~COUT1_20\,
 805         devclrn => ww_devclrn,
 806         devpor => ww_devpor,
 807         regout => \vga_driver_unit|hsync_counter_7\,
 808         cout0 => \vga_driver_unit|hsync_counter_cout\(7),
 809         cout1 => \vga_driver_unit|hsync_counter_cout[7]~COUT1_22\);
 810
 811 \vga_driver_unit|hsync_counter_8_\ : stratix_lcell
 812 -- Equation(s):
 813 -- \vga_driver_unit|hsync_counter_8\ = DFFEAS(\vga_driver_unit|hsync_counter_8\ $ (!(!\vga_driver_unit|hsync_counter_cout\(4) & \vga_driver_unit|hsync_counter_cout\(7)) # (\vga_driver_unit|hsync_counter_cout\(4) &
 814 -- \vga_driver_unit|hsync_counter_cout[7]~COUT1_22\)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, !\vga_driver_unit|un9_hsync_counterlt9\)
 815 -- \vga_driver_unit|hsync_counter_cout\(8) = CARRY(\vga_driver_unit|hsync_counter_8\ & (!\vga_driver_unit|hsync_counter_cout\(7)))
 816 -- \vga_driver_unit|hsync_counter_cout[8]~COUT1_24\ = CARRY(\vga_driver_unit|hsync_counter_8\ & (!\vga_driver_unit|hsync_counter_cout[7]~COUT1_22\))
 817
 818 -- pragma translate_off
 819 GENERIC MAP (
 820         cin0_used => "true",
 821         cin1_used => "true",
 822         cin_used => "true",
 823         lut_mask => "a50a",
 824         operation_mode => "arithmetic",
 825         output_mode => "reg_only",
 826         register_cascade_mode => "off",
 827         sum_lutc_input => "cin",
 828         synch_mode => "on")
 829 -- pragma translate_on
 830 PORT MAP (
 831         clk => \clk_pin~combout\,
 832         dataa => \vga_driver_unit|hsync_counter_8\,
 833         datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
 834         aclr => GND,
 835         sclr => \vga_driver_unit|ALT_INV_G_2_i\,
 836         sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
 837         cin => \vga_driver_unit|hsync_counter_cout\(4),
 838         cin0 => \vga_driver_unit|hsync_counter_cout\(7),
 839         cin1 => \vga_driver_unit|hsync_counter_cout[7]~COUT1_22\,
 840         devclrn => ww_devclrn,
 841         devpor => ww_devpor,
 842         regout => \vga_driver_unit|hsync_counter_8\,
 843         cout0 => \vga_driver_unit|hsync_counter_cout\(8),
 844         cout1 => \vga_driver_unit|hsync_counter_cout[8]~COUT1_24\);
 845
 846 \vga_driver_unit|hsync_counter_9_\ : stratix_lcell
 847 -- Equation(s):
 848 -- \vga_driver_unit|hsync_counter_9\ = DFFEAS((!\vga_driver_unit|hsync_counter_cout\(4) & \vga_driver_unit|hsync_counter_cout\(8)) # (\vga_driver_unit|hsync_counter_cout\(4) & \vga_driver_unit|hsync_counter_cout[8]~COUT1_24\) $
 849 -- \vga_driver_unit|hsync_counter_9\, GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|hsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_2_i\, !\vga_driver_unit|un9_hsync_counterlt9\)
 850
 851 -- pragma translate_off
 852 GENERIC MAP (
 853         cin0_used => "true",
 854         cin1_used => "true",
 855         cin_used => "true",
 856         lut_mask => "0ff0",
 857         operation_mode => "normal",
 858         output_mode => "reg_only",
 859         register_cascade_mode => "off",
 860         sum_lutc_input => "cin",
 861         synch_mode => "on")
 862 -- pragma translate_on
 863 PORT MAP (
 864         clk => \clk_pin~combout\,
 865         datac => \vga_driver_unit|hsync_counter_next_1_sqmuxa\,
 866         datad => \vga_driver_unit|hsync_counter_9\,
 867         aclr => GND,
 868         sclr => \vga_driver_unit|ALT_INV_G_2_i\,
 869         sload => \vga_driver_unit|ALT_INV_un9_hsync_counterlt9\,
 870         cin => \vga_driver_unit|hsync_counter_cout\(4),
 871         cin0 => \vga_driver_unit|hsync_counter_cout\(8),
 872         cin1 => \vga_driver_unit|hsync_counter_cout[8]~COUT1_24\,
 873         devclrn => ww_devclrn,
 874         devpor => ww_devpor,
 875         regout => \vga_driver_unit|hsync_counter_9\);
 876
 877 \vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9_3\ : stratix_lcell
 878 -- Equation(s):
 879 -- \vga_driver_unit|un9_hsync_counterlt9_3\ = !\vga_driver_unit|hsync_counter_4\ # !\vga_driver_unit|hsync_counter_6\ # !\vga_driver_unit|hsync_counter_7\ # !\vga_driver_unit|hsync_counter_5\
 880
 881 -- pragma translate_off
 882 GENERIC MAP (
 883         lut_mask => "7fff",
 884         operation_mode => "normal",
 885         output_mode => "comb_only",
 886         register_cascade_mode => "off",
 887         sum_lutc_input => "datac",
 888         synch_mode => "off")
 889 -- pragma translate_on
 890 PORT MAP (
 891         dataa => \vga_driver_unit|hsync_counter_5\,
 892         datab => \vga_driver_unit|hsync_counter_7\,
 893         datac => \vga_driver_unit|hsync_counter_6\,
 894         datad => \vga_driver_unit|hsync_counter_4\,
 895         devclrn => ww_devclrn,
 896         devpor => ww_devpor,
 897         combout => \vga_driver_unit|un9_hsync_counterlt9_3\);
 898
 899 \vga_driver_unit|HSYNC_COUNT_next_un9_hsync_counterlt9\ : stratix_lcell
 900 -- Equation(s):
 901 -- \vga_driver_unit|un9_hsync_counterlt9\ = \vga_driver_unit|un9_hsync_counterlt9_3\ # !\vga_driver_unit|hsync_counter_8\ # !\vga_driver_unit|hsync_counter_9\ # !\vga_driver_unit|un13_hsync_counter_7\
 902
 903 -- pragma translate_off
 904 GENERIC MAP (
 905         lut_mask => "ff7f",
 906         operation_mode => "normal",
 907         output_mode => "comb_only",
 908         register_cascade_mode => "off",
 909         sum_lutc_input => "datac",
 910         synch_mode => "off")
 911 -- pragma translate_on
 912 PORT MAP (
 913         dataa => \vga_driver_unit|un13_hsync_counter_7\,
 914         datab => \vga_driver_unit|hsync_counter_9\,
 915         datac => \vga_driver_unit|hsync_counter_8\,
 916         datad => \vga_driver_unit|un9_hsync_counterlt9_3\,
 917         devclrn => ww_devclrn,
 918         devpor => ww_devpor,
 919         combout => \vga_driver_unit|un9_hsync_counterlt9\);
 920
 921 \vga_driver_unit|G_2\ : stratix_lcell
 922 -- Equation(s):
 923 -- \vga_driver_unit|G_2_i\ = !\vga_driver_unit|hsync_state_6\ & !\vga_driver_unit|hsync_state_0\ & !\vga_driver_unit|un6_dly_counter_0_x\ # !\vga_driver_unit|un9_hsync_counterlt9\
 924
 925 -- pragma translate_off
 926 GENERIC MAP (
 927         lut_mask => "01ff",
 928         operation_mode => "normal",
 929         output_mode => "comb_only",
 930         register_cascade_mode => "off",
 931         sum_lutc_input => "datac",
 932         synch_mode => "off")
 933 -- pragma translate_on
 934 PORT MAP (
 935         dataa => \vga_driver_unit|hsync_state_6\,
 936         datab => \vga_driver_unit|hsync_state_0\,
 937         datac => \vga_driver_unit|un6_dly_counter_0_x\,
 938         datad => \vga_driver_unit|un9_hsync_counterlt9\,
 939         devclrn => ww_devclrn,
 940         devpor => ww_devpor,
 941         combout => \vga_driver_unit|G_2_i\);
 942
 943 \vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_7\ : stratix_lcell
 944 -- Equation(s):
 945 -- \vga_driver_unit|un13_hsync_counter_7\ = \vga_driver_unit|hsync_counter_1\ & \vga_driver_unit|hsync_counter_0\ & \vga_driver_unit|hsync_counter_3\ & \vga_driver_unit|hsync_counter_2\
 946
 947 -- pragma translate_off
 948 GENERIC MAP (
 949         lut_mask => "8000",
 950         operation_mode => "normal",
 951         output_mode => "comb_only",
 952         register_cascade_mode => "off",
 953         sum_lutc_input => "datac",
 954         synch_mode => "off")
 955 -- pragma translate_on
 956 PORT MAP (
 957         dataa => \vga_driver_unit|hsync_counter_1\,
 958         datab => \vga_driver_unit|hsync_counter_0\,
 959         datac => \vga_driver_unit|hsync_counter_3\,
 960         datad => \vga_driver_unit|hsync_counter_2\,
 961         devclrn => ww_devclrn,
 962         devpor => ww_devpor,
 963         combout => \vga_driver_unit|un13_hsync_counter_7\);
 964
 965 \vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter_2\ : stratix_lcell
 966 -- Equation(s):
 967 -- \vga_driver_unit|un13_hsync_counter_2\ = !\vga_driver_unit|hsync_counter_5\ & \vga_driver_unit|hsync_counter_8\ & \vga_driver_unit|hsync_counter_4\ & \vga_driver_unit|hsync_counter_9\
 968
 969 -- pragma translate_off
 970 GENERIC MAP (
 971         lut_mask => "4000",
 972         operation_mode => "normal",
 973         output_mode => "comb_only",
 974         register_cascade_mode => "off",
 975         sum_lutc_input => "datac",
 976         synch_mode => "off")
 977 -- pragma translate_on
 978 PORT MAP (
 979         dataa => \vga_driver_unit|hsync_counter_5\,
 980         datab => \vga_driver_unit|hsync_counter_8\,
 981         datac => \vga_driver_unit|hsync_counter_4\,
 982         datad => \vga_driver_unit|hsync_counter_9\,
 983         devclrn => ww_devclrn,
 984         devpor => ww_devpor,
 985         combout => \vga_driver_unit|un13_hsync_counter_2\);
 986
 987 \vga_driver_unit|HSYNC_FSM_next_un13_hsync_counter\ : stratix_lcell
 988 -- Equation(s):
 989 -- \vga_driver_unit|un13_hsync_counter\ = !\vga_driver_unit|hsync_counter_7\ & \vga_driver_unit|un13_hsync_counter_7\ & !\vga_driver_unit|hsync_counter_6\ & \vga_driver_unit|un13_hsync_counter_2\
 990
 991 -- pragma translate_off
 992 GENERIC MAP (
 993         lut_mask => "0400",
 994         operation_mode => "normal",
 995         output_mode => "comb_only",
 996         register_cascade_mode => "off",
 997         sum_lutc_input => "datac",
 998         synch_mode => "off")
 999 -- pragma translate_on
1000 PORT MAP (
1001         dataa => \vga_driver_unit|hsync_counter_7\,
1002         datab => \vga_driver_unit|un13_hsync_counter_7\,
1003         datac => \vga_driver_unit|hsync_counter_6\,
1004         datad => \vga_driver_unit|un13_hsync_counter_2\,
1005         devclrn => ww_devclrn,
1006         devpor => ww_devpor,
1007         combout => \vga_driver_unit|un13_hsync_counter\);
1008
1009 \vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_3\ : stratix_lcell
1010 -- Equation(s):
1011 -- \vga_driver_unit|un12_hsync_counter_3\ = !\vga_driver_unit|hsync_counter_3\ & \vga_driver_unit|hsync_counter_9\ & \vga_driver_unit|hsync_counter_8\ & !\vga_driver_unit|hsync_counter_5\
1012
1013 -- pragma translate_off
1014 GENERIC MAP (
1015         lut_mask => "0040",
1016         operation_mode => "normal",
1017         output_mode => "comb_only",
1018         register_cascade_mode => "off",
1019         sum_lutc_input => "datac",
1020         synch_mode => "off")
1021 -- pragma translate_on
1022 PORT MAP (
1023         dataa => \vga_driver_unit|hsync_counter_3\,
1024         datab => \vga_driver_unit|hsync_counter_9\,
1025         datac => \vga_driver_unit|hsync_counter_8\,
1026         datad => \vga_driver_unit|hsync_counter_5\,
1027         devclrn => ww_devclrn,
1028         devpor => ww_devpor,
1029         combout => \vga_driver_unit|un12_hsync_counter_3\);
1030
1031 \vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter_4\ : stratix_lcell
1032 -- Equation(s):
1033 -- \vga_driver_unit|un12_hsync_counter_4\ = !\vga_driver_unit|hsync_counter_7\ & !\vga_driver_unit|hsync_counter_6\ & !\vga_driver_unit|hsync_counter_4\ & \vga_driver_unit|hsync_counter_2\
1034
1035 -- pragma translate_off
1036 GENERIC MAP (
1037         lut_mask => "0100",
1038         operation_mode => "normal",
1039         output_mode => "comb_only",
1040         register_cascade_mode => "off",
1041         sum_lutc_input => "datac",
1042         synch_mode => "off")
1043 -- pragma translate_on
1044 PORT MAP (
1045         dataa => \vga_driver_unit|hsync_counter_7\,
1046         datab => \vga_driver_unit|hsync_counter_6\,
1047         datac => \vga_driver_unit|hsync_counter_4\,
1048         datad => \vga_driver_unit|hsync_counter_2\,
1049         devclrn => ww_devclrn,
1050         devpor => ww_devpor,
1051         combout => \vga_driver_unit|un12_hsync_counter_4\);
1052
1053 \vga_driver_unit|HSYNC_FSM_next_un12_hsync_counter\ : stratix_lcell
1054 -- Equation(s):
1055 -- \vga_driver_unit|un12_hsync_counter\ = \vga_driver_unit|hsync_counter_1\ & \vga_driver_unit|un12_hsync_counter_3\ & \vga_driver_unit|hsync_counter_0\ & \vga_driver_unit|un12_hsync_counter_4\
1056
1057 -- pragma translate_off
1058 GENERIC MAP (
1059         lut_mask => "8000",
1060         operation_mode => "normal",
1061         output_mode => "comb_only",
1062         register_cascade_mode => "off",
1063         sum_lutc_input => "datac",
1064         synch_mode => "off")
1065 -- pragma translate_on
1066 PORT MAP (
1067         dataa => \vga_driver_unit|hsync_counter_1\,
1068         datab => \vga_driver_unit|un12_hsync_counter_3\,
1069         datac => \vga_driver_unit|hsync_counter_0\,
1070         datad => \vga_driver_unit|un12_hsync_counter_4\,
1071         devclrn => ww_devclrn,
1072         devpor => ww_devpor,
1073         combout => \vga_driver_unit|un12_hsync_counter\);
1074
1075 \vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_4\ : stratix_lcell
1076 -- Equation(s):
1077 -- \vga_driver_unit|un10_hsync_counter_4\ = \vga_driver_unit|hsync_counter_1\ & \vga_driver_unit|hsync_counter_4\ & \vga_driver_unit|hsync_counter_3\ & \vga_driver_unit|hsync_counter_6\
1078
1079 -- pragma translate_off
1080 GENERIC MAP (
1081         lut_mask => "8000",
1082         operation_mode => "normal",
1083         output_mode => "comb_only",
1084         register_cascade_mode => "off",
1085         sum_lutc_input => "datac",
1086         synch_mode => "off")
1087 -- pragma translate_on
1088 PORT MAP (
1089         dataa => \vga_driver_unit|hsync_counter_1\,
1090         datab => \vga_driver_unit|hsync_counter_4\,
1091         datac => \vga_driver_unit|hsync_counter_3\,
1092         datad => \vga_driver_unit|hsync_counter_6\,
1093         devclrn => ww_devclrn,
1094         devpor => ww_devpor,
1095         combout => \vga_driver_unit|un10_hsync_counter_4\);
1096
1097 \vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_3\ : stratix_lcell
1098 -- Equation(s):
1099 -- \vga_driver_unit|un10_hsync_counter_3\ = !\vga_driver_unit|hsync_counter_7\ & !\vga_driver_unit|hsync_counter_2\ & (!\vga_driver_unit|hsync_counter_0\)
1100
1101 -- pragma translate_off
1102 GENERIC MAP (
1103         lut_mask => "0011",
1104         operation_mode => "normal",
1105         output_mode => "comb_only",
1106         register_cascade_mode => "off",
1107         sum_lutc_input => "datac",
1108         synch_mode => "off")
1109 -- pragma translate_on
1110 PORT MAP (
1111         dataa => \vga_driver_unit|hsync_counter_7\,
1112         datab => \vga_driver_unit|hsync_counter_2\,
1113         datad => \vga_driver_unit|hsync_counter_0\,
1114         devclrn => ww_devclrn,
1115         devpor => ww_devpor,
1116         combout => \vga_driver_unit|un10_hsync_counter_3\);
1117
1118 \vga_driver_unit|HSYNC_FSM_next_un10_hsync_counter_1\ : stratix_lcell
1119 -- Equation(s):
1120 -- \vga_driver_unit|un10_hsync_counter_1\ = !\vga_driver_unit|hsync_counter_8\ & !\vga_driver_unit|hsync_counter_9\ & !\vga_driver_unit|hsync_counter_5\
1121
1122 -- pragma translate_off
1123 GENERIC MAP (
1124         lut_mask => "0003",
1125         operation_mode => "normal",
1126         output_mode => "comb_only",
1127         register_cascade_mode => "off",
1128         sum_lutc_input => "datac",
1129         synch_mode => "off")
1130 -- pragma translate_on
1131 PORT MAP (
1132         datab => \vga_driver_unit|hsync_counter_8\,
1133         datac => \vga_driver_unit|hsync_counter_9\,
1134         datad => \vga_driver_unit|hsync_counter_5\,
1135         devclrn => ww_devclrn,
1136         devpor => ww_devpor,
1137         combout => \vga_driver_unit|un10_hsync_counter_1\);
1138
1139 \vga_driver_unit|hsync_state_5_\ : stratix_lcell
1140 -- Equation(s):
1141 -- \vga_driver_unit|hsync_state_5\ = DFFEAS(\vga_driver_unit|hsync_state_6\ # \vga_driver_unit|hsync_state_0\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
1142
1143 -- pragma translate_off
1144 GENERIC MAP (
1145         lut_mask => "fff0",
1146         operation_mode => "normal",
1147         output_mode => "reg_only",
1148         register_cascade_mode => "off",
1149         sum_lutc_input => "datac",
1150         synch_mode => "on")
1151 -- pragma translate_on
1152 PORT MAP (
1153         clk => \clk_pin~combout\,
1154         datac => \vga_driver_unit|hsync_state_6\,
1155         datad => \vga_driver_unit|hsync_state_0\,
1156         aclr => GND,
1157         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
1158         ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\,
1159         devclrn => ww_devclrn,
1160         devpor => ww_devpor,
1161         regout => \vga_driver_unit|hsync_state_5\);
1162
1163 \vga_driver_unit|hsync_state_4_\ : stratix_lcell
1164 -- Equation(s):
1165 -- \vga_driver_unit|hsync_state_4\ = DFFEAS(\vga_driver_unit|un10_hsync_counter_4\ & \vga_driver_unit|un10_hsync_counter_3\ & \vga_driver_unit|un10_hsync_counter_1\ & \vga_driver_unit|hsync_state_5\, GLOBAL(\clk_pin~combout\), VCC, ,
1166 -- \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
1167
1168 -- pragma translate_off
1169 GENERIC MAP (
1170         lut_mask => "8000",
1171         operation_mode => "normal",
1172         output_mode => "reg_only",
1173         register_cascade_mode => "off",
1174         sum_lutc_input => "datac",
1175         synch_mode => "on")
1176 -- pragma translate_on
1177 PORT MAP (
1178         clk => \clk_pin~combout\,
1179         dataa => \vga_driver_unit|un10_hsync_counter_4\,
1180         datab => \vga_driver_unit|un10_hsync_counter_3\,
1181         datac => \vga_driver_unit|un10_hsync_counter_1\,
1182         datad => \vga_driver_unit|hsync_state_5\,
1183         aclr => GND,
1184         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
1185         ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\,
1186         devclrn => ww_devclrn,
1187         devpor => ww_devpor,
1188         regout => \vga_driver_unit|hsync_state_4\);
1189
1190 \vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_3\ : stratix_lcell
1191 -- Equation(s):
1192 -- \vga_driver_unit|un11_hsync_counter_3\ = \vga_driver_unit|hsync_counter_1\ & !\vga_driver_unit|hsync_counter_4\ & !\vga_driver_unit|hsync_counter_3\ & \vga_driver_unit|hsync_counter_0\
1193
1194 -- pragma translate_off
1195 GENERIC MAP (
1196         lut_mask => "0200",
1197         operation_mode => "normal",
1198         output_mode => "comb_only",
1199         register_cascade_mode => "off",
1200         sum_lutc_input => "datac",
1201         synch_mode => "off")
1202 -- pragma translate_on
1203 PORT MAP (
1204         dataa => \vga_driver_unit|hsync_counter_1\,
1205         datab => \vga_driver_unit|hsync_counter_4\,
1206         datac => \vga_driver_unit|hsync_counter_3\,
1207         datad => \vga_driver_unit|hsync_counter_0\,
1208         devclrn => ww_devclrn,
1209         devpor => ww_devpor,
1210         combout => \vga_driver_unit|un11_hsync_counter_3\);
1211
1212 \vga_driver_unit|hsync_state_next_1_sqmuxa_2_cZ\ : stratix_lcell
1213 -- Equation(s):
1214 -- \vga_driver_unit|hsync_state_next_1_sqmuxa_2\ = \vga_driver_unit|hsync_state_4\ & (!\vga_driver_unit|un11_hsync_counter_3\ # !\vga_driver_unit|un10_hsync_counter_1\ # !\vga_driver_unit|un11_hsync_counter_2\)
1215
1216 -- pragma translate_off
1217 GENERIC MAP (
1218         lut_mask => "4ccc",
1219         operation_mode => "normal",
1220         output_mode => "comb_only",
1221         register_cascade_mode => "off",
1222         sum_lutc_input => "datac",
1223         synch_mode => "off")
1224 -- pragma translate_on
1225 PORT MAP (
1226         dataa => \vga_driver_unit|un11_hsync_counter_2\,
1227         datab => \vga_driver_unit|hsync_state_4\,
1228         datac => \vga_driver_unit|un10_hsync_counter_1\,
1229         datad => \vga_driver_unit|un11_hsync_counter_3\,
1230         devclrn => ww_devclrn,
1231         devpor => ww_devpor,
1232         combout => \vga_driver_unit|hsync_state_next_1_sqmuxa_2\);
1233
1234 \vga_driver_unit|hsync_state_3_\ : stratix_lcell
1235 -- Equation(s):
1236 -- \vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\ = \vga_driver_unit|un13_hsync_counter\ & !\vga_driver_unit|un12_hsync_counter\ & C1_hsync_state_3 # !\vga_driver_unit|un13_hsync_counter\ & (\vga_driver_unit|hsync_state_2\ #
1237 -- !\vga_driver_unit|un12_hsync_counter\ & C1_hsync_state_3)
1238 -- \vga_driver_unit|hsync_state_3\ = DFFEAS(\vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, \vga_driver_unit|hsync_state_1\, , \vga_driver_unit|un6_dly_counter_0_x\, VCC)
1239
1240 -- pragma translate_off
1241 GENERIC MAP (
1242         lut_mask => "7530",
1243         operation_mode => "normal",
1244         output_mode => "reg_and_comb",
1245         register_cascade_mode => "off",
1246         sum_lutc_input => "qfbk",
1247         synch_mode => "on")
1248 -- pragma translate_on
1249 PORT MAP (
1250         clk => \clk_pin~combout\,
1251         dataa => \vga_driver_unit|un13_hsync_counter\,
1252         datab => \vga_driver_unit|un12_hsync_counter\,
1253         datac => \vga_driver_unit|hsync_state_1\,
1254         datad => \vga_driver_unit|hsync_state_2\,
1255         aclr => GND,
1256         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
1257         sload => VCC,
1258         ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\,
1259         devclrn => ww_devclrn,
1260         devpor => ww_devpor,
1261         combout => \vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\,
1262         regout => \vga_driver_unit|hsync_state_3\);
1263
1264 \vga_driver_unit|hsync_state_next_1_sqmuxa_1_cZ\ : stratix_lcell
1265 -- Equation(s):
1266 -- \vga_driver_unit|hsync_state_next_1_sqmuxa_1\ = \vga_driver_unit|hsync_state_5\ & (!\vga_driver_unit|un10_hsync_counter_1\ # !\vga_driver_unit|un10_hsync_counter_4\ # !\vga_driver_unit|un10_hsync_counter_3\)
1267
1268 -- pragma translate_off
1269 GENERIC MAP (
1270         lut_mask => "2aaa",
1271         operation_mode => "normal",
1272         output_mode => "comb_only",
1273         register_cascade_mode => "off",
1274         sum_lutc_input => "datac",
1275         synch_mode => "off")
1276 -- pragma translate_on
1277 PORT MAP (
1278         dataa => \vga_driver_unit|hsync_state_5\,
1279         datab => \vga_driver_unit|un10_hsync_counter_3\,
1280         datac => \vga_driver_unit|un10_hsync_counter_4\,
1281         datad => \vga_driver_unit|un10_hsync_counter_1\,
1282         devclrn => ww_devclrn,
1283         devpor => ww_devpor,
1284         combout => \vga_driver_unit|hsync_state_next_1_sqmuxa_1\);
1285
1286 \vga_driver_unit|hsync_state_3_0_0_0__g0_0_cZ\ : stratix_lcell
1287 -- Equation(s):
1288 -- \vga_driver_unit|hsync_state_3_0_0_0__g0_0\ = \vga_driver_unit|un6_dly_counter_0_x\ # !\vga_driver_unit|hsync_state_next_1_sqmuxa_2\ & !\vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\ & !\vga_driver_unit|hsync_state_next_1_sqmuxa_1\
1289
1290 -- pragma translate_off
1291 GENERIC MAP (
1292         lut_mask => "aaab",
1293         operation_mode => "normal",
1294         output_mode => "comb_only",
1295         register_cascade_mode => "off",
1296         sum_lutc_input => "datac",
1297         synch_mode => "off")
1298 -- pragma translate_on
1299 PORT MAP (
1300         dataa => \vga_driver_unit|un6_dly_counter_0_x\,
1301         datab => \vga_driver_unit|hsync_state_next_1_sqmuxa_2\,
1302         datac => \vga_driver_unit|un1_hsync_state_next_1_sqmuxa_0\,
1303         datad => \vga_driver_unit|hsync_state_next_1_sqmuxa_1\,
1304         devclrn => ww_devclrn,
1305         devpor => ww_devpor,
1306         combout => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\);
1307
1308 \vga_driver_unit|hsync_state_2_\ : stratix_lcell
1309 -- Equation(s):
1310 -- \vga_driver_unit|hsync_state_2\ = DFFEAS(\vga_driver_unit|un12_hsync_counter\ & (\vga_driver_unit|hsync_state_3\), GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
1311
1312 -- pragma translate_off
1313 GENERIC MAP (
1314         lut_mask => "a0a0",
1315         operation_mode => "normal",
1316         output_mode => "reg_only",
1317         register_cascade_mode => "off",
1318         sum_lutc_input => "datac",
1319         synch_mode => "on")
1320 -- pragma translate_on
1321 PORT MAP (
1322         clk => \clk_pin~combout\,
1323         dataa => \vga_driver_unit|un12_hsync_counter\,
1324         datac => \vga_driver_unit|hsync_state_3\,
1325         aclr => GND,
1326         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
1327         ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\,
1328         devclrn => ww_devclrn,
1329         devpor => ww_devpor,
1330         regout => \vga_driver_unit|hsync_state_2\);
1331
1332 \vga_driver_unit|hsync_state_0_\ : stratix_lcell
1333 -- Equation(s):
1334 -- \vga_driver_unit|hsync_state_0\ = DFFEAS(\vga_driver_unit|un13_hsync_counter\ & \vga_driver_unit|hsync_state_2\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
1335
1336 -- pragma translate_off
1337 GENERIC MAP (
1338         lut_mask => "f000",
1339         operation_mode => "normal",
1340         output_mode => "reg_only",
1341         register_cascade_mode => "off",
1342         sum_lutc_input => "datac",
1343         synch_mode => "on")
1344 -- pragma translate_on
1345 PORT MAP (
1346         clk => \clk_pin~combout\,
1347         datac => \vga_driver_unit|un13_hsync_counter\,
1348         datad => \vga_driver_unit|hsync_state_2\,
1349         aclr => GND,
1350         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
1351         ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\,
1352         devclrn => ww_devclrn,
1353         devpor => ww_devpor,
1354         regout => \vga_driver_unit|hsync_state_0\);
1355
1356 \vga_driver_unit|hsync_counter_next_1_sqmuxa_cZ\ : stratix_lcell
1357 -- Equation(s):
1358 -- \vga_driver_unit|hsync_counter_next_1_sqmuxa\ = dly_counter(1) & dly_counter(0) & \reset_pin~combout\ & !\vga_driver_unit|d_set_hsync_counter\
1359
1360 -- pragma translate_off
1361 GENERIC MAP (
1362         lut_mask => "0080",
1363         operation_mode => "normal",
1364         output_mode => "comb_only",
1365         register_cascade_mode => "off",
1366         sum_lutc_input => "datac",
1367         synch_mode => "off")
1368 -- pragma translate_on
1369 PORT MAP (
1370         dataa => dly_counter(1),
1371         datab => dly_counter(0),
1372         datac => \reset_pin~combout\,
1373         datad => \vga_driver_unit|d_set_hsync_counter\,
1374         devclrn => ww_devclrn,
1375         devpor => ww_devpor,
1376         combout => \vga_driver_unit|hsync_counter_next_1_sqmuxa\);
1377
1378 \vga_driver_unit|HSYNC_FSM_next_un11_hsync_counter_2\ : stratix_lcell
1379 -- Equation(s):
1380 -- \vga_driver_unit|un11_hsync_counter_2\ = \vga_driver_unit|hsync_counter_7\ & \vga_driver_unit|hsync_counter_2\ & (!\vga_driver_unit|hsync_counter_6\)
1381
1382 -- pragma translate_off
1383 GENERIC MAP (
1384         lut_mask => "0088",
1385         operation_mode => "normal",
1386         output_mode => "comb_only",
1387         register_cascade_mode => "off",
1388         sum_lutc_input => "datac",
1389         synch_mode => "off")
1390 -- pragma translate_on
1391 PORT MAP (
1392         dataa => \vga_driver_unit|hsync_counter_7\,
1393         datab => \vga_driver_unit|hsync_counter_2\,
1394         datad => \vga_driver_unit|hsync_counter_6\,
1395         devclrn => ww_devclrn,
1396         devpor => ww_devpor,
1397         combout => \vga_driver_unit|un11_hsync_counter_2\);
1398
1399 \vga_driver_unit|hsync_state_1_\ : stratix_lcell
1400 -- Equation(s):
1401 -- \vga_driver_unit|hsync_state_1\ = DFFEAS(\vga_driver_unit|un11_hsync_counter_2\ & \vga_driver_unit|hsync_state_4\ & \vga_driver_unit|un10_hsync_counter_1\ & \vga_driver_unit|un11_hsync_counter_3\, GLOBAL(\clk_pin~combout\), VCC, ,
1402 -- \vga_driver_unit|hsync_state_3_0_0_0__g0_0\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
1403
1404 -- pragma translate_off
1405 GENERIC MAP (
1406         lut_mask => "8000",
1407         operation_mode => "normal",
1408         output_mode => "reg_only",
1409         register_cascade_mode => "off",
1410         sum_lutc_input => "datac",
1411         synch_mode => "on")
1412 -- pragma translate_on
1413 PORT MAP (
1414         clk => \clk_pin~combout\,
1415         dataa => \vga_driver_unit|un11_hsync_counter_2\,
1416         datab => \vga_driver_unit|hsync_state_4\,
1417         datac => \vga_driver_unit|un10_hsync_counter_1\,
1418         datad => \vga_driver_unit|un11_hsync_counter_3\,
1419         aclr => GND,
1420         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
1421         ena => \vga_driver_unit|hsync_state_3_0_0_0__g0_0\,
1422         devclrn => ww_devclrn,
1423         devpor => ww_devpor,
1424         regout => \vga_driver_unit|hsync_state_1\);
1425
1426 \vga_driver_unit|column_counter_next_0_sqmuxa_1_1_cZ\ : stratix_lcell
1427 -- Equation(s):
1428 -- \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\ = dly_counter(0) & dly_counter(1) & \reset_pin~combout\ & !\vga_driver_unit|hsync_state_1\
1429
1430 -- pragma translate_off
1431 GENERIC MAP (
1432         lut_mask => "0080",
1433         operation_mode => "normal",
1434         output_mode => "comb_only",
1435         register_cascade_mode => "off",
1436         sum_lutc_input => "datac",
1437         synch_mode => "off")
1438 -- pragma translate_on
1439 PORT MAP (
1440         dataa => dly_counter(0),
1441         datab => dly_counter(1),
1442         datac => \reset_pin~combout\,
1443         datad => \vga_driver_unit|hsync_state_1\,
1444         devclrn => ww_devclrn,
1445         devpor => ww_devpor,
1446         combout => \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\);
1447
1448 \vga_driver_unit|column_counter_sig_0_\ : stratix_lcell
1449 -- Equation(s):
1450 -- \vga_driver_unit|column_counter_sig_0\ = DFFEAS(!\vga_driver_unit|un10_column_counter_siglto9\ # !\vga_driver_unit|column_counter_sig_0\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, )
1451
1452 -- pragma translate_off
1453 GENERIC MAP (
1454         lut_mask => "0fff",
1455         operation_mode => "normal",
1456         output_mode => "reg_only",
1457         register_cascade_mode => "off",
1458         sum_lutc_input => "datac",
1459         synch_mode => "on")
1460 -- pragma translate_on
1461 PORT MAP (
1462         clk => \clk_pin~combout\,
1463         datac => \vga_driver_unit|column_counter_sig_0\,
1464         datad => \vga_driver_unit|un10_column_counter_siglto9\,
1465         aclr => GND,
1466         sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\,
1467         devclrn => ww_devclrn,
1468         devpor => ww_devpor,
1469         regout => \vga_driver_unit|column_counter_sig_0\);
1470
1471 \vga_driver_unit|un2_column_counter_next_1_\ : stratix_lcell
1472 -- Equation(s):
1473 -- \vga_driver_unit|un2_column_counter_next_combout\(1) = \vga_driver_unit|column_counter_sig_1\ $ \vga_driver_unit|column_counter_sig_0\
1474 -- \vga_driver_unit|un2_column_counter_next_cout\(1) = CARRY(\vga_driver_unit|column_counter_sig_1\ & \vga_driver_unit|column_counter_sig_0\)
1475 -- \vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10\ = CARRY(\vga_driver_unit|column_counter_sig_1\ & \vga_driver_unit|column_counter_sig_0\)
1476
1477 -- pragma translate_off
1478 GENERIC MAP (
1479         lut_mask => "6688",
1480         operation_mode => "arithmetic",
1481         output_mode => "comb_only",
1482         register_cascade_mode => "off",
1483         sum_lutc_input => "datac",
1484         synch_mode => "off")
1485 -- pragma translate_on
1486 PORT MAP (
1487         dataa => \vga_driver_unit|column_counter_sig_1\,
1488         datab => \vga_driver_unit|column_counter_sig_0\,
1489         devclrn => ww_devclrn,
1490         devpor => ww_devpor,
1491         combout => \vga_driver_unit|un2_column_counter_next_combout\(1),
1492         cout0 => \vga_driver_unit|un2_column_counter_next_cout\(1),
1493         cout1 => \vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10\);
1494
1495 \vga_driver_unit|column_counter_sig_1_\ : stratix_lcell
1496 -- Equation(s):
1497 -- \vga_driver_unit|column_counter_sig_1\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(1) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, )
1498
1499 -- pragma translate_off
1500 GENERIC MAP (
1501         lut_mask => "f0ff",
1502         operation_mode => "normal",
1503         output_mode => "reg_only",
1504         register_cascade_mode => "off",
1505         sum_lutc_input => "datac",
1506         synch_mode => "on")
1507 -- pragma translate_on
1508 PORT MAP (
1509         clk => \clk_pin~combout\,
1510         datac => \vga_driver_unit|un2_column_counter_next_combout\(1),
1511         datad => \vga_driver_unit|un10_column_counter_siglto9\,
1512         aclr => GND,
1513         sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\,
1514         devclrn => ww_devclrn,
1515         devpor => ww_devpor,
1516         regout => \vga_driver_unit|column_counter_sig_1\);
1517
1518 \vga_driver_unit|un2_column_counter_next_0_\ : stratix_lcell
1519 -- Equation(s):
1520 -- \vga_driver_unit|un2_column_counter_next_cout\(0) = CARRY(\vga_driver_unit|column_counter_sig_1\ & \vga_driver_unit|column_counter_sig_0\)
1521 -- \vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18\ = CARRY(\vga_driver_unit|column_counter_sig_1\ & \vga_driver_unit|column_counter_sig_0\)
1522
1523 -- pragma translate_off
1524 GENERIC MAP (
1525         lut_mask => "ff88",
1526         operation_mode => "arithmetic",
1527         output_mode => "none",
1528         register_cascade_mode => "off",
1529         sum_lutc_input => "datac",
1530         synch_mode => "off")
1531 -- pragma translate_on
1532 PORT MAP (
1533         dataa => \vga_driver_unit|column_counter_sig_1\,
1534         datab => \vga_driver_unit|column_counter_sig_0\,
1535         devclrn => ww_devclrn,
1536         devpor => ww_devpor,
1537         combout => \vga_driver_unit|un2_column_counter_next_0_~COMBOUT\,
1538         cout0 => \vga_driver_unit|un2_column_counter_next_cout\(0),
1539         cout1 => \vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18\);
1540
1541 \vga_driver_unit|un2_column_counter_next_2_\ : stratix_lcell
1542 -- Equation(s):
1543 -- \vga_driver_unit|un2_column_counter_next_combout\(2) = \vga_driver_unit|column_counter_sig_2\ $ (\vga_driver_unit|un2_column_counter_next_cout\(0))
1544 -- \vga_driver_unit|un2_column_counter_next_cout\(2) = CARRY(!\vga_driver_unit|un2_column_counter_next_cout\(0) # !\vga_driver_unit|column_counter_sig_3\ # !\vga_driver_unit|column_counter_sig_2\)
1545 -- \vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20\ = CARRY(!\vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18\ # !\vga_driver_unit|column_counter_sig_3\ # !\vga_driver_unit|column_counter_sig_2\)
1546
1547 -- pragma translate_off
1548 GENERIC MAP (
1549         cin0_used => "true",
1550         cin1_used => "true",
1551         lut_mask => "5a7f",
1552         operation_mode => "arithmetic",
1553         output_mode => "comb_only",
1554         register_cascade_mode => "off",
1555         sum_lutc_input => "cin",
1556         synch_mode => "off")
1557 -- pragma translate_on
1558 PORT MAP (
1559         dataa => \vga_driver_unit|column_counter_sig_2\,
1560         datab => \vga_driver_unit|column_counter_sig_3\,
1561         cin0 => \vga_driver_unit|un2_column_counter_next_cout\(0),
1562         cin1 => \vga_driver_unit|un2_column_counter_next_cout[0]~COUT1_18\,
1563         devclrn => ww_devclrn,
1564         devpor => ww_devpor,
1565         combout => \vga_driver_unit|un2_column_counter_next_combout\(2),
1566         cout0 => \vga_driver_unit|un2_column_counter_next_cout\(2),
1567         cout1 => \vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20\);
1568
1569 \vga_driver_unit|un2_column_counter_next_4_\ : stratix_lcell
1570 -- Equation(s):
1571 -- \vga_driver_unit|un2_column_counter_next_combout\(4) = \vga_driver_unit|column_counter_sig_4\ $ !\vga_driver_unit|un2_column_counter_next_cout\(2)
1572 -- \vga_driver_unit|un2_column_counter_next_cout\(4) = CARRY(\vga_driver_unit|column_counter_sig_5\ & \vga_driver_unit|column_counter_sig_4\ & !\vga_driver_unit|un2_column_counter_next_cout\(2))
1573 -- \vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22\ = CARRY(\vga_driver_unit|column_counter_sig_5\ & \vga_driver_unit|column_counter_sig_4\ & !\vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20\)
1574
1575 -- pragma translate_off
1576 GENERIC MAP (
1577         cin0_used => "true",
1578         cin1_used => "true",
1579         lut_mask => "c308",
1580         operation_mode => "arithmetic",
1581         output_mode => "comb_only",
1582         register_cascade_mode => "off",
1583         sum_lutc_input => "cin",
1584         synch_mode => "off")
1585 -- pragma translate_on
1586 PORT MAP (
1587         dataa => \vga_driver_unit|column_counter_sig_5\,
1588         datab => \vga_driver_unit|column_counter_sig_4\,
1589         cin0 => \vga_driver_unit|un2_column_counter_next_cout\(2),
1590         cin1 => \vga_driver_unit|un2_column_counter_next_cout[2]~COUT1_20\,
1591         devclrn => ww_devclrn,
1592         devpor => ww_devpor,
1593         combout => \vga_driver_unit|un2_column_counter_next_combout\(4),
1594         cout0 => \vga_driver_unit|un2_column_counter_next_cout\(4),
1595         cout1 => \vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22\);
1596
1597 \vga_driver_unit|column_counter_sig_4_\ : stratix_lcell
1598 -- Equation(s):
1599 -- \vga_driver_unit|column_counter_sig_4\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(4) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, )
1600
1601 -- pragma translate_off
1602 GENERIC MAP (
1603         lut_mask => "ff0f",
1604         operation_mode => "normal",
1605         output_mode => "reg_only",
1606         register_cascade_mode => "off",
1607         sum_lutc_input => "datac",
1608         synch_mode => "on")
1609 -- pragma translate_on
1610 PORT MAP (
1611         clk => \clk_pin~combout\,
1612         datac => \vga_driver_unit|un10_column_counter_siglto9\,
1613         datad => \vga_driver_unit|un2_column_counter_next_combout\(4),
1614         aclr => GND,
1615         sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\,
1616         devclrn => ww_devclrn,
1617         devpor => ww_devpor,
1618         regout => \vga_driver_unit|column_counter_sig_4\);
1619
1620 \vga_driver_unit|un2_column_counter_next_3_\ : stratix_lcell
1621 -- Equation(s):
1622 -- \vga_driver_unit|un2_column_counter_next_combout\(3) = \vga_driver_unit|column_counter_sig_3\ $ (\vga_driver_unit|column_counter_sig_2\ & \vga_driver_unit|un2_column_counter_next_cout\(1))
1623 -- \vga_driver_unit|un2_column_counter_next_cout\(3) = CARRY(!\vga_driver_unit|un2_column_counter_next_cout\(1) # !\vga_driver_unit|column_counter_sig_2\ # !\vga_driver_unit|column_counter_sig_3\)
1624 -- \vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12\ = CARRY(!\vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10\ # !\vga_driver_unit|column_counter_sig_2\ # !\vga_driver_unit|column_counter_sig_3\)
1625
1626 -- pragma translate_off
1627 GENERIC MAP (
1628         cin0_used => "true",
1629         cin1_used => "true",
1630         lut_mask => "6a7f",
1631         operation_mode => "arithmetic",
1632         output_mode => "comb_only",
1633         register_cascade_mode => "off",
1634         sum_lutc_input => "cin",
1635         synch_mode => "off")
1636 -- pragma translate_on
1637 PORT MAP (
1638         dataa => \vga_driver_unit|column_counter_sig_3\,
1639         datab => \vga_driver_unit|column_counter_sig_2\,
1640         cin0 => \vga_driver_unit|un2_column_counter_next_cout\(1),
1641         cin1 => \vga_driver_unit|un2_column_counter_next_cout[1]~COUT1_10\,
1642         devclrn => ww_devclrn,
1643         devpor => ww_devpor,
1644         combout => \vga_driver_unit|un2_column_counter_next_combout\(3),
1645         cout0 => \vga_driver_unit|un2_column_counter_next_cout\(3),
1646         cout1 => \vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12\);
1647
1648 \vga_driver_unit|un2_column_counter_next_5_\ : stratix_lcell
1649 -- Equation(s):
1650 -- \vga_driver_unit|un2_column_counter_next_combout\(5) = \vga_driver_unit|column_counter_sig_5\ $ (\vga_driver_unit|column_counter_sig_4\ & !\vga_driver_unit|un2_column_counter_next_cout\(3))
1651 -- \vga_driver_unit|un2_column_counter_next_cout\(5) = CARRY(\vga_driver_unit|column_counter_sig_5\ & \vga_driver_unit|column_counter_sig_4\ & !\vga_driver_unit|un2_column_counter_next_cout\(3))
1652 -- \vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14\ = CARRY(\vga_driver_unit|column_counter_sig_5\ & \vga_driver_unit|column_counter_sig_4\ & !\vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12\)
1653
1654 -- pragma translate_off
1655 GENERIC MAP (
1656         cin0_used => "true",
1657         cin1_used => "true",
1658         lut_mask => "a608",
1659         operation_mode => "arithmetic",
1660         output_mode => "comb_only",
1661         register_cascade_mode => "off",
1662         sum_lutc_input => "cin",
1663         synch_mode => "off")
1664 -- pragma translate_on
1665 PORT MAP (
1666         dataa => \vga_driver_unit|column_counter_sig_5\,
1667         datab => \vga_driver_unit|column_counter_sig_4\,
1668         cin0 => \vga_driver_unit|un2_column_counter_next_cout\(3),
1669         cin1 => \vga_driver_unit|un2_column_counter_next_cout[3]~COUT1_12\,
1670         devclrn => ww_devclrn,
1671         devpor => ww_devpor,
1672         combout => \vga_driver_unit|un2_column_counter_next_combout\(5),
1673         cout0 => \vga_driver_unit|un2_column_counter_next_cout\(5),
1674         cout1 => \vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14\);
1675
1676 \vga_driver_unit|column_counter_sig_5_\ : stratix_lcell
1677 -- Equation(s):
1678 -- \vga_driver_unit|column_counter_sig_5\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(5) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, )
1679
1680 -- pragma translate_off
1681 GENERIC MAP (
1682         lut_mask => "ff0f",
1683         operation_mode => "normal",
1684         output_mode => "reg_only",
1685         register_cascade_mode => "off",
1686         sum_lutc_input => "datac",
1687         synch_mode => "on")
1688 -- pragma translate_on
1689 PORT MAP (
1690         clk => \clk_pin~combout\,
1691         datac => \vga_driver_unit|un10_column_counter_siglto9\,
1692         datad => \vga_driver_unit|un2_column_counter_next_combout\(5),
1693         aclr => GND,
1694         sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\,
1695         devclrn => ww_devclrn,
1696         devpor => ww_devpor,
1697         regout => \vga_driver_unit|column_counter_sig_5\);
1698
1699 \vga_driver_unit|un2_column_counter_next_7_\ : stratix_lcell
1700 -- Equation(s):
1701 -- \vga_driver_unit|un2_column_counter_next_combout\(7) = \vga_driver_unit|column_counter_sig_7\ $ (\vga_driver_unit|column_counter_sig_6\ & \vga_driver_unit|un2_column_counter_next_cout\(5))
1702 -- \vga_driver_unit|un2_column_counter_next_cout\(7) = CARRY(!\vga_driver_unit|un2_column_counter_next_cout\(5) # !\vga_driver_unit|column_counter_sig_7\ # !\vga_driver_unit|column_counter_sig_6\)
1703 -- \vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16\ = CARRY(!\vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14\ # !\vga_driver_unit|column_counter_sig_7\ # !\vga_driver_unit|column_counter_sig_6\)
1704
1705 -- pragma translate_off
1706 GENERIC MAP (
1707         cin0_used => "true",
1708         cin1_used => "true",
1709         lut_mask => "6c7f",
1710         operation_mode => "arithmetic",
1711         output_mode => "comb_only",
1712         register_cascade_mode => "off",
1713         sum_lutc_input => "cin",
1714         synch_mode => "off")
1715 -- pragma translate_on
1716 PORT MAP (
1717         dataa => \vga_driver_unit|column_counter_sig_6\,
1718         datab => \vga_driver_unit|column_counter_sig_7\,
1719         cin0 => \vga_driver_unit|un2_column_counter_next_cout\(5),
1720         cin1 => \vga_driver_unit|un2_column_counter_next_cout[5]~COUT1_14\,
1721         devclrn => ww_devclrn,
1722         devpor => ww_devpor,
1723         combout => \vga_driver_unit|un2_column_counter_next_combout\(7),
1724         cout0 => \vga_driver_unit|un2_column_counter_next_cout\(7),
1725         cout1 => \vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16\);
1726
1727 \vga_driver_unit|column_counter_sig_7_\ : stratix_lcell
1728 -- Equation(s):
1729 -- \vga_driver_unit|column_counter_sig_7\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(7) & \vga_driver_unit|un10_column_counter_siglto9\ & \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, GLOBAL(\clk_pin~combout\), VCC, , , , , , )
1730
1731 -- pragma translate_off
1732 GENERIC MAP (
1733         lut_mask => "8080",
1734         operation_mode => "normal",
1735         output_mode => "reg_only",
1736         register_cascade_mode => "off",
1737         sum_lutc_input => "datac",
1738         synch_mode => "off")
1739 -- pragma translate_on
1740 PORT MAP (
1741         clk => \clk_pin~combout\,
1742         dataa => \vga_driver_unit|un2_column_counter_next_combout\(7),
1743         datab => \vga_driver_unit|un10_column_counter_siglto9\,
1744         datac => \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\,
1745         aclr => GND,
1746         devclrn => ww_devclrn,
1747         devpor => ww_devpor,
1748         regout => \vga_driver_unit|column_counter_sig_7\);
1749
1750 \vga_driver_unit|un2_column_counter_next_6_\ : stratix_lcell
1751 -- Equation(s):
1752 -- \vga_driver_unit|un2_column_counter_next_combout\(6) = \vga_driver_unit|column_counter_sig_6\ $ (\vga_driver_unit|un2_column_counter_next_cout\(4))
1753 -- \vga_driver_unit|un2_column_counter_next_cout\(6) = CARRY(!\vga_driver_unit|un2_column_counter_next_cout\(4) # !\vga_driver_unit|column_counter_sig_7\ # !\vga_driver_unit|column_counter_sig_6\)
1754 -- \vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24\ = CARRY(!\vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22\ # !\vga_driver_unit|column_counter_sig_7\ # !\vga_driver_unit|column_counter_sig_6\)
1755
1756 -- pragma translate_off
1757 GENERIC MAP (
1758         cin0_used => "true",
1759         cin1_used => "true",
1760         lut_mask => "5a7f",
1761         operation_mode => "arithmetic",
1762         output_mode => "comb_only",
1763         register_cascade_mode => "off",
1764         sum_lutc_input => "cin",
1765         synch_mode => "off")
1766 -- pragma translate_on
1767 PORT MAP (
1768         dataa => \vga_driver_unit|column_counter_sig_6\,
1769         datab => \vga_driver_unit|column_counter_sig_7\,
1770         cin0 => \vga_driver_unit|un2_column_counter_next_cout\(4),
1771         cin1 => \vga_driver_unit|un2_column_counter_next_cout[4]~COUT1_22\,
1772         devclrn => ww_devclrn,
1773         devpor => ww_devpor,
1774         combout => \vga_driver_unit|un2_column_counter_next_combout\(6),
1775         cout0 => \vga_driver_unit|un2_column_counter_next_cout\(6),
1776         cout1 => \vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24\);
1777
1778 \vga_driver_unit|column_counter_sig_6_\ : stratix_lcell
1779 -- Equation(s):
1780 -- \vga_driver_unit|column_counter_sig_6\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(6) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, )
1781
1782 -- pragma translate_off
1783 GENERIC MAP (
1784         lut_mask => "ff0f",
1785         operation_mode => "normal",
1786         output_mode => "reg_only",
1787         register_cascade_mode => "off",
1788         sum_lutc_input => "datac",
1789         synch_mode => "on")
1790 -- pragma translate_on
1791 PORT MAP (
1792         clk => \clk_pin~combout\,
1793         datac => \vga_driver_unit|un10_column_counter_siglto9\,
1794         datad => \vga_driver_unit|un2_column_counter_next_combout\(6),
1795         aclr => GND,
1796         sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\,
1797         devclrn => ww_devclrn,
1798         devpor => ww_devpor,
1799         regout => \vga_driver_unit|column_counter_sig_6\);
1800
1801 \vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_1\ : stratix_lcell
1802 -- Equation(s):
1803 -- \vga_driver_unit|un10_column_counter_siglt6_1\ = !\vga_driver_unit|column_counter_sig_5\ # !\vga_driver_unit|column_counter_sig_6\
1804
1805 -- pragma translate_off
1806 GENERIC MAP (
1807         lut_mask => "55ff",
1808         operation_mode => "normal",
1809         output_mode => "comb_only",
1810         register_cascade_mode => "off",
1811         sum_lutc_input => "datac",
1812         synch_mode => "off")
1813 -- pragma translate_on
1814 PORT MAP (
1815         dataa => \vga_driver_unit|column_counter_sig_6\,
1816         datad => \vga_driver_unit|column_counter_sig_5\,
1817         devclrn => ww_devclrn,
1818         devpor => ww_devpor,
1819         combout => \vga_driver_unit|un10_column_counter_siglt6_1\);
1820
1821 \vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6_2\ : stratix_lcell
1822 -- Equation(s):
1823 -- \vga_driver_unit|un10_column_counter_siglt6_2\ = !\vga_driver_unit|column_counter_sig_4\ # !\vga_driver_unit|column_counter_sig_2\ # !\vga_driver_unit|column_counter_sig_3\
1824
1825 -- pragma translate_off
1826 GENERIC MAP (
1827         lut_mask => "3fff",
1828         operation_mode => "normal",
1829         output_mode => "comb_only",
1830         register_cascade_mode => "off",
1831         sum_lutc_input => "datac",
1832         synch_mode => "off")
1833 -- pragma translate_on
1834 PORT MAP (
1835         datab => \vga_driver_unit|column_counter_sig_3\,
1836         datac => \vga_driver_unit|column_counter_sig_2\,
1837         datad => \vga_driver_unit|column_counter_sig_4\,
1838         devclrn => ww_devclrn,
1839         devpor => ww_devpor,
1840         combout => \vga_driver_unit|un10_column_counter_siglt6_2\);
1841
1842 \vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglt6\ : stratix_lcell
1843 -- Equation(s):
1844 -- \vga_driver_unit|un10_column_counter_siglt6\ = \vga_driver_unit|un10_column_counter_siglt6_1\ # \vga_driver_unit|un10_column_counter_siglt6_2\ # !\vga_driver_unit|column_counter_sig_1\ # !\vga_driver_unit|column_counter_sig_0\
1845
1846 -- pragma translate_off
1847 GENERIC MAP (
1848         lut_mask => "fff7",
1849         operation_mode => "normal",
1850         output_mode => "comb_only",
1851         register_cascade_mode => "off",
1852         sum_lutc_input => "datac",
1853         synch_mode => "off")
1854 -- pragma translate_on
1855 PORT MAP (
1856         dataa => \vga_driver_unit|column_counter_sig_0\,
1857         datab => \vga_driver_unit|column_counter_sig_1\,
1858         datac => \vga_driver_unit|un10_column_counter_siglt6_1\,
1859         datad => \vga_driver_unit|un10_column_counter_siglt6_2\,
1860         devclrn => ww_devclrn,
1861         devpor => ww_devpor,
1862         combout => \vga_driver_unit|un10_column_counter_siglt6\);
1863
1864 \vga_driver_unit|un2_column_counter_next_8_\ : stratix_lcell
1865 -- Equation(s):
1866 -- \vga_driver_unit|un2_column_counter_next_combout\(8) = \vga_driver_unit|un2_column_counter_next_cout\(6) $ !\vga_driver_unit|column_counter_sig_8\
1867
1868 -- pragma translate_off
1869 GENERIC MAP (
1870         cin0_used => "true",
1871         cin1_used => "true",
1872         lut_mask => "f00f",
1873         operation_mode => "normal",
1874         output_mode => "comb_only",
1875         register_cascade_mode => "off",
1876         sum_lutc_input => "cin",
1877         synch_mode => "off")
1878 -- pragma translate_on
1879 PORT MAP (
1880         datad => \vga_driver_unit|column_counter_sig_8\,
1881         cin0 => \vga_driver_unit|un2_column_counter_next_cout\(6),
1882         cin1 => \vga_driver_unit|un2_column_counter_next_cout[6]~COUT1_24\,
1883         devclrn => ww_devclrn,
1884         devpor => ww_devpor,
1885         combout => \vga_driver_unit|un2_column_counter_next_combout\(8));
1886
1887 \vga_driver_unit|column_counter_sig_8_\ : stratix_lcell
1888 -- Equation(s):
1889 -- \vga_driver_unit|column_counter_sig_8\ = DFFEAS(\vga_driver_unit|un10_column_counter_siglto9\ & \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\ & \vga_driver_unit|un2_column_counter_next_combout\(8), GLOBAL(\clk_pin~combout\), VCC, , , , , , )
1890
1891 -- pragma translate_off
1892 GENERIC MAP (
1893         lut_mask => "c000",
1894         operation_mode => "normal",
1895         output_mode => "reg_only",
1896         register_cascade_mode => "off",
1897         sum_lutc_input => "datac",
1898         synch_mode => "off")
1899 -- pragma translate_on
1900 PORT MAP (
1901         clk => \clk_pin~combout\,
1902         datab => \vga_driver_unit|un10_column_counter_siglto9\,
1903         datac => \vga_driver_unit|column_counter_next_0_sqmuxa_1_1\,
1904         datad => \vga_driver_unit|un2_column_counter_next_combout\(8),
1905         aclr => GND,
1906         devclrn => ww_devclrn,
1907         devpor => ww_devpor,
1908         regout => \vga_driver_unit|column_counter_sig_8\);
1909
1910 \vga_driver_unit|un2_column_counter_next_9_\ : stratix_lcell
1911 -- Equation(s):
1912 -- \vga_driver_unit|un2_column_counter_next_combout\(9) = \vga_driver_unit|column_counter_sig_9\ $ (!\vga_driver_unit|un2_column_counter_next_cout\(7) & \vga_driver_unit|column_counter_sig_8\)
1913
1914 -- pragma translate_off
1915 GENERIC MAP (
1916         cin0_used => "true",
1917         cin1_used => "true",
1918         lut_mask => "a5aa",
1919         operation_mode => "normal",
1920         output_mode => "comb_only",
1921         register_cascade_mode => "off",
1922         sum_lutc_input => "cin",
1923         synch_mode => "off")
1924 -- pragma translate_on
1925 PORT MAP (
1926         dataa => \vga_driver_unit|column_counter_sig_9\,
1927         datad => \vga_driver_unit|column_counter_sig_8\,
1928         cin0 => \vga_driver_unit|un2_column_counter_next_cout\(7),
1929         cin1 => \vga_driver_unit|un2_column_counter_next_cout[7]~COUT1_16\,
1930         devclrn => ww_devclrn,
1931         devpor => ww_devpor,
1932         combout => \vga_driver_unit|un2_column_counter_next_combout\(9));
1933
1934 \vga_driver_unit|column_counter_sig_9_\ : stratix_lcell
1935 -- Equation(s):
1936 -- \vga_driver_unit|column_counter_sig_9\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(9) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, )
1937
1938 -- pragma translate_off
1939 GENERIC MAP (
1940         lut_mask => "ff0f",
1941         operation_mode => "normal",
1942         output_mode => "reg_only",
1943         register_cascade_mode => "off",
1944         sum_lutc_input => "datac",
1945         synch_mode => "on")
1946 -- pragma translate_on
1947 PORT MAP (
1948         clk => \clk_pin~combout\,
1949         datac => \vga_driver_unit|un10_column_counter_siglto9\,
1950         datad => \vga_driver_unit|un2_column_counter_next_combout\(9),
1951         aclr => GND,
1952         sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\,
1953         devclrn => ww_devclrn,
1954         devpor => ww_devpor,
1955         regout => \vga_driver_unit|column_counter_sig_9\);
1956
1957 \vga_driver_unit|COLUMN_COUNT_next_un10_column_counter_siglto9\ : stratix_lcell
1958 -- Equation(s):
1959 -- \vga_driver_unit|un10_column_counter_siglto9\ = \vga_driver_unit|un10_column_counter_siglt6\ & !\vga_driver_unit|column_counter_sig_8\ & !\vga_driver_unit|column_counter_sig_7\ # !\vga_driver_unit|column_counter_sig_9\
1960
1961 -- pragma translate_off
1962 GENERIC MAP (
1963         lut_mask => "333b",
1964         operation_mode => "normal",
1965         output_mode => "comb_only",
1966         register_cascade_mode => "off",
1967         sum_lutc_input => "datac",
1968         synch_mode => "off")
1969 -- pragma translate_on
1970 PORT MAP (
1971         dataa => \vga_driver_unit|un10_column_counter_siglt6\,
1972         datab => \vga_driver_unit|column_counter_sig_9\,
1973         datac => \vga_driver_unit|column_counter_sig_8\,
1974         datad => \vga_driver_unit|column_counter_sig_7\,
1975         devclrn => ww_devclrn,
1976         devpor => ww_devpor,
1977         combout => \vga_driver_unit|un10_column_counter_siglto9\);
1978
1979 \vga_driver_unit|column_counter_sig_2_\ : stratix_lcell
1980 -- Equation(s):
1981 -- \vga_driver_unit|column_counter_sig_2\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(2) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, )
1982
1983 -- pragma translate_off
1984 GENERIC MAP (
1985         lut_mask => "ff55",
1986         operation_mode => "normal",
1987         output_mode => "reg_only",
1988         register_cascade_mode => "off",
1989         sum_lutc_input => "datac",
1990         synch_mode => "on")
1991 -- pragma translate_on
1992 PORT MAP (
1993         clk => \clk_pin~combout\,
1994         dataa => \vga_driver_unit|un10_column_counter_siglto9\,
1995         datad => \vga_driver_unit|un2_column_counter_next_combout\(2),
1996         aclr => GND,
1997         sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\,
1998         devclrn => ww_devclrn,
1999         devpor => ww_devpor,
2000         regout => \vga_driver_unit|column_counter_sig_2\);
2001
2002 \vga_driver_unit|column_counter_sig_3_\ : stratix_lcell
2003 -- Equation(s):
2004 -- \vga_driver_unit|column_counter_sig_3\ = DFFEAS(\vga_driver_unit|un2_column_counter_next_combout\(3) # !\vga_driver_unit|un10_column_counter_siglto9\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|column_counter_next_0_sqmuxa_1_1\, )
2005
2006 -- pragma translate_off
2007 GENERIC MAP (
2008         lut_mask => "f0ff",
2009         operation_mode => "normal",
2010         output_mode => "reg_only",
2011         register_cascade_mode => "off",
2012         sum_lutc_input => "datac",
2013         synch_mode => "on")
2014 -- pragma translate_on
2015 PORT MAP (
2016         clk => \clk_pin~combout\,
2017         datac => \vga_driver_unit|un2_column_counter_next_combout\(3),
2018         datad => \vga_driver_unit|un10_column_counter_siglto9\,
2019         aclr => GND,
2020         sclr => \vga_driver_unit|ALT_INV_column_counter_next_0_sqmuxa_1_1\,
2021         devclrn => ww_devclrn,
2022         devpor => ww_devpor,
2023         regout => \vga_driver_unit|column_counter_sig_3\);
2024
2025 \vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto3\ : stratix_lcell
2026 -- Equation(s):
2027 -- \vga_control_unit|un5_v_enablelto3\ = \vga_driver_unit|column_counter_sig_3\ & (\vga_driver_unit|column_counter_sig_2\ # \vga_driver_unit|column_counter_sig_0\ # \vga_driver_unit|column_counter_sig_1\)
2028
2029 -- pragma translate_off
2030 GENERIC MAP (
2031         lut_mask => "aaa8",
2032         operation_mode => "normal",
2033         output_mode => "comb_only",
2034         register_cascade_mode => "off",
2035         sum_lutc_input => "datac",
2036         synch_mode => "off")
2037 -- pragma translate_on
2038 PORT MAP (
2039         dataa => \vga_driver_unit|column_counter_sig_3\,
2040         datab => \vga_driver_unit|column_counter_sig_2\,
2041         datac => \vga_driver_unit|column_counter_sig_0\,
2042         datad => \vga_driver_unit|column_counter_sig_1\,
2043         devclrn => ww_devclrn,
2044         devpor => ww_devpor,
2045         combout => \vga_control_unit|un5_v_enablelto3\);
2046
2047 \vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto5_0\ : stratix_lcell
2048 -- Equation(s):
2049 -- \vga_control_unit|un5_v_enablelto5_0\ = \vga_driver_unit|column_counter_sig_4\ # \vga_driver_unit|column_counter_sig_5\
2050
2051 -- pragma translate_off
2052 GENERIC MAP (
2053         lut_mask => "fff0",
2054         operation_mode => "normal",
2055         output_mode => "comb_only",
2056         register_cascade_mode => "off",
2057         sum_lutc_input => "datac",
2058         synch_mode => "off")
2059 -- pragma translate_on
2060 PORT MAP (
2061         datac => \vga_driver_unit|column_counter_sig_4\,
2062         datad => \vga_driver_unit|column_counter_sig_5\,
2063         devclrn => ww_devclrn,
2064         devpor => ww_devpor,
2065         combout => \vga_control_unit|un5_v_enablelto5_0\);
2066
2067 \vga_control_unit|DRAW_SQUARE_next_un5_v_enablelto7\ : stratix_lcell
2068 -- Equation(s):
2069 -- \vga_control_unit|un5_v_enablelto7\ = \vga_driver_unit|column_counter_sig_6\ & \vga_driver_unit|column_counter_sig_7\ & (\vga_control_unit|un5_v_enablelto3\ # \vga_control_unit|un5_v_enablelto5_0\)
2070
2071 -- pragma translate_off
2072 GENERIC MAP (
2073         lut_mask => "e000",
2074         operation_mode => "normal",
2075         output_mode => "comb_only",
2076         register_cascade_mode => "off",
2077         sum_lutc_input => "datac",
2078         synch_mode => "off")
2079 -- pragma translate_on
2080 PORT MAP (
2081         dataa => \vga_control_unit|un5_v_enablelto3\,
2082         datab => \vga_control_unit|un5_v_enablelto5_0\,
2083         datac => \vga_driver_unit|column_counter_sig_6\,
2084         datad => \vga_driver_unit|column_counter_sig_7\,
2085         devclrn => ww_devclrn,
2086         devpor => ww_devpor,
2087         combout => \vga_control_unit|un5_v_enablelto7\);
2088
2089 \vga_driver_unit|un1_line_counter_sig_1_\ : stratix_lcell
2090 -- Equation(s):
2091 -- \vga_driver_unit|un1_line_counter_sig_combout\(1) = \vga_driver_unit|d_set_hsync_counter\ $ \vga_driver_unit|line_counter_sig_0\
2092 -- \vga_driver_unit|un1_line_counter_sig_cout\(1) = CARRY(\vga_driver_unit|d_set_hsync_counter\ & \vga_driver_unit|line_counter_sig_0\)
2093 -- \vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9\ = CARRY(\vga_driver_unit|d_set_hsync_counter\ & \vga_driver_unit|line_counter_sig_0\)
2094
2095 -- pragma translate_off
2096 GENERIC MAP (
2097         lut_mask => "6688",
2098         operation_mode => "arithmetic",
2099         output_mode => "comb_only",
2100         register_cascade_mode => "off",
2101         sum_lutc_input => "datac",
2102         synch_mode => "off")
2103 -- pragma translate_on
2104 PORT MAP (
2105         dataa => \vga_driver_unit|d_set_hsync_counter\,
2106         datab => \vga_driver_unit|line_counter_sig_0\,
2107         devclrn => ww_devclrn,
2108         devpor => ww_devpor,
2109         combout => \vga_driver_unit|un1_line_counter_sig_combout\(1),
2110         cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(1),
2111         cout1 => \vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9\);
2112
2113 \vga_driver_unit|vsync_counter_0_\ : stratix_lcell
2114 -- Equation(s):
2115 -- \vga_driver_unit|vsync_counter_0\ = DFFEAS(\vga_driver_unit|d_set_hsync_counter\ $ \vga_driver_unit|vsync_counter_0\, GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\,
2116 -- !\vga_driver_unit|un9_vsync_counterlt9\)
2117 -- \vga_driver_unit|vsync_counter_cout\(0) = CARRY(\vga_driver_unit|d_set_hsync_counter\ & \vga_driver_unit|vsync_counter_0\)
2118 -- \vga_driver_unit|vsync_counter_cout[0]~COUT1_10\ = CARRY(\vga_driver_unit|d_set_hsync_counter\ & \vga_driver_unit|vsync_counter_0\)
2119
2120 -- pragma translate_off
2121 GENERIC MAP (
2122         lut_mask => "6688",
2123         operation_mode => "arithmetic",
2124         output_mode => "reg_only",
2125         register_cascade_mode => "off",
2126         sum_lutc_input => "datac",
2127         synch_mode => "on")
2128 -- pragma translate_on
2129 PORT MAP (
2130         clk => \clk_pin~combout\,
2131         dataa => \vga_driver_unit|d_set_hsync_counter\,
2132         datab => \vga_driver_unit|vsync_counter_0\,
2133         datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
2134         aclr => GND,
2135         sclr => \vga_driver_unit|ALT_INV_G_16_i\,
2136         sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
2137         devclrn => ww_devclrn,
2138         devpor => ww_devpor,
2139         regout => \vga_driver_unit|vsync_counter_0\,
2140         cout0 => \vga_driver_unit|vsync_counter_cout\(0),
2141         cout1 => \vga_driver_unit|vsync_counter_cout[0]~COUT1_10\);
2142
2143 \vga_driver_unit|vsync_counter_1_\ : stratix_lcell
2144 -- Equation(s):
2145 -- \vga_driver_unit|vsync_counter_1\ = DFFEAS(\vga_driver_unit|vsync_counter_1\ $ \vga_driver_unit|vsync_counter_cout\(0), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\,
2146 -- !\vga_driver_unit|un9_vsync_counterlt9\)
2147 -- \vga_driver_unit|vsync_counter_cout\(1) = CARRY(!\vga_driver_unit|vsync_counter_cout\(0) # !\vga_driver_unit|vsync_counter_1\)
2148 -- \vga_driver_unit|vsync_counter_cout[1]~COUT1_12\ = CARRY(!\vga_driver_unit|vsync_counter_cout[0]~COUT1_10\ # !\vga_driver_unit|vsync_counter_1\)
2149
2150 -- pragma translate_off
2151 GENERIC MAP (
2152         cin0_used => "true",
2153         cin1_used => "true",
2154         lut_mask => "3c3f",
2155         operation_mode => "arithmetic",
2156         output_mode => "reg_only",
2157         register_cascade_mode => "off",
2158         sum_lutc_input => "cin",
2159         synch_mode => "on")
2160 -- pragma translate_on
2161 PORT MAP (
2162         clk => \clk_pin~combout\,
2163         datab => \vga_driver_unit|vsync_counter_1\,
2164         datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
2165         aclr => GND,
2166         sclr => \vga_driver_unit|ALT_INV_G_16_i\,
2167         sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
2168         cin0 => \vga_driver_unit|vsync_counter_cout\(0),
2169         cin1 => \vga_driver_unit|vsync_counter_cout[0]~COUT1_10\,
2170         devclrn => ww_devclrn,
2171         devpor => ww_devpor,
2172         regout => \vga_driver_unit|vsync_counter_1\,
2173         cout0 => \vga_driver_unit|vsync_counter_cout\(1),
2174         cout1 => \vga_driver_unit|vsync_counter_cout[1]~COUT1_12\);
2175
2176 \vga_driver_unit|vsync_counter_2_\ : stratix_lcell
2177 -- Equation(s):
2178 -- \vga_driver_unit|vsync_counter_2\ = DFFEAS(\vga_driver_unit|vsync_counter_2\ $ (!\vga_driver_unit|vsync_counter_cout\(1)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\,
2179 -- !\vga_driver_unit|un9_vsync_counterlt9\)
2180 -- \vga_driver_unit|vsync_counter_cout\(2) = CARRY(\vga_driver_unit|vsync_counter_2\ & (!\vga_driver_unit|vsync_counter_cout\(1)))
2181 -- \vga_driver_unit|vsync_counter_cout[2]~COUT1_14\ = CARRY(\vga_driver_unit|vsync_counter_2\ & (!\vga_driver_unit|vsync_counter_cout[1]~COUT1_12\))
2182
2183 -- pragma translate_off
2184 GENERIC MAP (
2185         cin0_used => "true",
2186         cin1_used => "true",
2187         lut_mask => "a50a",
2188         operation_mode => "arithmetic",
2189         output_mode => "reg_only",
2190         register_cascade_mode => "off",
2191         sum_lutc_input => "cin",
2192         synch_mode => "on")
2193 -- pragma translate_on
2194 PORT MAP (
2195         clk => \clk_pin~combout\,
2196         dataa => \vga_driver_unit|vsync_counter_2\,
2197         datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
2198         aclr => GND,
2199         sclr => \vga_driver_unit|ALT_INV_G_16_i\,
2200         sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
2201         cin0 => \vga_driver_unit|vsync_counter_cout\(1),
2202         cin1 => \vga_driver_unit|vsync_counter_cout[1]~COUT1_12\,
2203         devclrn => ww_devclrn,
2204         devpor => ww_devpor,
2205         regout => \vga_driver_unit|vsync_counter_2\,
2206         cout0 => \vga_driver_unit|vsync_counter_cout\(2),
2207         cout1 => \vga_driver_unit|vsync_counter_cout[2]~COUT1_14\);
2208
2209 \vga_driver_unit|vsync_counter_3_\ : stratix_lcell
2210 -- Equation(s):
2211 -- \vga_driver_unit|vsync_counter_3\ = DFFEAS(\vga_driver_unit|vsync_counter_3\ $ (\vga_driver_unit|vsync_counter_cout\(2)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\,
2212 -- !\vga_driver_unit|un9_vsync_counterlt9\)
2213 -- \vga_driver_unit|vsync_counter_cout\(3) = CARRY(!\vga_driver_unit|vsync_counter_cout\(2) # !\vga_driver_unit|vsync_counter_3\)
2214 -- \vga_driver_unit|vsync_counter_cout[3]~COUT1_16\ = CARRY(!\vga_driver_unit|vsync_counter_cout[2]~COUT1_14\ # !\vga_driver_unit|vsync_counter_3\)
2215
2216 -- pragma translate_off
2217 GENERIC MAP (
2218         cin0_used => "true",
2219         cin1_used => "true",
2220         lut_mask => "5a5f",
2221         operation_mode => "arithmetic",
2222         output_mode => "reg_only",
2223         register_cascade_mode => "off",
2224         sum_lutc_input => "cin",
2225         synch_mode => "on")
2226 -- pragma translate_on
2227 PORT MAP (
2228         clk => \clk_pin~combout\,
2229         dataa => \vga_driver_unit|vsync_counter_3\,
2230         datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
2231         aclr => GND,
2232         sclr => \vga_driver_unit|ALT_INV_G_16_i\,
2233         sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
2234         cin0 => \vga_driver_unit|vsync_counter_cout\(2),
2235         cin1 => \vga_driver_unit|vsync_counter_cout[2]~COUT1_14\,
2236         devclrn => ww_devclrn,
2237         devpor => ww_devpor,
2238         regout => \vga_driver_unit|vsync_counter_3\,
2239         cout0 => \vga_driver_unit|vsync_counter_cout\(3),
2240         cout1 => \vga_driver_unit|vsync_counter_cout[3]~COUT1_16\);
2241
2242 \vga_driver_unit|vsync_counter_4_\ : stratix_lcell
2243 -- Equation(s):
2244 -- \vga_driver_unit|vsync_counter_4\ = DFFEAS(\vga_driver_unit|vsync_counter_4\ $ (!\vga_driver_unit|vsync_counter_cout\(3)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\,
2245 -- !\vga_driver_unit|un9_vsync_counterlt9\)
2246 -- \vga_driver_unit|vsync_counter_cout\(4) = CARRY(\vga_driver_unit|vsync_counter_4\ & (!\vga_driver_unit|vsync_counter_cout[3]~COUT1_16\))
2247
2248 -- pragma translate_off
2249 GENERIC MAP (
2250         cin0_used => "true",
2251         cin1_used => "true",
2252         lut_mask => "a50a",
2253         operation_mode => "arithmetic",
2254         output_mode => "reg_only",
2255         register_cascade_mode => "off",
2256         sum_lutc_input => "cin",
2257         synch_mode => "on")
2258 -- pragma translate_on
2259 PORT MAP (
2260         clk => \clk_pin~combout\,
2261         dataa => \vga_driver_unit|vsync_counter_4\,
2262         datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
2263         aclr => GND,
2264         sclr => \vga_driver_unit|ALT_INV_G_16_i\,
2265         sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
2266         cin0 => \vga_driver_unit|vsync_counter_cout\(3),
2267         cin1 => \vga_driver_unit|vsync_counter_cout[3]~COUT1_16\,
2268         devclrn => ww_devclrn,
2269         devpor => ww_devpor,
2270         regout => \vga_driver_unit|vsync_counter_4\,
2271         cout => \vga_driver_unit|vsync_counter_cout\(4));
2272
2273 \vga_driver_unit|vsync_counter_5_\ : stratix_lcell
2274 -- Equation(s):
2275 -- \vga_driver_unit|vsync_counter_5\ = DFFEAS(\vga_driver_unit|vsync_counter_5\ $ \vga_driver_unit|vsync_counter_cout\(4), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\,
2276 -- !\vga_driver_unit|un9_vsync_counterlt9\)
2277 -- \vga_driver_unit|vsync_counter_cout\(5) = CARRY(!\vga_driver_unit|vsync_counter_cout\(4) # !\vga_driver_unit|vsync_counter_5\)
2278 -- \vga_driver_unit|vsync_counter_cout[5]~COUT1_18\ = CARRY(!\vga_driver_unit|vsync_counter_cout\(4) # !\vga_driver_unit|vsync_counter_5\)
2279
2280 -- pragma translate_off
2281 GENERIC MAP (
2282         cin_used => "true",
2283         lut_mask => "3c3f",
2284         operation_mode => "arithmetic",
2285         output_mode => "reg_only",
2286         register_cascade_mode => "off",
2287         sum_lutc_input => "cin",
2288         synch_mode => "on")
2289 -- pragma translate_on
2290 PORT MAP (
2291         clk => \clk_pin~combout\,
2292         datab => \vga_driver_unit|vsync_counter_5\,
2293         datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
2294         aclr => GND,
2295         sclr => \vga_driver_unit|ALT_INV_G_16_i\,
2296         sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
2297         cin => \vga_driver_unit|vsync_counter_cout\(4),
2298         devclrn => ww_devclrn,
2299         devpor => ww_devpor,
2300         regout => \vga_driver_unit|vsync_counter_5\,
2301         cout0 => \vga_driver_unit|vsync_counter_cout\(5),
2302         cout1 => \vga_driver_unit|vsync_counter_cout[5]~COUT1_18\);
2303
2304 \vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_6\ : stratix_lcell
2305 -- Equation(s):
2306 -- \vga_driver_unit|un9_vsync_counterlt9_6\ = !\vga_driver_unit|vsync_counter_0\ # !\vga_driver_unit|vsync_counter_3\ # !\vga_driver_unit|vsync_counter_1\ # !\vga_driver_unit|vsync_counter_2\
2307
2308 -- pragma translate_off
2309 GENERIC MAP (
2310         lut_mask => "7fff",
2311         operation_mode => "normal",
2312         output_mode => "comb_only",
2313         register_cascade_mode => "off",
2314         sum_lutc_input => "datac",
2315         synch_mode => "off")
2316 -- pragma translate_on
2317 PORT MAP (
2318         dataa => \vga_driver_unit|vsync_counter_2\,
2319         datab => \vga_driver_unit|vsync_counter_1\,
2320         datac => \vga_driver_unit|vsync_counter_3\,
2321         datad => \vga_driver_unit|vsync_counter_0\,
2322         devclrn => ww_devclrn,
2323         devpor => ww_devpor,
2324         combout => \vga_driver_unit|un9_vsync_counterlt9_6\);
2325
2326 \vga_driver_unit|vsync_counter_6_\ : stratix_lcell
2327 -- Equation(s):
2328 -- \vga_driver_unit|vsync_counter_6\ = DFFEAS(\vga_driver_unit|vsync_counter_6\ $ !(!\vga_driver_unit|vsync_counter_cout\(4) & \vga_driver_unit|vsync_counter_cout\(5)) # (\vga_driver_unit|vsync_counter_cout\(4) &
2329 -- \vga_driver_unit|vsync_counter_cout[5]~COUT1_18\), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, !\vga_driver_unit|un9_vsync_counterlt9\)
2330 -- \vga_driver_unit|vsync_counter_cout\(6) = CARRY(\vga_driver_unit|vsync_counter_6\ & !\vga_driver_unit|vsync_counter_cout\(5))
2331 -- \vga_driver_unit|vsync_counter_cout[6]~COUT1_20\ = CARRY(\vga_driver_unit|vsync_counter_6\ & !\vga_driver_unit|vsync_counter_cout[5]~COUT1_18\)
2332
2333 -- pragma translate_off
2334 GENERIC MAP (
2335         cin0_used => "true",
2336         cin1_used => "true",
2337         cin_used => "true",
2338         lut_mask => "c30c",
2339         operation_mode => "arithmetic",
2340         output_mode => "reg_only",
2341         register_cascade_mode => "off",
2342         sum_lutc_input => "cin",
2343         synch_mode => "on")
2344 -- pragma translate_on
2345 PORT MAP (
2346         clk => \clk_pin~combout\,
2347         datab => \vga_driver_unit|vsync_counter_6\,
2348         datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
2349         aclr => GND,
2350         sclr => \vga_driver_unit|ALT_INV_G_16_i\,
2351         sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
2352         cin => \vga_driver_unit|vsync_counter_cout\(4),
2353         cin0 => \vga_driver_unit|vsync_counter_cout\(5),
2354         cin1 => \vga_driver_unit|vsync_counter_cout[5]~COUT1_18\,
2355         devclrn => ww_devclrn,
2356         devpor => ww_devpor,
2357         regout => \vga_driver_unit|vsync_counter_6\,
2358         cout0 => \vga_driver_unit|vsync_counter_cout\(6),
2359         cout1 => \vga_driver_unit|vsync_counter_cout[6]~COUT1_20\);
2360
2361 \vga_driver_unit|vsync_counter_7_\ : stratix_lcell
2362 -- Equation(s):
2363 -- \vga_driver_unit|vsync_counter_7\ = DFFEAS(\vga_driver_unit|vsync_counter_7\ $ ((!\vga_driver_unit|vsync_counter_cout\(4) & \vga_driver_unit|vsync_counter_cout\(6)) # (\vga_driver_unit|vsync_counter_cout\(4) &
2364 -- \vga_driver_unit|vsync_counter_cout[6]~COUT1_20\)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, !\vga_driver_unit|un9_vsync_counterlt9\)
2365 -- \vga_driver_unit|vsync_counter_cout\(7) = CARRY(!\vga_driver_unit|vsync_counter_cout\(6) # !\vga_driver_unit|vsync_counter_7\)
2366 -- \vga_driver_unit|vsync_counter_cout[7]~COUT1_22\ = CARRY(!\vga_driver_unit|vsync_counter_cout[6]~COUT1_20\ # !\vga_driver_unit|vsync_counter_7\)
2367
2368 -- pragma translate_off
2369 GENERIC MAP (
2370         cin0_used => "true",
2371         cin1_used => "true",
2372         cin_used => "true",
2373         lut_mask => "5a5f",
2374         operation_mode => "arithmetic",
2375         output_mode => "reg_only",
2376         register_cascade_mode => "off",
2377         sum_lutc_input => "cin",
2378         synch_mode => "on")
2379 -- pragma translate_on
2380 PORT MAP (
2381         clk => \clk_pin~combout\,
2382         dataa => \vga_driver_unit|vsync_counter_7\,
2383         datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
2384         aclr => GND,
2385         sclr => \vga_driver_unit|ALT_INV_G_16_i\,
2386         sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
2387         cin => \vga_driver_unit|vsync_counter_cout\(4),
2388         cin0 => \vga_driver_unit|vsync_counter_cout\(6),
2389         cin1 => \vga_driver_unit|vsync_counter_cout[6]~COUT1_20\,
2390         devclrn => ww_devclrn,
2391         devpor => ww_devpor,
2392         regout => \vga_driver_unit|vsync_counter_7\,
2393         cout0 => \vga_driver_unit|vsync_counter_cout\(7),
2394         cout1 => \vga_driver_unit|vsync_counter_cout[7]~COUT1_22\);
2395
2396 \vga_driver_unit|vsync_counter_8_\ : stratix_lcell
2397 -- Equation(s):
2398 -- \vga_driver_unit|vsync_counter_8\ = DFFEAS(\vga_driver_unit|vsync_counter_8\ $ (!(!\vga_driver_unit|vsync_counter_cout\(4) & \vga_driver_unit|vsync_counter_cout\(7)) # (\vga_driver_unit|vsync_counter_cout\(4) &
2399 -- \vga_driver_unit|vsync_counter_cout[7]~COUT1_22\)), GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, !\vga_driver_unit|un9_vsync_counterlt9\)
2400 -- \vga_driver_unit|vsync_counter_cout\(8) = CARRY(\vga_driver_unit|vsync_counter_8\ & (!\vga_driver_unit|vsync_counter_cout\(7)))
2401 -- \vga_driver_unit|vsync_counter_cout[8]~COUT1_24\ = CARRY(\vga_driver_unit|vsync_counter_8\ & (!\vga_driver_unit|vsync_counter_cout[7]~COUT1_22\))
2402
2403 -- pragma translate_off
2404 GENERIC MAP (
2405         cin0_used => "true",
2406         cin1_used => "true",
2407         cin_used => "true",
2408         lut_mask => "a50a",
2409         operation_mode => "arithmetic",
2410         output_mode => "reg_only",
2411         register_cascade_mode => "off",
2412         sum_lutc_input => "cin",
2413         synch_mode => "on")
2414 -- pragma translate_on
2415 PORT MAP (
2416         clk => \clk_pin~combout\,
2417         dataa => \vga_driver_unit|vsync_counter_8\,
2418         datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
2419         aclr => GND,
2420         sclr => \vga_driver_unit|ALT_INV_G_16_i\,
2421         sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
2422         cin => \vga_driver_unit|vsync_counter_cout\(4),
2423         cin0 => \vga_driver_unit|vsync_counter_cout\(7),
2424         cin1 => \vga_driver_unit|vsync_counter_cout[7]~COUT1_22\,
2425         devclrn => ww_devclrn,
2426         devpor => ww_devpor,
2427         regout => \vga_driver_unit|vsync_counter_8\,
2428         cout0 => \vga_driver_unit|vsync_counter_cout\(8),
2429         cout1 => \vga_driver_unit|vsync_counter_cout[8]~COUT1_24\);
2430
2431 \vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9_5\ : stratix_lcell
2432 -- Equation(s):
2433 -- \vga_driver_unit|un9_vsync_counterlt9_5\ = !\vga_driver_unit|vsync_counter_6\ # !\vga_driver_unit|vsync_counter_7\ # !\vga_driver_unit|vsync_counter_8\ # !\vga_driver_unit|vsync_counter_9\
2434
2435 -- pragma translate_off
2436 GENERIC MAP (
2437         lut_mask => "7fff",
2438         operation_mode => "normal",
2439         output_mode => "comb_only",
2440         register_cascade_mode => "off",
2441         sum_lutc_input => "datac",
2442         synch_mode => "off")
2443 -- pragma translate_on
2444 PORT MAP (
2445         dataa => \vga_driver_unit|vsync_counter_9\,
2446         datab => \vga_driver_unit|vsync_counter_8\,
2447         datac => \vga_driver_unit|vsync_counter_7\,
2448         datad => \vga_driver_unit|vsync_counter_6\,
2449         devclrn => ww_devclrn,
2450         devpor => ww_devpor,
2451         combout => \vga_driver_unit|un9_vsync_counterlt9_5\);
2452
2453 \vga_driver_unit|VSYNC_COUNT_next_un9_vsync_counterlt9\ : stratix_lcell
2454 -- Equation(s):
2455 -- \vga_driver_unit|un9_vsync_counterlt9\ = \vga_driver_unit|un9_vsync_counterlt9_6\ # \vga_driver_unit|un9_vsync_counterlt9_5\ # !\vga_driver_unit|vsync_counter_4\ # !\vga_driver_unit|vsync_counter_5\
2456
2457 -- pragma translate_off
2458 GENERIC MAP (
2459         lut_mask => "ffdf",
2460         operation_mode => "normal",
2461         output_mode => "comb_only",
2462         register_cascade_mode => "off",
2463         sum_lutc_input => "datac",
2464         synch_mode => "off")
2465 -- pragma translate_on
2466 PORT MAP (
2467         dataa => \vga_driver_unit|vsync_counter_5\,
2468         datab => \vga_driver_unit|un9_vsync_counterlt9_6\,
2469         datac => \vga_driver_unit|vsync_counter_4\,
2470         datad => \vga_driver_unit|un9_vsync_counterlt9_5\,
2471         devclrn => ww_devclrn,
2472         devpor => ww_devpor,
2473         combout => \vga_driver_unit|un9_vsync_counterlt9\);
2474
2475 \vga_driver_unit|G_16\ : stratix_lcell
2476 -- Equation(s):
2477 -- \vga_driver_unit|G_16_i\ = !\vga_driver_unit|un6_dly_counter_0_x\ & !\vga_driver_unit|vsync_state_0\ & !\vga_driver_unit|vsync_state_6\ # !\vga_driver_unit|un9_vsync_counterlt9\
2478
2479 -- pragma translate_off
2480 GENERIC MAP (
2481         lut_mask => "5557",
2482         operation_mode => "normal",
2483         output_mode => "comb_only",
2484         register_cascade_mode => "off",
2485         sum_lutc_input => "datac",
2486         synch_mode => "off")
2487 -- pragma translate_on
2488 PORT MAP (
2489         dataa => \vga_driver_unit|un9_vsync_counterlt9\,
2490         datab => \vga_driver_unit|un6_dly_counter_0_x\,
2491         datac => \vga_driver_unit|vsync_state_0\,
2492         datad => \vga_driver_unit|vsync_state_6\,
2493         devclrn => ww_devclrn,
2494         devpor => ww_devpor,
2495         combout => \vga_driver_unit|G_16_i\);
2496
2497 \vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_7\ : stratix_lcell
2498 -- Equation(s):
2499 -- \vga_driver_unit|un12_vsync_counter_7\ = !\vga_driver_unit|vsync_counter_1\ & !\vga_driver_unit|vsync_counter_2\ & !\vga_driver_unit|vsync_counter_4\ & !\vga_driver_unit|vsync_counter_3\
2500
2501 -- pragma translate_off
2502 GENERIC MAP (
2503         lut_mask => "0001",
2504         operation_mode => "normal",
2505         output_mode => "comb_only",
2506         register_cascade_mode => "off",
2507         sum_lutc_input => "datac",
2508         synch_mode => "off")
2509 -- pragma translate_on
2510 PORT MAP (
2511         dataa => \vga_driver_unit|vsync_counter_1\,
2512         datab => \vga_driver_unit|vsync_counter_2\,
2513         datac => \vga_driver_unit|vsync_counter_4\,
2514         datad => \vga_driver_unit|vsync_counter_3\,
2515         devclrn => ww_devclrn,
2516         devpor => ww_devpor,
2517         combout => \vga_driver_unit|un12_vsync_counter_7\);
2518
2519 \vga_driver_unit|VSYNC_FSM_next_un12_vsync_counter_6\ : stratix_lcell
2520 -- Equation(s):
2521 -- \vga_driver_unit|un12_vsync_counter_6\ = !\vga_driver_unit|vsync_counter_7\ & !\vga_driver_unit|vsync_counter_8\ & !\vga_driver_unit|vsync_counter_6\ & !\vga_driver_unit|vsync_counter_5\
2522
2523 -- pragma translate_off
2524 GENERIC MAP (
2525         lut_mask => "0001",
2526         operation_mode => "normal",
2527         output_mode => "comb_only",
2528         register_cascade_mode => "off",
2529         sum_lutc_input => "datac",
2530         synch_mode => "off")
2531 -- pragma translate_on
2532 PORT MAP (
2533         dataa => \vga_driver_unit|vsync_counter_7\,
2534         datab => \vga_driver_unit|vsync_counter_8\,
2535         datac => \vga_driver_unit|vsync_counter_6\,
2536         datad => \vga_driver_unit|vsync_counter_5\,
2537         devclrn => ww_devclrn,
2538         devpor => ww_devpor,
2539         combout => \vga_driver_unit|un12_vsync_counter_6\);
2540
2541 \vga_driver_unit|VSYNC_FSM_next_un14_vsync_counter_8\ : stratix_lcell
2542 -- Equation(s):
2543 -- \vga_driver_unit|un14_vsync_counter_8\ = \vga_driver_unit|un12_vsync_counter_7\ & (\vga_driver_unit|un12_vsync_counter_6\)
2544
2545 -- pragma translate_off
2546 GENERIC MAP (
2547         lut_mask => "cc00",
2548         operation_mode => "normal",
2549         output_mode => "comb_only",
2550         register_cascade_mode => "off",
2551         sum_lutc_input => "datac",
2552         synch_mode => "off")
2553 -- pragma translate_on
2554 PORT MAP (
2555         datab => \vga_driver_unit|un12_vsync_counter_7\,
2556         datad => \vga_driver_unit|un12_vsync_counter_6\,
2557         devclrn => ww_devclrn,
2558         devpor => ww_devpor,
2559         combout => \vga_driver_unit|un14_vsync_counter_8\);
2560
2561 \vga_driver_unit|vsync_state_3_\ : stratix_lcell
2562 -- Equation(s):
2563 -- \vga_driver_unit|vsync_state_next_1_sqmuxa_3\ = C1_vsync_state_3 & (!\vga_driver_unit|vsync_counter_9\ # !\vga_driver_unit|vsync_counter_0\ # !\vga_driver_unit|un14_vsync_counter_8\)
2564 -- \vga_driver_unit|vsync_state_3\ = DFFEAS(\vga_driver_unit|vsync_state_next_1_sqmuxa_3\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|vsync_state_next_2_sqmuxa\, \vga_driver_unit|vsync_state_1\, , \vga_driver_unit|un6_dly_counter_0_x\, VCC)
2565
2566 -- pragma translate_off
2567 GENERIC MAP (
2568         lut_mask => "70f0",
2569         operation_mode => "normal",
2570         output_mode => "reg_and_comb",
2571         register_cascade_mode => "off",
2572         sum_lutc_input => "qfbk",
2573         synch_mode => "on")
2574 -- pragma translate_on
2575 PORT MAP (
2576         clk => \clk_pin~combout\,
2577         dataa => \vga_driver_unit|un14_vsync_counter_8\,
2578         datab => \vga_driver_unit|vsync_counter_0\,
2579         datac => \vga_driver_unit|vsync_state_1\,
2580         datad => \vga_driver_unit|vsync_counter_9\,
2581         aclr => GND,
2582         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
2583         sload => VCC,
2584         ena => \vga_driver_unit|vsync_state_next_2_sqmuxa\,
2585         devclrn => ww_devclrn,
2586         devpor => ww_devpor,
2587         combout => \vga_driver_unit|vsync_state_next_1_sqmuxa_3\,
2588         regout => \vga_driver_unit|vsync_state_3\);
2589
2590 \vga_driver_unit|vsync_state_5_\ : stratix_lcell
2591 -- Equation(s):
2592 -- \vga_driver_unit|vsync_state_5\ = DFFEAS(\vga_driver_unit|vsync_state_6\ # \vga_driver_unit|vsync_state_0\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|vsync_state_next_2_sqmuxa\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
2593
2594 -- pragma translate_off
2595 GENERIC MAP (
2596         lut_mask => "fcfc",
2597         operation_mode => "normal",
2598         output_mode => "reg_only",
2599         register_cascade_mode => "off",
2600         sum_lutc_input => "datac",
2601         synch_mode => "on")
2602 -- pragma translate_on
2603 PORT MAP (
2604         clk => \clk_pin~combout\,
2605         datab => \vga_driver_unit|vsync_state_6\,
2606         datac => \vga_driver_unit|vsync_state_0\,
2607         aclr => GND,
2608         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
2609         ena => \vga_driver_unit|vsync_state_next_2_sqmuxa\,
2610         devclrn => ww_devclrn,
2611         devpor => ww_devpor,
2612         regout => \vga_driver_unit|vsync_state_5\);
2613
2614 \vga_driver_unit|vsync_state_next_1_sqmuxa_1_cZ\ : stratix_lcell
2615 -- Equation(s):
2616 -- \vga_driver_unit|vsync_state_next_1_sqmuxa_1\ = \vga_driver_unit|vsync_state_5\ & (\vga_driver_unit|vsync_counter_9\ # !\vga_driver_unit|un14_vsync_counter_8\ # !\vga_driver_unit|vsync_counter_0\)
2617
2618 -- pragma translate_off
2619 GENERIC MAP (
2620         lut_mask => "8ccc",
2621         operation_mode => "normal",
2622         output_mode => "comb_only",
2623         register_cascade_mode => "off",
2624         sum_lutc_input => "datac",
2625         synch_mode => "off")
2626 -- pragma translate_on
2627 PORT MAP (
2628         dataa => \vga_driver_unit|vsync_counter_9\,
2629         datab => \vga_driver_unit|vsync_state_5\,
2630         datac => \vga_driver_unit|vsync_counter_0\,
2631         datad => \vga_driver_unit|un14_vsync_counter_8\,
2632         devclrn => ww_devclrn,
2633         devpor => ww_devpor,
2634         combout => \vga_driver_unit|vsync_state_next_1_sqmuxa_1\);
2635
2636 \vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_3\ : stratix_lcell
2637 -- Equation(s):
2638 -- \vga_driver_unit|un15_vsync_counter_3\ = !\vga_driver_unit|vsync_counter_0\ & \vga_driver_unit|vsync_counter_9\ & \vga_driver_unit|vsync_counter_3\ & !\vga_driver_unit|vsync_counter_2\
2639
2640 -- pragma translate_off
2641 GENERIC MAP (
2642         lut_mask => "0040",
2643         operation_mode => "normal",
2644         output_mode => "comb_only",
2645         register_cascade_mode => "off",
2646         sum_lutc_input => "datac",
2647         synch_mode => "off")
2648 -- pragma translate_on
2649 PORT MAP (
2650         dataa => \vga_driver_unit|vsync_counter_0\,
2651         datab => \vga_driver_unit|vsync_counter_9\,
2652         datac => \vga_driver_unit|vsync_counter_3\,
2653         datad => \vga_driver_unit|vsync_counter_2\,
2654         devclrn => ww_devclrn,
2655         devpor => ww_devpor,
2656         combout => \vga_driver_unit|un15_vsync_counter_3\);
2657
2658 \vga_driver_unit|VSYNC_FSM_next_un15_vsync_counter_4\ : stratix_lcell
2659 -- Equation(s):
2660 -- \vga_driver_unit|un15_vsync_counter_4\ = !\vga_driver_unit|vsync_counter_1\ & !\vga_driver_unit|vsync_counter_4\ & \vga_driver_unit|un15_vsync_counter_3\
2661
2662 -- pragma translate_off
2663 GENERIC MAP (
2664         lut_mask => "0300",
2665         operation_mode => "normal",
2666         output_mode => "comb_only",
2667         register_cascade_mode => "off",
2668         sum_lutc_input => "datac",
2669         synch_mode => "off")
2670 -- pragma translate_on
2671 PORT MAP (
2672         datab => \vga_driver_unit|vsync_counter_1\,
2673         datac => \vga_driver_unit|vsync_counter_4\,
2674         datad => \vga_driver_unit|un15_vsync_counter_3\,
2675         devclrn => ww_devclrn,
2676         devpor => ww_devpor,
2677         combout => \vga_driver_unit|un15_vsync_counter_4\);
2678
2679 \vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_3\ : stratix_lcell
2680 -- Equation(s):
2681 -- \vga_driver_unit|un13_vsync_counter_3\ = !\vga_driver_unit|vsync_counter_7\ & !\vga_driver_unit|vsync_counter_8\ & !\vga_driver_unit|vsync_counter_6\ & !\vga_driver_unit|vsync_counter_9\
2682
2683 -- pragma translate_off
2684 GENERIC MAP (
2685         lut_mask => "0001",
2686         operation_mode => "normal",
2687         output_mode => "comb_only",
2688         register_cascade_mode => "off",
2689         sum_lutc_input => "datac",
2690         synch_mode => "off")
2691 -- pragma translate_on
2692 PORT MAP (
2693         dataa => \vga_driver_unit|vsync_counter_7\,
2694         datab => \vga_driver_unit|vsync_counter_8\,
2695         datac => \vga_driver_unit|vsync_counter_6\,
2696         datad => \vga_driver_unit|vsync_counter_9\,
2697         devclrn => ww_devclrn,
2698         devpor => ww_devpor,
2699         combout => \vga_driver_unit|un13_vsync_counter_3\);
2700
2701 \vga_driver_unit|VSYNC_FSM_next_un13_vsync_counter_4\ : stratix_lcell
2702 -- Equation(s):
2703 -- \vga_driver_unit|un13_vsync_counter_4\ = \vga_driver_unit|vsync_counter_5\ & (\vga_driver_unit|vsync_counter_0\ & \vga_driver_unit|un13_vsync_counter_3\)
2704
2705 -- pragma translate_off
2706 GENERIC MAP (
2707         lut_mask => "a000",
2708         operation_mode => "normal",
2709         output_mode => "comb_only",
2710         register_cascade_mode => "off",
2711         sum_lutc_input => "datac",
2712         synch_mode => "off")
2713 -- pragma translate_on
2714 PORT MAP (
2715         dataa => \vga_driver_unit|vsync_counter_5\,
2716         datac => \vga_driver_unit|vsync_counter_0\,
2717         datad => \vga_driver_unit|un13_vsync_counter_3\,
2718         devclrn => ww_devclrn,
2719         devpor => ww_devpor,
2720         combout => \vga_driver_unit|un13_vsync_counter_4\);
2721
2722 \vga_driver_unit|vsync_state_next_1_sqmuxa_2_cZ\ : stratix_lcell
2723 -- Equation(s):
2724 -- \vga_driver_unit|vsync_state_next_1_sqmuxa_2\ = \vga_driver_unit|vsync_state_4\ & (!\vga_driver_unit|un13_vsync_counter_4\ # !\vga_driver_unit|un12_vsync_counter_7\)
2725
2726 -- pragma translate_off
2727 GENERIC MAP (
2728         lut_mask => "30f0",
2729         operation_mode => "normal",
2730         output_mode => "comb_only",
2731         register_cascade_mode => "off",
2732         sum_lutc_input => "datac",
2733         synch_mode => "off")
2734 -- pragma translate_on
2735 PORT MAP (
2736         datab => \vga_driver_unit|un12_vsync_counter_7\,
2737         datac => \vga_driver_unit|vsync_state_4\,
2738         datad => \vga_driver_unit|un13_vsync_counter_4\,
2739         devclrn => ww_devclrn,
2740         devpor => ww_devpor,
2741         combout => \vga_driver_unit|vsync_state_next_1_sqmuxa_2\);
2742
2743 \vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0_cZ\ : stratix_lcell
2744 -- Equation(s):
2745 -- \vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0\ = \vga_driver_unit|vsync_state_next_1_sqmuxa_2\ # \vga_driver_unit|vsync_state_2\ & (!\vga_driver_unit|un15_vsync_counter_4\ # !\vga_driver_unit|un12_vsync_counter_6\)
2746
2747 -- pragma translate_off
2748 GENERIC MAP (
2749         lut_mask => "ff4c",
2750         operation_mode => "normal",
2751         output_mode => "comb_only",
2752         register_cascade_mode => "off",
2753         sum_lutc_input => "datac",
2754         synch_mode => "off")
2755 -- pragma translate_on
2756 PORT MAP (
2757         dataa => \vga_driver_unit|un12_vsync_counter_6\,
2758         datab => \vga_driver_unit|vsync_state_2\,
2759         datac => \vga_driver_unit|un15_vsync_counter_4\,
2760         datad => \vga_driver_unit|vsync_state_next_1_sqmuxa_2\,
2761         devclrn => ww_devclrn,
2762         devpor => ww_devpor,
2763         combout => \vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0\);
2764
2765 \vga_driver_unit|vsync_state_next_2_sqmuxa_cZ\ : stratix_lcell
2766 -- Equation(s):
2767 -- \vga_driver_unit|vsync_state_next_2_sqmuxa\ = \vga_driver_unit|un6_dly_counter_0_x\ # !\vga_driver_unit|vsync_state_next_1_sqmuxa_3\ & !\vga_driver_unit|vsync_state_next_1_sqmuxa_1\ & !\vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0\
2768
2769 -- pragma translate_off
2770 GENERIC MAP (
2771         lut_mask => "aaab",
2772         operation_mode => "normal",
2773         output_mode => "comb_only",
2774         register_cascade_mode => "off",
2775         sum_lutc_input => "datac",
2776         synch_mode => "off")
2777 -- pragma translate_on
2778 PORT MAP (
2779         dataa => \vga_driver_unit|un6_dly_counter_0_x\,
2780         datab => \vga_driver_unit|vsync_state_next_1_sqmuxa_3\,
2781         datac => \vga_driver_unit|vsync_state_next_1_sqmuxa_1\,
2782         datad => \vga_driver_unit|un1_vsync_state_next_1_sqmuxa_0\,
2783         devclrn => ww_devclrn,
2784         devpor => ww_devpor,
2785         combout => \vga_driver_unit|vsync_state_next_2_sqmuxa\);
2786
2787 \vga_driver_unit|vsync_state_2_\ : stratix_lcell
2788 -- Equation(s):
2789 -- \vga_driver_unit|vsync_state_2\ = DFFEAS(\vga_driver_unit|vsync_counter_9\ & \vga_driver_unit|un14_vsync_counter_8\ & \vga_driver_unit|vsync_state_3\ & \vga_driver_unit|vsync_counter_0\, GLOBAL(\clk_pin~combout\), VCC, ,
2790 -- \vga_driver_unit|vsync_state_next_2_sqmuxa\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
2791
2792 -- pragma translate_off
2793 GENERIC MAP (
2794         lut_mask => "8000",
2795         operation_mode => "normal",
2796         output_mode => "reg_only",
2797         register_cascade_mode => "off",
2798         sum_lutc_input => "datac",
2799         synch_mode => "on")
2800 -- pragma translate_on
2801 PORT MAP (
2802         clk => \clk_pin~combout\,
2803         dataa => \vga_driver_unit|vsync_counter_9\,
2804         datab => \vga_driver_unit|un14_vsync_counter_8\,
2805         datac => \vga_driver_unit|vsync_state_3\,
2806         datad => \vga_driver_unit|vsync_counter_0\,
2807         aclr => GND,
2808         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
2809         ena => \vga_driver_unit|vsync_state_next_2_sqmuxa\,
2810         devclrn => ww_devclrn,
2811         devpor => ww_devpor,
2812         regout => \vga_driver_unit|vsync_state_2\);
2813
2814 \vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0_cZ\ : stratix_lcell
2815 -- Equation(s):
2816 -- \vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\ = \vga_driver_unit|vsync_state_2\ & \vga_driver_unit|un12_vsync_counter_6\ & \vga_driver_unit|un15_vsync_counter_4\
2817
2818 -- pragma translate_off
2819 GENERIC MAP (
2820         lut_mask => "c000",
2821         operation_mode => "normal",
2822         output_mode => "comb_only",
2823         register_cascade_mode => "off",
2824         sum_lutc_input => "datac",
2825         synch_mode => "off")
2826 -- pragma translate_on
2827 PORT MAP (
2828         datab => \vga_driver_unit|vsync_state_2\,
2829         datac => \vga_driver_unit|un12_vsync_counter_6\,
2830         datad => \vga_driver_unit|un15_vsync_counter_4\,
2831         devclrn => ww_devclrn,
2832         devpor => ww_devpor,
2833         combout => \vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\);
2834
2835 \vga_driver_unit|vsync_state_0_\ : stratix_lcell
2836 -- Equation(s):
2837 -- \vga_driver_unit|vsync_state_0\ = DFFEAS(\vga_driver_unit|un6_dly_counter_0_x\ & \vga_driver_unit|vsync_state_0\ & (!\vga_driver_unit|vsync_state_next_2_sqmuxa\) # !\vga_driver_unit|un6_dly_counter_0_x\ & (\vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\
2838 -- # \vga_driver_unit|vsync_state_0\ & !\vga_driver_unit|vsync_state_next_2_sqmuxa\), GLOBAL(\clk_pin~combout\), VCC, , , , , , )
2839
2840 -- pragma translate_off
2841 GENERIC MAP (
2842         lut_mask => "50dc",
2843         operation_mode => "normal",
2844         output_mode => "reg_only",
2845         register_cascade_mode => "off",
2846         sum_lutc_input => "datac",
2847         synch_mode => "off")
2848 -- pragma translate_on
2849 PORT MAP (
2850         clk => \clk_pin~combout\,
2851         dataa => \vga_driver_unit|un6_dly_counter_0_x\,
2852         datab => \vga_driver_unit|vsync_state_0\,
2853         datac => \vga_driver_unit|vsync_state_3_iv_0_0__g0_0_a3_0\,
2854         datad => \vga_driver_unit|vsync_state_next_2_sqmuxa\,
2855         aclr => GND,
2856         devclrn => ww_devclrn,
2857         devpor => ww_devpor,
2858         regout => \vga_driver_unit|vsync_state_0\);
2859
2860 \vga_driver_unit|d_set_vsync_counter_cZ\ : stratix_lcell
2861 -- Equation(s):
2862 -- \vga_driver_unit|d_set_vsync_counter\ = \vga_driver_unit|vsync_state_0\ # \vga_driver_unit|vsync_state_6\
2863
2864 -- pragma translate_off
2865 GENERIC MAP (
2866         lut_mask => "fff0",
2867         operation_mode => "normal",
2868         output_mode => "comb_only",
2869         register_cascade_mode => "off",
2870         sum_lutc_input => "datac",
2871         synch_mode => "off")
2872 -- pragma translate_on
2873 PORT MAP (
2874         datac => \vga_driver_unit|vsync_state_0\,
2875         datad => \vga_driver_unit|vsync_state_6\,
2876         devclrn => ww_devclrn,
2877         devpor => ww_devpor,
2878         combout => \vga_driver_unit|d_set_vsync_counter\);
2879
2880 \vga_driver_unit|vsync_counter_next_1_sqmuxa_cZ\ : stratix_lcell
2881 -- Equation(s):
2882 -- \vga_driver_unit|vsync_counter_next_1_sqmuxa\ = dly_counter(0) & dly_counter(1) & \reset_pin~combout\ & !\vga_driver_unit|d_set_vsync_counter\
2883
2884 -- pragma translate_off
2885 GENERIC MAP (
2886         lut_mask => "0080",
2887         operation_mode => "normal",
2888         output_mode => "comb_only",
2889         register_cascade_mode => "off",
2890         sum_lutc_input => "datac",
2891         synch_mode => "off")
2892 -- pragma translate_on
2893 PORT MAP (
2894         dataa => dly_counter(0),
2895         datab => dly_counter(1),
2896         datac => \reset_pin~combout\,
2897         datad => \vga_driver_unit|d_set_vsync_counter\,
2898         devclrn => ww_devclrn,
2899         devpor => ww_devpor,
2900         combout => \vga_driver_unit|vsync_counter_next_1_sqmuxa\);
2901
2902 \vga_driver_unit|vsync_counter_9_\ : stratix_lcell
2903 -- Equation(s):
2904 -- \vga_driver_unit|vsync_counter_9\ = DFFEAS((!\vga_driver_unit|vsync_counter_cout\(4) & \vga_driver_unit|vsync_counter_cout\(8)) # (\vga_driver_unit|vsync_counter_cout\(4) & \vga_driver_unit|vsync_counter_cout[8]~COUT1_24\) $
2905 -- \vga_driver_unit|vsync_counter_9\, GLOBAL(\clk_pin~combout\), VCC, , , \vga_driver_unit|vsync_counter_next_1_sqmuxa\, , !\vga_driver_unit|G_16_i\, !\vga_driver_unit|un9_vsync_counterlt9\)
2906
2907 -- pragma translate_off
2908 GENERIC MAP (
2909         cin0_used => "true",
2910         cin1_used => "true",
2911         cin_used => "true",
2912         lut_mask => "0ff0",
2913         operation_mode => "normal",
2914         output_mode => "reg_only",
2915         register_cascade_mode => "off",
2916         sum_lutc_input => "cin",
2917         synch_mode => "on")
2918 -- pragma translate_on
2919 PORT MAP (
2920         clk => \clk_pin~combout\,
2921         datac => \vga_driver_unit|vsync_counter_next_1_sqmuxa\,
2922         datad => \vga_driver_unit|vsync_counter_9\,
2923         aclr => GND,
2924         sclr => \vga_driver_unit|ALT_INV_G_16_i\,
2925         sload => \vga_driver_unit|ALT_INV_un9_vsync_counterlt9\,
2926         cin => \vga_driver_unit|vsync_counter_cout\(4),
2927         cin0 => \vga_driver_unit|vsync_counter_cout\(8),
2928         cin1 => \vga_driver_unit|vsync_counter_cout[8]~COUT1_24\,
2929         devclrn => ww_devclrn,
2930         devpor => ww_devpor,
2931         regout => \vga_driver_unit|vsync_counter_9\);
2932
2933 \vga_driver_unit|vsync_state_4_\ : stratix_lcell
2934 -- Equation(s):
2935 -- \vga_driver_unit|vsync_state_4\ = DFFEAS(!\vga_driver_unit|vsync_counter_9\ & \vga_driver_unit|un14_vsync_counter_8\ & \vga_driver_unit|vsync_state_5\ & \vga_driver_unit|vsync_counter_0\, GLOBAL(\clk_pin~combout\), VCC, ,
2936 -- \vga_driver_unit|vsync_state_next_2_sqmuxa\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
2937
2938 -- pragma translate_off
2939 GENERIC MAP (
2940         lut_mask => "4000",
2941         operation_mode => "normal",
2942         output_mode => "reg_only",
2943         register_cascade_mode => "off",
2944         sum_lutc_input => "datac",
2945         synch_mode => "on")
2946 -- pragma translate_on
2947 PORT MAP (
2948         clk => \clk_pin~combout\,
2949         dataa => \vga_driver_unit|vsync_counter_9\,
2950         datab => \vga_driver_unit|un14_vsync_counter_8\,
2951         datac => \vga_driver_unit|vsync_state_5\,
2952         datad => \vga_driver_unit|vsync_counter_0\,
2953         aclr => GND,
2954         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
2955         ena => \vga_driver_unit|vsync_state_next_2_sqmuxa\,
2956         devclrn => ww_devclrn,
2957         devpor => ww_devpor,
2958         regout => \vga_driver_unit|vsync_state_4\);
2959
2960 \vga_driver_unit|vsync_state_1_\ : stratix_lcell
2961 -- Equation(s):
2962 -- \vga_driver_unit|vsync_state_1\ = DFFEAS(\vga_driver_unit|vsync_state_4\ & \vga_driver_unit|un12_vsync_counter_7\ & !\vga_driver_unit|un6_dly_counter_0_x\ & \vga_driver_unit|un13_vsync_counter_4\, GLOBAL(\clk_pin~combout\), VCC, , , , , , )
2963
2964 -- pragma translate_off
2965 GENERIC MAP (
2966         lut_mask => "0800",
2967         operation_mode => "normal",
2968         output_mode => "reg_only",
2969         register_cascade_mode => "off",
2970         sum_lutc_input => "datac",
2971         synch_mode => "off")
2972 -- pragma translate_on
2973 PORT MAP (
2974         clk => \clk_pin~combout\,
2975         dataa => \vga_driver_unit|vsync_state_4\,
2976         datab => \vga_driver_unit|un12_vsync_counter_7\,
2977         datac => \vga_driver_unit|un6_dly_counter_0_x\,
2978         datad => \vga_driver_unit|un13_vsync_counter_4\,
2979         aclr => GND,
2980         devclrn => ww_devclrn,
2981         devpor => ww_devpor,
2982         regout => \vga_driver_unit|vsync_state_1\);
2983
2984 \vga_driver_unit|line_counter_next_0_sqmuxa_1_1_cZ\ : stratix_lcell
2985 -- Equation(s):
2986 -- \vga_driver_unit|line_counter_next_0_sqmuxa_1_1\ = dly_counter(1) & \reset_pin~combout\ & dly_counter(0) & !\vga_driver_unit|vsync_state_1\
2987
2988 -- pragma translate_off
2989 GENERIC MAP (
2990         lut_mask => "0080",
2991         operation_mode => "normal",
2992         output_mode => "comb_only",
2993         register_cascade_mode => "off",
2994         sum_lutc_input => "datac",
2995         synch_mode => "off")
2996 -- pragma translate_on
2997 PORT MAP (
2998         dataa => dly_counter(1),
2999         datab => \reset_pin~combout\,
3000         datac => dly_counter(0),
3001         datad => \vga_driver_unit|vsync_state_1\,
3002         devclrn => ww_devclrn,
3003         devpor => ww_devpor,
3004         combout => \vga_driver_unit|line_counter_next_0_sqmuxa_1_1\);
3005
3006 \vga_driver_unit|line_counter_sig_0_\ : stratix_lcell
3007 -- Equation(s):
3008 -- \vga_driver_unit|line_counter_sig_0\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(1) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, )
3009
3010 -- pragma translate_off
3011 GENERIC MAP (
3012         lut_mask => "f0ff",
3013         operation_mode => "normal",
3014         output_mode => "reg_only",
3015         register_cascade_mode => "off",
3016         sum_lutc_input => "datac",
3017         synch_mode => "on")
3018 -- pragma translate_on
3019 PORT MAP (
3020         clk => \clk_pin~combout\,
3021         datac => \vga_driver_unit|un1_line_counter_sig_combout\(1),
3022         datad => \vga_driver_unit|un10_line_counter_siglto8\,
3023         aclr => GND,
3024         sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\,
3025         devclrn => ww_devclrn,
3026         devpor => ww_devpor,
3027         regout => \vga_driver_unit|line_counter_sig_0\);
3028
3029 \vga_driver_unit|un1_line_counter_sig_a_1_\ : stratix_lcell
3030 -- Equation(s):
3031 -- \vga_driver_unit|un1_line_counter_sig_a_cout\(1) = CARRY(\vga_driver_unit|line_counter_sig_0\ & \vga_driver_unit|d_set_hsync_counter\)
3032 -- \vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3\ = CARRY(\vga_driver_unit|line_counter_sig_0\ & \vga_driver_unit|d_set_hsync_counter\)
3033
3034 -- pragma translate_off
3035 GENERIC MAP (
3036         lut_mask => "ff88",
3037         operation_mode => "arithmetic",
3038         output_mode => "none",
3039         register_cascade_mode => "off",
3040         sum_lutc_input => "datac",
3041         synch_mode => "off")
3042 -- pragma translate_on
3043 PORT MAP (
3044         dataa => \vga_driver_unit|line_counter_sig_0\,
3045         datab => \vga_driver_unit|d_set_hsync_counter\,
3046         devclrn => ww_devclrn,
3047         devpor => ww_devpor,
3048         combout => \vga_driver_unit|un1_line_counter_sig_a_1_~COMBOUT\,
3049         cout0 => \vga_driver_unit|un1_line_counter_sig_a_cout\(1),
3050         cout1 => \vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3\);
3051
3052 \vga_driver_unit|un1_line_counter_sig_2_\ : stratix_lcell
3053 -- Equation(s):
3054 -- \vga_driver_unit|un1_line_counter_sig_combout\(2) = \vga_driver_unit|line_counter_sig_1\ $ \vga_driver_unit|un1_line_counter_sig_a_cout\(1)
3055 -- \vga_driver_unit|un1_line_counter_sig_cout\(2) = CARRY(!\vga_driver_unit|un1_line_counter_sig_a_cout\(1) # !\vga_driver_unit|line_counter_sig_1\ # !\vga_driver_unit|line_counter_sig_2\)
3056 -- \vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17\ = CARRY(!\vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3\ # !\vga_driver_unit|line_counter_sig_1\ # !\vga_driver_unit|line_counter_sig_2\)
3057
3058 -- pragma translate_off
3059 GENERIC MAP (
3060         cin0_used => "true",
3061         cin1_used => "true",
3062         lut_mask => "3c7f",
3063         operation_mode => "arithmetic",
3064         output_mode => "comb_only",
3065         register_cascade_mode => "off",
3066         sum_lutc_input => "cin",
3067         synch_mode => "off")
3068 -- pragma translate_on
3069 PORT MAP (
3070         dataa => \vga_driver_unit|line_counter_sig_2\,
3071         datab => \vga_driver_unit|line_counter_sig_1\,
3072         cin0 => \vga_driver_unit|un1_line_counter_sig_a_cout\(1),
3073         cin1 => \vga_driver_unit|un1_line_counter_sig_a_cout[1]~COUT1_3\,
3074         devclrn => ww_devclrn,
3075         devpor => ww_devpor,
3076         combout => \vga_driver_unit|un1_line_counter_sig_combout\(2),
3077         cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(2),
3078         cout1 => \vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17\);
3079
3080 \vga_driver_unit|line_counter_sig_1_\ : stratix_lcell
3081 -- Equation(s):
3082 -- \vga_driver_unit|line_counter_sig_1\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(2) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, )
3083
3084 -- pragma translate_off
3085 GENERIC MAP (
3086         lut_mask => "ff55",
3087         operation_mode => "normal",
3088         output_mode => "reg_only",
3089         register_cascade_mode => "off",
3090         sum_lutc_input => "datac",
3091         synch_mode => "on")
3092 -- pragma translate_on
3093 PORT MAP (
3094         clk => \clk_pin~combout\,
3095         dataa => \vga_driver_unit|un10_line_counter_siglto8\,
3096         datad => \vga_driver_unit|un1_line_counter_sig_combout\(2),
3097         aclr => GND,
3098         sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\,
3099         devclrn => ww_devclrn,
3100         devpor => ww_devpor,
3101         regout => \vga_driver_unit|line_counter_sig_1\);
3102
3103 \vga_driver_unit|un1_line_counter_sig_3_\ : stratix_lcell
3104 -- Equation(s):
3105 -- \vga_driver_unit|un1_line_counter_sig_combout\(3) = \vga_driver_unit|line_counter_sig_2\ $ (\vga_driver_unit|line_counter_sig_1\ & \vga_driver_unit|un1_line_counter_sig_cout\(1))
3106 -- \vga_driver_unit|un1_line_counter_sig_cout\(3) = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout\(1) # !\vga_driver_unit|line_counter_sig_2\ # !\vga_driver_unit|line_counter_sig_1\)
3107 -- \vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11\ = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9\ # !\vga_driver_unit|line_counter_sig_2\ # !\vga_driver_unit|line_counter_sig_1\)
3108
3109 -- pragma translate_off
3110 GENERIC MAP (
3111         cin0_used => "true",
3112         cin1_used => "true",
3113         lut_mask => "6c7f",
3114         operation_mode => "arithmetic",
3115         output_mode => "comb_only",
3116         register_cascade_mode => "off",
3117         sum_lutc_input => "cin",
3118         synch_mode => "off")
3119 -- pragma translate_on
3120 PORT MAP (
3121         dataa => \vga_driver_unit|line_counter_sig_1\,
3122         datab => \vga_driver_unit|line_counter_sig_2\,
3123         cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(1),
3124         cin1 => \vga_driver_unit|un1_line_counter_sig_cout[1]~COUT1_9\,
3125         devclrn => ww_devclrn,
3126         devpor => ww_devpor,
3127         combout => \vga_driver_unit|un1_line_counter_sig_combout\(3),
3128         cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(3),
3129         cout1 => \vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11\);
3130
3131 \vga_driver_unit|line_counter_sig_2_\ : stratix_lcell
3132 -- Equation(s):
3133 -- \vga_driver_unit|line_counter_sig_2\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(3) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, )
3134
3135 -- pragma translate_off
3136 GENERIC MAP (
3137         lut_mask => "ff55",
3138         operation_mode => "normal",
3139         output_mode => "reg_only",
3140         register_cascade_mode => "off",
3141         sum_lutc_input => "datac",
3142         synch_mode => "on")
3143 -- pragma translate_on
3144 PORT MAP (
3145         clk => \clk_pin~combout\,
3146         dataa => \vga_driver_unit|un10_line_counter_siglto8\,
3147         datad => \vga_driver_unit|un1_line_counter_sig_combout\(3),
3148         aclr => GND,
3149         sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\,
3150         devclrn => ww_devclrn,
3151         devpor => ww_devpor,
3152         regout => \vga_driver_unit|line_counter_sig_2\);
3153
3154 \vga_driver_unit|un1_line_counter_sig_5_\ : stratix_lcell
3155 -- Equation(s):
3156 -- \vga_driver_unit|un1_line_counter_sig_combout\(5) = \vga_driver_unit|line_counter_sig_4\ $ (\vga_driver_unit|line_counter_sig_3\ & !\vga_driver_unit|un1_line_counter_sig_cout\(3))
3157 -- \vga_driver_unit|un1_line_counter_sig_cout\(5) = CARRY(\vga_driver_unit|line_counter_sig_3\ & \vga_driver_unit|line_counter_sig_4\ & !\vga_driver_unit|un1_line_counter_sig_cout\(3))
3158 -- \vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13\ = CARRY(\vga_driver_unit|line_counter_sig_3\ & \vga_driver_unit|line_counter_sig_4\ & !\vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11\)
3159
3160 -- pragma translate_off
3161 GENERIC MAP (
3162         cin0_used => "true",
3163         cin1_used => "true",
3164         lut_mask => "c608",
3165         operation_mode => "arithmetic",
3166         output_mode => "comb_only",
3167         register_cascade_mode => "off",
3168         sum_lutc_input => "cin",
3169         synch_mode => "off")
3170 -- pragma translate_on
3171 PORT MAP (
3172         dataa => \vga_driver_unit|line_counter_sig_3\,
3173         datab => \vga_driver_unit|line_counter_sig_4\,
3174         cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(3),
3175         cin1 => \vga_driver_unit|un1_line_counter_sig_cout[3]~COUT1_11\,
3176         devclrn => ww_devclrn,
3177         devpor => ww_devpor,
3178         combout => \vga_driver_unit|un1_line_counter_sig_combout\(5),
3179         cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(5),
3180         cout1 => \vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13\);
3181
3182 \vga_driver_unit|line_counter_sig_4_\ : stratix_lcell
3183 -- Equation(s):
3184 -- \vga_driver_unit|line_counter_sig_4\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(5) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, )
3185
3186 -- pragma translate_off
3187 GENERIC MAP (
3188         lut_mask => "f0ff",
3189         operation_mode => "normal",
3190         output_mode => "reg_only",
3191         register_cascade_mode => "off",
3192         sum_lutc_input => "datac",
3193         synch_mode => "on")
3194 -- pragma translate_on
3195 PORT MAP (
3196         clk => \clk_pin~combout\,
3197         datac => \vga_driver_unit|un1_line_counter_sig_combout\(5),
3198         datad => \vga_driver_unit|un10_line_counter_siglto8\,
3199         aclr => GND,
3200         sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\,
3201         devclrn => ww_devclrn,
3202         devpor => ww_devpor,
3203         regout => \vga_driver_unit|line_counter_sig_4\);
3204
3205 \vga_driver_unit|un1_line_counter_sig_4_\ : stratix_lcell
3206 -- Equation(s):
3207 -- \vga_driver_unit|un1_line_counter_sig_combout\(4) = \vga_driver_unit|line_counter_sig_3\ $ (!\vga_driver_unit|un1_line_counter_sig_cout\(2))
3208 -- \vga_driver_unit|un1_line_counter_sig_cout\(4) = CARRY(\vga_driver_unit|line_counter_sig_3\ & \vga_driver_unit|line_counter_sig_4\ & !\vga_driver_unit|un1_line_counter_sig_cout\(2))
3209 -- \vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19\ = CARRY(\vga_driver_unit|line_counter_sig_3\ & \vga_driver_unit|line_counter_sig_4\ & !\vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17\)
3210
3211 -- pragma translate_off
3212 GENERIC MAP (
3213         cin0_used => "true",
3214         cin1_used => "true",
3215         lut_mask => "a508",
3216         operation_mode => "arithmetic",
3217         output_mode => "comb_only",
3218         register_cascade_mode => "off",
3219         sum_lutc_input => "cin",
3220         synch_mode => "off")
3221 -- pragma translate_on
3222 PORT MAP (
3223         dataa => \vga_driver_unit|line_counter_sig_3\,
3224         datab => \vga_driver_unit|line_counter_sig_4\,
3225         cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(2),
3226         cin1 => \vga_driver_unit|un1_line_counter_sig_cout[2]~COUT1_17\,
3227         devclrn => ww_devclrn,
3228         devpor => ww_devpor,
3229         combout => \vga_driver_unit|un1_line_counter_sig_combout\(4),
3230         cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(4),
3231         cout1 => \vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19\);
3232
3233 \vga_driver_unit|line_counter_sig_3_\ : stratix_lcell
3234 -- Equation(s):
3235 -- \vga_driver_unit|line_counter_sig_3\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(4) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, )
3236
3237 -- pragma translate_off
3238 GENERIC MAP (
3239         lut_mask => "ff55",
3240         operation_mode => "normal",
3241         output_mode => "reg_only",
3242         register_cascade_mode => "off",
3243         sum_lutc_input => "datac",
3244         synch_mode => "on")
3245 -- pragma translate_on
3246 PORT MAP (
3247         clk => \clk_pin~combout\,
3248         dataa => \vga_driver_unit|un10_line_counter_siglto8\,
3249         datad => \vga_driver_unit|un1_line_counter_sig_combout\(4),
3250         aclr => GND,
3251         sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\,
3252         devclrn => ww_devclrn,
3253         devpor => ww_devpor,
3254         regout => \vga_driver_unit|line_counter_sig_3\);
3255
3256 \vga_driver_unit|un1_line_counter_sig_7_\ : stratix_lcell
3257 -- Equation(s):
3258 -- \vga_driver_unit|un1_line_counter_sig_combout\(7) = \vga_driver_unit|line_counter_sig_6\ $ (\vga_driver_unit|line_counter_sig_5\ & \vga_driver_unit|un1_line_counter_sig_cout\(5))
3259 -- \vga_driver_unit|un1_line_counter_sig_cout\(7) = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout\(5) # !\vga_driver_unit|line_counter_sig_5\ # !\vga_driver_unit|line_counter_sig_6\)
3260 -- \vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15\ = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13\ # !\vga_driver_unit|line_counter_sig_5\ # !\vga_driver_unit|line_counter_sig_6\)
3261
3262 -- pragma translate_off
3263 GENERIC MAP (
3264         cin0_used => "true",
3265         cin1_used => "true",
3266         lut_mask => "6a7f",
3267         operation_mode => "arithmetic",
3268         output_mode => "comb_only",
3269         register_cascade_mode => "off",
3270         sum_lutc_input => "cin",
3271         synch_mode => "off")
3272 -- pragma translate_on
3273 PORT MAP (
3274         dataa => \vga_driver_unit|line_counter_sig_6\,
3275         datab => \vga_driver_unit|line_counter_sig_5\,
3276         cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(5),
3277         cin1 => \vga_driver_unit|un1_line_counter_sig_cout[5]~COUT1_13\,
3278         devclrn => ww_devclrn,
3279         devpor => ww_devpor,
3280         combout => \vga_driver_unit|un1_line_counter_sig_combout\(7),
3281         cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(7),
3282         cout1 => \vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15\);
3283
3284 \vga_driver_unit|line_counter_sig_6_\ : stratix_lcell
3285 -- Equation(s):
3286 -- \vga_driver_unit|line_counter_sig_6\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(7) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, )
3287
3288 -- pragma translate_off
3289 GENERIC MAP (
3290         lut_mask => "ff55",
3291         operation_mode => "normal",
3292         output_mode => "reg_only",
3293         register_cascade_mode => "off",
3294         sum_lutc_input => "datac",
3295         synch_mode => "on")
3296 -- pragma translate_on
3297 PORT MAP (
3298         clk => \clk_pin~combout\,
3299         dataa => \vga_driver_unit|un10_line_counter_siglto8\,
3300         datad => \vga_driver_unit|un1_line_counter_sig_combout\(7),
3301         aclr => GND,
3302         sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\,
3303         devclrn => ww_devclrn,
3304         devpor => ww_devpor,
3305         regout => \vga_driver_unit|line_counter_sig_6\);
3306
3307 \vga_driver_unit|un1_line_counter_sig_6_\ : stratix_lcell
3308 -- Equation(s):
3309 -- \vga_driver_unit|un1_line_counter_sig_combout\(6) = \vga_driver_unit|line_counter_sig_5\ $ \vga_driver_unit|un1_line_counter_sig_cout\(4)
3310 -- \vga_driver_unit|un1_line_counter_sig_cout\(6) = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout\(4) # !\vga_driver_unit|line_counter_sig_5\ # !\vga_driver_unit|line_counter_sig_6\)
3311 -- \vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21\ = CARRY(!\vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19\ # !\vga_driver_unit|line_counter_sig_5\ # !\vga_driver_unit|line_counter_sig_6\)
3312
3313 -- pragma translate_off
3314 GENERIC MAP (
3315         cin0_used => "true",
3316         cin1_used => "true",
3317         lut_mask => "3c7f",
3318         operation_mode => "arithmetic",
3319         output_mode => "comb_only",
3320         register_cascade_mode => "off",
3321         sum_lutc_input => "cin",
3322         synch_mode => "off")
3323 -- pragma translate_on
3324 PORT MAP (
3325         dataa => \vga_driver_unit|line_counter_sig_6\,
3326         datab => \vga_driver_unit|line_counter_sig_5\,
3327         cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(4),
3328         cin1 => \vga_driver_unit|un1_line_counter_sig_cout[4]~COUT1_19\,
3329         devclrn => ww_devclrn,
3330         devpor => ww_devpor,
3331         combout => \vga_driver_unit|un1_line_counter_sig_combout\(6),
3332         cout0 => \vga_driver_unit|un1_line_counter_sig_cout\(6),
3333         cout1 => \vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21\);
3334
3335 \vga_driver_unit|line_counter_sig_5_\ : stratix_lcell
3336 -- Equation(s):
3337 -- \vga_driver_unit|line_counter_sig_5\ = DFFEAS(\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\ & \vga_driver_unit|un10_line_counter_siglto8\ & \vga_driver_unit|un1_line_counter_sig_combout\(6), GLOBAL(\clk_pin~combout\), VCC, , , , , , )
3338
3339 -- pragma translate_off
3340 GENERIC MAP (
3341         lut_mask => "c000",
3342         operation_mode => "normal",
3343         output_mode => "reg_only",
3344         register_cascade_mode => "off",
3345         sum_lutc_input => "datac",
3346         synch_mode => "off")
3347 -- pragma translate_on
3348 PORT MAP (
3349         clk => \clk_pin~combout\,
3350         datab => \vga_driver_unit|line_counter_next_0_sqmuxa_1_1\,
3351         datac => \vga_driver_unit|un10_line_counter_siglto8\,
3352         datad => \vga_driver_unit|un1_line_counter_sig_combout\(6),
3353         aclr => GND,
3354         devclrn => ww_devclrn,
3355         devpor => ww_devpor,
3356         regout => \vga_driver_unit|line_counter_sig_5\);
3357
3358 \vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglt4_2\ : stratix_lcell
3359 -- Equation(s):
3360 -- \vga_driver_unit|un10_line_counter_siglt4_2\ = !\vga_driver_unit|line_counter_sig_0\ # !\vga_driver_unit|line_counter_sig_3\ # !\vga_driver_unit|line_counter_sig_4\
3361
3362 -- pragma translate_off
3363 GENERIC MAP (
3364         lut_mask => "3fff",
3365         operation_mode => "normal",
3366         output_mode => "comb_only",
3367         register_cascade_mode => "off",
3368         sum_lutc_input => "datac",
3369         synch_mode => "off")
3370 -- pragma translate_on
3371 PORT MAP (
3372         datab => \vga_driver_unit|line_counter_sig_4\,
3373         datac => \vga_driver_unit|line_counter_sig_3\,
3374         datad => \vga_driver_unit|line_counter_sig_0\,
3375         devclrn => ww_devclrn,
3376         devpor => ww_devpor,
3377         combout => \vga_driver_unit|un10_line_counter_siglt4_2\);
3378
3379 \vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto5\ : stratix_lcell
3380 -- Equation(s):
3381 -- \vga_driver_unit|un10_line_counter_siglto5\ = !\vga_driver_unit|line_counter_sig_5\ & (\vga_driver_unit|un10_line_counter_siglt4_2\ # !\vga_driver_unit|line_counter_sig_1\ # !\vga_driver_unit|line_counter_sig_2\)
3382
3383 -- pragma translate_off
3384 GENERIC MAP (
3385         lut_mask => "3313",
3386         operation_mode => "normal",
3387         output_mode => "comb_only",
3388         register_cascade_mode => "off",
3389         sum_lutc_input => "datac",
3390         synch_mode => "off")
3391 -- pragma translate_on
3392 PORT MAP (
3393         dataa => \vga_driver_unit|line_counter_sig_2\,
3394         datab => \vga_driver_unit|line_counter_sig_5\,
3395         datac => \vga_driver_unit|line_counter_sig_1\,
3396         datad => \vga_driver_unit|un10_line_counter_siglt4_2\,
3397         devclrn => ww_devclrn,
3398         devpor => ww_devpor,
3399         combout => \vga_driver_unit|un10_line_counter_siglto5\);
3400
3401 \vga_driver_unit|un1_line_counter_sig_9_\ : stratix_lcell
3402 -- Equation(s):
3403 -- \vga_driver_unit|un1_line_counter_sig_combout\(9) = \vga_driver_unit|line_counter_sig_8\ $ (\vga_driver_unit|line_counter_sig_7\ & !\vga_driver_unit|un1_line_counter_sig_cout\(7))
3404
3405 -- pragma translate_off
3406 GENERIC MAP (
3407         cin0_used => "true",
3408         cin1_used => "true",
3409         lut_mask => "a6a6",
3410         operation_mode => "normal",
3411         output_mode => "comb_only",
3412         register_cascade_mode => "off",
3413         sum_lutc_input => "cin",
3414         synch_mode => "off")
3415 -- pragma translate_on
3416 PORT MAP (
3417         dataa => \vga_driver_unit|line_counter_sig_8\,
3418         datab => \vga_driver_unit|line_counter_sig_7\,
3419         cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(7),
3420         cin1 => \vga_driver_unit|un1_line_counter_sig_cout[7]~COUT1_15\,
3421         devclrn => ww_devclrn,
3422         devpor => ww_devpor,
3423         combout => \vga_driver_unit|un1_line_counter_sig_combout\(9));
3424
3425 \vga_driver_unit|line_counter_sig_8_\ : stratix_lcell
3426 -- Equation(s):
3427 -- \vga_driver_unit|line_counter_sig_8\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(9) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, )
3428
3429 -- pragma translate_off
3430 GENERIC MAP (
3431         lut_mask => "ff55",
3432         operation_mode => "normal",
3433         output_mode => "reg_only",
3434         register_cascade_mode => "off",
3435         sum_lutc_input => "datac",
3436         synch_mode => "on")
3437 -- pragma translate_on
3438 PORT MAP (
3439         clk => \clk_pin~combout\,
3440         dataa => \vga_driver_unit|un10_line_counter_siglto8\,
3441         datad => \vga_driver_unit|un1_line_counter_sig_combout\(9),
3442         aclr => GND,
3443         sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\,
3444         devclrn => ww_devclrn,
3445         devpor => ww_devpor,
3446         regout => \vga_driver_unit|line_counter_sig_8\);
3447
3448 \vga_driver_unit|LINE_COUNT_next_un10_line_counter_siglto8\ : stratix_lcell
3449 -- Equation(s):
3450 -- \vga_driver_unit|un10_line_counter_siglto8\ = \vga_driver_unit|un10_line_counter_siglto5\ # !\vga_driver_unit|line_counter_sig_6\ # !\vga_driver_unit|line_counter_sig_8\ # !\vga_driver_unit|line_counter_sig_7\
3451
3452 -- pragma translate_off
3453 GENERIC MAP (
3454         lut_mask => "dfff",
3455         operation_mode => "normal",
3456         output_mode => "comb_only",
3457         register_cascade_mode => "off",
3458         sum_lutc_input => "datac",
3459         synch_mode => "off")
3460 -- pragma translate_on
3461 PORT MAP (
3462         dataa => \vga_driver_unit|line_counter_sig_7\,
3463         datab => \vga_driver_unit|un10_line_counter_siglto5\,
3464         datac => \vga_driver_unit|line_counter_sig_8\,
3465         datad => \vga_driver_unit|line_counter_sig_6\,
3466         devclrn => ww_devclrn,
3467         devpor => ww_devpor,
3468         combout => \vga_driver_unit|un10_line_counter_siglto8\);
3469
3470 \vga_driver_unit|un1_line_counter_sig_8_\ : stratix_lcell
3471 -- Equation(s):
3472 -- \vga_driver_unit|un1_line_counter_sig_combout\(8) = \vga_driver_unit|un1_line_counter_sig_cout\(6) $ !\vga_driver_unit|line_counter_sig_7\
3473
3474 -- pragma translate_off
3475 GENERIC MAP (
3476         cin0_used => "true",
3477         cin1_used => "true",
3478         lut_mask => "f00f",
3479         operation_mode => "normal",
3480         output_mode => "comb_only",
3481         register_cascade_mode => "off",
3482         sum_lutc_input => "cin",
3483         synch_mode => "off")
3484 -- pragma translate_on
3485 PORT MAP (
3486         datad => \vga_driver_unit|line_counter_sig_7\,
3487         cin0 => \vga_driver_unit|un1_line_counter_sig_cout\(6),
3488         cin1 => \vga_driver_unit|un1_line_counter_sig_cout[6]~COUT1_21\,
3489         devclrn => ww_devclrn,
3490         devpor => ww_devpor,
3491         combout => \vga_driver_unit|un1_line_counter_sig_combout\(8));
3492
3493 \vga_driver_unit|line_counter_sig_7_\ : stratix_lcell
3494 -- Equation(s):
3495 -- \vga_driver_unit|line_counter_sig_7\ = DFFEAS(\vga_driver_unit|un1_line_counter_sig_combout\(8) # !\vga_driver_unit|un10_line_counter_siglto8\, GLOBAL(\clk_pin~combout\), VCC, , , , , !\vga_driver_unit|line_counter_next_0_sqmuxa_1_1\, )
3496
3497 -- pragma translate_off
3498 GENERIC MAP (
3499         lut_mask => "ff55",
3500         operation_mode => "normal",
3501         output_mode => "reg_only",
3502         register_cascade_mode => "off",
3503         sum_lutc_input => "datac",
3504         synch_mode => "on")
3505 -- pragma translate_on
3506 PORT MAP (
3507         clk => \clk_pin~combout\,
3508         dataa => \vga_driver_unit|un10_line_counter_siglto8\,
3509         datad => \vga_driver_unit|un1_line_counter_sig_combout\(8),
3510         aclr => GND,
3511         sclr => \vga_driver_unit|ALT_INV_line_counter_next_0_sqmuxa_1_1\,
3512         devclrn => ww_devclrn,
3513         devpor => ww_devpor,
3514         regout => \vga_driver_unit|line_counter_sig_7\);
3515
3516 \vga_control_unit|DRAW_SQUARE_next_un17_v_enablelt2\ : stratix_lcell
3517 -- Equation(s):
3518 -- \vga_control_unit|un17_v_enablelt2\ = \vga_driver_unit|line_counter_sig_2\ # \vga_driver_unit|line_counter_sig_1\ # \vga_driver_unit|line_counter_sig_0\
3519
3520 -- pragma translate_off
3521 GENERIC MAP (
3522         lut_mask => "ffee",
3523         operation_mode => "normal",
3524         output_mode => "comb_only",
3525         register_cascade_mode => "off",
3526         sum_lutc_input => "datac",
3527         synch_mode => "off")
3528 -- pragma translate_on
3529 PORT MAP (
3530         dataa => \vga_driver_unit|line_counter_sig_2\,
3531         datab => \vga_driver_unit|line_counter_sig_1\,
3532         datad => \vga_driver_unit|line_counter_sig_0\,
3533         devclrn => ww_devclrn,
3534         devpor => ww_devpor,
3535         combout => \vga_control_unit|un17_v_enablelt2\);
3536
3537 \vga_control_unit|DRAW_SQUARE_next_un17_v_enablelto5\ : stratix_lcell
3538 -- Equation(s):
3539 -- \vga_control_unit|un17_v_enablelto5\ = \vga_driver_unit|line_counter_sig_5\ # \vga_driver_unit|line_counter_sig_4\ # \vga_driver_unit|line_counter_sig_3\ & \vga_control_unit|un17_v_enablelt2\
3540
3541 -- pragma translate_off
3542 GENERIC MAP (
3543         lut_mask => "fefa",
3544         operation_mode => "normal",
3545         output_mode => "comb_only",
3546         register_cascade_mode => "off",
3547         sum_lutc_input => "datac",
3548         synch_mode => "off")
3549 -- pragma translate_on
3550 PORT MAP (
3551         dataa => \vga_driver_unit|line_counter_sig_5\,
3552         datab => \vga_driver_unit|line_counter_sig_3\,
3553         datac => \vga_driver_unit|line_counter_sig_4\,
3554         datad => \vga_control_unit|un17_v_enablelt2\,
3555         devclrn => ww_devclrn,
3556         devpor => ww_devpor,
3557         combout => \vga_control_unit|un17_v_enablelto5\);
3558
3559 \vga_control_unit|DRAW_SQUARE_next_un17_v_enablelto7\ : stratix_lcell
3560 -- Equation(s):
3561 -- \vga_control_unit|un17_v_enablelto7\ = \vga_driver_unit|line_counter_sig_7\ & \vga_control_unit|un17_v_enablelto5\ & \vga_driver_unit|line_counter_sig_6\
3562
3563 -- pragma translate_off
3564 GENERIC MAP (
3565         lut_mask => "c000",
3566         operation_mode => "normal",
3567         output_mode => "comb_only",
3568         register_cascade_mode => "off",
3569         sum_lutc_input => "datac",
3570         synch_mode => "off")
3571 -- pragma translate_on
3572 PORT MAP (
3573         datab => \vga_driver_unit|line_counter_sig_7\,
3574         datac => \vga_control_unit|un17_v_enablelto5\,
3575         datad => \vga_driver_unit|line_counter_sig_6\,
3576         devclrn => ww_devclrn,
3577         devpor => ww_devpor,
3578         combout => \vga_control_unit|un17_v_enablelto7\);
3579
3580 \vga_control_unit|toggle_counter_sig_0_\ : stratix_lcell
3581 -- Equation(s):
3582 -- \vga_control_unit|toggle_counter_sig_0\ = DFFEAS(!\vga_control_unit|toggle_counter_sig_0\, GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
3583
3584 -- pragma translate_off
3585 GENERIC MAP (
3586         lut_mask => "0f0f",
3587         operation_mode => "normal",
3588         output_mode => "reg_only",
3589         register_cascade_mode => "off",
3590         sum_lutc_input => "datac",
3591         synch_mode => "on")
3592 -- pragma translate_on
3593 PORT MAP (
3594         clk => \clk_pin~combout\,
3595         datac => \vga_control_unit|toggle_counter_sig_0\,
3596         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
3597         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
3598         devclrn => ww_devclrn,
3599         devpor => ww_devpor,
3600         regout => \vga_control_unit|toggle_counter_sig_0\);
3601
3602 \vga_control_unit|toggle_counter_sig_1_\ : stratix_lcell
3603 -- Equation(s):
3604 -- \vga_control_unit|toggle_counter_sig_1\ = DFFEAS(\vga_control_unit|toggle_counter_sig_0\ $ \vga_control_unit|toggle_counter_sig_1\, GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\,
3605 -- )
3606 -- \vga_control_unit|toggle_counter_sig_cout\(1) = CARRY(\vga_control_unit|toggle_counter_sig_0\ & \vga_control_unit|toggle_counter_sig_1\)
3607 -- \vga_control_unit|toggle_counter_sig_cout[1]~COUT1_17\ = CARRY(\vga_control_unit|toggle_counter_sig_0\ & \vga_control_unit|toggle_counter_sig_1\)
3608
3609 -- pragma translate_off
3610 GENERIC MAP (
3611         lut_mask => "6688",
3612         operation_mode => "arithmetic",
3613         output_mode => "reg_only",
3614         register_cascade_mode => "off",
3615         sum_lutc_input => "datac",
3616         synch_mode => "on")
3617 -- pragma translate_on
3618 PORT MAP (
3619         clk => \clk_pin~combout\,
3620         dataa => \vga_control_unit|toggle_counter_sig_0\,
3621         datab => \vga_control_unit|toggle_counter_sig_1\,
3622         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
3623         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
3624         devclrn => ww_devclrn,
3625         devpor => ww_devpor,
3626         regout => \vga_control_unit|toggle_counter_sig_1\,
3627         cout0 => \vga_control_unit|toggle_counter_sig_cout\(1),
3628         cout1 => \vga_control_unit|toggle_counter_sig_cout[1]~COUT1_17\);
3629
3630 \vga_control_unit|toggle_counter_sig_3_\ : stratix_lcell
3631 -- Equation(s):
3632 -- \vga_control_unit|toggle_counter_sig_3\ = DFFEAS(\vga_control_unit|toggle_counter_sig_3\ $ (\vga_control_unit|toggle_counter_sig_2\ & \vga_control_unit|toggle_counter_sig_cout\(1)), GLOBAL(\clk_pin~combout\),
3633 -- !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
3634 -- \vga_control_unit|toggle_counter_sig_cout\(3) = CARRY(!\vga_control_unit|toggle_counter_sig_cout\(1) # !\vga_control_unit|toggle_counter_sig_3\ # !\vga_control_unit|toggle_counter_sig_2\)
3635 -- \vga_control_unit|toggle_counter_sig_cout[3]~COUT1_19\ = CARRY(!\vga_control_unit|toggle_counter_sig_cout[1]~COUT1_17\ # !\vga_control_unit|toggle_counter_sig_3\ # !\vga_control_unit|toggle_counter_sig_2\)
3636
3637 -- pragma translate_off
3638 GENERIC MAP (
3639         cin0_used => "true",
3640         cin1_used => "true",
3641         lut_mask => "6c7f",
3642         operation_mode => "arithmetic",
3643         output_mode => "reg_only",
3644         register_cascade_mode => "off",
3645         sum_lutc_input => "cin",
3646         synch_mode => "on")
3647 -- pragma translate_on
3648 PORT MAP (
3649         clk => \clk_pin~combout\,
3650         dataa => \vga_control_unit|toggle_counter_sig_2\,
3651         datab => \vga_control_unit|toggle_counter_sig_3\,
3652         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
3653         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
3654         cin0 => \vga_control_unit|toggle_counter_sig_cout\(1),
3655         cin1 => \vga_control_unit|toggle_counter_sig_cout[1]~COUT1_17\,
3656         devclrn => ww_devclrn,
3657         devpor => ww_devpor,
3658         regout => \vga_control_unit|toggle_counter_sig_3\,
3659         cout0 => \vga_control_unit|toggle_counter_sig_cout\(3),
3660         cout1 => \vga_control_unit|toggle_counter_sig_cout[3]~COUT1_19\);
3661
3662 \vga_control_unit|un2_toggle_counter_next_0_\ : stratix_lcell
3663 -- Equation(s):
3664 -- \vga_control_unit|un2_toggle_counter_next_cout\(0) = CARRY(\vga_control_unit|toggle_counter_sig_0\ & \vga_control_unit|toggle_counter_sig_1\)
3665 -- \vga_control_unit|un2_toggle_counter_next_cout[0]~COUT1_3\ = CARRY(\vga_control_unit|toggle_counter_sig_0\ & \vga_control_unit|toggle_counter_sig_1\)
3666
3667 -- pragma translate_off
3668 GENERIC MAP (
3669         lut_mask => "ff88",
3670         operation_mode => "arithmetic",
3671         output_mode => "none",
3672         register_cascade_mode => "off",
3673         sum_lutc_input => "datac",
3674         synch_mode => "off")
3675 -- pragma translate_on
3676 PORT MAP (
3677         dataa => \vga_control_unit|toggle_counter_sig_0\,
3678         datab => \vga_control_unit|toggle_counter_sig_1\,
3679         devclrn => ww_devclrn,
3680         devpor => ww_devpor,
3681         combout => \vga_control_unit|un2_toggle_counter_next_0_~COMBOUT\,
3682         cout0 => \vga_control_unit|un2_toggle_counter_next_cout\(0),
3683         cout1 => \vga_control_unit|un2_toggle_counter_next_cout[0]~COUT1_3\);
3684
3685 \vga_control_unit|toggle_counter_sig_2_\ : stratix_lcell
3686 -- Equation(s):
3687 -- \vga_control_unit|toggle_counter_sig_2\ = DFFEAS(\vga_control_unit|toggle_counter_sig_2\ $ (\vga_control_unit|un2_toggle_counter_next_cout\(0)), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , ,
3688 -- !\vga_control_unit|toggle_sig_0_0_0_g1\, )
3689 -- \vga_control_unit|toggle_counter_sig_cout\(2) = CARRY(!\vga_control_unit|un2_toggle_counter_next_cout\(0) # !\vga_control_unit|toggle_counter_sig_3\ # !\vga_control_unit|toggle_counter_sig_2\)
3690 -- \vga_control_unit|toggle_counter_sig_cout[2]~COUT1_33\ = CARRY(!\vga_control_unit|un2_toggle_counter_next_cout[0]~COUT1_3\ # !\vga_control_unit|toggle_counter_sig_3\ # !\vga_control_unit|toggle_counter_sig_2\)
3691
3692 -- pragma translate_off
3693 GENERIC MAP (
3694         cin0_used => "true",
3695         cin1_used => "true",
3696         lut_mask => "5a7f",
3697         operation_mode => "arithmetic",
3698         output_mode => "reg_only",
3699         register_cascade_mode => "off",
3700         sum_lutc_input => "cin",
3701         synch_mode => "on")
3702 -- pragma translate_on
3703 PORT MAP (
3704         clk => \clk_pin~combout\,
3705         dataa => \vga_control_unit|toggle_counter_sig_2\,
3706         datab => \vga_control_unit|toggle_counter_sig_3\,
3707         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
3708         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
3709         cin0 => \vga_control_unit|un2_toggle_counter_next_cout\(0),
3710         cin1 => \vga_control_unit|un2_toggle_counter_next_cout[0]~COUT1_3\,
3711         devclrn => ww_devclrn,
3712         devpor => ww_devpor,
3713         regout => \vga_control_unit|toggle_counter_sig_2\,
3714         cout0 => \vga_control_unit|toggle_counter_sig_cout\(2),
3715         cout1 => \vga_control_unit|toggle_counter_sig_cout[2]~COUT1_33\);
3716
3717 \vga_control_unit|toggle_counter_sig_5_\ : stratix_lcell
3718 -- Equation(s):
3719 -- \vga_control_unit|toggle_counter_sig_5\ = DFFEAS(\vga_control_unit|toggle_counter_sig_5\ $ (\vga_control_unit|toggle_counter_sig_4\ & !\vga_control_unit|toggle_counter_sig_cout\(3)), GLOBAL(\clk_pin~combout\),
3720 -- !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
3721 -- \vga_control_unit|toggle_counter_sig_cout\(5) = CARRY(\vga_control_unit|toggle_counter_sig_5\ & \vga_control_unit|toggle_counter_sig_4\ & !\vga_control_unit|toggle_counter_sig_cout\(3))
3722 -- \vga_control_unit|toggle_counter_sig_cout[5]~COUT1_21\ = CARRY(\vga_control_unit|toggle_counter_sig_5\ & \vga_control_unit|toggle_counter_sig_4\ & !\vga_control_unit|toggle_counter_sig_cout[3]~COUT1_19\)
3723
3724 -- pragma translate_off
3725 GENERIC MAP (
3726         cin0_used => "true",
3727         cin1_used => "true",
3728         lut_mask => "a608",
3729         operation_mode => "arithmetic",
3730         output_mode => "reg_only",
3731         register_cascade_mode => "off",
3732         sum_lutc_input => "cin",
3733         synch_mode => "on")
3734 -- pragma translate_on
3735 PORT MAP (
3736         clk => \clk_pin~combout\,
3737         dataa => \vga_control_unit|toggle_counter_sig_5\,
3738         datab => \vga_control_unit|toggle_counter_sig_4\,
3739         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
3740         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
3741         cin0 => \vga_control_unit|toggle_counter_sig_cout\(3),
3742         cin1 => \vga_control_unit|toggle_counter_sig_cout[3]~COUT1_19\,
3743         devclrn => ww_devclrn,
3744         devpor => ww_devpor,
3745         regout => \vga_control_unit|toggle_counter_sig_5\,
3746         cout0 => \vga_control_unit|toggle_counter_sig_cout\(5),
3747         cout1 => \vga_control_unit|toggle_counter_sig_cout[5]~COUT1_21\);
3748
3749 \vga_control_unit|toggle_counter_sig_4_\ : stratix_lcell
3750 -- Equation(s):
3751 -- \vga_control_unit|toggle_counter_sig_4\ = DFFEAS(\vga_control_unit|toggle_counter_sig_4\ $ (!\vga_control_unit|toggle_counter_sig_cout\(2)), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , ,
3752 -- !\vga_control_unit|toggle_sig_0_0_0_g1\, )
3753 -- \vga_control_unit|toggle_counter_sig_cout\(4) = CARRY(\vga_control_unit|toggle_counter_sig_4\ & \vga_control_unit|toggle_counter_sig_5\ & !\vga_control_unit|toggle_counter_sig_cout\(2))
3754 -- \vga_control_unit|toggle_counter_sig_cout[4]~COUT1_35\ = CARRY(\vga_control_unit|toggle_counter_sig_4\ & \vga_control_unit|toggle_counter_sig_5\ & !\vga_control_unit|toggle_counter_sig_cout[2]~COUT1_33\)
3755
3756 -- pragma translate_off
3757 GENERIC MAP (
3758         cin0_used => "true",
3759         cin1_used => "true",
3760         lut_mask => "a508",
3761         operation_mode => "arithmetic",
3762         output_mode => "reg_only",
3763         register_cascade_mode => "off",
3764         sum_lutc_input => "cin",
3765         synch_mode => "on")
3766 -- pragma translate_on
3767 PORT MAP (
3768         clk => \clk_pin~combout\,
3769         dataa => \vga_control_unit|toggle_counter_sig_4\,
3770         datab => \vga_control_unit|toggle_counter_sig_5\,
3771         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
3772         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
3773         cin0 => \vga_control_unit|toggle_counter_sig_cout\(2),
3774         cin1 => \vga_control_unit|toggle_counter_sig_cout[2]~COUT1_33\,
3775         devclrn => ww_devclrn,
3776         devpor => ww_devpor,
3777         regout => \vga_control_unit|toggle_counter_sig_4\,
3778         cout0 => \vga_control_unit|toggle_counter_sig_cout\(4),
3779         cout1 => \vga_control_unit|toggle_counter_sig_cout[4]~COUT1_35\);
3780
3781 \vga_control_unit|toggle_counter_sig_6_\ : stratix_lcell
3782 -- Equation(s):
3783 -- \vga_control_unit|toggle_counter_sig_6\ = DFFEAS(\vga_control_unit|toggle_counter_sig_6\ $ (\vga_control_unit|toggle_counter_sig_cout\(4)), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , ,
3784 -- !\vga_control_unit|toggle_sig_0_0_0_g1\, )
3785 -- \vga_control_unit|toggle_counter_sig_cout\(6) = CARRY(!\vga_control_unit|toggle_counter_sig_cout\(4) # !\vga_control_unit|toggle_counter_sig_7\ # !\vga_control_unit|toggle_counter_sig_6\)
3786 -- \vga_control_unit|toggle_counter_sig_cout[6]~COUT1_37\ = CARRY(!\vga_control_unit|toggle_counter_sig_cout[4]~COUT1_35\ # !\vga_control_unit|toggle_counter_sig_7\ # !\vga_control_unit|toggle_counter_sig_6\)
3787
3788 -- pragma translate_off
3789 GENERIC MAP (
3790         cin0_used => "true",
3791         cin1_used => "true",
3792         lut_mask => "5a7f",
3793         operation_mode => "arithmetic",
3794         output_mode => "reg_only",
3795         register_cascade_mode => "off",
3796         sum_lutc_input => "cin",
3797         synch_mode => "on")
3798 -- pragma translate_on
3799 PORT MAP (
3800         clk => \clk_pin~combout\,
3801         dataa => \vga_control_unit|toggle_counter_sig_6\,
3802         datab => \vga_control_unit|toggle_counter_sig_7\,
3803         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
3804         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
3805         cin0 => \vga_control_unit|toggle_counter_sig_cout\(4),
3806         cin1 => \vga_control_unit|toggle_counter_sig_cout[4]~COUT1_35\,
3807         devclrn => ww_devclrn,
3808         devpor => ww_devpor,
3809         regout => \vga_control_unit|toggle_counter_sig_6\,
3810         cout0 => \vga_control_unit|toggle_counter_sig_cout\(6),
3811         cout1 => \vga_control_unit|toggle_counter_sig_cout[6]~COUT1_37\);
3812
3813 \vga_control_unit|toggle_counter_sig_7_\ : stratix_lcell
3814 -- Equation(s):
3815 -- \vga_control_unit|toggle_counter_sig_7\ = DFFEAS(\vga_control_unit|toggle_counter_sig_7\ $ (\vga_control_unit|toggle_counter_sig_6\ & \vga_control_unit|toggle_counter_sig_cout\(5)), GLOBAL(\clk_pin~combout\),
3816 -- !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
3817 -- \vga_control_unit|toggle_counter_sig_cout\(7) = CARRY(!\vga_control_unit|toggle_counter_sig_cout\(5) # !\vga_control_unit|toggle_counter_sig_6\ # !\vga_control_unit|toggle_counter_sig_7\)
3818 -- \vga_control_unit|toggle_counter_sig_cout[7]~COUT1_23\ = CARRY(!\vga_control_unit|toggle_counter_sig_cout[5]~COUT1_21\ # !\vga_control_unit|toggle_counter_sig_6\ # !\vga_control_unit|toggle_counter_sig_7\)
3819
3820 -- pragma translate_off
3821 GENERIC MAP (
3822         cin0_used => "true",
3823         cin1_used => "true",
3824         lut_mask => "6a7f",
3825         operation_mode => "arithmetic",
3826         output_mode => "reg_only",
3827         register_cascade_mode => "off",
3828         sum_lutc_input => "cin",
3829         synch_mode => "on")
3830 -- pragma translate_on
3831 PORT MAP (
3832         clk => \clk_pin~combout\,
3833         dataa => \vga_control_unit|toggle_counter_sig_7\,
3834         datab => \vga_control_unit|toggle_counter_sig_6\,
3835         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
3836         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
3837         cin0 => \vga_control_unit|toggle_counter_sig_cout\(5),
3838         cin1 => \vga_control_unit|toggle_counter_sig_cout[5]~COUT1_21\,
3839         devclrn => ww_devclrn,
3840         devpor => ww_devpor,
3841         regout => \vga_control_unit|toggle_counter_sig_7\,
3842         cout0 => \vga_control_unit|toggle_counter_sig_cout\(7),
3843         cout1 => \vga_control_unit|toggle_counter_sig_cout[7]~COUT1_23\);
3844
3845 \vga_control_unit|toggle_counter_sig_9_\ : stratix_lcell
3846 -- Equation(s):
3847 -- \vga_control_unit|toggle_counter_sig_9\ = DFFEAS(\vga_control_unit|toggle_counter_sig_9\ $ (\vga_control_unit|toggle_counter_sig_8\ & !\vga_control_unit|toggle_counter_sig_cout\(7)), GLOBAL(\clk_pin~combout\),
3848 -- !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
3849 -- \vga_control_unit|toggle_counter_sig_cout\(9) = CARRY(\vga_control_unit|toggle_counter_sig_9\ & \vga_control_unit|toggle_counter_sig_8\ & !\vga_control_unit|toggle_counter_sig_cout[7]~COUT1_23\)
3850
3851 -- pragma translate_off
3852 GENERIC MAP (
3853         cin0_used => "true",
3854         cin1_used => "true",
3855         lut_mask => "a608",
3856         operation_mode => "arithmetic",
3857         output_mode => "reg_only",
3858         register_cascade_mode => "off",
3859         sum_lutc_input => "cin",
3860         synch_mode => "on")
3861 -- pragma translate_on
3862 PORT MAP (
3863         clk => \clk_pin~combout\,
3864         dataa => \vga_control_unit|toggle_counter_sig_9\,
3865         datab => \vga_control_unit|toggle_counter_sig_8\,
3866         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
3867         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
3868         cin0 => \vga_control_unit|toggle_counter_sig_cout\(7),
3869         cin1 => \vga_control_unit|toggle_counter_sig_cout[7]~COUT1_23\,
3870         devclrn => ww_devclrn,
3871         devpor => ww_devpor,
3872         regout => \vga_control_unit|toggle_counter_sig_9\,
3873         cout => \vga_control_unit|toggle_counter_sig_cout\(9));
3874
3875 \vga_control_unit|toggle_counter_sig_8_\ : stratix_lcell
3876 -- Equation(s):
3877 -- \vga_control_unit|toggle_counter_sig_8\ = DFFEAS(\vga_control_unit|toggle_counter_sig_8\ $ (!\vga_control_unit|toggle_counter_sig_cout\(6)), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , ,
3878 -- !\vga_control_unit|toggle_sig_0_0_0_g1\, )
3879 -- \vga_control_unit|toggle_counter_sig_cout\(8) = CARRY(\vga_control_unit|toggle_counter_sig_8\ & \vga_control_unit|toggle_counter_sig_9\ & !\vga_control_unit|toggle_counter_sig_cout[6]~COUT1_37\)
3880
3881 -- pragma translate_off
3882 GENERIC MAP (
3883         cin0_used => "true",
3884         cin1_used => "true",
3885         lut_mask => "a508",
3886         operation_mode => "arithmetic",
3887         output_mode => "reg_only",
3888         register_cascade_mode => "off",
3889         sum_lutc_input => "cin",
3890         synch_mode => "on")
3891 -- pragma translate_on
3892 PORT MAP (
3893         clk => \clk_pin~combout\,
3894         dataa => \vga_control_unit|toggle_counter_sig_8\,
3895         datab => \vga_control_unit|toggle_counter_sig_9\,
3896         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
3897         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
3898         cin0 => \vga_control_unit|toggle_counter_sig_cout\(6),
3899         cin1 => \vga_control_unit|toggle_counter_sig_cout[6]~COUT1_37\,
3900         devclrn => ww_devclrn,
3901         devpor => ww_devpor,
3902         regout => \vga_control_unit|toggle_counter_sig_8\,
3903         cout => \vga_control_unit|toggle_counter_sig_cout\(8));
3904
3905 \vga_control_unit|toggle_counter_sig_10_\ : stratix_lcell
3906 -- Equation(s):
3907 -- \vga_control_unit|toggle_counter_sig_10\ = DFFEAS(\vga_control_unit|toggle_counter_sig_10\ $ (\vga_control_unit|toggle_counter_sig_cout\(8)), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , ,
3908 -- !\vga_control_unit|toggle_sig_0_0_0_g1\, )
3909 -- \vga_control_unit|toggle_counter_sig_cout\(10) = CARRY(!\vga_control_unit|toggle_counter_sig_cout\(8) # !\vga_control_unit|toggle_counter_sig_11\ # !\vga_control_unit|toggle_counter_sig_10\)
3910 -- \vga_control_unit|toggle_counter_sig_cout[10]~COUT1_39\ = CARRY(!\vga_control_unit|toggle_counter_sig_cout\(8) # !\vga_control_unit|toggle_counter_sig_11\ # !\vga_control_unit|toggle_counter_sig_10\)
3911
3912 -- pragma translate_off
3913 GENERIC MAP (
3914         cin_used => "true",
3915         lut_mask => "5a7f",
3916         operation_mode => "arithmetic",
3917         output_mode => "reg_only",
3918         register_cascade_mode => "off",
3919         sum_lutc_input => "cin",
3920         synch_mode => "on")
3921 -- pragma translate_on
3922 PORT MAP (
3923         clk => \clk_pin~combout\,
3924         dataa => \vga_control_unit|toggle_counter_sig_10\,
3925         datab => \vga_control_unit|toggle_counter_sig_11\,
3926         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
3927         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
3928         cin => \vga_control_unit|toggle_counter_sig_cout\(8),
3929         devclrn => ww_devclrn,
3930         devpor => ww_devpor,
3931         regout => \vga_control_unit|toggle_counter_sig_10\,
3932         cout0 => \vga_control_unit|toggle_counter_sig_cout\(10),
3933         cout1 => \vga_control_unit|toggle_counter_sig_cout[10]~COUT1_39\);
3934
3935 \vga_control_unit|toggle_counter_sig_11_\ : stratix_lcell
3936 -- Equation(s):
3937 -- \vga_control_unit|toggle_counter_sig_11\ = DFFEAS(\vga_control_unit|toggle_counter_sig_11\ $ (\vga_control_unit|toggle_counter_sig_10\ & \vga_control_unit|toggle_counter_sig_cout\(9)), GLOBAL(\clk_pin~combout\),
3938 -- !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
3939 -- \vga_control_unit|toggle_counter_sig_cout\(11) = CARRY(!\vga_control_unit|toggle_counter_sig_cout\(9) # !\vga_control_unit|toggle_counter_sig_11\ # !\vga_control_unit|toggle_counter_sig_10\)
3940 -- \vga_control_unit|toggle_counter_sig_cout[11]~COUT1_25\ = CARRY(!\vga_control_unit|toggle_counter_sig_cout\(9) # !\vga_control_unit|toggle_counter_sig_11\ # !\vga_control_unit|toggle_counter_sig_10\)
3941
3942 -- pragma translate_off
3943 GENERIC MAP (
3944         cin_used => "true",
3945         lut_mask => "6c7f",
3946         operation_mode => "arithmetic",
3947         output_mode => "reg_only",
3948         register_cascade_mode => "off",
3949         sum_lutc_input => "cin",
3950         synch_mode => "on")
3951 -- pragma translate_on
3952 PORT MAP (
3953         clk => \clk_pin~combout\,
3954         dataa => \vga_control_unit|toggle_counter_sig_10\,
3955         datab => \vga_control_unit|toggle_counter_sig_11\,
3956         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
3957         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
3958         cin => \vga_control_unit|toggle_counter_sig_cout\(9),
3959         devclrn => ww_devclrn,
3960         devpor => ww_devpor,
3961         regout => \vga_control_unit|toggle_counter_sig_11\,
3962         cout0 => \vga_control_unit|toggle_counter_sig_cout\(11),
3963         cout1 => \vga_control_unit|toggle_counter_sig_cout[11]~COUT1_25\);
3964
3965 \vga_control_unit|toggle_counter_sig_13_\ : stratix_lcell
3966 -- Equation(s):
3967 -- \vga_control_unit|toggle_counter_sig_13\ = DFFEAS(\vga_control_unit|toggle_counter_sig_13\ $ (\vga_control_unit|toggle_counter_sig_12\ & !(!\vga_control_unit|toggle_counter_sig_cout\(9) & \vga_control_unit|toggle_counter_sig_cout\(11)) #
3968 -- (\vga_control_unit|toggle_counter_sig_cout\(9) & \vga_control_unit|toggle_counter_sig_cout[11]~COUT1_25\)), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
3969 -- \vga_control_unit|toggle_counter_sig_cout\(13) = CARRY(\vga_control_unit|toggle_counter_sig_12\ & \vga_control_unit|toggle_counter_sig_13\ & !\vga_control_unit|toggle_counter_sig_cout\(11))
3970 -- \vga_control_unit|toggle_counter_sig_cout[13]~COUT1_27\ = CARRY(\vga_control_unit|toggle_counter_sig_12\ & \vga_control_unit|toggle_counter_sig_13\ & !\vga_control_unit|toggle_counter_sig_cout[11]~COUT1_25\)
3971
3972 -- pragma translate_off
3973 GENERIC MAP (
3974         cin0_used => "true",
3975         cin1_used => "true",
3976         cin_used => "true",
3977         lut_mask => "c608",
3978         operation_mode => "arithmetic",
3979         output_mode => "reg_only",
3980         register_cascade_mode => "off",
3981         sum_lutc_input => "cin",
3982         synch_mode => "on")
3983 -- pragma translate_on
3984 PORT MAP (
3985         clk => \clk_pin~combout\,
3986         dataa => \vga_control_unit|toggle_counter_sig_12\,
3987         datab => \vga_control_unit|toggle_counter_sig_13\,
3988         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
3989         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
3990         cin => \vga_control_unit|toggle_counter_sig_cout\(9),
3991         cin0 => \vga_control_unit|toggle_counter_sig_cout\(11),
3992         cin1 => \vga_control_unit|toggle_counter_sig_cout[11]~COUT1_25\,
3993         devclrn => ww_devclrn,
3994         devpor => ww_devpor,
3995         regout => \vga_control_unit|toggle_counter_sig_13\,
3996         cout0 => \vga_control_unit|toggle_counter_sig_cout\(13),
3997         cout1 => \vga_control_unit|toggle_counter_sig_cout[13]~COUT1_27\);
3998
3999 \vga_control_unit|toggle_counter_sig_12_\ : stratix_lcell
4000 -- Equation(s):
4001 -- \vga_control_unit|toggle_counter_sig_12\ = DFFEAS(\vga_control_unit|toggle_counter_sig_12\ $ (!(!\vga_control_unit|toggle_counter_sig_cout\(8) & \vga_control_unit|toggle_counter_sig_cout\(10)) # (\vga_control_unit|toggle_counter_sig_cout\(8) &
4002 -- \vga_control_unit|toggle_counter_sig_cout[10]~COUT1_39\)), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
4003 -- \vga_control_unit|toggle_counter_sig_cout\(12) = CARRY(\vga_control_unit|toggle_counter_sig_12\ & \vga_control_unit|toggle_counter_sig_13\ & !\vga_control_unit|toggle_counter_sig_cout\(10))
4004 -- \vga_control_unit|toggle_counter_sig_cout[12]~COUT1_41\ = CARRY(\vga_control_unit|toggle_counter_sig_12\ & \vga_control_unit|toggle_counter_sig_13\ & !\vga_control_unit|toggle_counter_sig_cout[10]~COUT1_39\)
4005
4006 -- pragma translate_off
4007 GENERIC MAP (
4008         cin0_used => "true",
4009         cin1_used => "true",
4010         cin_used => "true",
4011         lut_mask => "a508",
4012         operation_mode => "arithmetic",
4013         output_mode => "reg_only",
4014         register_cascade_mode => "off",
4015         sum_lutc_input => "cin",
4016         synch_mode => "on")
4017 -- pragma translate_on
4018 PORT MAP (
4019         clk => \clk_pin~combout\,
4020         dataa => \vga_control_unit|toggle_counter_sig_12\,
4021         datab => \vga_control_unit|toggle_counter_sig_13\,
4022         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
4023         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
4024         cin => \vga_control_unit|toggle_counter_sig_cout\(8),
4025         cin0 => \vga_control_unit|toggle_counter_sig_cout\(10),
4026         cin1 => \vga_control_unit|toggle_counter_sig_cout[10]~COUT1_39\,
4027         devclrn => ww_devclrn,
4028         devpor => ww_devpor,
4029         regout => \vga_control_unit|toggle_counter_sig_12\,
4030         cout0 => \vga_control_unit|toggle_counter_sig_cout\(12),
4031         cout1 => \vga_control_unit|toggle_counter_sig_cout[12]~COUT1_41\);
4032
4033 \vga_control_unit|toggle_counter_sig_15_\ : stratix_lcell
4034 -- Equation(s):
4035 -- \vga_control_unit|toggle_counter_sig_15\ = DFFEAS(\vga_control_unit|toggle_counter_sig_15\ $ (\vga_control_unit|toggle_counter_sig_14\ & (!\vga_control_unit|toggle_counter_sig_cout\(9) & \vga_control_unit|toggle_counter_sig_cout\(13)) #
4036 -- (\vga_control_unit|toggle_counter_sig_cout\(9) & \vga_control_unit|toggle_counter_sig_cout[13]~COUT1_27\)), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
4037 -- \vga_control_unit|toggle_counter_sig_cout\(15) = CARRY(!\vga_control_unit|toggle_counter_sig_cout\(13) # !\vga_control_unit|toggle_counter_sig_14\ # !\vga_control_unit|toggle_counter_sig_15\)
4038 -- \vga_control_unit|toggle_counter_sig_cout[15]~COUT1_29\ = CARRY(!\vga_control_unit|toggle_counter_sig_cout[13]~COUT1_27\ # !\vga_control_unit|toggle_counter_sig_14\ # !\vga_control_unit|toggle_counter_sig_15\)
4039
4040 -- pragma translate_off
4041 GENERIC MAP (
4042         cin0_used => "true",
4043         cin1_used => "true",
4044         cin_used => "true",
4045         lut_mask => "6a7f",
4046         operation_mode => "arithmetic",
4047         output_mode => "reg_only",
4048         register_cascade_mode => "off",
4049         sum_lutc_input => "cin",
4050         synch_mode => "on")
4051 -- pragma translate_on
4052 PORT MAP (
4053         clk => \clk_pin~combout\,
4054         dataa => \vga_control_unit|toggle_counter_sig_15\,
4055         datab => \vga_control_unit|toggle_counter_sig_14\,
4056         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
4057         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
4058         cin => \vga_control_unit|toggle_counter_sig_cout\(9),
4059         cin0 => \vga_control_unit|toggle_counter_sig_cout\(13),
4060         cin1 => \vga_control_unit|toggle_counter_sig_cout[13]~COUT1_27\,
4061         devclrn => ww_devclrn,
4062         devpor => ww_devpor,
4063         regout => \vga_control_unit|toggle_counter_sig_15\,
4064         cout0 => \vga_control_unit|toggle_counter_sig_cout\(15),
4065         cout1 => \vga_control_unit|toggle_counter_sig_cout[15]~COUT1_29\);
4066
4067 \vga_control_unit|toggle_counter_sig_14_\ : stratix_lcell
4068 -- Equation(s):
4069 -- \vga_control_unit|toggle_counter_sig_14\ = DFFEAS(\vga_control_unit|toggle_counter_sig_14\ $ ((!\vga_control_unit|toggle_counter_sig_cout\(8) & \vga_control_unit|toggle_counter_sig_cout\(12)) # (\vga_control_unit|toggle_counter_sig_cout\(8) &
4070 -- \vga_control_unit|toggle_counter_sig_cout[12]~COUT1_41\)), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
4071 -- \vga_control_unit|toggle_counter_sig_cout\(14) = CARRY(!\vga_control_unit|toggle_counter_sig_cout\(12) # !\vga_control_unit|toggle_counter_sig_15\ # !\vga_control_unit|toggle_counter_sig_14\)
4072 -- \vga_control_unit|toggle_counter_sig_cout[14]~COUT1_43\ = CARRY(!\vga_control_unit|toggle_counter_sig_cout[12]~COUT1_41\ # !\vga_control_unit|toggle_counter_sig_15\ # !\vga_control_unit|toggle_counter_sig_14\)
4073
4074 -- pragma translate_off
4075 GENERIC MAP (
4076         cin0_used => "true",
4077         cin1_used => "true",
4078         cin_used => "true",
4079         lut_mask => "5a7f",
4080         operation_mode => "arithmetic",
4081         output_mode => "reg_only",
4082         register_cascade_mode => "off",
4083         sum_lutc_input => "cin",
4084         synch_mode => "on")
4085 -- pragma translate_on
4086 PORT MAP (
4087         clk => \clk_pin~combout\,
4088         dataa => \vga_control_unit|toggle_counter_sig_14\,
4089         datab => \vga_control_unit|toggle_counter_sig_15\,
4090         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
4091         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
4092         cin => \vga_control_unit|toggle_counter_sig_cout\(8),
4093         cin0 => \vga_control_unit|toggle_counter_sig_cout\(12),
4094         cin1 => \vga_control_unit|toggle_counter_sig_cout[12]~COUT1_41\,
4095         devclrn => ww_devclrn,
4096         devpor => ww_devpor,
4097         regout => \vga_control_unit|toggle_counter_sig_14\,
4098         cout0 => \vga_control_unit|toggle_counter_sig_cout\(14),
4099         cout1 => \vga_control_unit|toggle_counter_sig_cout[14]~COUT1_43\);
4100
4101 \vga_control_unit|toggle_counter_sig_17_\ : stratix_lcell
4102 -- Equation(s):
4103 -- \vga_control_unit|toggle_counter_sig_17\ = DFFEAS(\vga_control_unit|toggle_counter_sig_17\ $ (\vga_control_unit|toggle_counter_sig_16\ & !(!\vga_control_unit|toggle_counter_sig_cout\(9) & \vga_control_unit|toggle_counter_sig_cout\(15)) #
4104 -- (\vga_control_unit|toggle_counter_sig_cout\(9) & \vga_control_unit|toggle_counter_sig_cout[15]~COUT1_29\)), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
4105 -- \vga_control_unit|toggle_counter_sig_cout\(17) = CARRY(\vga_control_unit|toggle_counter_sig_17\ & \vga_control_unit|toggle_counter_sig_16\ & !\vga_control_unit|toggle_counter_sig_cout\(15))
4106 -- \vga_control_unit|toggle_counter_sig_cout[17]~COUT1_31\ = CARRY(\vga_control_unit|toggle_counter_sig_17\ & \vga_control_unit|toggle_counter_sig_16\ & !\vga_control_unit|toggle_counter_sig_cout[15]~COUT1_29\)
4107
4108 -- pragma translate_off
4109 GENERIC MAP (
4110         cin0_used => "true",
4111         cin1_used => "true",
4112         cin_used => "true",
4113         lut_mask => "a608",
4114         operation_mode => "arithmetic",
4115         output_mode => "reg_only",
4116         register_cascade_mode => "off",
4117         sum_lutc_input => "cin",
4118         synch_mode => "on")
4119 -- pragma translate_on
4120 PORT MAP (
4121         clk => \clk_pin~combout\,
4122         dataa => \vga_control_unit|toggle_counter_sig_17\,
4123         datab => \vga_control_unit|toggle_counter_sig_16\,
4124         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
4125         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
4126         cin => \vga_control_unit|toggle_counter_sig_cout\(9),
4127         cin0 => \vga_control_unit|toggle_counter_sig_cout\(15),
4128         cin1 => \vga_control_unit|toggle_counter_sig_cout[15]~COUT1_29\,
4129         devclrn => ww_devclrn,
4130         devpor => ww_devpor,
4131         regout => \vga_control_unit|toggle_counter_sig_17\,
4132         cout0 => \vga_control_unit|toggle_counter_sig_cout\(17),
4133         cout1 => \vga_control_unit|toggle_counter_sig_cout[17]~COUT1_31\);
4134
4135 \vga_control_unit|toggle_counter_sig_16_\ : stratix_lcell
4136 -- Equation(s):
4137 -- \vga_control_unit|toggle_counter_sig_16\ = DFFEAS(\vga_control_unit|toggle_counter_sig_16\ $ (!(!\vga_control_unit|toggle_counter_sig_cout\(8) & \vga_control_unit|toggle_counter_sig_cout\(14)) # (\vga_control_unit|toggle_counter_sig_cout\(8) &
4138 -- \vga_control_unit|toggle_counter_sig_cout[14]~COUT1_43\)), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
4139 -- \vga_control_unit|toggle_counter_sig_cout\(16) = CARRY(\vga_control_unit|toggle_counter_sig_16\ & \vga_control_unit|toggle_counter_sig_17\ & !\vga_control_unit|toggle_counter_sig_cout\(14))
4140 -- \vga_control_unit|toggle_counter_sig_cout[16]~COUT1_45\ = CARRY(\vga_control_unit|toggle_counter_sig_16\ & \vga_control_unit|toggle_counter_sig_17\ & !\vga_control_unit|toggle_counter_sig_cout[14]~COUT1_43\)
4141
4142 -- pragma translate_off
4143 GENERIC MAP (
4144         cin0_used => "true",
4145         cin1_used => "true",
4146         cin_used => "true",
4147         lut_mask => "a508",
4148         operation_mode => "arithmetic",
4149         output_mode => "reg_only",
4150         register_cascade_mode => "off",
4151         sum_lutc_input => "cin",
4152         synch_mode => "on")
4153 -- pragma translate_on
4154 PORT MAP (
4155         clk => \clk_pin~combout\,
4156         dataa => \vga_control_unit|toggle_counter_sig_16\,
4157         datab => \vga_control_unit|toggle_counter_sig_17\,
4158         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
4159         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
4160         cin => \vga_control_unit|toggle_counter_sig_cout\(8),
4161         cin0 => \vga_control_unit|toggle_counter_sig_cout\(14),
4162         cin1 => \vga_control_unit|toggle_counter_sig_cout[14]~COUT1_43\,
4163         devclrn => ww_devclrn,
4164         devpor => ww_devpor,
4165         regout => \vga_control_unit|toggle_counter_sig_16\,
4166         cout0 => \vga_control_unit|toggle_counter_sig_cout\(16),
4167         cout1 => \vga_control_unit|toggle_counter_sig_cout[16]~COUT1_45\);
4168
4169 \vga_control_unit|toggle_counter_sig_18_\ : stratix_lcell
4170 -- Equation(s):
4171 -- \vga_control_unit|toggle_counter_sig_18\ = DFFEAS((!\vga_control_unit|toggle_counter_sig_cout\(8) & \vga_control_unit|toggle_counter_sig_cout\(16)) # (\vga_control_unit|toggle_counter_sig_cout\(8) & \vga_control_unit|toggle_counter_sig_cout[16]~COUT1_45\)
4172 -- $ \vga_control_unit|toggle_counter_sig_18\, GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
4173
4174 -- pragma translate_off
4175 GENERIC MAP (
4176         cin0_used => "true",
4177         cin1_used => "true",
4178         cin_used => "true",
4179         lut_mask => "0ff0",
4180         operation_mode => "normal",
4181         output_mode => "reg_only",
4182         register_cascade_mode => "off",
4183         sum_lutc_input => "cin",
4184         synch_mode => "on")
4185 -- pragma translate_on
4186 PORT MAP (
4187         clk => \clk_pin~combout\,
4188         datad => \vga_control_unit|toggle_counter_sig_18\,
4189         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
4190         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
4191         cin => \vga_control_unit|toggle_counter_sig_cout\(8),
4192         cin0 => \vga_control_unit|toggle_counter_sig_cout\(16),
4193         cin1 => \vga_control_unit|toggle_counter_sig_cout[16]~COUT1_45\,
4194         devclrn => ww_devclrn,
4195         devpor => ww_devpor,
4196         regout => \vga_control_unit|toggle_counter_sig_18\);
4197
4198 \vga_control_unit|toggle_counter_sig_19_\ : stratix_lcell
4199 -- Equation(s):
4200 -- \vga_control_unit|toggle_counter_sig_19\ = DFFEAS(\vga_control_unit|toggle_counter_sig_19\ $ (\vga_control_unit|toggle_counter_sig_18\ & (!\vga_control_unit|toggle_counter_sig_cout\(9) & \vga_control_unit|toggle_counter_sig_cout\(17)) #
4201 -- (\vga_control_unit|toggle_counter_sig_cout\(9) & \vga_control_unit|toggle_counter_sig_cout[17]~COUT1_31\)), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , !\vga_control_unit|toggle_sig_0_0_0_g1\, )
4202
4203 -- pragma translate_off
4204 GENERIC MAP (
4205         cin0_used => "true",
4206         cin1_used => "true",
4207         cin_used => "true",
4208         lut_mask => "3fc0",
4209         operation_mode => "normal",
4210         output_mode => "reg_only",
4211         register_cascade_mode => "off",
4212         sum_lutc_input => "cin",
4213         synch_mode => "on")
4214 -- pragma translate_on
4215 PORT MAP (
4216         clk => \clk_pin~combout\,
4217         datab => \vga_control_unit|toggle_counter_sig_18\,
4218         datad => \vga_control_unit|toggle_counter_sig_19\,
4219         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
4220         sclr => \vga_control_unit|ALT_INV_toggle_sig_0_0_0_g1\,
4221         cin => \vga_control_unit|toggle_counter_sig_cout\(9),
4222         cin0 => \vga_control_unit|toggle_counter_sig_cout\(17),
4223         cin1 => \vga_control_unit|toggle_counter_sig_cout[17]~COUT1_31\,
4224         devclrn => ww_devclrn,
4225         devpor => ww_devpor,
4226         regout => \vga_control_unit|toggle_counter_sig_19\);
4227
4228 \vga_control_unit|BLINKER_next_un1_toggle_counter_siglto19_4\ : stratix_lcell
4229 -- Equation(s):
4230 -- \vga_control_unit|un1_toggle_counter_siglto19_4\ = !\vga_control_unit|toggle_counter_sig_19\ # !\vga_control_unit|toggle_counter_sig_17\ # !\vga_control_unit|toggle_counter_sig_18\ # !\vga_control_unit|toggle_counter_sig_16\
4231
4232 -- pragma translate_off
4233 GENERIC MAP (
4234         lut_mask => "7fff",
4235         operation_mode => "normal",
4236         output_mode => "comb_only",
4237         register_cascade_mode => "off",
4238         sum_lutc_input => "datac",
4239         synch_mode => "off")
4240 -- pragma translate_on
4241 PORT MAP (
4242         dataa => \vga_control_unit|toggle_counter_sig_16\,
4243         datab => \vga_control_unit|toggle_counter_sig_18\,
4244         datac => \vga_control_unit|toggle_counter_sig_17\,
4245         datad => \vga_control_unit|toggle_counter_sig_19\,
4246         devclrn => ww_devclrn,
4247         devpor => ww_devpor,
4248         combout => \vga_control_unit|un1_toggle_counter_siglto19_4\);
4249
4250 \vga_control_unit|BLINKER_next_un1_toggle_counter_siglto19_5\ : stratix_lcell
4251 -- Equation(s):
4252 -- \vga_control_unit|un1_toggle_counter_siglto19_5\ = \vga_control_unit|un1_toggle_counter_siglto19_4\ # !\vga_control_unit|toggle_counter_sig_15\ # !\vga_control_unit|toggle_counter_sig_13\ # !\vga_control_unit|toggle_counter_sig_14\
4253
4254 -- pragma translate_off
4255 GENERIC MAP (
4256         lut_mask => "ff7f",
4257         operation_mode => "normal",
4258         output_mode => "comb_only",
4259         register_cascade_mode => "off",
4260         sum_lutc_input => "datac",
4261         synch_mode => "off")
4262 -- pragma translate_on
4263 PORT MAP (
4264         dataa => \vga_control_unit|toggle_counter_sig_14\,
4265         datab => \vga_control_unit|toggle_counter_sig_13\,
4266         datac => \vga_control_unit|toggle_counter_sig_15\,
4267         datad => \vga_control_unit|un1_toggle_counter_siglto19_4\,
4268         devclrn => ww_devclrn,
4269         devpor => ww_devpor,
4270         combout => \vga_control_unit|un1_toggle_counter_siglto19_5\);
4271
4272 \vga_control_unit|BLINKER_next_un1_toggle_counter_siglto7_4\ : stratix_lcell
4273 -- Equation(s):
4274 -- \vga_control_unit|un1_toggle_counter_siglto7_4\ = !\vga_control_unit|toggle_counter_sig_7\ & !\vga_control_unit|toggle_counter_sig_6\ & !\vga_control_unit|toggle_counter_sig_1\ & !\vga_control_unit|toggle_counter_sig_5\
4275
4276 -- pragma translate_off
4277 GENERIC MAP (
4278         lut_mask => "0001",
4279         operation_mode => "normal",
4280         output_mode => "comb_only",
4281         register_cascade_mode => "off",
4282         sum_lutc_input => "datac",
4283         synch_mode => "off")
4284 -- pragma translate_on
4285 PORT MAP (
4286         dataa => \vga_control_unit|toggle_counter_sig_7\,
4287         datab => \vga_control_unit|toggle_counter_sig_6\,
4288         datac => \vga_control_unit|toggle_counter_sig_1\,
4289         datad => \vga_control_unit|toggle_counter_sig_5\,
4290         devclrn => ww_devclrn,
4291         devpor => ww_devpor,
4292         combout => \vga_control_unit|un1_toggle_counter_siglto7_4\);
4293
4294 \vga_control_unit|BLINKER_next_un1_toggle_counter_siglto7\ : stratix_lcell
4295 -- Equation(s):
4296 -- \vga_control_unit|un1_toggle_counter_siglto7\ = !\vga_control_unit|toggle_counter_sig_2\ & !\vga_control_unit|toggle_counter_sig_4\ & \vga_control_unit|un1_toggle_counter_siglto7_4\ & !\vga_control_unit|toggle_counter_sig_3\
4297
4298 -- pragma translate_off
4299 GENERIC MAP (
4300         lut_mask => "0010",
4301         operation_mode => "normal",
4302         output_mode => "comb_only",
4303         register_cascade_mode => "off",
4304         sum_lutc_input => "datac",
4305         synch_mode => "off")
4306 -- pragma translate_on
4307 PORT MAP (
4308         dataa => \vga_control_unit|toggle_counter_sig_2\,
4309         datab => \vga_control_unit|toggle_counter_sig_4\,
4310         datac => \vga_control_unit|un1_toggle_counter_siglto7_4\,
4311         datad => \vga_control_unit|toggle_counter_sig_3\,
4312         devclrn => ww_devclrn,
4313         devpor => ww_devpor,
4314         combout => \vga_control_unit|un1_toggle_counter_siglto7\);
4315
4316 \vga_control_unit|BLINKER_next_un1_toggle_counter_siglto10\ : stratix_lcell
4317 -- Equation(s):
4318 -- \vga_control_unit|un1_toggle_counter_siglto10\ = !\vga_control_unit|toggle_counter_sig_9\ & (\vga_control_unit|un1_toggle_counter_siglto7\ # !\vga_control_unit|toggle_counter_sig_8\) # !\vga_control_unit|toggle_counter_sig_10\
4319
4320 -- pragma translate_off
4321 GENERIC MAP (
4322         lut_mask => "5f57",
4323         operation_mode => "normal",
4324         output_mode => "comb_only",
4325         register_cascade_mode => "off",
4326         sum_lutc_input => "datac",
4327         synch_mode => "off")
4328 -- pragma translate_on
4329 PORT MAP (
4330         dataa => \vga_control_unit|toggle_counter_sig_10\,
4331         datab => \vga_control_unit|toggle_counter_sig_8\,
4332         datac => \vga_control_unit|toggle_counter_sig_9\,
4333         datad => \vga_control_unit|un1_toggle_counter_siglto7\,
4334         devclrn => ww_devclrn,
4335         devpor => ww_devpor,
4336         combout => \vga_control_unit|un1_toggle_counter_siglto10\);
4337
4338 \vga_control_unit|BLINKER_next_un1_toggle_counter_siglto19\ : stratix_lcell
4339 -- Equation(s):
4340 -- \vga_control_unit|un1_toggle_counter_siglto19\ = \vga_control_unit|un1_toggle_counter_siglto19_5\ # !\vga_control_unit|toggle_counter_sig_11\ & !\vga_control_unit|toggle_counter_sig_12\ & \vga_control_unit|un1_toggle_counter_siglto10\
4341
4342 -- pragma translate_off
4343 GENERIC MAP (
4344         lut_mask => "f1f0",
4345         operation_mode => "normal",
4346         output_mode => "comb_only",
4347         register_cascade_mode => "off",
4348         sum_lutc_input => "datac",
4349         synch_mode => "off")
4350 -- pragma translate_on
4351 PORT MAP (
4352         dataa => \vga_control_unit|toggle_counter_sig_11\,
4353         datab => \vga_control_unit|toggle_counter_sig_12\,
4354         datac => \vga_control_unit|un1_toggle_counter_siglto19_5\,
4355         datad => \vga_control_unit|un1_toggle_counter_siglto10\,
4356         devclrn => ww_devclrn,
4357         devpor => ww_devpor,
4358         combout => \vga_control_unit|un1_toggle_counter_siglto19\);
4359
4360 \vga_control_unit|toggle_sig_0_0_0_g1_cZ\ : stratix_lcell
4361 -- Equation(s):
4362 -- \vga_control_unit|toggle_sig_0_0_0_g1\ = \vga_control_unit|un1_toggle_counter_siglto19\
4363
4364 -- pragma translate_off
4365 GENERIC MAP (
4366         lut_mask => "ff00",
4367         operation_mode => "normal",
4368         output_mode => "comb_only",
4369         register_cascade_mode => "off",
4370         sum_lutc_input => "datac",
4371         synch_mode => "off")
4372 -- pragma translate_on
4373 PORT MAP (
4374         datad => \vga_control_unit|un1_toggle_counter_siglto19\,
4375         devclrn => ww_devclrn,
4376         devpor => ww_devpor,
4377         combout => \vga_control_unit|toggle_sig_0_0_0_g1\);
4378
4379 \vga_control_unit|toggle_sig_Z\ : stratix_lcell
4380 -- Equation(s):
4381 -- \vga_control_unit|toggle_sig\ = DFFEAS(\vga_control_unit|toggle_sig_0_0_0_g1\ $ (!\vga_control_unit|toggle_sig\), GLOBAL(\clk_pin~combout\), !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , , )
4382
4383 -- pragma translate_off
4384 GENERIC MAP (
4385         lut_mask => "aa55",
4386         operation_mode => "normal",
4387         output_mode => "reg_only",
4388         register_cascade_mode => "off",
4389         sum_lutc_input => "datac",
4390         synch_mode => "off")
4391 -- pragma translate_on
4392 PORT MAP (
4393         clk => \clk_pin~combout\,
4394         dataa => \vga_control_unit|toggle_sig_0_0_0_g1\,
4395         datad => \vga_control_unit|toggle_sig\,
4396         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
4397         devclrn => ww_devclrn,
4398         devpor => ww_devpor,
4399         regout => \vga_control_unit|toggle_sig\);
4400
4401 \vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto6\ : stratix_lcell
4402 -- Equation(s):
4403 -- \vga_control_unit|un9_v_enablelto6\ = \vga_driver_unit|un10_column_counter_siglt6_1\ # !\vga_driver_unit|column_counter_sig_4\ & !\vga_driver_unit|column_counter_sig_2\ & !\vga_driver_unit|column_counter_sig_3\
4404
4405 -- pragma translate_off
4406 GENERIC MAP (
4407         lut_mask => "f0f1",
4408         operation_mode => "normal",
4409         output_mode => "comb_only",
4410         register_cascade_mode => "off",
4411         sum_lutc_input => "datac",
4412         synch_mode => "off")
4413 -- pragma translate_on
4414 PORT MAP (
4415         dataa => \vga_driver_unit|column_counter_sig_4\,
4416         datab => \vga_driver_unit|column_counter_sig_2\,
4417         datac => \vga_driver_unit|un10_column_counter_siglt6_1\,
4418         datad => \vga_driver_unit|column_counter_sig_3\,
4419         devclrn => ww_devclrn,
4420         devpor => ww_devpor,
4421         combout => \vga_control_unit|un9_v_enablelto6\);
4422
4423 \vga_control_unit|DRAW_SQUARE_next_un9_v_enablelto9\ : stratix_lcell
4424 -- Equation(s):
4425 -- \vga_control_unit|un9_v_enablelto9\ = \vga_control_unit|un9_v_enablelto6\ & !\vga_driver_unit|column_counter_sig_9\ & !\vga_driver_unit|column_counter_sig_8\ & !\vga_driver_unit|column_counter_sig_7\
4426
4427 -- pragma translate_off
4428 GENERIC MAP (
4429         lut_mask => "0002",
4430         operation_mode => "normal",
4431         output_mode => "comb_only",
4432         register_cascade_mode => "off",
4433         sum_lutc_input => "datac",
4434         synch_mode => "off")
4435 -- pragma translate_on
4436 PORT MAP (
4437         dataa => \vga_control_unit|un9_v_enablelto6\,
4438         datab => \vga_driver_unit|column_counter_sig_9\,
4439         datac => \vga_driver_unit|column_counter_sig_8\,
4440         datad => \vga_driver_unit|column_counter_sig_7\,
4441         devclrn => ww_devclrn,
4442         devpor => ww_devpor,
4443         combout => \vga_control_unit|un9_v_enablelto9\);
4444
4445 \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4_cZ\ : stratix_lcell
4446 -- Equation(s):
4447 -- \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4\ = \vga_driver_unit|un6_dly_counter_0_x\ # !\vga_driver_unit|vsync_state_5\ & !\vga_driver_unit|vsync_state_4\
4448
4449 -- pragma translate_off
4450 GENERIC MAP (
4451         lut_mask => "f0f3",
4452         operation_mode => "normal",
4453         output_mode => "comb_only",
4454         register_cascade_mode => "off",
4455         sum_lutc_input => "datac",
4456         synch_mode => "off")
4457 -- pragma translate_on
4458 PORT MAP (
4459         datab => \vga_driver_unit|vsync_state_5\,
4460         datac => \vga_driver_unit|un6_dly_counter_0_x\,
4461         datad => \vga_driver_unit|vsync_state_4\,
4462         devclrn => ww_devclrn,
4463         devpor => ww_devpor,
4464         combout => \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4\);
4465
4466 \vga_driver_unit|h_enable_sig_Z\ : stratix_lcell
4467 -- Equation(s):
4468 -- \vga_driver_unit|h_enable_sig\ = DFFEAS(\vga_driver_unit|vsync_state_1\ # \vga_driver_unit|vsync_state_3\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
4469
4470 -- pragma translate_off
4471 GENERIC MAP (
4472         lut_mask => "ffaa",
4473         operation_mode => "normal",
4474         output_mode => "reg_only",
4475         register_cascade_mode => "off",
4476         sum_lutc_input => "datac",
4477         synch_mode => "on")
4478 -- pragma translate_on
4479 PORT MAP (
4480         clk => \clk_pin~combout\,
4481         dataa => \vga_driver_unit|vsync_state_1\,
4482         datad => \vga_driver_unit|vsync_state_3\,
4483         aclr => GND,
4484         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
4485         ena => \vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4\,
4486         devclrn => ww_devclrn,
4487         devpor => ww_devpor,
4488         regout => \vga_driver_unit|h_enable_sig\);
4489
4490 \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4_cZ\ : stratix_lcell
4491 -- Equation(s):
4492 -- \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4\ = \vga_driver_unit|un6_dly_counter_0_x\ # !\vga_driver_unit|hsync_state_4\ & !\vga_driver_unit|hsync_state_5\
4493
4494 -- pragma translate_off
4495 GENERIC MAP (
4496         lut_mask => "f0f5",
4497         operation_mode => "normal",
4498         output_mode => "comb_only",
4499         register_cascade_mode => "off",
4500         sum_lutc_input => "datac",
4501         synch_mode => "off")
4502 -- pragma translate_on
4503 PORT MAP (
4504         dataa => \vga_driver_unit|hsync_state_4\,
4505         datac => \vga_driver_unit|un6_dly_counter_0_x\,
4506         datad => \vga_driver_unit|hsync_state_5\,
4507         devclrn => ww_devclrn,
4508         devpor => ww_devpor,
4509         combout => \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4\);
4510
4511 \vga_driver_unit|v_enable_sig_Z\ : stratix_lcell
4512 -- Equation(s):
4513 -- \vga_driver_unit|v_enable_sig\ = DFFEAS(\vga_driver_unit|hsync_state_3\ # \vga_driver_unit|hsync_state_1\, GLOBAL(\clk_pin~combout\), VCC, , \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4\, , , \vga_driver_unit|un6_dly_counter_0_x\, )
4514
4515 -- pragma translate_off
4516 GENERIC MAP (
4517         lut_mask => "ffaa",
4518         operation_mode => "normal",
4519         output_mode => "reg_only",
4520         register_cascade_mode => "off",
4521         sum_lutc_input => "datac",
4522         synch_mode => "on")
4523 -- pragma translate_on
4524 PORT MAP (
4525         clk => \clk_pin~combout\,
4526         dataa => \vga_driver_unit|hsync_state_3\,
4527         datad => \vga_driver_unit|hsync_state_1\,
4528         aclr => GND,
4529         sclr => \vga_driver_unit|un6_dly_counter_0_x\,
4530         ena => \vga_driver_unit|v_enable_sig_1_0_0_0_g0_i_o4\,
4531         devclrn => ww_devclrn,
4532         devpor => ww_devpor,
4533         regout => \vga_driver_unit|v_enable_sig\);
4534
4535 \vga_control_unit|b_next_0_g0_3_cZ\ : stratix_lcell
4536 -- Equation(s):
4537 -- \vga_control_unit|b_next_0_g0_3\ = \vga_driver_unit|v_enable_sig\ & !\vga_driver_unit|column_counter_sig_9\ & !\vga_driver_unit|column_counter_sig_8\ & !\vga_driver_unit|line_counter_sig_8\
4538
4539 -- pragma translate_off
4540 GENERIC MAP (
4541         lut_mask => "0002",
4542         operation_mode => "normal",
4543         output_mode => "comb_only",
4544         register_cascade_mode => "off",
4545         sum_lutc_input => "datac",
4546         synch_mode => "off")
4547 -- pragma translate_on
4548 PORT MAP (
4549         dataa => \vga_driver_unit|v_enable_sig\,
4550         datab => \vga_driver_unit|column_counter_sig_9\,
4551         datac => \vga_driver_unit|column_counter_sig_8\,
4552         datad => \vga_driver_unit|line_counter_sig_8\,
4553         devclrn => ww_devclrn,
4554         devpor => ww_devpor,
4555         combout => \vga_control_unit|b_next_0_g0_3\);
4556
4557 \vga_control_unit|b_next_0_g0_5_cZ\ : stratix_lcell
4558 -- Equation(s):
4559 -- \vga_control_unit|b_next_0_g0_5\ = \vga_control_unit|toggle_sig\ & !\vga_control_unit|un9_v_enablelto9\ & \vga_driver_unit|h_enable_sig\ & \vga_control_unit|b_next_0_g0_3\
4560
4561 -- pragma translate_off
4562 GENERIC MAP (
4563         lut_mask => "2000",
4564         operation_mode => "normal",
4565         output_mode => "comb_only",
4566         register_cascade_mode => "off",
4567         sum_lutc_input => "datac",
4568         synch_mode => "off")
4569 -- pragma translate_on
4570 PORT MAP (
4571         dataa => \vga_control_unit|toggle_sig\,
4572         datab => \vga_control_unit|un9_v_enablelto9\,
4573         datac => \vga_driver_unit|h_enable_sig\,
4574         datad => \vga_control_unit|b_next_0_g0_3\,
4575         devclrn => ww_devclrn,
4576         devpor => ww_devpor,
4577         combout => \vga_control_unit|b_next_0_g0_5\);
4578
4579 \vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto8_a\ : stratix_lcell
4580 -- Equation(s):
4581 -- \vga_control_unit|un13_v_enablelto8_a\ = !\vga_driver_unit|line_counter_sig_2\ & !\vga_driver_unit|line_counter_sig_3\ & !\vga_driver_unit|line_counter_sig_4\ # !\vga_driver_unit|line_counter_sig_5\
4582
4583 -- pragma translate_off
4584 GENERIC MAP (
4585         lut_mask => "01ff",
4586         operation_mode => "normal",
4587         output_mode => "comb_only",
4588         register_cascade_mode => "off",
4589         sum_lutc_input => "datac",
4590         synch_mode => "off")
4591 -- pragma translate_on
4592 PORT MAP (
4593         dataa => \vga_driver_unit|line_counter_sig_2\,
4594         datab => \vga_driver_unit|line_counter_sig_3\,
4595         datac => \vga_driver_unit|line_counter_sig_4\,
4596         datad => \vga_driver_unit|line_counter_sig_5\,
4597         devclrn => ww_devclrn,
4598         devpor => ww_devpor,
4599         combout => \vga_control_unit|un13_v_enablelto8_a\);
4600
4601 \vga_control_unit|DRAW_SQUARE_next_un13_v_enablelto8\ : stratix_lcell
4602 -- Equation(s):
4603 -- \vga_control_unit|un13_v_enablelto8\ = !\vga_driver_unit|line_counter_sig_8\ & !\vga_driver_unit|line_counter_sig_7\ & (\vga_control_unit|un13_v_enablelto8_a\ # !\vga_driver_unit|line_counter_sig_6\)
4604
4605 -- pragma translate_off
4606 GENERIC MAP (
4607         lut_mask => "0501",
4608         operation_mode => "normal",
4609         output_mode => "comb_only",
4610         register_cascade_mode => "off",
4611         sum_lutc_input => "datac",
4612         synch_mode => "off")
4613 -- pragma translate_on
4614 PORT MAP (
4615         dataa => \vga_driver_unit|line_counter_sig_8\,
4616         datab => \vga_driver_unit|line_counter_sig_6\,
4617         datac => \vga_driver_unit|line_counter_sig_7\,
4618         datad => \vga_control_unit|un13_v_enablelto8_a\,
4619         devclrn => ww_devclrn,
4620         devpor => ww_devpor,
4621         combout => \vga_control_unit|un13_v_enablelto8\);
4622
4623 \vga_control_unit|b_Z\ : stratix_lcell
4624 -- Equation(s):
4625 -- \vga_control_unit|b\ = DFFEAS(!\vga_control_unit|un5_v_enablelto7\ & !\vga_control_unit|un17_v_enablelto7\ & \vga_control_unit|b_next_0_g0_5\ & !\vga_control_unit|un13_v_enablelto8\, GLOBAL(\clk_pin~combout\),
4626 -- !GLOBAL(\vga_driver_unit|un6_dly_counter_0_x\), , , , , , )
4627
4628 -- pragma translate_off
4629 GENERIC MAP (
4630         lut_mask => "0010",
4631         operation_mode => "normal",
4632         output_mode => "reg_only",
4633         register_cascade_mode => "off",
4634         sum_lutc_input => "datac",
4635         synch_mode => "off")
4636 -- pragma translate_on
4637 PORT MAP (
4638         clk => \clk_pin~combout\,
4639         dataa => \vga_control_unit|un5_v_enablelto7\,
4640         datab => \vga_control_unit|un17_v_enablelto7\,
4641         datac => \vga_control_unit|b_next_0_g0_5\,
4642         datad => \vga_control_unit|un13_v_enablelto8\,
4643         aclr => \vga_driver_unit|un6_dly_counter_0_x\,
4644         devclrn => ww_devclrn,
4645         devpor => ww_devpor,
4646         regout => \vga_control_unit|b\);
4647
4648 \vga_driver_unit|un1_hsync_state_3_0_cZ\ : stratix_lcell
4649 -- Equation(s):
4650 -- \vga_driver_unit|un1_hsync_state_3_0\ = \vga_driver_unit|hsync_state_3\ # \vga_driver_unit|hsync_state_1\
4651
4652 -- pragma translate_off
4653 GENERIC MAP (
4654         lut_mask => "fff0",
4655         operation_mode => "normal",
4656         output_mode => "comb_only",
4657         register_cascade_mode => "off",
4658         sum_lutc_input => "datac",
4659         synch_mode => "off")
4660 -- pragma translate_on
4661 PORT MAP (
4662         datac => \vga_driver_unit|hsync_state_3\,
4663         datad => \vga_driver_unit|hsync_state_1\,
4664         devclrn => ww_devclrn,
4665         devpor => ww_devpor,
4666         combout => \vga_driver_unit|un1_hsync_state_3_0\);
4667
4668 \vga_driver_unit|h_sync_1_0_0_0_g1_cZ\ : stratix_lcell
4669 -- Equation(s):
4670 -- \vga_driver_unit|h_sync_1_0_0_0_g1\ = \vga_driver_unit|un1_hsync_state_3_0\ & (\vga_driver_unit|h_sync\) # !\vga_driver_unit|un1_hsync_state_3_0\ & (\vga_driver_unit|hsync_state_2\ & (\vga_driver_unit|h_sync\) # !\vga_driver_unit|hsync_state_2\ &
4671 -- \vga_driver_unit|hsync_state_4\)
4672
4673 -- pragma translate_off
4674 GENERIC MAP (
4675         lut_mask => "ccca",
4676         operation_mode => "normal",
4677         output_mode => "comb_only",
4678         register_cascade_mode => "off",
4679         sum_lutc_input => "datac",
4680         synch_mode => "off")
4681 -- pragma translate_on
4682 PORT MAP (
4683         dataa => \vga_driver_unit|hsync_state_4\,
4684         datab => \vga_driver_unit|h_sync\,
4685         datac => \vga_driver_unit|un1_hsync_state_3_0\,
4686         datad => \vga_driver_unit|hsync_state_2\,
4687         devclrn => ww_devclrn,
4688         devpor => ww_devpor,
4689         combout => \vga_driver_unit|h_sync_1_0_0_0_g1\);
4690
4691 \vga_driver_unit|h_sync_Z\ : stratix_lcell
4692 -- Equation(s):
4693 -- \vga_driver_unit|h_sync\ = DFFEAS(\vga_driver_unit|h_sync_1_0_0_0_g1\ # !\reset_pin~combout\ # !dly_counter(0) # !dly_counter(1), GLOBAL(\clk_pin~combout\), VCC, , , , , , )
4694
4695 -- pragma translate_off
4696 GENERIC MAP (
4697         lut_mask => "ff7f",
4698         operation_mode => "normal",
4699         output_mode => "reg_only",
4700         register_cascade_mode => "off",
4701         sum_lutc_input => "datac",
4702         synch_mode => "off")
4703 -- pragma translate_on
4704 PORT MAP (
4705         clk => \clk_pin~combout\,
4706         dataa => dly_counter(1),
4707         datab => dly_counter(0),
4708         datac => \reset_pin~combout\,
4709         datad => \vga_driver_unit|h_sync_1_0_0_0_g1\,
4710         aclr => GND,
4711         devclrn => ww_devclrn,
4712         devpor => ww_devpor,
4713         regout => \vga_driver_unit|h_sync\);
4714
4715 \vga_driver_unit|un1_vsync_state_2_0_cZ\ : stratix_lcell
4716 -- Equation(s):
4717 -- \vga_driver_unit|un1_vsync_state_2_0\ = \vga_driver_unit|vsync_state_3\ # \vga_driver_unit|vsync_state_1\
4718
4719 -- pragma translate_off
4720 GENERIC MAP (
4721         lut_mask => "fafa",
4722         operation_mode => "normal",
4723         output_mode => "comb_only",
4724         register_cascade_mode => "off",
4725         sum_lutc_input => "datac",
4726         synch_mode => "off")
4727 -- pragma translate_on
4728 PORT MAP (
4729         dataa => \vga_driver_unit|vsync_state_3\,
4730         datac => \vga_driver_unit|vsync_state_1\,
4731         devclrn => ww_devclrn,
4732         devpor => ww_devpor,
4733         combout => \vga_driver_unit|un1_vsync_state_2_0\);
4734
4735 \vga_driver_unit|v_sync_1_0_0_0_g1_cZ\ : stratix_lcell
4736 -- Equation(s):
4737 -- \vga_driver_unit|v_sync_1_0_0_0_g1\ = \vga_driver_unit|un1_vsync_state_2_0\ & (\vga_driver_unit|v_sync\) # !\vga_driver_unit|un1_vsync_state_2_0\ & (\vga_driver_unit|vsync_state_2\ & (\vga_driver_unit|v_sync\) # !\vga_driver_unit|vsync_state_2\ &
4738 -- \vga_driver_unit|vsync_state_4\)
4739
4740 -- pragma translate_off
4741 GENERIC MAP (
4742         lut_mask => "fe10",
4743         operation_mode => "normal",
4744         output_mode => "comb_only",
4745         register_cascade_mode => "off",
4746         sum_lutc_input => "datac",
4747         synch_mode => "off")
4748 -- pragma translate_on
4749 PORT MAP (
4750         dataa => \vga_driver_unit|un1_vsync_state_2_0\,
4751         datab => \vga_driver_unit|vsync_state_2\,
4752         datac => \vga_driver_unit|vsync_state_4\,
4753         datad => \vga_driver_unit|v_sync\,
4754         devclrn => ww_devclrn,
4755         devpor => ww_devpor,
4756         combout => \vga_driver_unit|v_sync_1_0_0_0_g1\);
4757
4758 \vga_driver_unit|v_sync_Z\ : stratix_lcell
4759 -- Equation(s):
4760 -- \vga_driver_unit|v_sync\ = DFFEAS(\vga_driver_unit|v_sync_1_0_0_0_g1\ # !\reset_pin~combout\ # !dly_counter(1) # !dly_counter(0), GLOBAL(\clk_pin~combout\), VCC, , , , , , )
4761
4762 -- pragma translate_off
4763 GENERIC MAP (
4764         lut_mask => "bfff",
4765         operation_mode => "normal",
4766         output_mode => "reg_only",
4767         register_cascade_mode => "off",
4768         sum_lutc_input => "datac",
4769         synch_mode => "off")
4770 -- pragma translate_on
4771 PORT MAP (
4772         clk => \clk_pin~combout\,
4773         dataa => \vga_driver_unit|v_sync_1_0_0_0_g1\,
4774         datab => dly_counter(0),
4775         datac => dly_counter(1),
4776         datad => \reset_pin~combout\,
4777         aclr => GND,
4778         devclrn => ww_devclrn,
4779         devpor => ww_devpor,
4780         regout => \vga_driver_unit|v_sync\);
4781
4782 r0_pin_out : stratix_io
4783 -- pragma translate_off
4784 GENERIC MAP (
4785         ddio_mode => "none",
4786         input_async_reset => "none",
4787         input_power_up => "low",
4788         input_register_mode => "none",
4789         input_sync_reset => "none",
4790         oe_async_reset => "none",
4791         oe_power_up => "low",
4792         oe_register_mode => "none",
4793         oe_sync_reset => "none",
4794         operation_mode => "output",
4795         output_async_reset => "none",
4796         output_power_up => "low",
4797         output_register_mode => "none",
4798         output_sync_reset => "none")
4799 -- pragma translate_on
4800 PORT MAP (
4801         datain => \~STRATIX_FITTER_CREATED_GND~I_combout\,
4802         devclrn => ww_devclrn,
4803         devpor => ww_devpor,
4804         devoe => ww_devoe,
4805         oe => VCC,
4806         padio => ww_r0_pin);
4807
4808 r1_pin_out : stratix_io
4809 -- pragma translate_off
4810 GENERIC MAP (
4811         ddio_mode => "none",
4812         input_async_reset => "none",
4813         input_power_up => "low",
4814         input_register_mode => "none",
4815         input_sync_reset => "none",
4816         oe_async_reset => "none",
4817         oe_power_up => "low",
4818         oe_register_mode => "none",
4819         oe_sync_reset => "none",
4820         operation_mode => "output",
4821         output_async_reset => "none",
4822         output_power_up => "low",
4823         output_register_mode => "none",
4824         output_sync_reset => "none")
4825 -- pragma translate_on
4826 PORT MAP (
4827         datain => \~STRATIX_FITTER_CREATED_GND~I_combout\,
4828         devclrn => ww_devclrn,
4829         devpor => ww_devpor,
4830         devoe => ww_devoe,
4831         oe => VCC,
4832         padio => ww_r1_pin);
4833
4834 r2_pin_out : stratix_io
4835 -- pragma translate_off
4836 GENERIC MAP (
4837         ddio_mode => "none",
4838         input_async_reset => "none",
4839         input_power_up => "low",
4840         input_register_mode => "none",
4841         input_sync_reset => "none",
4842         oe_async_reset => "none",
4843         oe_power_up => "low",
4844         oe_register_mode => "none",
4845         oe_sync_reset => "none",
4846         operation_mode => "output",
4847         output_async_reset => "none",
4848         output_power_up => "low",
4849         output_register_mode => "none",
4850         output_sync_reset => "none")
4851 -- pragma translate_on
4852 PORT MAP (
4853         datain => \~STRATIX_FITTER_CREATED_GND~I_combout\,
4854         devclrn => ww_devclrn,
4855         devpor => ww_devpor,
4856         devoe => ww_devoe,
4857         oe => VCC,
4858         padio => ww_r2_pin);
4859
4860 g0_pin_out : stratix_io
4861 -- pragma translate_off
4862 GENERIC MAP (
4863         ddio_mode => "none",
4864         input_async_reset => "none",
4865         input_power_up => "low",
4866         input_register_mode => "none",
4867         input_sync_reset => "none",
4868         oe_async_reset => "none",
4869         oe_power_up => "low",
4870         oe_register_mode => "none",
4871         oe_sync_reset => "none",
4872         operation_mode => "output",
4873         output_async_reset => "none",
4874         output_power_up => "low",
4875         output_register_mode => "none",
4876         output_sync_reset => "none")
4877 -- pragma translate_on
4878 PORT MAP (
4879         datain => \~STRATIX_FITTER_CREATED_GND~I_combout\,
4880         devclrn => ww_devclrn,
4881         devpor => ww_devpor,
4882         devoe => ww_devoe,
4883         oe => VCC,
4884         padio => ww_g0_pin);
4885
4886 g1_pin_out : stratix_io
4887 -- pragma translate_off
4888 GENERIC MAP (
4889         ddio_mode => "none",
4890         input_async_reset => "none",
4891         input_power_up => "low",
4892         input_register_mode => "none",
4893         input_sync_reset => "none",
4894         oe_async_reset => "none",
4895         oe_power_up => "low",
4896         oe_register_mode => "none",
4897         oe_sync_reset => "none",
4898         operation_mode => "output",
4899         output_async_reset => "none",
4900         output_power_up => "low",
4901         output_register_mode => "none",
4902         output_sync_reset => "none")
4903 -- pragma translate_on
4904 PORT MAP (
4905         datain => \~STRATIX_FITTER_CREATED_GND~I_combout\,
4906         devclrn => ww_devclrn,
4907         devpor => ww_devpor,
4908         devoe => ww_devoe,
4909         oe => VCC,
4910         padio => ww_g1_pin);
4911
4912 g2_pin_out : stratix_io
4913 -- pragma translate_off
4914 GENERIC MAP (
4915         ddio_mode => "none",
4916         input_async_reset => "none",
4917         input_power_up => "low",
4918         input_register_mode => "none",
4919         input_sync_reset => "none",
4920         oe_async_reset => "none",
4921         oe_power_up => "low",
4922         oe_register_mode => "none",
4923         oe_sync_reset => "none",
4924         operation_mode => "output",
4925         output_async_reset => "none",
4926         output_power_up => "low",
4927         output_register_mode => "none",
4928         output_sync_reset => "none")
4929 -- pragma translate_on
4930 PORT MAP (
4931         datain => \~STRATIX_FITTER_CREATED_GND~I_combout\,
4932         devclrn => ww_devclrn,
4933         devpor => ww_devpor,
4934         devoe => ww_devoe,
4935         oe => VCC,
4936         padio => ww_g2_pin);
4937
4938 b0_pin_out : stratix_io
4939 -- pragma translate_off
4940 GENERIC MAP (
4941         ddio_mode => "none",
4942         input_async_reset => "none",
4943         input_power_up => "low",
4944         input_register_mode => "none",
4945         input_sync_reset => "none",
4946         oe_async_reset => "none",
4947         oe_power_up => "low",
4948         oe_register_mode => "none",
4949         oe_sync_reset => "none",
4950         operation_mode => "output",
4951         output_async_reset => "none",
4952         output_power_up => "low",
4953         output_register_mode => "none",
4954         output_sync_reset => "none")
4955 -- pragma translate_on
4956 PORT MAP (
4957         datain => \vga_control_unit|b\,
4958         devclrn => ww_devclrn,
4959         devpor => ww_devpor,
4960         devoe => ww_devoe,
4961         oe => VCC,
4962         padio => ww_b0_pin);
4963
4964 b1_pin_out : stratix_io
4965 -- pragma translate_off
4966 GENERIC MAP (
4967         ddio_mode => "none",
4968         input_async_reset => "none",
4969         input_power_up => "low",
4970         input_register_mode => "none",
4971         input_sync_reset => "none",
4972         oe_async_reset => "none",
4973         oe_power_up => "low",
4974         oe_register_mode => "none",
4975         oe_sync_reset => "none",
4976         operation_mode => "output",
4977         output_async_reset => "none",
4978         output_power_up => "low",
4979         output_register_mode => "none",
4980         output_sync_reset => "none")
4981 -- pragma translate_on
4982 PORT MAP (
4983         datain => \vga_control_unit|b\,
4984         devclrn => ww_devclrn,
4985         devpor => ww_devpor,
4986         devoe => ww_devoe,
4987         oe => VCC,
4988         padio => ww_b1_pin);
4989
4990 hsync_pin_out : stratix_io
4991 -- pragma translate_off
4992 GENERIC MAP (
4993         ddio_mode => "none",
4994         input_async_reset => "none",
4995         input_power_up => "low",
4996         input_register_mode => "none",
4997         input_sync_reset => "none",
4998         oe_async_reset => "none",
4999         oe_power_up => "low",
5000         oe_register_mode => "none",
5001         oe_sync_reset => "none",
5002         operation_mode => "output",
5003         output_async_reset => "none",
5004         output_power_up => "low",
5005         output_register_mode => "none",
5006         output_sync_reset => "none")
5007 -- pragma translate_on
5008 PORT MAP (
5009         datain => \vga_driver_unit|h_sync\,
5010         devclrn => ww_devclrn,
5011         devpor => ww_devpor,
5012         devoe => ww_devoe,
5013         oe => VCC,
5014         padio => ww_hsync_pin);
5015
5016 vsync_pin_out : stratix_io
5017 -- pragma translate_off
5018 GENERIC MAP (
5019         ddio_mode => "none",
5020         input_async_reset => "none",
5021         input_power_up => "low",
5022         input_register_mode => "none",
5023         input_sync_reset => "none",
5024         oe_async_reset => "none",
5025         oe_power_up => "low",
5026         oe_register_mode => "none",
5027         oe_sync_reset => "none",
5028         operation_mode => "output",
5029         output_async_reset => "none",
5030         output_power_up => "low",
5031         output_register_mode => "none",
5032         output_sync_reset => "none")
5033 -- pragma translate_on
5034 PORT MAP (
5035         datain => \vga_driver_unit|v_sync\,
5036         devclrn => ww_devclrn,
5037         devpor => ww_devpor,
5038         devoe => ww_devoe,
5039         oe => VCC,
5040         padio => ww_vsync_pin);
5041
5042 \seven_seg_pin_tri_0_\ : stratix_io
5043 -- pragma translate_off
5044 GENERIC MAP (
5045         ddio_mode => "none",
5046         input_async_reset => "none",
5047         input_power_up => "low",
5048         input_register_mode => "none",
5049         input_sync_reset => "none",
5050         oe_async_reset => "none",
5051         oe_power_up => "low",
5052         oe_register_mode => "none",
5053         oe_sync_reset => "none",
5054         operation_mode => "output",
5055         output_async_reset => "none",
5056         output_power_up => "low",
5057         output_register_mode => "none",
5058         output_sync_reset => "none")
5059 -- pragma translate_on
5060 PORT MAP (
5061         datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\,
5062         devclrn => ww_devclrn,
5063         devpor => ww_devpor,
5064         devoe => ww_devoe,
5065         oe => VCC,
5066         padio => ww_seven_seg_pin(0));
5067
5068 \seven_seg_pin_out_1_\ : stratix_io
5069 -- pragma translate_off
5070 GENERIC MAP (
5071         ddio_mode => "none",
5072         input_async_reset => "none",
5073         input_power_up => "low",
5074         input_register_mode => "none",
5075         input_sync_reset => "none",
5076         oe_async_reset => "none",
5077         oe_power_up => "low",
5078         oe_register_mode => "none",
5079         oe_sync_reset => "none",
5080         operation_mode => "output",
5081         output_async_reset => "none",
5082         output_power_up => "low",
5083         output_register_mode => "none",
5084         output_sync_reset => "none")
5085 -- pragma translate_on
5086 PORT MAP (
5087         datain => \vga_driver_unit|un6_dly_counter_0_x\,
5088         devclrn => ww_devclrn,
5089         devpor => ww_devpor,
5090         devoe => ww_devoe,
5091         oe => VCC,
5092         padio => ww_seven_seg_pin(1));
5093
5094 \seven_seg_pin_out_2_\ : stratix_io
5095 -- pragma translate_off
5096 GENERIC MAP (
5097         ddio_mode => "none",
5098         input_async_reset => "none",
5099         input_power_up => "low",
5100         input_register_mode => "none",
5101         input_sync_reset => "none",
5102         oe_async_reset => "none",
5103         oe_power_up => "low",
5104         oe_register_mode => "none",
5105         oe_sync_reset => "none",
5106         operation_mode => "output",
5107         output_async_reset => "none",
5108         output_power_up => "low",
5109         output_register_mode => "none",
5110         output_sync_reset => "none")
5111 -- pragma translate_on
5112 PORT MAP (
5113         datain => \vga_driver_unit|un6_dly_counter_0_x\,
5114         devclrn => ww_devclrn,
5115         devpor => ww_devpor,
5116         devoe => ww_devoe,
5117         oe => VCC,
5118         padio => ww_seven_seg_pin(2));
5119
5120 \seven_seg_pin_tri_3_\ : stratix_io
5121 -- pragma translate_off
5122 GENERIC MAP (
5123         ddio_mode => "none",
5124         input_async_reset => "none",
5125         input_power_up => "low",
5126         input_register_mode => "none",
5127         input_sync_reset => "none",
5128         oe_async_reset => "none",
5129         oe_power_up => "low",
5130         oe_register_mode => "none",
5131         oe_sync_reset => "none",
5132         operation_mode => "output",
5133         output_async_reset => "none",
5134         output_power_up => "low",
5135         output_register_mode => "none",
5136         output_sync_reset => "none")
5137 -- pragma translate_on
5138 PORT MAP (
5139         datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\,
5140         devclrn => ww_devclrn,
5141         devpor => ww_devpor,
5142         devoe => ww_devoe,
5143         oe => VCC,
5144         padio => ww_seven_seg_pin(3));
5145
5146 \seven_seg_pin_tri_4_\ : stratix_io
5147 -- pragma translate_off
5148 GENERIC MAP (
5149         ddio_mode => "none",
5150         input_async_reset => "none",
5151         input_power_up => "low",
5152         input_register_mode => "none",
5153         input_sync_reset => "none",
5154         oe_async_reset => "none",
5155         oe_power_up => "low",
5156         oe_register_mode => "none",
5157         oe_sync_reset => "none",
5158         operation_mode => "output",
5159         output_async_reset => "none",
5160         output_power_up => "low",
5161         output_register_mode => "none",
5162         output_sync_reset => "none")
5163 -- pragma translate_on
5164 PORT MAP (
5165         datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\,
5166         devclrn => ww_devclrn,
5167         devpor => ww_devpor,
5168         devoe => ww_devoe,
5169         oe => VCC,
5170         padio => ww_seven_seg_pin(4));
5171
5172 \seven_seg_pin_tri_5_\ : stratix_io
5173 -- pragma translate_off
5174 GENERIC MAP (
5175         ddio_mode => "none",
5176         input_async_reset => "none",
5177         input_power_up => "low",
5178         input_register_mode => "none",
5179         input_sync_reset => "none",
5180         oe_async_reset => "none",
5181         oe_power_up => "low",
5182         oe_register_mode => "none",
5183         oe_sync_reset => "none",
5184         operation_mode => "output",
5185         output_async_reset => "none",
5186         output_power_up => "low",
5187         output_register_mode => "none",
5188         output_sync_reset => "none")
5189 -- pragma translate_on
5190 PORT MAP (
5191         datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\,
5192         devclrn => ww_devclrn,
5193         devpor => ww_devpor,
5194         devoe => ww_devoe,
5195         oe => VCC,
5196         padio => ww_seven_seg_pin(5));
5197
5198 \seven_seg_pin_tri_6_\ : stratix_io
5199 -- pragma translate_off
5200 GENERIC MAP (
5201         ddio_mode => "none",
5202         input_async_reset => "none",
5203         input_power_up => "low",
5204         input_register_mode => "none",
5205         input_sync_reset => "none",
5206         oe_async_reset => "none",
5207         oe_power_up => "low",
5208         oe_register_mode => "none",
5209         oe_sync_reset => "none",
5210         operation_mode => "output",
5211         output_async_reset => "none",
5212         output_power_up => "low",
5213         output_register_mode => "none",
5214         output_sync_reset => "none")
5215 -- pragma translate_on
5216 PORT MAP (
5217         datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\,
5218         devclrn => ww_devclrn,
5219         devpor => ww_devpor,
5220         devoe => ww_devoe,
5221         oe => VCC,
5222         padio => ww_seven_seg_pin(6));
5223
5224 \seven_seg_pin_out_7_\ : stratix_io
5225 -- pragma translate_off
5226 GENERIC MAP (
5227         ddio_mode => "none",
5228         input_async_reset => "none",
5229         input_power_up => "low",
5230         input_register_mode => "none",
5231         input_sync_reset => "none",
5232         oe_async_reset => "none",
5233         oe_power_up => "low",
5234         oe_register_mode => "none",
5235         oe_sync_reset => "none",
5236         operation_mode => "output",
5237         output_async_reset => "none",
5238         output_power_up => "low",
5239         output_register_mode => "none",
5240         output_sync_reset => "none")
5241 -- pragma translate_on
5242 PORT MAP (
5243         datain => \vga_driver_unit|un6_dly_counter_0_x\,
5244         devclrn => ww_devclrn,
5245         devpor => ww_devpor,
5246         devoe => ww_devoe,
5247         oe => VCC,
5248         padio => ww_seven_seg_pin(7));
5249
5250 \seven_seg_pin_out_8_\ : stratix_io
5251 -- pragma translate_off
5252 GENERIC MAP (
5253         ddio_mode => "none",
5254         input_async_reset => "none",
5255         input_power_up => "low",
5256         input_register_mode => "none",
5257         input_sync_reset => "none",
5258         oe_async_reset => "none",
5259         oe_power_up => "low",
5260         oe_register_mode => "none",
5261         oe_sync_reset => "none",
5262         operation_mode => "output",
5263         output_async_reset => "none",
5264         output_power_up => "low",
5265         output_register_mode => "none",
5266         output_sync_reset => "none")
5267 -- pragma translate_on
5268 PORT MAP (
5269         datain => \vga_driver_unit|un6_dly_counter_0_x\,
5270         devclrn => ww_devclrn,
5271         devpor => ww_devpor,
5272         devoe => ww_devoe,
5273         oe => VCC,
5274         padio => ww_seven_seg_pin(8));
5275
5276 \seven_seg_pin_out_9_\ : stratix_io
5277 -- pragma translate_off
5278 GENERIC MAP (
5279         ddio_mode => "none",
5280         input_async_reset => "none",
5281         input_power_up => "low",
5282         input_register_mode => "none",
5283         input_sync_reset => "none",
5284         oe_async_reset => "none",
5285         oe_power_up => "low",
5286         oe_register_mode => "none",
5287         oe_sync_reset => "none",
5288         operation_mode => "output",
5289         output_async_reset => "none",
5290         output_power_up => "low",
5291         output_register_mode => "none",
5292         output_sync_reset => "none")
5293 -- pragma translate_on
5294 PORT MAP (
5295         datain => \vga_driver_unit|un6_dly_counter_0_x\,
5296         devclrn => ww_devclrn,
5297         devpor => ww_devpor,
5298         devoe => ww_devoe,
5299         oe => VCC,
5300         padio => ww_seven_seg_pin(9));
5301
5302 \seven_seg_pin_out_10_\ : stratix_io
5303 -- pragma translate_off
5304 GENERIC MAP (
5305         ddio_mode => "none",
5306         input_async_reset => "none",
5307         input_power_up => "low",
5308         input_register_mode => "none",
5309         input_sync_reset => "none",
5310         oe_async_reset => "none",
5311         oe_power_up => "low",
5312         oe_register_mode => "none",
5313         oe_sync_reset => "none",
5314         operation_mode => "output",
5315         output_async_reset => "none",
5316         output_power_up => "low",
5317         output_register_mode => "none",
5318         output_sync_reset => "none")
5319 -- pragma translate_on
5320 PORT MAP (
5321         datain => \vga_driver_unit|un6_dly_counter_0_x\,
5322         devclrn => ww_devclrn,
5323         devpor => ww_devpor,
5324         devoe => ww_devoe,
5325         oe => VCC,
5326         padio => ww_seven_seg_pin(10));
5327
5328 \seven_seg_pin_out_11_\ : stratix_io
5329 -- pragma translate_off
5330 GENERIC MAP (
5331         ddio_mode => "none",
5332         input_async_reset => "none",
5333         input_power_up => "low",
5334         input_register_mode => "none",
5335         input_sync_reset => "none",
5336         oe_async_reset => "none",
5337         oe_power_up => "low",
5338         oe_register_mode => "none",
5339         oe_sync_reset => "none",
5340         operation_mode => "output",
5341         output_async_reset => "none",
5342         output_power_up => "low",
5343         output_register_mode => "none",
5344         output_sync_reset => "none")
5345 -- pragma translate_on
5346 PORT MAP (
5347         datain => \vga_driver_unit|un6_dly_counter_0_x\,
5348         devclrn => ww_devclrn,
5349         devpor => ww_devpor,
5350         devoe => ww_devoe,
5351         oe => VCC,
5352         padio => ww_seven_seg_pin(11));
5353
5354 \seven_seg_pin_out_12_\ : stratix_io
5355 -- pragma translate_off
5356 GENERIC MAP (
5357         ddio_mode => "none",
5358         input_async_reset => "none",
5359         input_power_up => "low",
5360         input_register_mode => "none",
5361         input_sync_reset => "none",
5362         oe_async_reset => "none",
5363         oe_power_up => "low",
5364         oe_register_mode => "none",
5365         oe_sync_reset => "none",
5366         operation_mode => "output",
5367         output_async_reset => "none",
5368         output_power_up => "low",
5369         output_register_mode => "none",
5370         output_sync_reset => "none")
5371 -- pragma translate_on
5372 PORT MAP (
5373         datain => \vga_driver_unit|un6_dly_counter_0_x\,
5374         devclrn => ww_devclrn,
5375         devpor => ww_devpor,
5376         devoe => ww_devoe,
5377         oe => VCC,
5378         padio => ww_seven_seg_pin(12));
5379
5380 \seven_seg_pin_tri_13_\ : stratix_io
5381 -- pragma translate_off
5382 GENERIC MAP (
5383         ddio_mode => "none",
5384         input_async_reset => "none",
5385         input_power_up => "low",
5386         input_register_mode => "none",
5387         input_sync_reset => "none",
5388         oe_async_reset => "none",
5389         oe_power_up => "low",
5390         oe_register_mode => "none",
5391         oe_sync_reset => "none",
5392         operation_mode => "output",
5393         output_async_reset => "none",
5394         output_power_up => "low",
5395         output_register_mode => "none",
5396         output_sync_reset => "none")
5397 -- pragma translate_on
5398 PORT MAP (
5399         datain => \ALT_INV_~STRATIX_FITTER_CREATED_GND~I_combout\,
5400         devclrn => ww_devclrn,
5401         devpor => ww_devpor,
5402         devoe => ww_devoe,
5403         oe => VCC,
5404         padio => ww_seven_seg_pin(13));
5405
5406 d_hsync_out : stratix_io
5407 -- pragma translate_off
5408 GENERIC MAP (
5409         ddio_mode => "none",
5410         input_async_reset => "none",
5411         input_power_up => "low",
5412         input_register_mode => "none",
5413         input_sync_reset => "none",
5414         oe_async_reset => "none",
5415         oe_power_up => "low",
5416         oe_register_mode => "none",
5417         oe_sync_reset => "none",
5418         operation_mode => "output",
5419         output_async_reset => "none",
5420         output_power_up => "low",
5421         output_register_mode => "none",
5422         output_sync_reset => "none")
5423 -- pragma translate_on
5424 PORT MAP (
5425         datain => \vga_driver_unit|h_sync\,
5426         devclrn => ww_devclrn,
5427         devpor => ww_devpor,
5428         devoe => ww_devoe,
5429         oe => VCC,
5430         padio => ww_d_hsync);
5431
5432 d_vsync_out : stratix_io
5433 -- pragma translate_off
5434 GENERIC MAP (
5435         ddio_mode => "none",
5436         input_async_reset => "none",
5437         input_power_up => "low",
5438         input_register_mode => "none",
5439         input_sync_reset => "none",
5440         oe_async_reset => "none",
5441         oe_power_up => "low",
5442         oe_register_mode => "none",
5443         oe_sync_reset => "none",
5444         operation_mode => "output",
5445         output_async_reset => "none",
5446         output_power_up => "low",
5447         output_register_mode => "none",
5448         output_sync_reset => "none")
5449 -- pragma translate_on
5450 PORT MAP (
5451         datain => \vga_driver_unit|v_sync\,
5452         devclrn => ww_devclrn,
5453         devpor => ww_devpor,
5454         devoe => ww_devoe,
5455         oe => VCC,
5456         padio => ww_d_vsync);
5457
5458 \d_column_counter_out_0_\ : stratix_io
5459 -- pragma translate_off
5460 GENERIC MAP (
5461         ddio_mode => "none",
5462         input_async_reset => "none",
5463         input_power_up => "low",
5464         input_register_mode => "none",
5465         input_sync_reset => "none",
5466         oe_async_reset => "none",
5467         oe_power_up => "low",
5468         oe_register_mode => "none",
5469         oe_sync_reset => "none",
5470         operation_mode => "output",
5471         output_async_reset => "none",
5472         output_power_up => "low",
5473         output_register_mode => "none",
5474         output_sync_reset => "none")
5475 -- pragma translate_on
5476 PORT MAP (
5477         datain => \vga_driver_unit|column_counter_sig_0\,
5478         devclrn => ww_devclrn,
5479         devpor => ww_devpor,
5480         devoe => ww_devoe,
5481         oe => VCC,
5482         padio => ww_d_column_counter(0));
5483
5484 \d_column_counter_out_1_\ : stratix_io
5485 -- pragma translate_off
5486 GENERIC MAP (
5487         ddio_mode => "none",
5488         input_async_reset => "none",
5489         input_power_up => "low",
5490         input_register_mode => "none",
5491         input_sync_reset => "none",
5492         oe_async_reset => "none",
5493         oe_power_up => "low",
5494         oe_register_mode => "none",
5495         oe_sync_reset => "none",
5496         operation_mode => "output",
5497         output_async_reset => "none",
5498         output_power_up => "low",
5499         output_register_mode => "none",
5500         output_sync_reset => "none")
5501 -- pragma translate_on
5502 PORT MAP (
5503         datain => \vga_driver_unit|column_counter_sig_1\,
5504         devclrn => ww_devclrn,
5505         devpor => ww_devpor,
5506         devoe => ww_devoe,
5507         oe => VCC,
5508         padio => ww_d_column_counter(1));
5509
5510 \d_column_counter_out_2_\ : stratix_io
5511 -- pragma translate_off
5512 GENERIC MAP (
5513         ddio_mode => "none",
5514         input_async_reset => "none",
5515         input_power_up => "low",
5516         input_register_mode => "none",
5517         input_sync_reset => "none",
5518         oe_async_reset => "none",
5519         oe_power_up => "low",
5520         oe_register_mode => "none",
5521         oe_sync_reset => "none",
5522         operation_mode => "output",
5523         output_async_reset => "none",
5524         output_power_up => "low",
5525         output_register_mode => "none",
5526         output_sync_reset => "none")
5527 -- pragma translate_on
5528 PORT MAP (
5529         datain => \vga_driver_unit|column_counter_sig_2\,
5530         devclrn => ww_devclrn,
5531         devpor => ww_devpor,
5532         devoe => ww_devoe,
5533         oe => VCC,
5534         padio => ww_d_column_counter(2));
5535
5536 \d_column_counter_out_3_\ : stratix_io
5537 -- pragma translate_off
5538 GENERIC MAP (
5539         ddio_mode => "none",
5540         input_async_reset => "none",
5541         input_power_up => "low",
5542         input_register_mode => "none",
5543         input_sync_reset => "none",
5544         oe_async_reset => "none",
5545         oe_power_up => "low",
5546         oe_register_mode => "none",
5547         oe_sync_reset => "none",
5548         operation_mode => "output",
5549         output_async_reset => "none",
5550         output_power_up => "low",
5551         output_register_mode => "none",
5552         output_sync_reset => "none")
5553 -- pragma translate_on
5554 PORT MAP (
5555         datain => \vga_driver_unit|column_counter_sig_3\,
5556         devclrn => ww_devclrn,
5557         devpor => ww_devpor,
5558         devoe => ww_devoe,
5559         oe => VCC,
5560         padio => ww_d_column_counter(3));
5561
5562 \d_column_counter_out_4_\ : stratix_io
5563 -- pragma translate_off
5564 GENERIC MAP (
5565         ddio_mode => "none",
5566         input_async_reset => "none",
5567         input_power_up => "low",
5568         input_register_mode => "none",
5569         input_sync_reset => "none",
5570         oe_async_reset => "none",
5571         oe_power_up => "low",
5572         oe_register_mode => "none",
5573         oe_sync_reset => "none",
5574         operation_mode => "output",
5575         output_async_reset => "none",
5576         output_power_up => "low",
5577         output_register_mode => "none",
5578         output_sync_reset => "none")
5579 -- pragma translate_on
5580 PORT MAP (
5581         datain => \vga_driver_unit|column_counter_sig_4\,
5582         devclrn => ww_devclrn,
5583         devpor => ww_devpor,
5584         devoe => ww_devoe,
5585         oe => VCC,
5586         padio => ww_d_column_counter(4));
5587
5588 \d_column_counter_out_5_\ : stratix_io
5589 -- pragma translate_off
5590 GENERIC MAP (
5591         ddio_mode => "none",
5592         input_async_reset => "none",
5593         input_power_up => "low",
5594         input_register_mode => "none",
5595         input_sync_reset => "none",
5596         oe_async_reset => "none",
5597         oe_power_up => "low",
5598         oe_register_mode => "none",
5599         oe_sync_reset => "none",
5600         operation_mode => "output",
5601         output_async_reset => "none",
5602         output_power_up => "low",
5603         output_register_mode => "none",
5604         output_sync_reset => "none")
5605 -- pragma translate_on
5606 PORT MAP (
5607         datain => \vga_driver_unit|column_counter_sig_5\,
5608         devclrn => ww_devclrn,
5609         devpor => ww_devpor,
5610         devoe => ww_devoe,
5611         oe => VCC,
5612         padio => ww_d_column_counter(5));
5613
5614 \d_column_counter_out_6_\ : stratix_io
5615 -- pragma translate_off
5616 GENERIC MAP (
5617         ddio_mode => "none",
5618         input_async_reset => "none",
5619         input_power_up => "low",
5620         input_register_mode => "none",
5621         input_sync_reset => "none",
5622         oe_async_reset => "none",
5623         oe_power_up => "low",
5624         oe_register_mode => "none",
5625         oe_sync_reset => "none",
5626         operation_mode => "output",
5627         output_async_reset => "none",
5628         output_power_up => "low",
5629         output_register_mode => "none",
5630         output_sync_reset => "none")
5631 -- pragma translate_on
5632 PORT MAP (
5633         datain => \vga_driver_unit|column_counter_sig_6\,
5634         devclrn => ww_devclrn,
5635         devpor => ww_devpor,
5636         devoe => ww_devoe,
5637         oe => VCC,
5638         padio => ww_d_column_counter(6));
5639
5640 \d_column_counter_out_7_\ : stratix_io
5641 -- pragma translate_off
5642 GENERIC MAP (
5643         ddio_mode => "none",
5644         input_async_reset => "none",
5645         input_power_up => "low",
5646         input_register_mode => "none",
5647         input_sync_reset => "none",
5648         oe_async_reset => "none",
5649         oe_power_up => "low",
5650         oe_register_mode => "none",
5651         oe_sync_reset => "none",
5652         operation_mode => "output",
5653         output_async_reset => "none",
5654         output_power_up => "low",
5655         output_register_mode => "none",
5656         output_sync_reset => "none")
5657 -- pragma translate_on
5658 PORT MAP (
5659         datain => \vga_driver_unit|column_counter_sig_7\,
5660         devclrn => ww_devclrn,
5661         devpor => ww_devpor,
5662         devoe => ww_devoe,
5663         oe => VCC,
5664         padio => ww_d_column_counter(7));
5665
5666 \d_column_counter_out_8_\ : stratix_io
5667 -- pragma translate_off
5668 GENERIC MAP (
5669         ddio_mode => "none",
5670         input_async_reset => "none",
5671         input_power_up => "low",
5672         input_register_mode => "none",
5673         input_sync_reset => "none",
5674         oe_async_reset => "none",
5675         oe_power_up => "low",
5676         oe_register_mode => "none",
5677         oe_sync_reset => "none",
5678         operation_mode => "output",
5679         output_async_reset => "none",
5680         output_power_up => "low",
5681         output_register_mode => "none",
5682         output_sync_reset => "none")
5683 -- pragma translate_on
5684 PORT MAP (
5685         datain => \vga_driver_unit|column_counter_sig_8\,
5686         devclrn => ww_devclrn,
5687         devpor => ww_devpor,
5688         devoe => ww_devoe,
5689         oe => VCC,
5690         padio => ww_d_column_counter(8));
5691
5692 \d_column_counter_out_9_\ : stratix_io
5693 -- pragma translate_off
5694 GENERIC MAP (
5695         ddio_mode => "none",
5696         input_async_reset => "none",
5697         input_power_up => "low",
5698         input_register_mode => "none",
5699         input_sync_reset => "none",
5700         oe_async_reset => "none",
5701         oe_power_up => "low",
5702         oe_register_mode => "none",
5703         oe_sync_reset => "none",
5704         operation_mode => "output",
5705         output_async_reset => "none",
5706         output_power_up => "low",
5707         output_register_mode => "none",
5708         output_sync_reset => "none")
5709 -- pragma translate_on
5710 PORT MAP (
5711         datain => \vga_driver_unit|column_counter_sig_9\,
5712         devclrn => ww_devclrn,
5713         devpor => ww_devpor,
5714         devoe => ww_devoe,
5715         oe => VCC,
5716         padio => ww_d_column_counter(9));
5717
5718 \d_line_counter_out_0_\ : stratix_io
5719 -- pragma translate_off
5720 GENERIC MAP (
5721         ddio_mode => "none",
5722         input_async_reset => "none",
5723         input_power_up => "low",
5724         input_register_mode => "none",
5725         input_sync_reset => "none",
5726         oe_async_reset => "none",
5727         oe_power_up => "low",
5728         oe_register_mode => "none",
5729         oe_sync_reset => "none",
5730         operation_mode => "output",
5731         output_async_reset => "none",
5732         output_power_up => "low",
5733         output_register_mode => "none",
5734         output_sync_reset => "none")
5735 -- pragma translate_on
5736 PORT MAP (
5737         datain => \vga_driver_unit|line_counter_sig_0\,
5738         devclrn => ww_devclrn,
5739         devpor => ww_devpor,
5740         devoe => ww_devoe,
5741         oe => VCC,
5742         padio => ww_d_line_counter(0));
5743
5744 \d_line_counter_out_1_\ : stratix_io
5745 -- pragma translate_off
5746 GENERIC MAP (
5747         ddio_mode => "none",
5748         input_async_reset => "none",
5749         input_power_up => "low",
5750         input_register_mode => "none",
5751         input_sync_reset => "none",
5752         oe_async_reset => "none",
5753         oe_power_up => "low",
5754         oe_register_mode => "none",
5755         oe_sync_reset => "none",
5756         operation_mode => "output",
5757         output_async_reset => "none",
5758         output_power_up => "low",
5759         output_register_mode => "none",
5760         output_sync_reset => "none")
5761 -- pragma translate_on
5762 PORT MAP (
5763         datain => \vga_driver_unit|line_counter_sig_1\,
5764         devclrn => ww_devclrn,
5765         devpor => ww_devpor,
5766         devoe => ww_devoe,
5767         oe => VCC,
5768         padio => ww_d_line_counter(1));
5769
5770 \d_line_counter_out_2_\ : stratix_io
5771 -- pragma translate_off
5772 GENERIC MAP (
5773         ddio_mode => "none",
5774         input_async_reset => "none",
5775         input_power_up => "low",
5776         input_register_mode => "none",
5777         input_sync_reset => "none",
5778         oe_async_reset => "none",
5779         oe_power_up => "low",
5780         oe_register_mode => "none",
5781         oe_sync_reset => "none",
5782         operation_mode => "output",
5783         output_async_reset => "none",
5784         output_power_up => "low",
5785         output_register_mode => "none",
5786         output_sync_reset => "none")
5787 -- pragma translate_on
5788 PORT MAP (
5789         datain => \vga_driver_unit|line_counter_sig_2\,
5790         devclrn => ww_devclrn,
5791         devpor => ww_devpor,
5792         devoe => ww_devoe,
5793         oe => VCC,
5794         padio => ww_d_line_counter(2));
5795
5796 \d_line_counter_out_3_\ : stratix_io
5797 -- pragma translate_off
5798 GENERIC MAP (
5799         ddio_mode => "none",
5800         input_async_reset => "none",
5801         input_power_up => "low",
5802         input_register_mode => "none",
5803         input_sync_reset => "none",
5804         oe_async_reset => "none",
5805         oe_power_up => "low",
5806         oe_register_mode => "none",
5807         oe_sync_reset => "none",
5808         operation_mode => "output",
5809         output_async_reset => "none",
5810         output_power_up => "low",
5811         output_register_mode => "none",
5812         output_sync_reset => "none")
5813 -- pragma translate_on
5814 PORT MAP (
5815         datain => \vga_driver_unit|line_counter_sig_3\,
5816         devclrn => ww_devclrn,
5817         devpor => ww_devpor,
5818         devoe => ww_devoe,
5819         oe => VCC,
5820         padio => ww_d_line_counter(3));
5821
5822 \d_line_counter_out_4_\ : stratix_io
5823 -- pragma translate_off
5824 GENERIC MAP (
5825         ddio_mode => "none",
5826         input_async_reset => "none",
5827         input_power_up => "low",
5828         input_register_mode => "none",
5829         input_sync_reset => "none",
5830         oe_async_reset => "none",
5831         oe_power_up => "low",
5832         oe_register_mode => "none",
5833         oe_sync_reset => "none",
5834         operation_mode => "output",
5835         output_async_reset => "none",
5836         output_power_up => "low",
5837         output_register_mode => "none",
5838         output_sync_reset => "none")
5839 -- pragma translate_on
5840 PORT MAP (
5841         datain => \vga_driver_unit|line_counter_sig_4\,
5842         devclrn => ww_devclrn,
5843         devpor => ww_devpor,
5844         devoe => ww_devoe,
5845         oe => VCC,
5846         padio => ww_d_line_counter(4));
5847
5848 \d_line_counter_out_5_\ : stratix_io
5849 -- pragma translate_off
5850 GENERIC MAP (
5851         ddio_mode => "none",
5852         input_async_reset => "none",
5853         input_power_up => "low",
5854         input_register_mode => "none",
5855         input_sync_reset => "none",
5856         oe_async_reset => "none",
5857         oe_power_up => "low",
5858         oe_register_mode => "none",
5859         oe_sync_reset => "none",
5860         operation_mode => "output",
5861         output_async_reset => "none",
5862         output_power_up => "low",
5863         output_register_mode => "none",
5864         output_sync_reset => "none")
5865 -- pragma translate_on
5866 PORT MAP (
5867         datain => \vga_driver_unit|line_counter_sig_5\,
5868         devclrn => ww_devclrn,
5869         devpor => ww_devpor,
5870         devoe => ww_devoe,
5871         oe => VCC,
5872         padio => ww_d_line_counter(5));
5873
5874 \d_line_counter_out_6_\ : stratix_io
5875 -- pragma translate_off
5876 GENERIC MAP (
5877         ddio_mode => "none",
5878         input_async_reset => "none",
5879         input_power_up => "low",
5880         input_register_mode => "none",
5881         input_sync_reset => "none",
5882         oe_async_reset => "none",
5883         oe_power_up => "low",
5884         oe_register_mode => "none",
5885         oe_sync_reset => "none",
5886         operation_mode => "output",
5887         output_async_reset => "none",
5888         output_power_up => "low",
5889         output_register_mode => "none",
5890         output_sync_reset => "none")
5891 -- pragma translate_on
5892 PORT MAP (
5893         datain => \vga_driver_unit|line_counter_sig_6\,
5894         devclrn => ww_devclrn,
5895         devpor => ww_devpor,
5896         devoe => ww_devoe,
5897         oe => VCC,
5898         padio => ww_d_line_counter(6));
5899
5900 \d_line_counter_out_7_\ : stratix_io
5901 -- pragma translate_off
5902 GENERIC MAP (
5903         ddio_mode => "none",
5904         input_async_reset => "none",
5905         input_power_up => "low",
5906         input_register_mode => "none",
5907         input_sync_reset => "none",
5908         oe_async_reset => "none",
5909         oe_power_up => "low",
5910         oe_register_mode => "none",
5911         oe_sync_reset => "none",
5912         operation_mode => "output",
5913         output_async_reset => "none",
5914         output_power_up => "low",
5915         output_register_mode => "none",
5916         output_sync_reset => "none")
5917 -- pragma translate_on
5918 PORT MAP (
5919         datain => \vga_driver_unit|line_counter_sig_7\,
5920         devclrn => ww_devclrn,
5921         devpor => ww_devpor,
5922         devoe => ww_devoe,
5923         oe => VCC,
5924         padio => ww_d_line_counter(7));
5925
5926 \d_line_counter_out_8_\ : stratix_io
5927 -- pragma translate_off
5928 GENERIC MAP (
5929         ddio_mode => "none",
5930         input_async_reset => "none",
5931         input_power_up => "low",
5932         input_register_mode => "none",
5933         input_sync_reset => "none",
5934         oe_async_reset => "none",
5935         oe_power_up => "low",
5936         oe_register_mode => "none",
5937         oe_sync_reset => "none",
5938         operation_mode => "output",
5939         output_async_reset => "none",
5940         output_power_up => "low",
5941         output_register_mode => "none",
5942         output_sync_reset => "none")
5943 -- pragma translate_on
5944 PORT MAP (
5945         datain => \vga_driver_unit|line_counter_sig_8\,
5946         devclrn => ww_devclrn,
5947         devpor => ww_devpor,
5948         devoe => ww_devoe,
5949         oe => VCC,
5950         padio => ww_d_line_counter(8));
5951
5952 d_set_column_counter_out : stratix_io
5953 -- pragma translate_off
5954 GENERIC MAP (
5955         ddio_mode => "none",
5956         input_async_reset => "none",
5957         input_power_up => "low",
5958         input_register_mode => "none",
5959         input_sync_reset => "none",
5960         oe_async_reset => "none",
5961         oe_power_up => "low",
5962         oe_register_mode => "none",
5963         oe_sync_reset => "none",
5964         operation_mode => "output",
5965         output_async_reset => "none",
5966         output_power_up => "low",
5967         output_register_mode => "none",
5968         output_sync_reset => "none")
5969 -- pragma translate_on
5970 PORT MAP (
5971         datain => \vga_driver_unit|hsync_state_1\,
5972         devclrn => ww_devclrn,
5973         devpor => ww_devpor,
5974         devoe => ww_devoe,
5975         oe => VCC,
5976         padio => ww_d_set_column_counter);
5977
5978 d_set_line_counter_out : stratix_io
5979 -- pragma translate_off
5980 GENERIC MAP (
5981         ddio_mode => "none",
5982         input_async_reset => "none",
5983         input_power_up => "low",
5984         input_register_mode => "none",
5985         input_sync_reset => "none",
5986         oe_async_reset => "none",
5987         oe_power_up => "low",
5988         oe_register_mode => "none",
5989         oe_sync_reset => "none",
5990         operation_mode => "output",
5991         output_async_reset => "none",
5992         output_power_up => "low",
5993         output_register_mode => "none",
5994         output_sync_reset => "none")
5995 -- pragma translate_on
5996 PORT MAP (
5997         datain => \vga_driver_unit|vsync_state_1\,
5998         devclrn => ww_devclrn,
5999         devpor => ww_devpor,
6000         devoe => ww_devoe,
6001         oe => VCC,
6002         padio => ww_d_set_line_counter);
6003
6004 \d_hsync_counter_out_0_\ : stratix_io
6005 -- pragma translate_off
6006 GENERIC MAP (
6007         ddio_mode => "none",
6008         input_async_reset => "none",
6009         input_power_up => "low",
6010         input_register_mode => "none",
6011         input_sync_reset => "none",
6012         oe_async_reset => "none",
6013         oe_power_up => "low",
6014         oe_register_mode => "none",
6015         oe_sync_reset => "none",
6016         operation_mode => "output",
6017         output_async_reset => "none",
6018         output_power_up => "low",
6019         output_register_mode => "none",
6020         output_sync_reset => "none")
6021 -- pragma translate_on
6022 PORT MAP (
6023         datain => \vga_driver_unit|hsync_counter_0\,
6024         devclrn => ww_devclrn,
6025         devpor => ww_devpor,
6026         devoe => ww_devoe,
6027         oe => VCC,
6028         padio => ww_d_hsync_counter(0));
6029
6030 \d_hsync_counter_out_1_\ : stratix_io
6031 -- pragma translate_off
6032 GENERIC MAP (
6033         ddio_mode => "none",
6034         input_async_reset => "none",
6035         input_power_up => "low",
6036         input_register_mode => "none",
6037         input_sync_reset => "none",
6038         oe_async_reset => "none",
6039         oe_power_up => "low",
6040         oe_register_mode => "none",
6041         oe_sync_reset => "none",
6042         operation_mode => "output",
6043         output_async_reset => "none",
6044         output_power_up => "low",
6045         output_register_mode => "none",
6046         output_sync_reset => "none")
6047 -- pragma translate_on
6048 PORT MAP (
6049         datain => \vga_driver_unit|hsync_counter_1\,
6050         devclrn => ww_devclrn,
6051         devpor => ww_devpor,
6052         devoe => ww_devoe,
6053         oe => VCC,
6054         padio => ww_d_hsync_counter(1));
6055
6056 \d_hsync_counter_out_2_\ : stratix_io
6057 -- pragma translate_off
6058 GENERIC MAP (
6059         ddio_mode => "none",
6060         input_async_reset => "none",
6061         input_power_up => "low",
6062         input_register_mode => "none",
6063         input_sync_reset => "none",
6064         oe_async_reset => "none",
6065         oe_power_up => "low",
6066         oe_register_mode => "none",
6067         oe_sync_reset => "none",
6068         operation_mode => "output",
6069         output_async_reset => "none",
6070         output_power_up => "low",
6071         output_register_mode => "none",
6072         output_sync_reset => "none")
6073 -- pragma translate_on
6074 PORT MAP (
6075         datain => \vga_driver_unit|hsync_counter_2\,
6076         devclrn => ww_devclrn,
6077         devpor => ww_devpor,
6078         devoe => ww_devoe,
6079         oe => VCC,
6080         padio => ww_d_hsync_counter(2));
6081
6082 \d_hsync_counter_out_3_\ : stratix_io
6083 -- pragma translate_off
6084 GENERIC MAP (
6085         ddio_mode => "none",
6086         input_async_reset => "none",
6087         input_power_up => "low",
6088         input_register_mode => "none",
6089         input_sync_reset => "none",
6090         oe_async_reset => "none",
6091         oe_power_up => "low",
6092         oe_register_mode => "none",
6093         oe_sync_reset => "none",
6094         operation_mode => "output",
6095         output_async_reset => "none",
6096         output_power_up => "low",
6097         output_register_mode => "none",
6098         output_sync_reset => "none")
6099 -- pragma translate_on
6100 PORT MAP (
6101         datain => \vga_driver_unit|hsync_counter_3\,
6102         devclrn => ww_devclrn,
6103         devpor => ww_devpor,
6104         devoe => ww_devoe,
6105         oe => VCC,
6106         padio => ww_d_hsync_counter(3));
6107
6108 \d_hsync_counter_out_4_\ : stratix_io
6109 -- pragma translate_off
6110 GENERIC MAP (
6111         ddio_mode => "none",
6112         input_async_reset => "none",
6113         input_power_up => "low",
6114         input_register_mode => "none",
6115         input_sync_reset => "none",
6116         oe_async_reset => "none",
6117         oe_power_up => "low",
6118         oe_register_mode => "none",
6119         oe_sync_reset => "none",
6120         operation_mode => "output",
6121         output_async_reset => "none",
6122         output_power_up => "low",
6123         output_register_mode => "none",
6124         output_sync_reset => "none")
6125 -- pragma translate_on
6126 PORT MAP (
6127         datain => \vga_driver_unit|hsync_counter_4\,
6128         devclrn => ww_devclrn,
6129         devpor => ww_devpor,
6130         devoe => ww_devoe,
6131         oe => VCC,
6132         padio => ww_d_hsync_counter(4));
6133
6134 \d_hsync_counter_out_5_\ : stratix_io
6135 -- pragma translate_off
6136 GENERIC MAP (
6137         ddio_mode => "none",
6138         input_async_reset => "none",
6139         input_power_up => "low",
6140         input_register_mode => "none",
6141         input_sync_reset => "none",
6142         oe_async_reset => "none",
6143         oe_power_up => "low",
6144         oe_register_mode => "none",
6145         oe_sync_reset => "none",
6146         operation_mode => "output",
6147         output_async_reset => "none",
6148         output_power_up => "low",
6149         output_register_mode => "none",
6150         output_sync_reset => "none")
6151 -- pragma translate_on
6152 PORT MAP (
6153         datain => \vga_driver_unit|hsync_counter_5\,
6154         devclrn => ww_devclrn,
6155         devpor => ww_devpor,
6156         devoe => ww_devoe,
6157         oe => VCC,
6158         padio => ww_d_hsync_counter(5));
6159
6160 \d_hsync_counter_out_6_\ : stratix_io
6161 -- pragma translate_off
6162 GENERIC MAP (
6163         ddio_mode => "none",
6164         input_async_reset => "none",
6165         input_power_up => "low",
6166         input_register_mode => "none",
6167         input_sync_reset => "none",
6168         oe_async_reset => "none",
6169         oe_power_up => "low",
6170         oe_register_mode => "none",
6171         oe_sync_reset => "none",
6172         operation_mode => "output",
6173         output_async_reset => "none",
6174         output_power_up => "low",
6175         output_register_mode => "none",
6176         output_sync_reset => "none")
6177 -- pragma translate_on
6178 PORT MAP (
6179         datain => \vga_driver_unit|hsync_counter_6\,
6180         devclrn => ww_devclrn,
6181         devpor => ww_devpor,
6182         devoe => ww_devoe,
6183         oe => VCC,
6184         padio => ww_d_hsync_counter(6));
6185
6186 \d_hsync_counter_out_7_\ : stratix_io
6187 -- pragma translate_off
6188 GENERIC MAP (
6189         ddio_mode => "none",
6190         input_async_reset => "none",
6191         input_power_up => "low",
6192         input_register_mode => "none",
6193         input_sync_reset => "none",
6194         oe_async_reset => "none",
6195         oe_power_up => "low",
6196         oe_register_mode => "none",
6197         oe_sync_reset => "none",
6198         operation_mode => "output",
6199         output_async_reset => "none",
6200         output_power_up => "low",
6201         output_register_mode => "none",
6202         output_sync_reset => "none")
6203 -- pragma translate_on
6204 PORT MAP (
6205         datain => \vga_driver_unit|hsync_counter_7\,
6206         devclrn => ww_devclrn,
6207         devpor => ww_devpor,
6208         devoe => ww_devoe,
6209         oe => VCC,
6210         padio => ww_d_hsync_counter(7));
6211
6212 \d_hsync_counter_out_8_\ : stratix_io
6213 -- pragma translate_off
6214 GENERIC MAP (
6215         ddio_mode => "none",
6216         input_async_reset => "none",
6217         input_power_up => "low",
6218         input_register_mode => "none",
6219         input_sync_reset => "none",
6220         oe_async_reset => "none",
6221         oe_power_up => "low",
6222         oe_register_mode => "none",
6223         oe_sync_reset => "none",
6224         operation_mode => "output",
6225         output_async_reset => "none",
6226         output_power_up => "low",
6227         output_register_mode => "none",
6228         output_sync_reset => "none")
6229 -- pragma translate_on
6230 PORT MAP (
6231         datain => \vga_driver_unit|hsync_counter_8\,
6232         devclrn => ww_devclrn,
6233         devpor => ww_devpor,
6234         devoe => ww_devoe,
6235         oe => VCC,
6236         padio => ww_d_hsync_counter(8));
6237
6238 \d_hsync_counter_out_9_\ : stratix_io
6239 -- pragma translate_off
6240 GENERIC MAP (
6241         ddio_mode => "none",
6242         input_async_reset => "none",
6243         input_power_up => "low",
6244         input_register_mode => "none",
6245         input_sync_reset => "none",
6246         oe_async_reset => "none",
6247         oe_power_up => "low",
6248         oe_register_mode => "none",
6249         oe_sync_reset => "none",
6250         operation_mode => "output",
6251         output_async_reset => "none",
6252         output_power_up => "low",
6253         output_register_mode => "none",
6254         output_sync_reset => "none")
6255 -- pragma translate_on
6256 PORT MAP (
6257         datain => \vga_driver_unit|hsync_counter_9\,
6258         devclrn => ww_devclrn,
6259         devpor => ww_devpor,
6260         devoe => ww_devoe,
6261         oe => VCC,
6262         padio => ww_d_hsync_counter(9));
6263
6264 \d_vsync_counter_out_0_\ : stratix_io
6265 -- pragma translate_off
6266 GENERIC MAP (
6267         ddio_mode => "none",
6268         input_async_reset => "none",
6269         input_power_up => "low",
6270         input_register_mode => "none",
6271         input_sync_reset => "none",
6272         oe_async_reset => "none",
6273         oe_power_up => "low",
6274         oe_register_mode => "none",
6275         oe_sync_reset => "none",
6276         operation_mode => "output",
6277         output_async_reset => "none",
6278         output_power_up => "low",
6279         output_register_mode => "none",
6280         output_sync_reset => "none")
6281 -- pragma translate_on
6282 PORT MAP (
6283         datain => \vga_driver_unit|vsync_counter_0\,
6284         devclrn => ww_devclrn,
6285         devpor => ww_devpor,
6286         devoe => ww_devoe,
6287         oe => VCC,
6288         padio => ww_d_vsync_counter(0));
6289
6290 \d_vsync_counter_out_1_\ : stratix_io
6291 -- pragma translate_off
6292 GENERIC MAP (
6293         ddio_mode => "none",
6294         input_async_reset => "none",
6295         input_power_up => "low",
6296         input_register_mode => "none",
6297         input_sync_reset => "none",
6298         oe_async_reset => "none",
6299         oe_power_up => "low",
6300         oe_register_mode => "none",
6301         oe_sync_reset => "none",
6302         operation_mode => "output",
6303         output_async_reset => "none",
6304         output_power_up => "low",
6305         output_register_mode => "none",
6306         output_sync_reset => "none")
6307 -- pragma translate_on
6308 PORT MAP (
6309         datain => \vga_driver_unit|vsync_counter_1\,
6310         devclrn => ww_devclrn,
6311         devpor => ww_devpor,
6312         devoe => ww_devoe,
6313         oe => VCC,
6314         padio => ww_d_vsync_counter(1));
6315
6316 \d_vsync_counter_out_2_\ : stratix_io
6317 -- pragma translate_off
6318 GENERIC MAP (
6319         ddio_mode => "none",
6320         input_async_reset => "none",
6321         input_power_up => "low",
6322         input_register_mode => "none",
6323         input_sync_reset => "none",
6324         oe_async_reset => "none",
6325         oe_power_up => "low",
6326         oe_register_mode => "none",
6327         oe_sync_reset => "none",
6328         operation_mode => "output",
6329         output_async_reset => "none",
6330         output_power_up => "low",
6331         output_register_mode => "none",
6332         output_sync_reset => "none")
6333 -- pragma translate_on
6334 PORT MAP (
6335         datain => \vga_driver_unit|vsync_counter_2\,
6336         devclrn => ww_devclrn,
6337         devpor => ww_devpor,
6338         devoe => ww_devoe,
6339         oe => VCC,
6340         padio => ww_d_vsync_counter(2));
6341
6342 \d_vsync_counter_out_3_\ : stratix_io
6343 -- pragma translate_off
6344 GENERIC MAP (
6345         ddio_mode => "none",
6346         input_async_reset => "none",
6347         input_power_up => "low",
6348         input_register_mode => "none",
6349         input_sync_reset => "none",
6350         oe_async_reset => "none",
6351         oe_power_up => "low",
6352         oe_register_mode => "none",
6353         oe_sync_reset => "none",
6354         operation_mode => "output",
6355         output_async_reset => "none",
6356         output_power_up => "low",
6357         output_register_mode => "none",
6358         output_sync_reset => "none")
6359 -- pragma translate_on
6360 PORT MAP (
6361         datain => \vga_driver_unit|vsync_counter_3\,
6362         devclrn => ww_devclrn,
6363         devpor => ww_devpor,
6364         devoe => ww_devoe,
6365         oe => VCC,
6366         padio => ww_d_vsync_counter(3));
6367
6368 \d_vsync_counter_out_4_\ : stratix_io
6369 -- pragma translate_off
6370 GENERIC MAP (
6371         ddio_mode => "none",
6372         input_async_reset => "none",
6373         input_power_up => "low",
6374         input_register_mode => "none",
6375         input_sync_reset => "none",
6376         oe_async_reset => "none",
6377         oe_power_up => "low",
6378         oe_register_mode => "none",
6379         oe_sync_reset => "none",
6380         operation_mode => "output",
6381         output_async_reset => "none",
6382         output_power_up => "low",
6383         output_register_mode => "none",
6384         output_sync_reset => "none")
6385 -- pragma translate_on
6386 PORT MAP (
6387         datain => \vga_driver_unit|vsync_counter_4\,
6388         devclrn => ww_devclrn,
6389         devpor => ww_devpor,
6390         devoe => ww_devoe,
6391         oe => VCC,
6392         padio => ww_d_vsync_counter(4));
6393
6394 \d_vsync_counter_out_5_\ : stratix_io
6395 -- pragma translate_off
6396 GENERIC MAP (
6397         ddio_mode => "none",
6398         input_async_reset => "none",
6399         input_power_up => "low",
6400         input_register_mode => "none",
6401         input_sync_reset => "none",
6402         oe_async_reset => "none",
6403         oe_power_up => "low",
6404         oe_register_mode => "none",
6405         oe_sync_reset => "none",
6406         operation_mode => "output",
6407         output_async_reset => "none",
6408         output_power_up => "low",
6409         output_register_mode => "none",
6410         output_sync_reset => "none")
6411 -- pragma translate_on
6412 PORT MAP (
6413         datain => \vga_driver_unit|vsync_counter_5\,
6414         devclrn => ww_devclrn,
6415         devpor => ww_devpor,
6416         devoe => ww_devoe,
6417         oe => VCC,
6418         padio => ww_d_vsync_counter(5));
6419
6420 \d_vsync_counter_out_6_\ : stratix_io
6421 -- pragma translate_off
6422 GENERIC MAP (
6423         ddio_mode => "none",
6424         input_async_reset => "none",
6425         input_power_up => "low",
6426         input_register_mode => "none",
6427         input_sync_reset => "none",
6428         oe_async_reset => "none",
6429         oe_power_up => "low",
6430         oe_register_mode => "none",
6431         oe_sync_reset => "none",
6432         operation_mode => "output",
6433         output_async_reset => "none",
6434         output_power_up => "low",
6435         output_register_mode => "none",
6436         output_sync_reset => "none")
6437 -- pragma translate_on
6438 PORT MAP (
6439         datain => \vga_driver_unit|vsync_counter_6\,
6440         devclrn => ww_devclrn,
6441         devpor => ww_devpor,
6442         devoe => ww_devoe,
6443         oe => VCC,
6444         padio => ww_d_vsync_counter(6));
6445
6446 \d_vsync_counter_out_7_\ : stratix_io
6447 -- pragma translate_off
6448 GENERIC MAP (
6449         ddio_mode => "none",
6450         input_async_reset => "none",
6451         input_power_up => "low",
6452         input_register_mode => "none",
6453         input_sync_reset => "none",
6454         oe_async_reset => "none",
6455         oe_power_up => "low",
6456         oe_register_mode => "none",
6457         oe_sync_reset => "none",
6458         operation_mode => "output",
6459         output_async_reset => "none",
6460         output_power_up => "low",
6461         output_register_mode => "none",
6462         output_sync_reset => "none")
6463 -- pragma translate_on
6464 PORT MAP (
6465         datain => \vga_driver_unit|vsync_counter_7\,
6466         devclrn => ww_devclrn,
6467         devpor => ww_devpor,
6468         devoe => ww_devoe,
6469         oe => VCC,
6470         padio => ww_d_vsync_counter(7));
6471
6472 \d_vsync_counter_out_8_\ : stratix_io
6473 -- pragma translate_off
6474 GENERIC MAP (
6475         ddio_mode => "none",
6476         input_async_reset => "none",
6477         input_power_up => "low",
6478         input_register_mode => "none",
6479         input_sync_reset => "none",
6480         oe_async_reset => "none",
6481         oe_power_up => "low",
6482         oe_register_mode => "none",
6483         oe_sync_reset => "none",
6484         operation_mode => "output",
6485         output_async_reset => "none",
6486         output_power_up => "low",
6487         output_register_mode => "none",
6488         output_sync_reset => "none")
6489 -- pragma translate_on
6490 PORT MAP (
6491         datain => \vga_driver_unit|vsync_counter_8\,
6492         devclrn => ww_devclrn,
6493         devpor => ww_devpor,
6494         devoe => ww_devoe,
6495         oe => VCC,
6496         padio => ww_d_vsync_counter(8));
6497
6498 \d_vsync_counter_out_9_\ : stratix_io
6499 -- pragma translate_off
6500 GENERIC MAP (
6501         ddio_mode => "none",
6502         input_async_reset => "none",
6503         input_power_up => "low",
6504         input_register_mode => "none",
6505         input_sync_reset => "none",
6506         oe_async_reset => "none",
6507         oe_power_up => "low",
6508         oe_register_mode => "none",
6509         oe_sync_reset => "none",
6510         operation_mode => "output",
6511         output_async_reset => "none",
6512         output_power_up => "low",
6513         output_register_mode => "none",
6514         output_sync_reset => "none")
6515 -- pragma translate_on
6516 PORT MAP (
6517         datain => \vga_driver_unit|vsync_counter_9\,
6518         devclrn => ww_devclrn,
6519         devpor => ww_devpor,
6520         devoe => ww_devoe,
6521         oe => VCC,
6522         padio => ww_d_vsync_counter(9));
6523
6524 d_set_hsync_counter_out : stratix_io
6525 -- pragma translate_off
6526 GENERIC MAP (
6527         ddio_mode => "none",
6528         input_async_reset => "none",
6529         input_power_up => "low",
6530         input_register_mode => "none",
6531         input_sync_reset => "none",
6532         oe_async_reset => "none",
6533         oe_power_up => "low",
6534         oe_register_mode => "none",
6535         oe_sync_reset => "none",
6536         operation_mode => "output",
6537         output_async_reset => "none",
6538         output_power_up => "low",
6539         output_register_mode => "none",
6540         output_sync_reset => "none")
6541 -- pragma translate_on
6542 PORT MAP (
6543         datain => \vga_driver_unit|d_set_hsync_counter\,
6544         devclrn => ww_devclrn,
6545         devpor => ww_devpor,
6546         devoe => ww_devoe,
6547         oe => VCC,
6548         padio => ww_d_set_hsync_counter);
6549
6550 d_set_vsync_counter_out : stratix_io
6551 -- pragma translate_off
6552 GENERIC MAP (
6553         ddio_mode => "none",
6554         input_async_reset => "none",
6555         input_power_up => "low",
6556         input_register_mode => "none",
6557         input_sync_reset => "none",
6558         oe_async_reset => "none",
6559         oe_power_up => "low",
6560         oe_register_mode => "none",
6561         oe_sync_reset => "none",
6562         operation_mode => "output",
6563         output_async_reset => "none",
6564         output_power_up => "low",
6565         output_register_mode => "none",
6566         output_sync_reset => "none")
6567 -- pragma translate_on
6568 PORT MAP (
6569         datain => \vga_driver_unit|d_set_vsync_counter\,
6570         devclrn => ww_devclrn,
6571         devpor => ww_devpor,
6572         devoe => ww_devoe,
6573         oe => VCC,
6574         padio => ww_d_set_vsync_counter);
6575
6576 d_h_enable_out : stratix_io
6577 -- pragma translate_off
6578 GENERIC MAP (
6579         ddio_mode => "none",
6580         input_async_reset => "none",
6581         input_power_up => "low",
6582         input_register_mode => "none",
6583         input_sync_reset => "none",
6584         oe_async_reset => "none",
6585         oe_power_up => "low",
6586         oe_register_mode => "none",
6587         oe_sync_reset => "none",
6588         operation_mode => "output",
6589         output_async_reset => "none",
6590         output_power_up => "low",
6591         output_register_mode => "none",
6592         output_sync_reset => "none")
6593 -- pragma translate_on
6594 PORT MAP (
6595         datain => \vga_driver_unit|h_enable_sig\,
6596         devclrn => ww_devclrn,
6597         devpor => ww_devpor,
6598         devoe => ww_devoe,
6599         oe => VCC,
6600         padio => ww_d_h_enable);
6601
6602 d_v_enable_out : stratix_io
6603 -- pragma translate_off
6604 GENERIC MAP (
6605         ddio_mode => "none",
6606         input_async_reset => "none",
6607         input_power_up => "low",
6608         input_register_mode => "none",
6609         input_sync_reset => "none",
6610         oe_async_reset => "none",
6611         oe_power_up => "low",
6612         oe_register_mode => "none",
6613         oe_sync_reset => "none",
6614         operation_mode => "output",
6615         output_async_reset => "none",
6616         output_power_up => "low",
6617         output_register_mode => "none",
6618         output_sync_reset => "none")
6619 -- pragma translate_on
6620 PORT MAP (
6621         datain => \vga_driver_unit|v_enable_sig\,
6622         devclrn => ww_devclrn,
6623         devpor => ww_devpor,
6624         devoe => ww_devoe,
6625         oe => VCC,
6626         padio => ww_d_v_enable);
6627
6628 d_r_out : stratix_io
6629 -- pragma translate_off
6630 GENERIC MAP (
6631         ddio_mode => "none",
6632         input_async_reset => "none",
6633         input_power_up => "low",
6634         input_register_mode => "none",
6635         input_sync_reset => "none",
6636         oe_async_reset => "none",
6637         oe_power_up => "low",
6638         oe_register_mode => "none",
6639         oe_sync_reset => "none",
6640         operation_mode => "output",
6641         output_async_reset => "none",
6642         output_power_up => "low",
6643         output_register_mode => "none",
6644         output_sync_reset => "none")
6645 -- pragma translate_on
6646 PORT MAP (
6647         datain => \~STRATIX_FITTER_CREATED_GND~I_combout\,
6648         devclrn => ww_devclrn,
6649         devpor => ww_devpor,
6650         devoe => ww_devoe,
6651         oe => VCC,
6652         padio => ww_d_r);
6653
6654 d_g_out : stratix_io
6655 -- pragma translate_off
6656 GENERIC MAP (
6657         ddio_mode => "none",
6658         input_async_reset => "none",
6659         input_power_up => "low",
6660         input_register_mode => "none",
6661         input_sync_reset => "none",
6662         oe_async_reset => "none",
6663         oe_power_up => "low",
6664         oe_register_mode => "none",
6665         oe_sync_reset => "none",
6666         operation_mode => "output",
6667         output_async_reset => "none",
6668         output_power_up => "low",
6669         output_register_mode => "none",
6670         output_sync_reset => "none")
6671 -- pragma translate_on
6672 PORT MAP (
6673         datain => \~STRATIX_FITTER_CREATED_GND~I_combout\,
6674         devclrn => ww_devclrn,
6675         devpor => ww_devpor,
6676         devoe => ww_devoe,
6677         oe => VCC,
6678         padio => ww_d_g);
6679
6680 d_b_out : stratix_io
6681 -- pragma translate_off
6682 GENERIC MAP (
6683         ddio_mode => "none",
6684         input_async_reset => "none",
6685         input_power_up => "low",
6686         input_register_mode => "none",
6687         input_sync_reset => "none",
6688         oe_async_reset => "none",
6689         oe_power_up => "low",
6690         oe_register_mode => "none",
6691         oe_sync_reset => "none",
6692         operation_mode => "output",
6693         output_async_reset => "none",
6694         output_power_up => "low",
6695         output_register_mode => "none",
6696         output_sync_reset => "none")
6697 -- pragma translate_on
6698 PORT MAP (
6699         datain => \vga_control_unit|b\,
6700         devclrn => ww_devclrn,
6701         devpor => ww_devpor,
6702         devoe => ww_devoe,
6703         oe => VCC,
6704         padio => ww_d_b);
6705
6706 \d_hsync_state_out_6_\ : stratix_io
6707 -- pragma translate_off
6708 GENERIC MAP (
6709         ddio_mode => "none",
6710         input_async_reset => "none",
6711         input_power_up => "low",
6712         input_register_mode => "none",
6713         input_sync_reset => "none",
6714         oe_async_reset => "none",
6715         oe_power_up => "low",
6716         oe_register_mode => "none",
6717         oe_sync_reset => "none",
6718         operation_mode => "output",
6719         output_async_reset => "none",
6720         output_power_up => "low",
6721         output_register_mode => "none",
6722         output_sync_reset => "none")
6723 -- pragma translate_on
6724 PORT MAP (
6725         datain => \vga_driver_unit|hsync_state_6\,
6726         devclrn => ww_devclrn,
6727         devpor => ww_devpor,
6728         devoe => ww_devoe,
6729         oe => VCC,
6730         padio => ww_d_hsync_state(6));
6731
6732 \d_hsync_state_out_5_\ : stratix_io
6733 -- pragma translate_off
6734 GENERIC MAP (
6735         ddio_mode => "none",
6736         input_async_reset => "none",
6737         input_power_up => "low",
6738         input_register_mode => "none",
6739         input_sync_reset => "none",
6740         oe_async_reset => "none",
6741         oe_power_up => "low",
6742         oe_register_mode => "none",
6743         oe_sync_reset => "none",
6744         operation_mode => "output",
6745         output_async_reset => "none",
6746         output_power_up => "low",
6747         output_register_mode => "none",
6748         output_sync_reset => "none")
6749 -- pragma translate_on
6750 PORT MAP (
6751         datain => \vga_driver_unit|hsync_state_5\,
6752         devclrn => ww_devclrn,
6753         devpor => ww_devpor,
6754         devoe => ww_devoe,
6755         oe => VCC,
6756         padio => ww_d_hsync_state(5));
6757
6758 \d_hsync_state_out_4_\ : stratix_io
6759 -- pragma translate_off
6760 GENERIC MAP (
6761         ddio_mode => "none",
6762         input_async_reset => "none",
6763         input_power_up => "low",
6764         input_register_mode => "none",
6765         input_sync_reset => "none",
6766         oe_async_reset => "none",
6767         oe_power_up => "low",
6768         oe_register_mode => "none",
6769         oe_sync_reset => "none",
6770         operation_mode => "output",
6771         output_async_reset => "none",
6772         output_power_up => "low",
6773         output_register_mode => "none",
6774         output_sync_reset => "none")
6775 -- pragma translate_on
6776 PORT MAP (
6777         datain => \vga_driver_unit|hsync_state_4\,
6778         devclrn => ww_devclrn,
6779         devpor => ww_devpor,
6780         devoe => ww_devoe,
6781         oe => VCC,
6782         padio => ww_d_hsync_state(4));
6783
6784 \d_hsync_state_out_3_\ : stratix_io
6785 -- pragma translate_off
6786 GENERIC MAP (
6787         ddio_mode => "none",
6788         input_async_reset => "none",
6789         input_power_up => "low",
6790         input_register_mode => "none",
6791         input_sync_reset => "none",
6792         oe_async_reset => "none",
6793         oe_power_up => "low",
6794         oe_register_mode => "none",
6795         oe_sync_reset => "none",
6796         operation_mode => "output",
6797         output_async_reset => "none",
6798         output_power_up => "low",
6799         output_register_mode => "none",
6800         output_sync_reset => "none")
6801 -- pragma translate_on
6802 PORT MAP (
6803         datain => \vga_driver_unit|hsync_state_3\,
6804         devclrn => ww_devclrn,
6805         devpor => ww_devpor,
6806         devoe => ww_devoe,
6807         oe => VCC,
6808         padio => ww_d_hsync_state(3));
6809
6810 \d_hsync_state_out_2_\ : stratix_io
6811 -- pragma translate_off
6812 GENERIC MAP (
6813         ddio_mode => "none",
6814         input_async_reset => "none",
6815         input_power_up => "low",
6816         input_register_mode => "none",
6817         input_sync_reset => "none",
6818         oe_async_reset => "none",
6819         oe_power_up => "low",
6820         oe_register_mode => "none",
6821         oe_sync_reset => "none",
6822         operation_mode => "output",
6823         output_async_reset => "none",
6824         output_power_up => "low",
6825         output_register_mode => "none",
6826         output_sync_reset => "none")
6827 -- pragma translate_on
6828 PORT MAP (
6829         datain => \vga_driver_unit|hsync_state_2\,
6830         devclrn => ww_devclrn,
6831         devpor => ww_devpor,
6832         devoe => ww_devoe,
6833         oe => VCC,
6834         padio => ww_d_hsync_state(2));
6835
6836 \d_hsync_state_out_1_\ : stratix_io
6837 -- pragma translate_off
6838 GENERIC MAP (
6839         ddio_mode => "none",
6840         input_async_reset => "none",
6841         input_power_up => "low",
6842         input_register_mode => "none",
6843         input_sync_reset => "none",
6844         oe_async_reset => "none",
6845         oe_power_up => "low",
6846         oe_register_mode => "none",
6847         oe_sync_reset => "none",
6848         operation_mode => "output",
6849         output_async_reset => "none",
6850         output_power_up => "low",
6851         output_register_mode => "none",
6852         output_sync_reset => "none")
6853 -- pragma translate_on
6854 PORT MAP (
6855         datain => \vga_driver_unit|hsync_state_1\,
6856         devclrn => ww_devclrn,
6857         devpor => ww_devpor,
6858         devoe => ww_devoe,
6859         oe => VCC,
6860         padio => ww_d_hsync_state(1));
6861
6862 \d_hsync_state_out_0_\ : stratix_io
6863 -- pragma translate_off
6864 GENERIC MAP (
6865         ddio_mode => "none",
6866         input_async_reset => "none",
6867         input_power_up => "low",
6868         input_register_mode => "none",
6869         input_sync_reset => "none",
6870         oe_async_reset => "none",
6871         oe_power_up => "low",
6872         oe_register_mode => "none",
6873         oe_sync_reset => "none",
6874         operation_mode => "output",
6875         output_async_reset => "none",
6876         output_power_up => "low",
6877         output_register_mode => "none",
6878         output_sync_reset => "none")
6879 -- pragma translate_on
6880 PORT MAP (
6881         datain => \vga_driver_unit|hsync_state_0\,
6882         devclrn => ww_devclrn,
6883         devpor => ww_devpor,
6884         devoe => ww_devoe,
6885         oe => VCC,
6886         padio => ww_d_hsync_state(0));
6887
6888 \d_vsync_state_out_6_\ : stratix_io
6889 -- pragma translate_off
6890 GENERIC MAP (
6891         ddio_mode => "none",
6892         input_async_reset => "none",
6893         input_power_up => "low",
6894         input_register_mode => "none",
6895         input_sync_reset => "none",
6896         oe_async_reset => "none",
6897         oe_power_up => "low",
6898         oe_register_mode => "none",
6899         oe_sync_reset => "none",
6900         operation_mode => "output",
6901         output_async_reset => "none",
6902         output_power_up => "low",
6903         output_register_mode => "none",
6904         output_sync_reset => "none")
6905 -- pragma translate_on
6906 PORT MAP (
6907         datain => \vga_driver_unit|vsync_state_6\,
6908         devclrn => ww_devclrn,
6909         devpor => ww_devpor,
6910         devoe => ww_devoe,
6911         oe => VCC,
6912         padio => ww_d_vsync_state(6));
6913
6914 \d_vsync_state_out_5_\ : stratix_io
6915 -- pragma translate_off
6916 GENERIC MAP (
6917         ddio_mode => "none",
6918         input_async_reset => "none",
6919         input_power_up => "low",
6920         input_register_mode => "none",
6921         input_sync_reset => "none",
6922         oe_async_reset => "none",
6923         oe_power_up => "low",
6924         oe_register_mode => "none",
6925         oe_sync_reset => "none",
6926         operation_mode => "output",
6927         output_async_reset => "none",
6928         output_power_up => "low",
6929         output_register_mode => "none",
6930         output_sync_reset => "none")
6931 -- pragma translate_on
6932 PORT MAP (
6933         datain => \vga_driver_unit|vsync_state_5\,
6934         devclrn => ww_devclrn,
6935         devpor => ww_devpor,
6936         devoe => ww_devoe,
6937         oe => VCC,
6938         padio => ww_d_vsync_state(5));
6939
6940 \d_vsync_state_out_4_\ : stratix_io
6941 -- pragma translate_off
6942 GENERIC MAP (
6943         ddio_mode => "none",
6944         input_async_reset => "none",
6945         input_power_up => "low",
6946         input_register_mode => "none",
6947         input_sync_reset => "none",
6948         oe_async_reset => "none",
6949         oe_power_up => "low",
6950         oe_register_mode => "none",
6951         oe_sync_reset => "none",
6952         operation_mode => "output",
6953         output_async_reset => "none",
6954         output_power_up => "low",
6955         output_register_mode => "none",
6956         output_sync_reset => "none")
6957 -- pragma translate_on
6958 PORT MAP (
6959         datain => \vga_driver_unit|vsync_state_4\,
6960         devclrn => ww_devclrn,
6961         devpor => ww_devpor,
6962         devoe => ww_devoe,
6963         oe => VCC,
6964         padio => ww_d_vsync_state(4));
6965
6966 \d_vsync_state_out_3_\ : stratix_io
6967 -- pragma translate_off
6968 GENERIC MAP (
6969         ddio_mode => "none",
6970         input_async_reset => "none",
6971         input_power_up => "low",
6972         input_register_mode => "none",
6973         input_sync_reset => "none",
6974         oe_async_reset => "none",
6975         oe_power_up => "low",
6976         oe_register_mode => "none",
6977         oe_sync_reset => "none",
6978         operation_mode => "output",
6979         output_async_reset => "none",
6980         output_power_up => "low",
6981         output_register_mode => "none",
6982         output_sync_reset => "none")
6983 -- pragma translate_on
6984 PORT MAP (
6985         datain => \vga_driver_unit|vsync_state_3\,
6986         devclrn => ww_devclrn,
6987         devpor => ww_devpor,
6988         devoe => ww_devoe,
6989         oe => VCC,
6990         padio => ww_d_vsync_state(3));
6991
6992 \d_vsync_state_out_2_\ : stratix_io
6993 -- pragma translate_off
6994 GENERIC MAP (
6995         ddio_mode => "none",
6996         input_async_reset => "none",
6997         input_power_up => "low",
6998         input_register_mode => "none",
6999         input_sync_reset => "none",
7000         oe_async_reset => "none",
7001         oe_power_up => "low",
7002         oe_register_mode => "none",
7003         oe_sync_reset => "none",
7004         operation_mode => "output",
7005         output_async_reset => "none",
7006         output_power_up => "low",
7007         output_register_mode => "none",
7008         output_sync_reset => "none")
7009 -- pragma translate_on
7010 PORT MAP (
7011         datain => \vga_driver_unit|vsync_state_2\,
7012         devclrn => ww_devclrn,
7013         devpor => ww_devpor,
7014         devoe => ww_devoe,
7015         oe => VCC,
7016         padio => ww_d_vsync_state(2));
7017
7018 \d_vsync_state_out_1_\ : stratix_io
7019 -- pragma translate_off
7020 GENERIC MAP (
7021         ddio_mode => "none",
7022         input_async_reset => "none",
7023         input_power_up => "low",
7024         input_register_mode => "none",
7025         input_sync_reset => "none",
7026         oe_async_reset => "none",
7027         oe_power_up => "low",
7028         oe_register_mode => "none",
7029         oe_sync_reset => "none",
7030         operation_mode => "output",
7031         output_async_reset => "none",
7032         output_power_up => "low",
7033         output_register_mode => "none",
7034         output_sync_reset => "none")
7035 -- pragma translate_on
7036 PORT MAP (
7037         datain => \vga_driver_unit|vsync_state_1\,
7038         devclrn => ww_devclrn,
7039         devpor => ww_devpor,
7040         devoe => ww_devoe,
7041         oe => VCC,
7042         padio => ww_d_vsync_state(1));
7043
7044 \d_vsync_state_out_0_\ : stratix_io
7045 -- pragma translate_off
7046 GENERIC MAP (
7047         ddio_mode => "none",
7048         input_async_reset => "none",
7049         input_power_up => "low",
7050         input_register_mode => "none",
7051         input_sync_reset => "none",
7052         oe_async_reset => "none",
7053         oe_power_up => "low",
7054         oe_register_mode => "none",
7055         oe_sync_reset => "none",
7056         operation_mode => "output",
7057         output_async_reset => "none",
7058         output_power_up => "low",
7059         output_register_mode => "none",
7060         output_sync_reset => "none")
7061 -- pragma translate_on
7062 PORT MAP (
7063         datain => \vga_driver_unit|vsync_state_0\,
7064         devclrn => ww_devclrn,
7065         devpor => ww_devpor,
7066         devoe => ww_devoe,
7067         oe => VCC,
7068         padio => ww_d_vsync_state(0));
7069
7070 d_state_clk_out : stratix_io
7071 -- pragma translate_off
7072 GENERIC MAP (
7073         ddio_mode => "none",
7074         input_async_reset => "none",
7075         input_power_up => "low",
7076         input_register_mode => "none",
7077         input_sync_reset => "none",
7078         oe_async_reset => "none",
7079         oe_power_up => "low",
7080         oe_register_mode => "none",
7081         oe_sync_reset => "none",
7082         operation_mode => "output",
7083         output_async_reset => "none",
7084         output_power_up => "low",
7085         output_register_mode => "none",
7086         output_sync_reset => "none")
7087 -- pragma translate_on
7088 PORT MAP (
7089         datain => \clk_pin~combout\,
7090         devclrn => ww_devclrn,
7091         devpor => ww_devpor,
7092         devoe => ww_devoe,
7093         oe => VCC,
7094         padio => ww_d_state_clk);
7095
7096 d_toggle_out : stratix_io
7097 -- pragma translate_off
7098 GENERIC MAP (
7099         ddio_mode => "none",
7100         input_async_reset => "none",
7101         input_power_up => "low",
7102         input_register_mode => "none",
7103         input_sync_reset => "none",
7104         oe_async_reset => "none",
7105         oe_power_up => "low",
7106         oe_register_mode => "none",
7107         oe_sync_reset => "none",
7108         operation_mode => "output",
7109         output_async_reset => "none",
7110         output_power_up => "low",
7111         output_register_mode => "none",
7112         output_sync_reset => "none")
7113 -- pragma translate_on
7114 PORT MAP (
7115         datain => \vga_control_unit|toggle_sig\,
7116         devclrn => ww_devclrn,
7117         devpor => ww_devpor,
7118         devoe => ww_devoe,
7119         oe => VCC,
7120         padio => ww_d_toggle);
7121
7122 \d_toggle_counter_out_0_\ : stratix_io
7123 -- pragma translate_off
7124 GENERIC MAP (
7125         ddio_mode => "none",
7126         input_async_reset => "none",
7127         input_power_up => "low",
7128         input_register_mode => "none",
7129         input_sync_reset => "none",
7130         oe_async_reset => "none",
7131         oe_power_up => "low",
7132         oe_register_mode => "none",
7133         oe_sync_reset => "none",
7134         operation_mode => "output",
7135         output_async_reset => "none",
7136         output_power_up => "low",
7137         output_register_mode => "none",
7138         output_sync_reset => "none")
7139 -- pragma translate_on
7140 PORT MAP (
7141         datain => \vga_control_unit|toggle_counter_sig_0\,
7142         devclrn => ww_devclrn,
7143         devpor => ww_devpor,
7144         devoe => ww_devoe,
7145         oe => VCC,
7146         padio => ww_d_toggle_counter(0));
7147
7148 \d_toggle_counter_out_1_\ : stratix_io
7149 -- pragma translate_off
7150 GENERIC MAP (
7151         ddio_mode => "none",
7152         input_async_reset => "none",
7153         input_power_up => "low",
7154         input_register_mode => "none",
7155         input_sync_reset => "none",
7156         oe_async_reset => "none",
7157         oe_power_up => "low",
7158         oe_register_mode => "none",
7159         oe_sync_reset => "none",
7160         operation_mode => "output",
7161         output_async_reset => "none",
7162         output_power_up => "low",
7163         output_register_mode => "none",
7164         output_sync_reset => "none")
7165 -- pragma translate_on
7166 PORT MAP (
7167         datain => \vga_control_unit|toggle_counter_sig_1\,
7168         devclrn => ww_devclrn,
7169         devpor => ww_devpor,
7170         devoe => ww_devoe,
7171         oe => VCC,
7172         padio => ww_d_toggle_counter(1));
7173
7174 \d_toggle_counter_out_2_\ : stratix_io
7175 -- pragma translate_off
7176 GENERIC MAP (
7177         ddio_mode => "none",
7178         input_async_reset => "none",
7179         input_power_up => "low",
7180         input_register_mode => "none",
7181         input_sync_reset => "none",
7182         oe_async_reset => "none",
7183         oe_power_up => "low",
7184         oe_register_mode => "none",
7185         oe_sync_reset => "none",
7186         operation_mode => "output",
7187         output_async_reset => "none",
7188         output_power_up => "low",
7189         output_register_mode => "none",
7190         output_sync_reset => "none")
7191 -- pragma translate_on
7192 PORT MAP (
7193         datain => \vga_control_unit|toggle_counter_sig_2\,
7194         devclrn => ww_devclrn,
7195         devpor => ww_devpor,
7196         devoe => ww_devoe,
7197         oe => VCC,
7198         padio => ww_d_toggle_counter(2));
7199
7200 \d_toggle_counter_out_3_\ : stratix_io
7201 -- pragma translate_off
7202 GENERIC MAP (
7203         ddio_mode => "none",
7204         input_async_reset => "none",
7205         input_power_up => "low",
7206         input_register_mode => "none",
7207         input_sync_reset => "none",
7208         oe_async_reset => "none",
7209         oe_power_up => "low",
7210         oe_register_mode => "none",
7211         oe_sync_reset => "none",
7212         operation_mode => "output",
7213         output_async_reset => "none",
7214         output_power_up => "low",
7215         output_register_mode => "none",
7216         output_sync_reset => "none")
7217 -- pragma translate_on
7218 PORT MAP (
7219         datain => \vga_control_unit|toggle_counter_sig_3\,
7220         devclrn => ww_devclrn,
7221         devpor => ww_devpor,
7222         devoe => ww_devoe,
7223         oe => VCC,
7224         padio => ww_d_toggle_counter(3));
7225
7226 \d_toggle_counter_out_4_\ : stratix_io
7227 -- pragma translate_off
7228 GENERIC MAP (
7229         ddio_mode => "none",
7230         input_async_reset => "none",
7231         input_power_up => "low",
7232         input_register_mode => "none",
7233         input_sync_reset => "none",
7234         oe_async_reset => "none",
7235         oe_power_up => "low",
7236         oe_register_mode => "none",
7237         oe_sync_reset => "none",
7238         operation_mode => "output",
7239         output_async_reset => "none",
7240         output_power_up => "low",
7241         output_register_mode => "none",
7242         output_sync_reset => "none")
7243 -- pragma translate_on
7244 PORT MAP (
7245         datain => \vga_control_unit|toggle_counter_sig_4\,
7246         devclrn => ww_devclrn,
7247         devpor => ww_devpor,
7248         devoe => ww_devoe,
7249         oe => VCC,
7250         padio => ww_d_toggle_counter(4));
7251
7252 \d_toggle_counter_out_5_\ : stratix_io
7253 -- pragma translate_off
7254 GENERIC MAP (
7255         ddio_mode => "none",
7256         input_async_reset => "none",
7257         input_power_up => "low",
7258         input_register_mode => "none",
7259         input_sync_reset => "none",
7260         oe_async_reset => "none",
7261         oe_power_up => "low",
7262         oe_register_mode => "none",
7263         oe_sync_reset => "none",
7264         operation_mode => "output",
7265         output_async_reset => "none",
7266         output_power_up => "low",
7267         output_register_mode => "none",
7268         output_sync_reset => "none")
7269 -- pragma translate_on
7270 PORT MAP (
7271         datain => \vga_control_unit|toggle_counter_sig_5\,
7272         devclrn => ww_devclrn,
7273         devpor => ww_devpor,
7274         devoe => ww_devoe,
7275         oe => VCC,
7276         padio => ww_d_toggle_counter(5));
7277
7278 \d_toggle_counter_out_6_\ : stratix_io
7279 -- pragma translate_off
7280 GENERIC MAP (
7281         ddio_mode => "none",
7282         input_async_reset => "none",
7283         input_power_up => "low",
7284         input_register_mode => "none",
7285         input_sync_reset => "none",
7286         oe_async_reset => "none",
7287         oe_power_up => "low",
7288         oe_register_mode => "none",
7289         oe_sync_reset => "none",
7290         operation_mode => "output",
7291         output_async_reset => "none",
7292         output_power_up => "low",
7293         output_register_mode => "none",
7294         output_sync_reset => "none")
7295 -- pragma translate_on
7296 PORT MAP (
7297         datain => \vga_control_unit|toggle_counter_sig_6\,
7298         devclrn => ww_devclrn,
7299         devpor => ww_devpor,
7300         devoe => ww_devoe,
7301         oe => VCC,
7302         padio => ww_d_toggle_counter(6));
7303
7304 \d_toggle_counter_out_7_\ : stratix_io
7305 -- pragma translate_off
7306 GENERIC MAP (
7307         ddio_mode => "none",
7308         input_async_reset => "none",
7309         input_power_up => "low",
7310         input_register_mode => "none",
7311         input_sync_reset => "none",
7312         oe_async_reset => "none",
7313         oe_power_up => "low",
7314         oe_register_mode => "none",
7315         oe_sync_reset => "none",
7316         operation_mode => "output",
7317         output_async_reset => "none",
7318         output_power_up => "low",
7319         output_register_mode => "none",
7320         output_sync_reset => "none")
7321 -- pragma translate_on
7322 PORT MAP (
7323         datain => \vga_control_unit|toggle_counter_sig_7\,
7324         devclrn => ww_devclrn,
7325         devpor => ww_devpor,
7326         devoe => ww_devoe,
7327         oe => VCC,
7328         padio => ww_d_toggle_counter(7));
7329
7330 \d_toggle_counter_out_8_\ : stratix_io
7331 -- pragma translate_off
7332 GENERIC MAP (
7333         ddio_mode => "none",
7334         input_async_reset => "none",
7335         input_power_up => "low",
7336         input_register_mode => "none",
7337         input_sync_reset => "none",
7338         oe_async_reset => "none",
7339         oe_power_up => "low",
7340         oe_register_mode => "none",
7341         oe_sync_reset => "none",
7342         operation_mode => "output",
7343         output_async_reset => "none",
7344         output_power_up => "low",
7345         output_register_mode => "none",
7346         output_sync_reset => "none")
7347 -- pragma translate_on
7348 PORT MAP (
7349         datain => \vga_control_unit|toggle_counter_sig_8\,
7350         devclrn => ww_devclrn,
7351         devpor => ww_devpor,
7352         devoe => ww_devoe,
7353         oe => VCC,
7354         padio => ww_d_toggle_counter(8));
7355
7356 \d_toggle_counter_out_9_\ : stratix_io
7357 -- pragma translate_off
7358 GENERIC MAP (
7359         ddio_mode => "none",
7360         input_async_reset => "none",
7361         input_power_up => "low",
7362         input_register_mode => "none",
7363         input_sync_reset => "none",
7364         oe_async_reset => "none",
7365         oe_power_up => "low",
7366         oe_register_mode => "none",
7367         oe_sync_reset => "none",
7368         operation_mode => "output",
7369         output_async_reset => "none",
7370         output_power_up => "low",
7371         output_register_mode => "none",
7372         output_sync_reset => "none")
7373 -- pragma translate_on
7374 PORT MAP (
7375         datain => \vga_control_unit|toggle_counter_sig_9\,
7376         devclrn => ww_devclrn,
7377         devpor => ww_devpor,
7378         devoe => ww_devoe,
7379         oe => VCC,
7380         padio => ww_d_toggle_counter(9));
7381
7382 \d_toggle_counter_out_10_\ : stratix_io
7383 -- pragma translate_off
7384 GENERIC MAP (
7385         ddio_mode => "none",
7386         input_async_reset => "none",
7387         input_power_up => "low",
7388         input_register_mode => "none",
7389         input_sync_reset => "none",
7390         oe_async_reset => "none",
7391         oe_power_up => "low",
7392         oe_register_mode => "none",
7393         oe_sync_reset => "none",
7394         operation_mode => "output",
7395         output_async_reset => "none",
7396         output_power_up => "low",
7397         output_register_mode => "none",
7398         output_sync_reset => "none")
7399 -- pragma translate_on
7400 PORT MAP (
7401         datain => \vga_control_unit|toggle_counter_sig_10\,
7402         devclrn => ww_devclrn,
7403         devpor => ww_devpor,
7404         devoe => ww_devoe,
7405         oe => VCC,
7406         padio => ww_d_toggle_counter(10));
7407
7408 \d_toggle_counter_out_11_\ : stratix_io
7409 -- pragma translate_off
7410 GENERIC MAP (
7411         ddio_mode => "none",
7412         input_async_reset => "none",
7413         input_power_up => "low",
7414         input_register_mode => "none",
7415         input_sync_reset => "none",
7416         oe_async_reset => "none",
7417         oe_power_up => "low",
7418         oe_register_mode => "none",
7419         oe_sync_reset => "none",
7420         operation_mode => "output",
7421         output_async_reset => "none",
7422         output_power_up => "low",
7423         output_register_mode => "none",
7424         output_sync_reset => "none")
7425 -- pragma translate_on
7426 PORT MAP (
7427         datain => \vga_control_unit|toggle_counter_sig_11\,
7428         devclrn => ww_devclrn,
7429         devpor => ww_devpor,
7430         devoe => ww_devoe,
7431         oe => VCC,
7432         padio => ww_d_toggle_counter(11));
7433
7434 \d_toggle_counter_out_12_\ : stratix_io
7435 -- pragma translate_off
7436 GENERIC MAP (
7437         ddio_mode => "none",
7438         input_async_reset => "none",
7439         input_power_up => "low",
7440         input_register_mode => "none",
7441         input_sync_reset => "none",
7442         oe_async_reset => "none",
7443         oe_power_up => "low",
7444         oe_register_mode => "none",
7445         oe_sync_reset => "none",
7446         operation_mode => "output",
7447         output_async_reset => "none",
7448         output_power_up => "low",
7449         output_register_mode => "none",
7450         output_sync_reset => "none")
7451 -- pragma translate_on
7452 PORT MAP (
7453         datain => \vga_control_unit|toggle_counter_sig_12\,
7454         devclrn => ww_devclrn,
7455         devpor => ww_devpor,
7456         devoe => ww_devoe,
7457         oe => VCC,
7458         padio => ww_d_toggle_counter(12));
7459
7460 \d_toggle_counter_out_13_\ : stratix_io
7461 -- pragma translate_off
7462 GENERIC MAP (
7463         ddio_mode => "none",
7464         input_async_reset => "none",
7465         input_power_up => "low",
7466         input_register_mode => "none",
7467         input_sync_reset => "none",
7468         oe_async_reset => "none",
7469         oe_power_up => "low",
7470         oe_register_mode => "none",
7471         oe_sync_reset => "none",
7472         operation_mode => "output",
7473         output_async_reset => "none",
7474         output_power_up => "low",
7475         output_register_mode => "none",
7476         output_sync_reset => "none")
7477 -- pragma translate_on
7478 PORT MAP (
7479         datain => \vga_control_unit|toggle_counter_sig_13\,
7480         devclrn => ww_devclrn,
7481         devpor => ww_devpor,
7482         devoe => ww_devoe,
7483         oe => VCC,
7484         padio => ww_d_toggle_counter(13));
7485
7486 \d_toggle_counter_out_14_\ : stratix_io
7487 -- pragma translate_off
7488 GENERIC MAP (
7489         ddio_mode => "none",
7490         input_async_reset => "none",
7491         input_power_up => "low",
7492         input_register_mode => "none",
7493         input_sync_reset => "none",
7494         oe_async_reset => "none",
7495         oe_power_up => "low",
7496         oe_register_mode => "none",
7497         oe_sync_reset => "none",
7498         operation_mode => "output",
7499         output_async_reset => "none",
7500         output_power_up => "low",
7501         output_register_mode => "none",
7502         output_sync_reset => "none")
7503 -- pragma translate_on
7504 PORT MAP (
7505         datain => \vga_control_unit|toggle_counter_sig_14\,
7506         devclrn => ww_devclrn,
7507         devpor => ww_devpor,
7508         devoe => ww_devoe,
7509         oe => VCC,
7510         padio => ww_d_toggle_counter(14));
7511
7512 \d_toggle_counter_out_15_\ : stratix_io
7513 -- pragma translate_off
7514 GENERIC MAP (
7515         ddio_mode => "none",
7516         input_async_reset => "none",
7517         input_power_up => "low",
7518         input_register_mode => "none",
7519         input_sync_reset => "none",
7520         oe_async_reset => "none",
7521         oe_power_up => "low",
7522         oe_register_mode => "none",
7523         oe_sync_reset => "none",
7524         operation_mode => "output",
7525         output_async_reset => "none",
7526         output_power_up => "low",
7527         output_register_mode => "none",
7528         output_sync_reset => "none")
7529 -- pragma translate_on
7530 PORT MAP (
7531         datain => \vga_control_unit|toggle_counter_sig_15\,
7532         devclrn => ww_devclrn,
7533         devpor => ww_devpor,
7534         devoe => ww_devoe,
7535         oe => VCC,
7536         padio => ww_d_toggle_counter(15));
7537
7538 \d_toggle_counter_out_16_\ : stratix_io
7539 -- pragma translate_off
7540 GENERIC MAP (
7541         ddio_mode => "none",
7542         input_async_reset => "none",
7543         input_power_up => "low",
7544         input_register_mode => "none",
7545         input_sync_reset => "none",
7546         oe_async_reset => "none",
7547         oe_power_up => "low",
7548         oe_register_mode => "none",
7549         oe_sync_reset => "none",
7550         operation_mode => "output",
7551         output_async_reset => "none",
7552         output_power_up => "low",
7553         output_register_mode => "none",
7554         output_sync_reset => "none")
7555 -- pragma translate_on
7556 PORT MAP (
7557         datain => \vga_control_unit|toggle_counter_sig_16\,
7558         devclrn => ww_devclrn,
7559         devpor => ww_devpor,
7560         devoe => ww_devoe,
7561         oe => VCC,
7562         padio => ww_d_toggle_counter(16));
7563
7564 \d_toggle_counter_out_17_\ : stratix_io
7565 -- pragma translate_off
7566 GENERIC MAP (
7567         ddio_mode => "none",
7568         input_async_reset => "none",
7569         input_power_up => "low",
7570         input_register_mode => "none",
7571         input_sync_reset => "none",
7572         oe_async_reset => "none",
7573         oe_power_up => "low",
7574         oe_register_mode => "none",
7575         oe_sync_reset => "none",
7576         operation_mode => "output",
7577         output_async_reset => "none",
7578         output_power_up => "low",
7579         output_register_mode => "none",
7580         output_sync_reset => "none")
7581 -- pragma translate_on
7582 PORT MAP (
7583         datain => \vga_control_unit|toggle_counter_sig_17\,
7584         devclrn => ww_devclrn,
7585         devpor => ww_devpor,
7586         devoe => ww_devoe,
7587         oe => VCC,
7588         padio => ww_d_toggle_counter(17));
7589
7590 \d_toggle_counter_out_18_\ : stratix_io
7591 -- pragma translate_off
7592 GENERIC MAP (
7593         ddio_mode => "none",
7594         input_async_reset => "none",
7595         input_power_up => "low",
7596         input_register_mode => "none",
7597         input_sync_reset => "none",
7598         oe_async_reset => "none",
7599         oe_power_up => "low",
7600         oe_register_mode => "none",
7601         oe_sync_reset => "none",
7602         operation_mode => "output",
7603         output_async_reset => "none",
7604         output_power_up => "low",
7605         output_register_mode => "none",
7606         output_sync_reset => "none")
7607 -- pragma translate_on
7608 PORT MAP (
7609         datain => \vga_control_unit|toggle_counter_sig_18\,
7610         devclrn => ww_devclrn,
7611         devpor => ww_devpor,
7612         devoe => ww_devoe,
7613         oe => VCC,
7614         padio => ww_d_toggle_counter(18));
7615
7616 \d_toggle_counter_out_19_\ : stratix_io
7617 -- pragma translate_off
7618 GENERIC MAP (
7619         ddio_mode => "none",
7620         input_async_reset => "none",
7621         input_power_up => "low",
7622         input_register_mode => "none",
7623         input_sync_reset => "none",
7624         oe_async_reset => "none",
7625         oe_power_up => "low",
7626         oe_register_mode => "none",
7627         oe_sync_reset => "none",
7628         operation_mode => "output",
7629         output_async_reset => "none",
7630         output_power_up => "low",
7631         output_register_mode => "none",
7632         output_sync_reset => "none")
7633 -- pragma translate_on
7634 PORT MAP (
7635         datain => \vga_control_unit|toggle_counter_sig_19\,
7636         devclrn => ww_devclrn,
7637         devpor => ww_devpor,
7638         devoe => ww_devoe,
7639         oe => VCC,
7640         padio => ww_d_toggle_counter(19));
7641
7642 \d_toggle_counter_out_20_\ : stratix_io
7643 -- pragma translate_off
7644 GENERIC MAP (
7645         ddio_mode => "none",
7646         input_async_reset => "none",
7647         input_power_up => "low",
7648         input_register_mode => "none",
7649         input_sync_reset => "none",
7650         oe_async_reset => "none",
7651         oe_power_up => "low",
7652         oe_register_mode => "none",
7653         oe_sync_reset => "none",
7654         operation_mode => "output",
7655         output_async_reset => "none",
7656         output_power_up => "low",
7657         output_register_mode => "none",
7658         output_sync_reset => "none")
7659 -- pragma translate_on
7660 PORT MAP (
7661         datain => \~STRATIX_FITTER_CREATED_GND~I_combout\,
7662         devclrn => ww_devclrn,
7663         devpor => ww_devpor,
7664         devoe => ww_devoe,
7665         oe => VCC,
7666         padio => ww_d_toggle_counter(20));
7667
7668 \d_toggle_counter_out_21_\ : stratix_io
7669 -- pragma translate_off
7670 GENERIC MAP (
7671         ddio_mode => "none",
7672         input_async_reset => "none",
7673         input_power_up => "low",
7674         input_register_mode => "none",
7675         input_sync_reset => "none",
7676         oe_async_reset => "none",
7677         oe_power_up => "low",
7678         oe_register_mode => "none",
7679         oe_sync_reset => "none",
7680         operation_mode => "output",
7681         output_async_reset => "none",
7682         output_power_up => "low",
7683         output_register_mode => "none",
7684         output_sync_reset => "none")
7685 -- pragma translate_on
7686 PORT MAP (
7687         datain => \~STRATIX_FITTER_CREATED_GND~I_combout\,
7688         devclrn => ww_devclrn,
7689         devpor => ww_devpor,
7690         devoe => ww_devoe,
7691         oe => VCC,
7692         padio => ww_d_toggle_counter(21));
7693
7694 \d_toggle_counter_out_22_\ : stratix_io
7695 -- pragma translate_off
7696 GENERIC MAP (
7697         ddio_mode => "none",
7698         input_async_reset => "none",
7699         input_power_up => "low",
7700         input_register_mode => "none",
7701         input_sync_reset => "none",
7702         oe_async_reset => "none",
7703         oe_power_up => "low",
7704         oe_register_mode => "none",
7705         oe_sync_reset => "none",
7706         operation_mode => "output",
7707         output_async_reset => "none",
7708         output_power_up => "low",
7709         output_register_mode => "none",
7710         output_sync_reset => "none")
7711 -- pragma translate_on
7712 PORT MAP (
7713         datain => \~STRATIX_FITTER_CREATED_GND~I_combout\,
7714         devclrn => ww_devclrn,
7715         devpor => ww_devpor,
7716         devoe => ww_devoe,
7717         oe => VCC,
7718         padio => ww_d_toggle_counter(22));
7719
7720 \d_toggle_counter_out_23_\ : stratix_io
7721 -- pragma translate_off
7722 GENERIC MAP (
7723         ddio_mode => "none",
7724         input_async_reset => "none",
7725         input_power_up => "low",
7726         input_register_mode => "none",
7727         input_sync_reset => "none",
7728         oe_async_reset => "none",
7729         oe_power_up => "low",
7730         oe_register_mode => "none",
7731         oe_sync_reset => "none",
7732         operation_mode => "output",
7733         output_async_reset => "none",
7734         output_power_up => "low",
7735         output_register_mode => "none",
7736         output_sync_reset => "none")
7737 -- pragma translate_on
7738 PORT MAP (
7739         datain => \~STRATIX_FITTER_CREATED_GND~I_combout\,
7740         devclrn => ww_devclrn,
7741         devpor => ww_devpor,
7742         devoe => ww_devoe,
7743         oe => VCC,
7744         padio => ww_d_toggle_counter(23));
7745
7746 \d_toggle_counter_out_24_\ : stratix_io
7747 -- pragma translate_off
7748 GENERIC MAP (
7749         ddio_mode => "none",
7750         input_async_reset => "none",
7751         input_power_up => "low",
7752         input_register_mode => "none",
7753         input_sync_reset => "none",
7754         oe_async_reset => "none",
7755         oe_power_up => "low",
7756         oe_register_mode => "none",
7757         oe_sync_reset => "none",
7758         operation_mode => "output",
7759         output_async_reset => "none",
7760         output_power_up => "low",
7761         output_register_mode => "none",
7762         output_sync_reset => "none")
7763 -- pragma translate_on
7764 PORT MAP (
7765         datain => \~STRATIX_FITTER_CREATED_GND~I_combout\,
7766         devclrn => ww_devclrn,
7767         devpor => ww_devpor,
7768         devoe => ww_devoe,
7769         oe => VCC,
7770         padio => ww_d_toggle_counter(24));
7771 END structure;
7772
7773