bsp4/Designflow/ppr/sim/db/vga.tmw_info

   1 start_full_compilation:s:00:01:19
   2 start_analysis_synthesis:s:00:00:13-start_full_compilation
   3 start_analysis_elaboration:s-start_full_compilation
   4 start_fitter:s:00:00:36-start_full_compilation
   5 start_assembler:s:00:00:23-start_full_compilation
   6 start_timing_analyzer:s:00:00:03-start_full_compilation
   7 start_eda_netlist_writer:s:00:00:04-start_full_compilation