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[dide_16.git]
/
bsp4
/
Designflow
/
ppr
/
download
/
simulation
/
modelsim
/
vga_pll.sft
1
set tool_name "ModelSim-Altera (Verilog)"
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set corner_file_list {
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{{"Slow Model"} {vga_pll.vo vga_pll_v.sdo}}
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}