bsp4/Designflow/ppr/download/db/vga_pll.hier_info

   1 |vga_pll
   2 d_hsync <= vga:inst.d_hsync
   3 board_clk => vpll:inst1.inclk0
   4 reset => vga:inst.reset_pin
   5 d_vsync <= vga:inst.d_vsync
   6 d_set_column_counter <= vga:inst.d_set_column_counter
   7 d_set_line_counter <= vga:inst.d_set_line_counter
   8 d_set_hsync_counter <= vga:inst.d_set_hsync_counter
   9 d_set_vsync_counter <= vga:inst.d_set_vsync_counter
  10 d_r <= vga:inst.d_r
  11 d_g <= vga:inst.d_g
  12 d_b <= vga:inst.d_b
  13 d_h_enable <= vga:inst.d_h_enable
  14 d_v_enable <= vga:inst.d_v_enable
  15 d_state_clk <= vga:inst.d_state_clk
  16 d_toggle <= vga:inst.d_toggle
  17 r0_pin <= vga:inst.r0_pin
  18 r1_pin <= vga:inst.r1_pin
  19 r2_pin <= vga:inst.r2_pin
  20 g0_pin <= vga:inst.g0_pin
  21 g1_pin <= vga:inst.g1_pin
  22 g2_pin <= vga:inst.g2_pin
  23 b0_pin <= vga:inst.b0_pin
  24 b1_pin <= vga:inst.b1_pin
  25 hsync_pin <= vga:inst.hsync_pin
  26 vsync_pin <= vga:inst.vsync_pin
  27 d_column_counter[0] <= vga:inst.d_column_counter[0]
  28 d_column_counter[1] <= vga:inst.d_column_counter[1]
  29 d_column_counter[2] <= vga:inst.d_column_counter[2]
  30 d_column_counter[3] <= vga:inst.d_column_counter[3]
  31 d_column_counter[4] <= vga:inst.d_column_counter[4]
  32 d_column_counter[5] <= vga:inst.d_column_counter[5]
  33 d_column_counter[6] <= vga:inst.d_column_counter[6]
  34 d_column_counter[7] <= vga:inst.d_column_counter[7]
  35 d_column_counter[8] <= vga:inst.d_column_counter[8]
  36 d_column_counter[9] <= vga:inst.d_column_counter[9]
  37 d_hsync_counter[0] <= vga:inst.d_hsync_counter[0]
  38 d_hsync_counter[1] <= vga:inst.d_hsync_counter[1]
  39 d_hsync_counter[2] <= vga:inst.d_hsync_counter[2]
  40 d_hsync_counter[3] <= vga:inst.d_hsync_counter[3]
  41 d_hsync_counter[4] <= vga:inst.d_hsync_counter[4]
  42 d_hsync_counter[5] <= vga:inst.d_hsync_counter[5]
  43 d_hsync_counter[6] <= vga:inst.d_hsync_counter[6]
  44 d_hsync_counter[7] <= vga:inst.d_hsync_counter[7]
  45 d_hsync_counter[8] <= vga:inst.d_hsync_counter[8]
  46 d_hsync_counter[9] <= vga:inst.d_hsync_counter[9]
  47 d_hsync_state[6] <= vga:inst.d_hsync_state[6]
  48 d_hsync_state[5] <= vga:inst.d_hsync_state[5]
  49 d_hsync_state[4] <= vga:inst.d_hsync_state[4]
  50 d_hsync_state[3] <= vga:inst.d_hsync_state[3]
  51 d_hsync_state[2] <= vga:inst.d_hsync_state[2]
  52 d_hsync_state[1] <= vga:inst.d_hsync_state[1]
  53 d_hsync_state[0] <= vga:inst.d_hsync_state[0]
  54 d_line_counter[0] <= vga:inst.d_line_counter[0]
  55 d_line_counter[1] <= vga:inst.d_line_counter[1]
  56 d_line_counter[2] <= vga:inst.d_line_counter[2]
  57 d_line_counter[3] <= vga:inst.d_line_counter[3]
  58 d_line_counter[4] <= vga:inst.d_line_counter[4]
  59 d_line_counter[5] <= vga:inst.d_line_counter[5]
  60 d_line_counter[6] <= vga:inst.d_line_counter[6]
  61 d_line_counter[7] <= vga:inst.d_line_counter[7]
  62 d_line_counter[8] <= vga:inst.d_line_counter[8]
  63 d_toggle_counter[0] <= vga:inst.d_toggle_counter[0]
  64 d_toggle_counter[1] <= vga:inst.d_toggle_counter[1]
  65 d_toggle_counter[2] <= vga:inst.d_toggle_counter[2]
  66 d_toggle_counter[3] <= vga:inst.d_toggle_counter[3]
  67 d_toggle_counter[4] <= vga:inst.d_toggle_counter[4]
  68 d_toggle_counter[5] <= vga:inst.d_toggle_counter[5]
  69 d_toggle_counter[6] <= vga:inst.d_toggle_counter[6]
  70 d_toggle_counter[7] <= vga:inst.d_toggle_counter[7]
  71 d_toggle_counter[8] <= vga:inst.d_toggle_counter[8]
  72 d_toggle_counter[9] <= vga:inst.d_toggle_counter[9]
  73 d_toggle_counter[10] <= vga:inst.d_toggle_counter[10]
  74 d_toggle_counter[11] <= vga:inst.d_toggle_counter[11]
  75 d_toggle_counter[12] <= vga:inst.d_toggle_counter[12]
  76 d_toggle_counter[13] <= vga:inst.d_toggle_counter[13]
  77 d_toggle_counter[14] <= vga:inst.d_toggle_counter[14]
  78 d_toggle_counter[15] <= vga:inst.d_toggle_counter[15]
  79 d_toggle_counter[16] <= vga:inst.d_toggle_counter[16]
  80 d_toggle_counter[17] <= vga:inst.d_toggle_counter[17]
  81 d_toggle_counter[18] <= vga:inst.d_toggle_counter[18]
  82 d_toggle_counter[19] <= vga:inst.d_toggle_counter[19]
  83 d_toggle_counter[20] <= vga:inst.d_toggle_counter[20]
  84 d_toggle_counter[21] <= vga:inst.d_toggle_counter[21]
  85 d_toggle_counter[22] <= vga:inst.d_toggle_counter[22]
  86 d_toggle_counter[23] <= vga:inst.d_toggle_counter[23]
  87 d_toggle_counter[24] <= vga:inst.d_toggle_counter[24]
  88 d_vsync_counter[0] <= vga:inst.d_vsync_counter[0]
  89 d_vsync_counter[1] <= vga:inst.d_vsync_counter[1]
  90 d_vsync_counter[2] <= vga:inst.d_vsync_counter[2]
  91 d_vsync_counter[3] <= vga:inst.d_vsync_counter[3]
  92 d_vsync_counter[4] <= vga:inst.d_vsync_counter[4]
  93 d_vsync_counter[5] <= vga:inst.d_vsync_counter[5]
  94 d_vsync_counter[6] <= vga:inst.d_vsync_counter[6]
  95 d_vsync_counter[7] <= vga:inst.d_vsync_counter[7]
  96 d_vsync_counter[8] <= vga:inst.d_vsync_counter[8]
  97 d_vsync_counter[9] <= vga:inst.d_vsync_counter[9]
  98 d_vsync_state[6] <= vga:inst.d_vsync_state[6]
  99 d_vsync_state[5] <= vga:inst.d_vsync_state[5]
 100 d_vsync_state[4] <= vga:inst.d_vsync_state[4]
 101 d_vsync_state[3] <= vga:inst.d_vsync_state[3]
 102 d_vsync_state[2] <= vga:inst.d_vsync_state[2]
 103 d_vsync_state[1] <= vga:inst.d_vsync_state[1]
 104 d_vsync_state[0] <= vga:inst.d_vsync_state[0]
 105 seven_seg_pin[0] <= vga:inst.seven_seg_pin[0]
 106 seven_seg_pin[1] <= vga:inst.seven_seg_pin[1]
 107 seven_seg_pin[2] <= vga:inst.seven_seg_pin[2]
 108 seven_seg_pin[3] <= vga:inst.seven_seg_pin[3]
 109 seven_seg_pin[4] <= vga:inst.seven_seg_pin[4]
 110 seven_seg_pin[5] <= vga:inst.seven_seg_pin[5]
 111 seven_seg_pin[6] <= vga:inst.seven_seg_pin[6]
 112 seven_seg_pin[7] <= vga:inst.seven_seg_pin[7]
 113 seven_seg_pin[8] <= vga:inst.seven_seg_pin[8]
 114 seven_seg_pin[9] <= vga:inst.seven_seg_pin[9]
 115 seven_seg_pin[10] <= vga:inst.seven_seg_pin[10]
 116 seven_seg_pin[11] <= vga:inst.seven_seg_pin[11]
 117 seven_seg_pin[12] <= vga:inst.seven_seg_pin[12]
 118 seven_seg_pin[13] <= vga:inst.seven_seg_pin[13]
 119
 120
 121 |vga_pll|vga:inst
 122 clk_pin => clk_pin_in.PADIO
 123 reset_pin => reset_pin_in.PADIO
 124 r0_pin <= r0_pin_out.PADIO
 125 r1_pin <= r1_pin_out.PADIO
 126 r2_pin <= r2_pin_out.PADIO
 127 g0_pin <= g0_pin_out.PADIO
 128 g1_pin <= g1_pin_out.PADIO
 129 g2_pin <= g2_pin_out.PADIO
 130 b0_pin <= b0_pin_out.PADIO
 131 b1_pin <= b1_pin_out.PADIO
 132 hsync_pin <= hsync_pin_out.PADIO
 133 vsync_pin <= vsync_pin_out.PADIO
 134 seven_seg_pin[0] <= seven_seg_pin_tri_0_.PADIO
 135 seven_seg_pin[1] <= seven_seg_pin_out_1_.PADIO
 136 seven_seg_pin[2] <= seven_seg_pin_out_2_.PADIO
 137 seven_seg_pin[3] <= seven_seg_pin_tri_3_.PADIO
 138 seven_seg_pin[4] <= seven_seg_pin_tri_4_.PADIO
 139 seven_seg_pin[5] <= seven_seg_pin_tri_5_.PADIO
 140 seven_seg_pin[6] <= seven_seg_pin_tri_6_.PADIO
 141 seven_seg_pin[7] <= seven_seg_pin_out_7_.PADIO
 142 seven_seg_pin[8] <= seven_seg_pin_out_8_.PADIO
 143 seven_seg_pin[9] <= seven_seg_pin_out_9_.PADIO
 144 seven_seg_pin[10] <= seven_seg_pin_out_10_.PADIO
 145 seven_seg_pin[11] <= seven_seg_pin_out_11_.PADIO
 146 seven_seg_pin[12] <= seven_seg_pin_out_12_.PADIO
 147 seven_seg_pin[13] <= seven_seg_pin_tri_13_.PADIO
 148 d_hsync <= d_hsync_out.PADIO
 149 d_vsync <= d_vsync_out.PADIO
 150 d_column_counter[0] <= d_column_counter_out_0_.PADIO
 151 d_column_counter[1] <= d_column_counter_out_1_.PADIO
 152 d_column_counter[2] <= d_column_counter_out_2_.PADIO
 153 d_column_counter[3] <= d_column_counter_out_3_.PADIO
 154 d_column_counter[4] <= d_column_counter_out_4_.PADIO
 155 d_column_counter[5] <= d_column_counter_out_5_.PADIO
 156 d_column_counter[6] <= d_column_counter_out_6_.PADIO
 157 d_column_counter[7] <= d_column_counter_out_7_.PADIO
 158 d_column_counter[8] <= d_column_counter_out_8_.PADIO
 159 d_column_counter[9] <= d_column_counter_out_9_.PADIO
 160 d_line_counter[0] <= d_line_counter_out_0_.PADIO
 161 d_line_counter[1] <= d_line_counter_out_1_.PADIO
 162 d_line_counter[2] <= d_line_counter_out_2_.PADIO
 163 d_line_counter[3] <= d_line_counter_out_3_.PADIO
 164 d_line_counter[4] <= d_line_counter_out_4_.PADIO
 165 d_line_counter[5] <= d_line_counter_out_5_.PADIO
 166 d_line_counter[6] <= d_line_counter_out_6_.PADIO
 167 d_line_counter[7] <= d_line_counter_out_7_.PADIO
 168 d_line_counter[8] <= d_line_counter_out_8_.PADIO
 169 d_set_column_counter <= d_set_column_counter_out.PADIO
 170 d_set_line_counter <= d_set_line_counter_out.PADIO
 171 d_hsync_counter[0] <= d_hsync_counter_out_0_.PADIO
 172 d_hsync_counter[1] <= d_hsync_counter_out_1_.PADIO
 173 d_hsync_counter[2] <= d_hsync_counter_out_2_.PADIO
 174 d_hsync_counter[3] <= d_hsync_counter_out_3_.PADIO
 175 d_hsync_counter[4] <= d_hsync_counter_out_4_.PADIO
 176 d_hsync_counter[5] <= d_hsync_counter_out_5_.PADIO
 177 d_hsync_counter[6] <= d_hsync_counter_out_6_.PADIO
 178 d_hsync_counter[7] <= d_hsync_counter_out_7_.PADIO
 179 d_hsync_counter[8] <= d_hsync_counter_out_8_.PADIO
 180 d_hsync_counter[9] <= d_hsync_counter_out_9_.PADIO
 181 d_vsync_counter[0] <= d_vsync_counter_out_0_.PADIO
 182 d_vsync_counter[1] <= d_vsync_counter_out_1_.PADIO
 183 d_vsync_counter[2] <= d_vsync_counter_out_2_.PADIO
 184 d_vsync_counter[3] <= d_vsync_counter_out_3_.PADIO
 185 d_vsync_counter[4] <= d_vsync_counter_out_4_.PADIO
 186 d_vsync_counter[5] <= d_vsync_counter_out_5_.PADIO
 187 d_vsync_counter[6] <= d_vsync_counter_out_6_.PADIO
 188 d_vsync_counter[7] <= d_vsync_counter_out_7_.PADIO
 189 d_vsync_counter[8] <= d_vsync_counter_out_8_.PADIO
 190 d_vsync_counter[9] <= d_vsync_counter_out_9_.PADIO
 191 d_set_hsync_counter <= d_set_hsync_counter_out.PADIO
 192 d_set_vsync_counter <= d_set_vsync_counter_out.PADIO
 193 d_h_enable <= d_h_enable_out.PADIO
 194 d_v_enable <= d_v_enable_out.PADIO
 195 d_r <= d_r_out.PADIO
 196 d_g <= d_g_out.PADIO
 197 d_b <= d_b_out.PADIO
 198 d_hsync_state[6] <= d_hsync_state_out_6_.PADIO
 199 d_hsync_state[5] <= d_hsync_state_out_5_.PADIO
 200 d_hsync_state[4] <= d_hsync_state_out_4_.PADIO
 201 d_hsync_state[3] <= d_hsync_state_out_3_.PADIO
 202 d_hsync_state[2] <= d_hsync_state_out_2_.PADIO
 203 d_hsync_state[1] <= d_hsync_state_out_1_.PADIO
 204 d_hsync_state[0] <= d_hsync_state_out_0_.PADIO
 205 d_vsync_state[6] <= d_vsync_state_out_6_.PADIO
 206 d_vsync_state[5] <= d_vsync_state_out_5_.PADIO
 207 d_vsync_state[4] <= d_vsync_state_out_4_.PADIO
 208 d_vsync_state[3] <= d_vsync_state_out_3_.PADIO
 209 d_vsync_state[2] <= d_vsync_state_out_2_.PADIO
 210 d_vsync_state[1] <= d_vsync_state_out_1_.PADIO
 211 d_vsync_state[0] <= d_vsync_state_out_0_.PADIO
 212 d_state_clk <= d_state_clk_out.PADIO
 213 d_toggle <= d_toggle_out.PADIO
 214 d_toggle_counter[0] <= d_toggle_counter_out_0_.PADIO
 215 d_toggle_counter[1] <= d_toggle_counter_out_1_.PADIO
 216 d_toggle_counter[2] <= d_toggle_counter_out_2_.PADIO
 217 d_toggle_counter[3] <= d_toggle_counter_out_3_.PADIO
 218 d_toggle_counter[4] <= d_toggle_counter_out_4_.PADIO
 219 d_toggle_counter[5] <= d_toggle_counter_out_5_.PADIO
 220 d_toggle_counter[6] <= d_toggle_counter_out_6_.PADIO
 221 d_toggle_counter[7] <= d_toggle_counter_out_7_.PADIO
 222 d_toggle_counter[8] <= d_toggle_counter_out_8_.PADIO
 223 d_toggle_counter[9] <= d_toggle_counter_out_9_.PADIO
 224 d_toggle_counter[10] <= d_toggle_counter_out_10_.PADIO
 225 d_toggle_counter[11] <= d_toggle_counter_out_11_.PADIO
 226 d_toggle_counter[12] <= d_toggle_counter_out_12_.PADIO
 227 d_toggle_counter[13] <= d_toggle_counter_out_13_.PADIO
 228 d_toggle_counter[14] <= d_toggle_counter_out_14_.PADIO
 229 d_toggle_counter[15] <= d_toggle_counter_out_15_.PADIO
 230 d_toggle_counter[16] <= d_toggle_counter_out_16_.PADIO
 231 d_toggle_counter[17] <= d_toggle_counter_out_17_.PADIO
 232 d_toggle_counter[18] <= d_toggle_counter_out_18_.PADIO
 233 d_toggle_counter[19] <= d_toggle_counter_out_19_.PADIO
 234 d_toggle_counter[20] <= d_toggle_counter_out_20_.PADIO
 235 d_toggle_counter[21] <= d_toggle_counter_out_21_.PADIO
 236 d_toggle_counter[22] <= d_toggle_counter_out_22_.PADIO
 237 d_toggle_counter[23] <= d_toggle_counter_out_23_.PADIO
 238 d_toggle_counter[24] <= d_toggle_counter_out_24_.PADIO
 239
 240
 241 |vga_pll|vga:inst|vga_driver:vga_driver_unit
 242 line_counter_sig_0 <= line_counter_sig_0_.REGOUT
 243 line_counter_sig_1 <= line_counter_sig_1_.REGOUT
 244 line_counter_sig_2 <= line_counter_sig_2_.REGOUT
 245 line_counter_sig_3 <= line_counter_sig_3_.REGOUT
 246 line_counter_sig_4 <= line_counter_sig_4_.REGOUT
 247 line_counter_sig_5 <= line_counter_sig_5_.REGOUT
 248 line_counter_sig_6 <= line_counter_sig_6_.REGOUT
 249 line_counter_sig_7 <= line_counter_sig_7_.REGOUT
 250 line_counter_sig_8 <= line_counter_sig_8_.REGOUT
 251 dly_counter_1 => vsync_state_6_.DATAC
 252 dly_counter_1 => h_sync_Z.DATAC
 253 dly_counter_1 => v_sync_Z.DATAC
 254 dly_counter_1 => hsync_counter_next_1_sqmuxa_cZ.DATAC
 255 dly_counter_1 => column_counter_next_0_sqmuxa_1_1_cZ.DATAC
 256 dly_counter_1 => line_counter_next_0_sqmuxa_1_1_cZ.DATAC
 257 dly_counter_1 => vsync_counter_next_1_sqmuxa_cZ.DATAC
 258 dly_counter_0 => vsync_state_6_.DATAB
 259 dly_counter_0 => h_sync_Z.DATAB
 260 dly_counter_0 => v_sync_Z.DATAB
 261 dly_counter_0 => hsync_counter_next_1_sqmuxa_cZ.DATAB
 262 dly_counter_0 => column_counter_next_0_sqmuxa_1_1_cZ.DATAB
 263 dly_counter_0 => line_counter_next_0_sqmuxa_1_1_cZ.DATAB
 264 dly_counter_0 => vsync_counter_next_1_sqmuxa_cZ.DATAB
 265 vsync_state_2 <= vsync_state_2_.REGOUT
 266 vsync_state_5 <= vsync_state_5_.REGOUT
 267 vsync_state_3 <= vsync_state_3_.REGOUT
 268 vsync_state_6 <= vsync_state_6_.REGOUT
 269 vsync_state_4 <= vsync_state_4_.REGOUT
 270 vsync_state_1 <= vsync_state_1_.REGOUT
 271 vsync_state_0 <= vsync_state_0_.REGOUT
 272 hsync_state_2 <= hsync_state_2_.REGOUT
 273 hsync_state_4 <= hsync_state_4_.REGOUT
 274 hsync_state_0 <= hsync_state_0_.REGOUT
 275 hsync_state_5 <= hsync_state_5_.REGOUT
 276 hsync_state_1 <= hsync_state_1_.REGOUT
 277 hsync_state_3 <= hsync_state_3_.REGOUT
 278 hsync_state_6 <= hsync_state_6_.REGOUT
 279 column_counter_sig_0 <= column_counter_sig_0_.REGOUT
 280 column_counter_sig_1 <= column_counter_sig_1_.REGOUT
 281 column_counter_sig_2 <= column_counter_sig_2_.REGOUT
 282 column_counter_sig_3 <= column_counter_sig_3_.REGOUT
 283 column_counter_sig_4 <= column_counter_sig_4_.REGOUT
 284 column_counter_sig_5 <= column_counter_sig_5_.REGOUT
 285 column_counter_sig_6 <= column_counter_sig_6_.REGOUT
 286 column_counter_sig_7 <= column_counter_sig_7_.REGOUT
 287 column_counter_sig_8 <= column_counter_sig_8_.REGOUT
 288 column_counter_sig_9 <= column_counter_sig_9_.REGOUT
 289 vsync_counter_9 <= vsync_counter_9_.REGOUT
 290 vsync_counter_8 <= vsync_counter_8_.REGOUT
 291 vsync_counter_7 <= vsync_counter_7_.REGOUT
 292 vsync_counter_6 <= vsync_counter_6_.REGOUT
 293 vsync_counter_5 <= vsync_counter_5_.REGOUT
 294 vsync_counter_4 <= vsync_counter_4_.REGOUT
 295 vsync_counter_3 <= vsync_counter_3_.REGOUT
 296 vsync_counter_2 <= vsync_counter_2_.REGOUT
 297 vsync_counter_1 <= vsync_counter_1_.REGOUT
 298 vsync_counter_0 <= vsync_counter_0_.REGOUT
 299 hsync_counter_9 <= hsync_counter_9_.REGOUT
 300 hsync_counter_8 <= hsync_counter_8_.REGOUT
 301 hsync_counter_7 <= hsync_counter_7_.REGOUT
 302 hsync_counter_6 <= hsync_counter_6_.REGOUT
 303 hsync_counter_5 <= hsync_counter_5_.REGOUT
 304 hsync_counter_4 <= hsync_counter_4_.REGOUT
 305 hsync_counter_3 <= hsync_counter_3_.REGOUT
 306 hsync_counter_2 <= hsync_counter_2_.REGOUT
 307 hsync_counter_1 <= hsync_counter_1_.REGOUT
 308 hsync_counter_0 <= hsync_counter_0_.REGOUT
 309 d_set_vsync_counter <= d_set_vsync_counter_cZ.COMBOUT
 310 un10_column_counter_siglt6_1 <= COLUMN_COUNT_next_un10_column_counter_siglt6_1.COMBOUT
 311 v_sync <= v_sync_Z.REGOUT
 312 h_sync <= h_sync_Z.REGOUT
 313 h_enable_sig <= h_enable_sig_Z.REGOUT
 314 v_enable_sig <= v_enable_sig_Z.REGOUT
 315 reset_pin_c => vsync_state_6_.DATAA
 316 reset_pin_c => h_sync_Z.DATAA
 317 reset_pin_c => v_sync_Z.DATAA
 318 reset_pin_c => hsync_counter_next_1_sqmuxa_cZ.DATAA
 319 reset_pin_c => column_counter_next_0_sqmuxa_1_1_cZ.DATAA
 320 reset_pin_c => line_counter_next_0_sqmuxa_1_1_cZ.DATAA
 321 reset_pin_c => vsync_counter_next_1_sqmuxa_cZ.DATAA
 322 un6_dly_counter_0_x <= vsync_state_6_.COMBOUT
 323 d_set_hsync_counter <= d_set_hsync_counter_cZ.COMBOUT
 324 clk_pin_c => hsync_counter_0_.CLK
 325 clk_pin_c => hsync_counter_1_.CLK
 326 clk_pin_c => hsync_counter_2_.CLK
 327 clk_pin_c => hsync_counter_3_.CLK
 328 clk_pin_c => hsync_counter_4_.CLK
 329 clk_pin_c => hsync_counter_5_.CLK
 330 clk_pin_c => hsync_counter_6_.CLK
 331 clk_pin_c => hsync_counter_7_.CLK
 332 clk_pin_c => hsync_counter_8_.CLK
 333 clk_pin_c => hsync_counter_9_.CLK
 334 clk_pin_c => vsync_counter_0_.CLK
 335 clk_pin_c => vsync_counter_1_.CLK
 336 clk_pin_c => vsync_counter_2_.CLK
 337 clk_pin_c => vsync_counter_3_.CLK
 338 clk_pin_c => vsync_counter_4_.CLK
 339 clk_pin_c => vsync_counter_5_.CLK
 340 clk_pin_c => vsync_counter_6_.CLK
 341 clk_pin_c => vsync_counter_7_.CLK
 342 clk_pin_c => vsync_counter_8_.CLK
 343 clk_pin_c => vsync_counter_9_.CLK
 344 clk_pin_c => column_counter_sig_9_.CLK
 345 clk_pin_c => column_counter_sig_8_.CLK
 346 clk_pin_c => column_counter_sig_7_.CLK
 347 clk_pin_c => column_counter_sig_6_.CLK
 348 clk_pin_c => column_counter_sig_5_.CLK
 349 clk_pin_c => column_counter_sig_4_.CLK
 350 clk_pin_c => column_counter_sig_3_.CLK
 351 clk_pin_c => column_counter_sig_2_.CLK
 352 clk_pin_c => column_counter_sig_1_.CLK
 353 clk_pin_c => column_counter_sig_0_.CLK
 354 clk_pin_c => hsync_state_6_.CLK
 355 clk_pin_c => vsync_state_0_.CLK
 356 clk_pin_c => vsync_state_1_.CLK
 357 clk_pin_c => vsync_state_6_.CLK
 358 clk_pin_c => line_counter_sig_8_.CLK
 359 clk_pin_c => line_counter_sig_7_.CLK
 360 clk_pin_c => line_counter_sig_6_.CLK
 361 clk_pin_c => line_counter_sig_5_.CLK
 362 clk_pin_c => line_counter_sig_4_.CLK
 363 clk_pin_c => line_counter_sig_3_.CLK
 364 clk_pin_c => line_counter_sig_2_.CLK
 365 clk_pin_c => line_counter_sig_1_.CLK
 366 clk_pin_c => line_counter_sig_0_.CLK
 367 clk_pin_c => v_enable_sig_Z.CLK
 368 clk_pin_c => h_enable_sig_Z.CLK
 369 clk_pin_c => h_sync_Z.CLK
 370 clk_pin_c => v_sync_Z.CLK
 371 clk_pin_c => vsync_state_5_.CLK
 372 clk_pin_c => vsync_state_4_.CLK
 373 clk_pin_c => vsync_state_3_.CLK
 374 clk_pin_c => vsync_state_2_.CLK
 375 clk_pin_c => hsync_state_5_.CLK
 376 clk_pin_c => hsync_state_4_.CLK
 377 clk_pin_c => hsync_state_3_.CLK
 378 clk_pin_c => hsync_state_2_.CLK
 379 clk_pin_c => hsync_state_1_.CLK
 380 clk_pin_c => hsync_state_0_.CLK
 381
 382
 383 |vga_pll|vga:inst|vga_control:vga_control_unit
 384 column_counter_sig_5 => DRAW_SQUARE_next_un5_v_enablelto5_0.DATAA
 385 column_counter_sig_0 => DRAW_SQUARE_next_un5_v_enablelto3.DATAC
 386 column_counter_sig_1 => DRAW_SQUARE_next_un5_v_enablelto3.DATAA
 387 column_counter_sig_3 => DRAW_SQUARE_next_un9_v_enablelto6.DATAC
 388 column_counter_sig_3 => DRAW_SQUARE_next_un5_v_enablelto3.DATAD
 389 column_counter_sig_4 => DRAW_SQUARE_next_un9_v_enablelto6.DATAB
 390 column_counter_sig_4 => DRAW_SQUARE_next_un5_v_enablelto5_0.DATAB
 391 column_counter_sig_2 => DRAW_SQUARE_next_un9_v_enablelto6.DATAA
 392 column_counter_sig_2 => DRAW_SQUARE_next_un5_v_enablelto3.DATAB
 393 column_counter_sig_9 => DRAW_SQUARE_next_un9_v_enablelto9.DATAC
 394 column_counter_sig_9 => b_next_0_g0_3_cZ.DATAD
 395 column_counter_sig_8 => DRAW_SQUARE_next_un9_v_enablelto9.DATAB
 396 column_counter_sig_8 => b_next_0_g0_3_cZ.DATAC
 397 column_counter_sig_7 => DRAW_SQUARE_next_un5_v_enablelto7.DATAB
 398 column_counter_sig_7 => DRAW_SQUARE_next_un9_v_enablelto9.DATAA
 399 column_counter_sig_6 => DRAW_SQUARE_next_un5_v_enablelto7.DATAA
 400 line_counter_sig_0 => DRAW_SQUARE_next_un17_v_enablelt2.DATAC
 401 line_counter_sig_1 => DRAW_SQUARE_next_un17_v_enablelt2.DATAA
 402 line_counter_sig_2 => DRAW_SQUARE_next_un13_v_enablelto8_a.DATAA
 403 line_counter_sig_2 => DRAW_SQUARE_next_un17_v_enablelt2.DATAB
 404 line_counter_sig_8 => DRAW_SQUARE_next_un13_v_enablelto8.DATAA
 405 line_counter_sig_8 => b_next_0_g0_3_cZ.DATAA
 406 line_counter_sig_3 => DRAW_SQUARE_next_un17_v_enablelto5.DATAC
 407 line_counter_sig_3 => DRAW_SQUARE_next_un13_v_enablelto8_a.DATAC
 408 line_counter_sig_5 => DRAW_SQUARE_next_un17_v_enablelto5.DATAB
 409 line_counter_sig_5 => DRAW_SQUARE_next_un13_v_enablelto8_a.DATAD
 410 line_counter_sig_4 => DRAW_SQUARE_next_un17_v_enablelto5.DATAA
 411 line_counter_sig_4 => DRAW_SQUARE_next_un13_v_enablelto8_a.DATAB
 412 line_counter_sig_7 => DRAW_SQUARE_next_un17_v_enablelto7.DATAB
 413 line_counter_sig_7 => DRAW_SQUARE_next_un13_v_enablelto8.DATAB
 414 line_counter_sig_6 => DRAW_SQUARE_next_un17_v_enablelto7.DATAA
 415 line_counter_sig_6 => DRAW_SQUARE_next_un13_v_enablelto8.DATAC
 416 toggle_counter_sig_0 <= toggle_counter_sig_0_.REGOUT
 417 toggle_counter_sig_1 <= toggle_counter_sig_1_.REGOUT
 418 toggle_counter_sig_2 <= toggle_counter_sig_2_.REGOUT
 419 toggle_counter_sig_3 <= toggle_counter_sig_3_.REGOUT
 420 toggle_counter_sig_4 <= toggle_counter_sig_4_.REGOUT
 421 toggle_counter_sig_5 <= toggle_counter_sig_5_.REGOUT
 422 toggle_counter_sig_6 <= toggle_counter_sig_6_.REGOUT
 423 toggle_counter_sig_7 <= toggle_counter_sig_7_.REGOUT
 424 toggle_counter_sig_8 <= toggle_counter_sig_8_.REGOUT
 425 toggle_counter_sig_9 <= toggle_counter_sig_9_.REGOUT
 426 toggle_counter_sig_10 <= toggle_counter_sig_10_.REGOUT
 427 toggle_counter_sig_11 <= toggle_counter_sig_11_.REGOUT
 428 toggle_counter_sig_12 <= toggle_counter_sig_12_.REGOUT
 429 toggle_counter_sig_13 <= toggle_counter_sig_13_.REGOUT
 430 toggle_counter_sig_14 <= toggle_counter_sig_14_.REGOUT
 431 toggle_counter_sig_15 <= toggle_counter_sig_15_.REGOUT
 432 toggle_counter_sig_16 <= toggle_counter_sig_16_.REGOUT
 433 toggle_counter_sig_17 <= toggle_counter_sig_17_.REGOUT
 434 toggle_counter_sig_18 <= toggle_counter_sig_18_.REGOUT
 435 toggle_counter_sig_19 <= toggle_counter_sig_19_.REGOUT
 436 toggle_counter_sig_20 <= toggle_counter_sig_20_.REGOUT
 437 toggle_counter_sig_21 <= toggle_counter_sig_21_.REGOUT
 438 toggle_counter_sig_22 <= toggle_counter_sig_22_.REGOUT
 439 toggle_counter_sig_23 <= toggle_counter_sig_23_.REGOUT
 440 toggle_counter_sig_24 <= toggle_counter_sig_24_.REGOUT
 441 v_enable_sig => b_next_0_g0_3_cZ.DATAB
 442 un10_column_counter_siglt6_1 => DRAW_SQUARE_next_un9_v_enablelto6.DATAD
 443 h_enable_sig => b_next_0_g0_5_cZ.DATAA
 444 g <= g_Z.REGOUT
 445 r <= r_Z.REGOUT
 446 b <= b_Z.REGOUT
 447 toggle_sig <= toggle_sig_Z.REGOUT
 448 un6_dly_counter_0_x => toggle_counter_sig_24_.ACLR
 449 un6_dly_counter_0_x => toggle_counter_sig_23_.ACLR
 450 un6_dly_counter_0_x => toggle_counter_sig_22_.ACLR
 451 un6_dly_counter_0_x => toggle_counter_sig_21_.ACLR
 452 un6_dly_counter_0_x => toggle_counter_sig_20_.ACLR
 453 un6_dly_counter_0_x => toggle_counter_sig_19_.ACLR
 454 un6_dly_counter_0_x => toggle_counter_sig_18_.ACLR
 455 un6_dly_counter_0_x => toggle_counter_sig_17_.ACLR
 456 un6_dly_counter_0_x => toggle_counter_sig_16_.ACLR
 457 un6_dly_counter_0_x => toggle_counter_sig_15_.ACLR
 458 un6_dly_counter_0_x => toggle_counter_sig_14_.ACLR
 459 un6_dly_counter_0_x => toggle_counter_sig_13_.ACLR
 460 un6_dly_counter_0_x => toggle_counter_sig_12_.ACLR
 461 un6_dly_counter_0_x => toggle_counter_sig_11_.ACLR
 462 un6_dly_counter_0_x => toggle_counter_sig_10_.ACLR
 463 un6_dly_counter_0_x => toggle_counter_sig_9_.ACLR
 464 un6_dly_counter_0_x => toggle_counter_sig_8_.ACLR
 465 un6_dly_counter_0_x => toggle_counter_sig_7_.ACLR
 466 un6_dly_counter_0_x => toggle_counter_sig_6_.ACLR
 467 un6_dly_counter_0_x => toggle_counter_sig_5_.ACLR
 468 un6_dly_counter_0_x => toggle_counter_sig_4_.ACLR
 469 un6_dly_counter_0_x => toggle_counter_sig_3_.ACLR
 470 un6_dly_counter_0_x => toggle_counter_sig_2_.ACLR
 471 un6_dly_counter_0_x => toggle_counter_sig_1_.ACLR
 472 un6_dly_counter_0_x => toggle_counter_sig_0_.ACLR
 473 un6_dly_counter_0_x => toggle_sig_Z.ACLR
 474 un6_dly_counter_0_x => b_Z.ACLR
 475 un6_dly_counter_0_x => r_Z.ACLR
 476 un6_dly_counter_0_x => g_Z.ACLR
 477 clk_pin_c => toggle_counter_sig_24_.CLK
 478 clk_pin_c => toggle_counter_sig_23_.CLK
 479 clk_pin_c => toggle_counter_sig_22_.CLK
 480 clk_pin_c => toggle_counter_sig_21_.CLK
 481 clk_pin_c => toggle_counter_sig_20_.CLK
 482 clk_pin_c => toggle_counter_sig_19_.CLK
 483 clk_pin_c => toggle_counter_sig_18_.CLK
 484 clk_pin_c => toggle_counter_sig_17_.CLK
 485 clk_pin_c => toggle_counter_sig_16_.CLK
 486 clk_pin_c => toggle_counter_sig_15_.CLK
 487 clk_pin_c => toggle_counter_sig_14_.CLK
 488 clk_pin_c => toggle_counter_sig_13_.CLK
 489 clk_pin_c => toggle_counter_sig_12_.CLK
 490 clk_pin_c => toggle_counter_sig_11_.CLK
 491 clk_pin_c => toggle_counter_sig_10_.CLK
 492 clk_pin_c => toggle_counter_sig_9_.CLK
 493 clk_pin_c => toggle_counter_sig_8_.CLK
 494 clk_pin_c => toggle_counter_sig_7_.CLK
 495 clk_pin_c => toggle_counter_sig_6_.CLK
 496 clk_pin_c => toggle_counter_sig_5_.CLK
 497 clk_pin_c => toggle_counter_sig_4_.CLK
 498 clk_pin_c => toggle_counter_sig_3_.CLK
 499 clk_pin_c => toggle_counter_sig_2_.CLK
 500 clk_pin_c => toggle_counter_sig_1_.CLK
 501 clk_pin_c => toggle_counter_sig_0_.CLK
 502 clk_pin_c => toggle_sig_Z.CLK
 503 clk_pin_c => b_Z.CLK
 504 clk_pin_c => r_Z.CLK
 505 clk_pin_c => g_Z.CLK
 506
 507
 508 |vga_pll|vpll:inst1
 509 inclk0 => altpll:altpll_component.inclk[0]
 510 c0 <= altpll:altpll_component.clk[0]
 511
 512
 513 |vga_pll|vpll:inst1|altpll:altpll_component
 514 inclk[0] => pll.CLK
 515 inclk[1] => ~NO_FANOUT~
 516 fbin => ~NO_FANOUT~
 517 pllena => ~NO_FANOUT~
 518 clkswitch => ~NO_FANOUT~
 519 areset => ~NO_FANOUT~
 520 pfdena => ~NO_FANOUT~
 521 clkena[0] => ~NO_FANOUT~
 522 clkena[1] => pll.ENA1
 523 clkena[2] => pll.ENA2
 524 clkena[3] => pll.ENA3
 525 clkena[4] => pll.ENA4
 526 clkena[5] => pll.ENA5
 527 extclkena[0] => pll.EXTCLKENA
 528 extclkena[1] => pll.EXTCLKENA1
 529 extclkena[2] => pll.EXTCLKENA2
 530 extclkena[3] => pll.EXTCLKENA3
 531 scanclk => ~NO_FANOUT~
 532 scanclkena => ~NO_FANOUT~
 533 scanaclr => ~NO_FANOUT~
 534 scanread => ~NO_FANOUT~
 535 scanwrite => ~NO_FANOUT~
 536 scandata => ~NO_FANOUT~
 537 phasecounterselect[0] => ~NO_FANOUT~
 538 phasecounterselect[1] => ~NO_FANOUT~
 539 phasecounterselect[2] => ~NO_FANOUT~
 540 phasecounterselect[3] => ~NO_FANOUT~
 541 phaseupdown => ~NO_FANOUT~
 542 phasestep => ~NO_FANOUT~
 543 configupdate => ~NO_FANOUT~
 544 fbmimicbidir <= <GND>
 545 clk[0] <= clk[0]~0.DB_MAX_OUTPUT_PORT_TYPE
 546 clk[1] <= <GND>
 547 clk[2] <= <GND>
 548 clk[3] <= <GND>
 549 clk[4] <= <GND>
 550 clk[5] <= <GND>
 551 extclk[0] <= <GND>
 552 extclk[1] <= <GND>
 553 extclk[2] <= <GND>
 554 extclk[3] <= <GND>
 555 clkbad[0] <= <GND>
 556 clkbad[1] <= <GND>
 557 enable1 <= <GND>
 558 enable0 <= <GND>
 559 activeclock <= <GND>
 560 clkloss <= <GND>
 561 locked <= <GND>
 562 scandataout <= <GND>
 563 scandone <= <GND>
 564 sclkout0 <= <GND>
 565 sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE
 566 phasedone <= <GND>
 567 vcooverrange <= <GND>
 568 vcounderrange <= <GND>
 569 fbout <= <GND>
 570
 571