bsp3/Designflow/syn/rev_1/vga.srr

   1 #Build: Synplify Pro C-2009.06, Build 063R, May 19 2009
   2 #install: /opt/synplify/fpga_c200906
   3 #OS: Linux
   4 #Hostname: ti14
   5
   6 #Implementation: rev_1
   7
   8 #Thu Oct 29 16:49:28 2009
   9
  10 $ Start of Compile
  11 #Thu Oct 29 16:49:28 2009
  12
  13 Synopsys VHDL Compiler, version comp400rc, Build 020R, built May 20 2009
  14 Copyright (C) 1994-2009, Synopsys Inc.  All Rights Reserved
  15
  16 @N: CD720 :"/opt/synplify/fpga_c200906/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ns
  17 @N:"/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_ent.vhd":38:7:38:9|Top entity is set to vga.
  18 VHDL syntax check successful!
  19 @N: CD630 :"/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_ent.vhd":38:7:38:9|Synthesizing work.vga.behav
  20 @N: CD231 :"/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pak.vhd":63:24:63:25|Using onehot encoding for type hsync_state_type (reset_state="1000000")
  21 @N: CD231 :"/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pak.vhd":65:24:65:25|Using onehot encoding for type vsync_state_type (reset_state="1000000")
  22 @N: CD630 :"/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_control_ent.vhd":37:7:37:17|Synthesizing work.vga_control.behav
  23 Post processing for work.vga_control.behav
  24 @N: CD630 :"/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_driver_ent.vhd":37:7:37:16|Synthesizing work.vga_driver.behav
  25 @N: CD231 :"/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pak.vhd":63:24:63:25|Using onehot encoding for type hsync_state_type (reset_state="1000000")
  26 @N: CD231 :"/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pak.vhd":65:24:65:25|Using onehot encoding for type vsync_state_type (reset_state="1000000")
  27 Post processing for work.vga_driver.behav
  28 @N: CD630 :"/homes/burban/didelu/dide_16/bsp3/Designflow/src/board_driver_ent.vhd":36:7:36:18|Synthesizing work.board_driver.behav
  29 Post processing for work.board_driver.behav
  30 Post processing for work.vga.behav
  31 @W: CL159 :"/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_control_ent.vhd":41:7:41:18|Input line_counter is unused
  32 @END
  33 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
  34 # Thu Oct 29 16:49:28 2009
  35
  36 ###########################################################]
  37 Synopsys Altera Technology Mapper, Version map450rc, Build 029R, Built May 22 2009 13:59:53
  38 Copyright (C) 1994-2009, Synopsys Inc.  All Rights Reserved
  39 Product Version C-2009.06
  40 @N: MF249 |Running in 32-bit mode.
  41 @N: MF257 |Gated clock conversion enabled
  42 @N|Running in logic synthesis mode without enhanced optimization
  43
  44 Automatic dissolve during optimization of view:work.vga(behav) of board_driver_unit(board_driver)
  45 Automatic dissolve at startup in view:work.vga(behav) of vga_control_unit(vga_control)
  46
  47 Available hyper_sources - for debug and ip models
  48         None Found
  49
  50 Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 54MB)
  51
  52 @N:"/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_driver_arc.vhd":267:4:267:5|Found counter in view:work.vga_driver(behav) inst vsync_counter[9:0]
  53 @N:"/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_driver_arc.vhd":158:4:158:5|Found counter in view:work.vga_driver(behav) inst hsync_counter[9:0]
  54 Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 54MB)
  55
  56 Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 54MB)
  57
  58 Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 54MB)
  59
  60
  61
  62 #################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[
  63
  64 ======================================================================================
  65                                 Instance:Pin        Generated Clock Optimization Status
  66 ======================================================================================
  67
  68
  69 ##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################]
  70
  71 Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 55MB)
  72
  73 Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 55MB)
  74
  75 Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 55MB)
  76
  77 Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 55MB)
  78
  79 Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 55MB)
  80
  81 Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 55MB)
  82
  83 Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 55MB)
  84
  85 Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 55MB)
  86
  87 Finished technology mapping (Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 68MB)
  88
  89 Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 68MB)
  90
  91 Finished restoring hierarchy (Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 69MB)
  92
  93
  94 Writing Analyst data base /homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.srm
  95 Finished Writing Netlist Databases (Time elapsed 0h:00m:04s; Memory used current: 64MB peak: 69MB)
  96
  97 Writing Verilog Netlist and constraint files
  98 Writing .vqm output for Quartus
  99 Writing Cross reference file for Quartus to /homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.xrf
 100 Finished Writing Verilog Netlist and constraint files (Time elapsed 0h:00m:04s; Memory used current: 64MB peak: 69MB)
 101
 102 Writing VHDL Simulation files
 103 Finished Writing VHDL Simulation files (Time elapsed 0h:00m:04s; Memory used current: 64MB peak: 69MB)
 104
 105 Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 64MB peak: 69MB)
 106
 107 @N: MF276 |Gated clock conversion enabled, but no gated clocks found in design
 108 Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 64MB peak: 69MB)
 109
 110 Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 64MB peak: 69MB)
 111
 112 @N: MF333 |Generated clock conversion enabled, but no generated clocks found in design
 113 Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 64MB peak: 69MB)
 114
 115 Found clock vga|clk_pin with period 39.72ns
 116
 117
 118 ##### START OF TIMING REPORT #####[
 119 # Timing Report written on Thu Oct 29 16:49:34 2009
 120 #
 121
 122
 123 Top view:               vga
 124 Requested Frequency:    25.2 MHz
 125 Wire load mode:         top
 126 Paths requested:        5
 127 Constraint File(s):
 128 @N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..
 129
 130 @N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock..
 131
 132
 133
 134 Performance Summary
 135 *******************
 136
 137
 138 Worst slack in design: 34.836
 139
 140                    Requested     Estimated     Requested     Estimated                Clock        Clock
 141 Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group
 142 ----------------------------------------------------------------------------------------------------------------------
 143 vga|clk_pin        25.2 MHz      204.7 MHz     39.722        4.886         34.836     inferred     Inferred_clkgroup_0
 144 ======================================================================================================================
 145
 146
 147
 148
 149
 150 Clock Relationships
 151 *******************
 152
 153 Clocks                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
 154 -----------------------------------------------------------------------------------------------------------------
 155 Starting     Ending       |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
 156 -----------------------------------------------------------------------------------------------------------------
 157 vga|clk_pin  vga|clk_pin  |  39.722      34.836  |  No paths    -      |  No paths    -      |  No paths    -
 158 =================================================================================================================
 159  Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
 160        'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 161
 162
 163
 164 Interface Information
 165 *********************
 166
 167                 No IO constraint found
 168
 169
 170
 171 ====================================
 172 Detailed Report for Clock: vga|clk_pin
 173 ====================================
 174
 175
 176
 177 Starting Points with Worst Slack
 178 ********************************
 179
 180                                      Starting                                                            Arrival
 181 Instance                             Reference       Type                 Pin        Net                 Time        Slack
 182                                      Clock
 183 ---------------------------------------------------------------------------------------------------------------------------
 184 vga_driver_unit.vsync_counter[6]     vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_6     0.176       34.836
 185 vga_driver_unit.vsync_counter[7]     vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_7     0.176       34.865
 186 vga_driver_unit.vsync_counter[3]     vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_3     0.176       34.992
 187 vga_driver_unit.vsync_counter[8]     vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_8     0.176       34.992
 188 vga_driver_unit.vsync_counter[5]     vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_5     0.176       35.111
 189 vga_driver_unit.vsync_counter[4]     vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_4     0.176       35.119
 190 vga_driver_unit.vsync_counter[9]     vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_9     0.176       35.208
 191 vga_driver_unit.vsync_counter[1]     vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_1     0.176       35.238
 192 vga_driver_unit.hsync_counter[8]     vga|clk_pin     stratix_lcell_ff     regout     hsync_counter_8     0.176       35.299
 193 dly_counter[0]                       vga|clk_pin     stratix_lcell_ff     regout     dly_counter[0]      0.176       35.308
 194 ===========================================================================================================================
 195
 196
 197 Ending Points with Worst Slack
 198 ******************************
 199
 200                                    Starting                                                                   Required
 201 Instance                           Reference       Type                 Pin     Net                           Time         Slack
 202                                    Clock
 203 ---------------------------------------------------------------------------------------------------------------------------------
 204 vga_driver_unit.vsync_state[2]     vga|clk_pin     stratix_lcell_ff     ena     vsync_state_next_2_sqmuxa     38.986       34.836
 205 vga_driver_unit.vsync_state[3]     vga|clk_pin     stratix_lcell_ff     ena     vsync_state_next_2_sqmuxa     38.986       34.836
 206 vga_driver_unit.vsync_state[4]     vga|clk_pin     stratix_lcell_ff     ena     vsync_state_next_2_sqmuxa     38.986       34.836
 207 vga_driver_unit.vsync_state[5]     vga|clk_pin     stratix_lcell_ff     ena     vsync_state_next_2_sqmuxa     38.986       34.836
 208 vga_driver_unit.hsync_state[0]     vga|clk_pin     stratix_lcell_ff     ena     hsync_state_3_0_0_0__g0_0     38.986       35.299
 209 vga_driver_unit.hsync_state[1]     vga|clk_pin     stratix_lcell_ff     ena     hsync_state_3_0_0_0__g0_0     38.986       35.299
 210 vga_driver_unit.hsync_state[2]     vga|clk_pin     stratix_lcell_ff     ena     hsync_state_3_0_0_0__g0_0     38.986       35.299
 211 vga_driver_unit.hsync_state[3]     vga|clk_pin     stratix_lcell_ff     ena     hsync_state_3_0_0_0__g0_0     38.986       35.299
 212 vga_driver_unit.hsync_state[4]     vga|clk_pin     stratix_lcell_ff     ena     hsync_state_3_0_0_0__g0_0     38.986       35.299
 213 vga_driver_unit.hsync_state[5]     vga|clk_pin     stratix_lcell_ff     ena     hsync_state_3_0_0_0__g0_0     38.986       35.299
 214 =================================================================================================================================
 215
 216
 217
 218 Worst Path Information
 219 ***********************
 220
 221
 222 Path information for path number 1:
 223     Requested Period:                        39.722
 224     - Setup time:                            0.736
 225     + Clock delay at ending point:           0.000 (ideal)
 226     = Required time:                         38.986
 227
 228     - Propagation time:                      4.150
 229     - Clock delay at starting point:         0.000 (ideal)
 230     = Slack (critical) :                     34.836
 231
 232     Number of logic level(s):                5
 233     Starting point:                          vga_driver_unit.vsync_counter[6] / regout
 234     Ending point:                            vga_driver_unit.vsync_state[2] / ena
 235     The start point is clocked by            vga|clk_pin [rising] on pin clk
 236     The end   point is clocked by            vga|clk_pin [rising] on pin clk
 237
 238 Instance / Net                                                               Pin         Pin               Arrival     No. of
 239 Name                                                    Type                 Name        Dir     Delay     Time        Fan Out(s)
 240 ---------------------------------------------------------------------------------------------------------------------------------
 241 vga_driver_unit.vsync_counter[6]                        stratix_lcell_ff     regout      Out     0.176     0.176       -
 242 vsync_counter_6                                         Net                  -           -       1.000     -           5
 243 vga_driver_unit.VSYNC_FSM_next\.un13_vsync_counter_3    stratix_lcell        dataa       In      -         1.176       -
 244 vga_driver_unit.VSYNC_FSM_next\.un13_vsync_counter_3    stratix_lcell        combout     Out     0.459     1.635       -
 245 un13_vsync_counter_3                                    Net                  -           -       0.376     -           1
 246 vga_driver_unit.VSYNC_FSM_next\.un13_vsync_counter_4    stratix_lcell        datac       In      -         2.011       -
 247 vga_driver_unit.VSYNC_FSM_next\.un13_vsync_counter_4    stratix_lcell        combout     Out     0.213     2.224       -
 248 un13_vsync_counter_4                                    Net                  -           -       0.393     -           2
 249 vga_driver_unit.vsync_state_next_1_sqmuxa_2             stratix_lcell        datac       In      -         2.618       -
 250 vga_driver_unit.vsync_state_next_1_sqmuxa_2             stratix_lcell        combout     Out     0.213     2.830       -
 251 vsync_state_next_1_sqmuxa_2                             Net                  -           -       0.376     -           1
 252 vga_driver_unit.un1_vsync_state_next_1_sqmuxa_0         stratix_lcell        datad       In      -         3.207       -
 253 vga_driver_unit.un1_vsync_state_next_1_sqmuxa_0         stratix_lcell        combout     Out     0.087     3.294       -
 254 un1_vsync_state_next_1_sqmuxa_0                         Net                  -           -       0.376     -           1
 255 vga_driver_unit.vsync_state_next_2_sqmuxa               stratix_lcell        datad       In      -         3.670       -
 256 vga_driver_unit.vsync_state_next_2_sqmuxa               stratix_lcell        combout     Out     0.087     3.757       -
 257 vsync_state_next_2_sqmuxa                               Net                  -           -       0.393     -           5(2)
 258 vga_driver_unit.vsync_state[2]                          stratix_lcell_ff     ena         In      -         4.150       -
 259 =================================================================================================================================
 260 Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 4.886 is 1.971(40.3%) logic and 2.915(59.7%) route.
 261 Fanout format: logic fanout (physical fanout)
 262 Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
 263 *Arrival time includes intrinsic clock delay at start point and clock delay at startpoint
 264
 265
 266
 267 ##### END OF TIMING REPORT #####]
 268
 269 ##### START OF AREA REPORT #####[
 270 Design view:work.vga(behav)
 271 Selecting part EP1S25F672C6
 272 @N: FA174 |The following device usage report estimates place and route data. Please look at the place and route report for final resource usage..
 273
 274 I/O ATOMs:       91
 275
 276 Total LUTs:  141 of 25660 ( 0%)
 277 Logic resources:  143 ATOMs of 25660 ( 0%)
 278
 279 Number of I/O registers
 280                         Output DDRs   :0
 281
 282 ATOM count by mode:
 283   normal:       109
 284   arithmetic:   34
 285
 286 DSP Blocks:     0  (0 nine-bit DSP elements).
 287 DSP Utilization: 0.00% of available 10 blocks (80 nine-bit).
 288 ShiftTap:       0  (0 registers)
 289 MRAM:           0  (0% of 2)
 290 M4Ks:           0  (0% of 138)
 291 M512s:          0  (0% of 224)
 292 Total ESB:      0 bits
 293
 294 ATOMs using regout pin: 62
 295   also using enable pin: 12
 296   also using combout pin: 1
 297 ATOMs using combout pin: 80
 298 Number of Inputs on ATOMs: 585
 299 Number of Nets:   40117
 300
 301 ##### END OF AREA REPORT #####]
 302
 303 Mapper successful!
 304 Process took 0h:00m:04s realtime, 0h:00m:04s cputime
 305 # Thu Oct 29 16:49:34 2009
 306
 307 ###########################################################]