bsp3/Designflow/syn/rev_1/syntmp/vga_srr.htm

   1 <html><body><samp><pre>
   2 <!@TC:1256831368>
   3 #Build: Synplify Pro C-2009.06, Build 063R, May 19 2009
   4 #install: /opt/synplify/fpga_c200906
   5 #OS: Linux
   6 #Hostname: ti14
   7
   8 #Implementation: rev_1
   9
  10 #Thu Oct 29 16:49:28 2009
  11
  12 <a name=compilerReport24>$ Start of Compile</a>
  13 #Thu Oct 29 16:49:28 2009
  14
  15 Synopsys VHDL Compiler, version comp400rc, Build 020R, built May 20 2009
  16 Copyright (C) 1994-2009, Synopsys Inc.  All Rights Reserved
  17
  18 @N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="/opt/synplify/fpga_c200906/lib/vhd/std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1256831368> | Setting time resolution to ns
  19 @N: : <a href="/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_ent.vhd:38:7:38:10:@N::@XP_MSG">vga_ent.vhd(38)</a><!@TM:1256831368> | Top entity is set to vga.
  20 VHDL syntax check successful!
  21 @N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_ent.vhd:38:7:38:10:@N:CD630:@XP_MSG">vga_ent.vhd(38)</a><!@TM:1256831368> | Synthesizing work.vga.behav
  22 @N:<a href="@N:CD231:@XP_HELP">CD231</a> : <a href="/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pak.vhd:63:24:63:26:@N:CD231:@XP_MSG">vga_pak.vhd(63)</a><!@TM:1256831368> | Using onehot encoding for type hsync_state_type (reset_state="1000000")
  23 @N:<a href="@N:CD231:@XP_HELP">CD231</a> : <a href="/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pak.vhd:65:24:65:26:@N:CD231:@XP_MSG">vga_pak.vhd(65)</a><!@TM:1256831368> | Using onehot encoding for type vsync_state_type (reset_state="1000000")
  24 @N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_control_ent.vhd:37:7:37:18:@N:CD630:@XP_MSG">vga_control_ent.vhd(37)</a><!@TM:1256831368> | Synthesizing work.vga_control.behav
  25 Post processing for work.vga_control.behav
  26 @N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_driver_ent.vhd:37:7:37:17:@N:CD630:@XP_MSG">vga_driver_ent.vhd(37)</a><!@TM:1256831368> | Synthesizing work.vga_driver.behav
  27 @N:<a href="@N:CD231:@XP_HELP">CD231</a> : <a href="/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pak.vhd:63:24:63:26:@N:CD231:@XP_MSG">vga_pak.vhd(63)</a><!@TM:1256831368> | Using onehot encoding for type hsync_state_type (reset_state="1000000")
  28 @N:<a href="@N:CD231:@XP_HELP">CD231</a> : <a href="/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pak.vhd:65:24:65:26:@N:CD231:@XP_MSG">vga_pak.vhd(65)</a><!@TM:1256831368> | Using onehot encoding for type vsync_state_type (reset_state="1000000")
  29 Post processing for work.vga_driver.behav
  30 @N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/homes/burban/didelu/dide_16/bsp3/Designflow/src/board_driver_ent.vhd:36:7:36:19:@N:CD630:@XP_MSG">board_driver_ent.vhd(36)</a><!@TM:1256831368> | Synthesizing work.board_driver.behav
  31 Post processing for work.board_driver.behav
  32 Post processing for work.vga.behav
  33 <font color=#A52A2A>@W:<a href="@W:CL159:@XP_HELP">CL159</a> : <a href="/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_control_ent.vhd:41:7:41:19:@W:CL159:@XP_MSG">vga_control_ent.vhd(41)</a><!@TM:1256831368> | Input line_counter is unused</font>
  34 @END
  35 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
  36 # Thu Oct 29 16:49:28 2009
  37
  38 ###########################################################]
  39 <a name=mapperReport25>Synopsys Altera Technology Mapper, Version map450rc, Build 029R, Built May 22 2009 13:59:53</a>
  40 Copyright (C) 1994-2009, Synopsys Inc.  All Rights Reserved
  41 Product Version C-2009.06
  42 @N:<a href="@N:MF249:@XP_HELP">MF249</a> : <!@TM:1256831374> | Running in 32-bit mode.
  43 @N:<a href="@N:MF257:@XP_HELP">MF257</a> : <!@TM:1256831374> | Gated clock conversion enabled
  44 @N: : <!@TM:1256831374> | Running in logic synthesis mode without enhanced optimization
  45
  46 Automatic dissolve during optimization of view:work.vga(behav) of board_driver_unit(board_driver)
  47 Automatic dissolve at startup in view:work.vga(behav) of vga_control_unit(vga_control)
  48
  49 Available hyper_sources - for debug and ip models
  50         None Found
  51
  52 Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 54MB)
  53
  54 @N: : <a href="/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_driver_arc.vhd:267:4:267:6:@N::@XP_MSG">vga_driver_arc.vhd(267)</a><!@TM:1256831374> | Found counter in view:work.vga_driver(behav) inst vsync_counter[9:0]
  55 @N: : <a href="/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_driver_arc.vhd:158:4:158:6:@N::@XP_MSG">vga_driver_arc.vhd(158)</a><!@TM:1256831374> | Found counter in view:work.vga_driver(behav) inst hsync_counter[9:0]
  56 Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 54MB)
  57
  58 Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 54MB)
  59
  60 Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 54MB)
  61
  62
  63
  64 #################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[
  65
  66 ======================================================================================
  67                                 Instance:Pin        Generated Clock Optimization Status
  68 ======================================================================================
  69
  70
  71 ##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################]
  72
  73 Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 55MB)
  74
  75 Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 55MB)
  76
  77 Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 55MB)
  78
  79 Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 55MB)
  80
  81 Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 55MB)
  82
  83 Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 55MB)
  84
  85 Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 55MB)
  86
  87 Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 55MB)
  88
  89 Finished technology mapping (Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 68MB)
  90
  91 Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 68MB)
  92
  93 Finished restoring hierarchy (Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 69MB)
  94
  95
  96 Writing Analyst data base /homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.srm
  97 Finished Writing Netlist Databases (Time elapsed 0h:00m:04s; Memory used current: 64MB peak: 69MB)
  98
  99 Writing Verilog Netlist and constraint files
 100 Writing .vqm output for Quartus
 101 Writing Cross reference file for Quartus to /homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.xrf
 102 Finished Writing Verilog Netlist and constraint files (Time elapsed 0h:00m:04s; Memory used current: 64MB peak: 69MB)
 103
 104 Writing VHDL Simulation files
 105 Finished Writing VHDL Simulation files (Time elapsed 0h:00m:04s; Memory used current: 64MB peak: 69MB)
 106
 107 Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 64MB peak: 69MB)
 108
 109 @N:<a href="@N:MF276:@XP_HELP">MF276</a> : <!@TM:1256831374> | Gated clock conversion enabled, but no gated clocks found in design
 110 Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 64MB peak: 69MB)
 111
 112 Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 64MB peak: 69MB)
 113
 114 @N:<a href="@N:MF333:@XP_HELP">MF333</a> : <!@TM:1256831374> | Generated clock conversion enabled, but no generated clocks found in design
 115 Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 64MB peak: 69MB)
 116
 117 Found clock vga|clk_pin with period 39.72ns
 118
 119
 120 <a name=timingReport26>##### START OF TIMING REPORT #####[</a>
 121 # Timing Report written on Thu Oct 29 16:49:34 2009
 122 #
 123
 124
 125 Top view:               vga
 126 Requested Frequency:    25.2 MHz
 127 Wire load mode:         top
 128 Paths requested:        5
 129 Constraint File(s):
 130 @N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1256831374> | This timing report estimates place and route data. Please look at the place and route timing report for final timing..
 131
 132 @N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1256831374> | Clock constraints cover only FF-to-FF paths associated with the clock..
 133
 134
 135
 136 <a name=performanceSummary27>Performance Summary </a>
 137 *******************
 138
 139
 140 Worst slack in design: 34.836
 141
 142                    Requested     Estimated     Requested     Estimated                Clock        Clock
 143 Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group
 144 ----------------------------------------------------------------------------------------------------------------------
 145 vga|clk_pin        25.2 MHz      204.7 MHz     39.722        4.886         34.836     inferred     Inferred_clkgroup_0
 146 ======================================================================================================================
 147
 148
 149
 150
 151
 152 <a name=clockRelationships28>Clock Relationships</a>
 153 *******************
 154
 155 Clocks                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
 156 -----------------------------------------------------------------------------------------------------------------
 157 Starting     Ending       |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
 158 -----------------------------------------------------------------------------------------------------------------
 159 vga|clk_pin  vga|clk_pin  |  39.722      34.836  |  No paths    -      |  No paths    -      |  No paths    -
 160 =================================================================================================================
 161  Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
 162        'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 163
 164
 165
 166 <a name=interfaceInfo29>Interface Information </a>
 167 *********************
 168
 169                 No IO constraint found
 170
 171
 172
 173 ====================================
 174 <a name=clockReport30>Detailed Report for Clock: vga|clk_pin</a>
 175 ====================================
 176
 177
 178
 179 <a name=startingSlack31>Starting Points with Worst Slack</a>
 180 ********************************
 181
 182                                      Starting                                                            Arrival
 183 Instance                             Reference       Type                 Pin        Net                 Time        Slack
 184                                      Clock
 185 ---------------------------------------------------------------------------------------------------------------------------
 186 vga_driver_unit.vsync_counter[6]     vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_6     0.176       34.836
 187 vga_driver_unit.vsync_counter[7]     vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_7     0.176       34.865
 188 vga_driver_unit.vsync_counter[3]     vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_3     0.176       34.992
 189 vga_driver_unit.vsync_counter[8]     vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_8     0.176       34.992
 190 vga_driver_unit.vsync_counter[5]     vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_5     0.176       35.111
 191 vga_driver_unit.vsync_counter[4]     vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_4     0.176       35.119
 192 vga_driver_unit.vsync_counter[9]     vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_9     0.176       35.208
 193 vga_driver_unit.vsync_counter[1]     vga|clk_pin     stratix_lcell_ff     regout     vsync_counter_1     0.176       35.238
 194 vga_driver_unit.hsync_counter[8]     vga|clk_pin     stratix_lcell_ff     regout     hsync_counter_8     0.176       35.299
 195 dly_counter[0]                       vga|clk_pin     stratix_lcell_ff     regout     dly_counter[0]      0.176       35.308
 196 ===========================================================================================================================
 197
 198
 199 <a name=endingSlack32>Ending Points with Worst Slack</a>
 200 ******************************
 201
 202                                    Starting                                                                   Required
 203 Instance                           Reference       Type                 Pin     Net                           Time         Slack
 204                                    Clock
 205 ---------------------------------------------------------------------------------------------------------------------------------
 206 vga_driver_unit.vsync_state[2]     vga|clk_pin     stratix_lcell_ff     ena     vsync_state_next_2_sqmuxa     38.986       34.836
 207 vga_driver_unit.vsync_state[3]     vga|clk_pin     stratix_lcell_ff     ena     vsync_state_next_2_sqmuxa     38.986       34.836
 208 vga_driver_unit.vsync_state[4]     vga|clk_pin     stratix_lcell_ff     ena     vsync_state_next_2_sqmuxa     38.986       34.836
 209 vga_driver_unit.vsync_state[5]     vga|clk_pin     stratix_lcell_ff     ena     vsync_state_next_2_sqmuxa     38.986       34.836
 210 vga_driver_unit.hsync_state[0]     vga|clk_pin     stratix_lcell_ff     ena     hsync_state_3_0_0_0__g0_0     38.986       35.299
 211 vga_driver_unit.hsync_state[1]     vga|clk_pin     stratix_lcell_ff     ena     hsync_state_3_0_0_0__g0_0     38.986       35.299
 212 vga_driver_unit.hsync_state[2]     vga|clk_pin     stratix_lcell_ff     ena     hsync_state_3_0_0_0__g0_0     38.986       35.299
 213 vga_driver_unit.hsync_state[3]     vga|clk_pin     stratix_lcell_ff     ena     hsync_state_3_0_0_0__g0_0     38.986       35.299
 214 vga_driver_unit.hsync_state[4]     vga|clk_pin     stratix_lcell_ff     ena     hsync_state_3_0_0_0__g0_0     38.986       35.299
 215 vga_driver_unit.hsync_state[5]     vga|clk_pin     stratix_lcell_ff     ena     hsync_state_3_0_0_0__g0_0     38.986       35.299
 216 =================================================================================================================================
 217
 218
 219
 220 <a name=worstPaths33>Worst Path Information</a>
 221 <a href="/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.srr:fp:13723:16063:@XP_NAMES_GATE">View Worst Path in Analyst</a>
 222 ***********************
 223
 224
 225 Path information for path number 1:
 226     Requested Period:                        39.722
 227     - Setup time:                            0.736
 228     + Clock delay at ending point:           0.000 (ideal)
 229     = Required time:                         38.986
 230
 231     - Propagation time:                      4.150
 232     - Clock delay at starting point:         0.000 (ideal)
 233     = Slack (critical) :                     34.836
 234
 235     Number of logic level(s):                5
 236     Starting point:                          vga_driver_unit.vsync_counter[6] / regout
 237     Ending point:                            vga_driver_unit.vsync_state[2] / ena
 238     The start point is clocked by            vga|clk_pin [rising] on pin clk
 239     The end   point is clocked by            vga|clk_pin [rising] on pin clk
 240
 241 Instance / Net                                                               Pin         Pin               Arrival     No. of
 242 Name                                                    Type                 Name        Dir     Delay     Time        Fan Out(s)
 243 ---------------------------------------------------------------------------------------------------------------------------------
 244 vga_driver_unit.vsync_counter[6]                        stratix_lcell_ff     regout      Out     0.176     0.176       -
 245 vsync_counter_6                                         Net                  -           -       1.000     -           5
 246 vga_driver_unit.VSYNC_FSM_next\.un13_vsync_counter_3    stratix_lcell        dataa       In      -         1.176       -
 247 vga_driver_unit.VSYNC_FSM_next\.un13_vsync_counter_3    stratix_lcell        combout     Out     0.459     1.635       -
 248 un13_vsync_counter_3                                    Net                  -           -       0.376     -           1
 249 vga_driver_unit.VSYNC_FSM_next\.un13_vsync_counter_4    stratix_lcell        datac       In      -         2.011       -
 250 vga_driver_unit.VSYNC_FSM_next\.un13_vsync_counter_4    stratix_lcell        combout     Out     0.213     2.224       -
 251 un13_vsync_counter_4                                    Net                  -           -       0.393     -           2
 252 vga_driver_unit.vsync_state_next_1_sqmuxa_2             stratix_lcell        datac       In      -         2.618       -
 253 vga_driver_unit.vsync_state_next_1_sqmuxa_2             stratix_lcell        combout     Out     0.213     2.830       -
 254 vsync_state_next_1_sqmuxa_2                             Net                  -           -       0.376     -           1
 255 vga_driver_unit.un1_vsync_state_next_1_sqmuxa_0         stratix_lcell        datad       In      -         3.207       -
 256 vga_driver_unit.un1_vsync_state_next_1_sqmuxa_0         stratix_lcell        combout     Out     0.087     3.294       -
 257 un1_vsync_state_next_1_sqmuxa_0                         Net                  -           -       0.376     -           1
 258 vga_driver_unit.vsync_state_next_2_sqmuxa               stratix_lcell        datad       In      -         3.670       -
 259 vga_driver_unit.vsync_state_next_2_sqmuxa               stratix_lcell        combout     Out     0.087     3.757       -
 260 vsync_state_next_2_sqmuxa                               Net                  -           -       0.393     -           5(2)
 261 vga_driver_unit.vsync_state[2]                          stratix_lcell_ff     ena         In      -         4.150       -
 262 =================================================================================================================================
 263 Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 4.886 is 1.971(40.3%) logic and 2.915(59.7%) route.
 264 Fanout format: logic fanout (physical fanout)
 265 Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
 266 *Arrival time includes intrinsic clock delay at start point and clock delay at startpoint
 267
 268
 269
 270 ##### END OF TIMING REPORT #####]
 271
 272 <a name=areaReport34>##### START OF AREA REPORT #####[</a>
 273 Design view:work.vga(behav)
 274 Selecting part EP1S25F672C6
 275 @N:<a href="@N:FA174:@XP_HELP">FA174</a> : <!@TM:1256831374> | The following device usage report estimates place and route data. Please look at the place and route report for final resource usage..
 276
 277 I/O ATOMs:       91
 278
 279 Total LUTs:  141 of 25660 ( 0%)
 280 Logic resources:  143 ATOMs of 25660 ( 0%)
 281
 282 Number of I/O registers
 283                         Output DDRs   :0
 284
 285 ATOM count by mode:
 286   normal:       109
 287   arithmetic:   34
 288
 289 DSP Blocks:     0  (0 nine-bit DSP elements).
 290 DSP Utilization: 0.00% of available 10 blocks (80 nine-bit).
 291 ShiftTap:       0  (0 registers)
 292 MRAM:           0  (0% of 2)
 293 M4Ks:           0  (0% of 138)
 294 M512s:          0  (0% of 224)
 295 Total ESB:      0 bits
 296
 297 ATOMs using regout pin: 62
 298   also using enable pin: 12
 299   also using combout pin: 1
 300 ATOMs using combout pin: 80
 301 Number of Inputs on ATOMs: 585
 302 Number of Nets:   40117
 303
 304 ##### END OF AREA REPORT #####]
 305
 306 Mapper successful!
 307 Process took 0h:00m:04s realtime, 0h:00m:04s cputime
 308 # Thu Oct 29 16:49:34 2009
 309
 310 ###########################################################]