bsp3/Designflow/syn/rev_1/backup/vga.srr

   1 #Build: Synplify Pro C-2009.06, Build 063R, May 19 2009
   2 #install: /opt/synplify/fpga_c200906
   3 #OS: Linux
   4 #Hostname: ti14
   5
   6 #Implementation: rev_1
   7
   8 #Thu Oct 29 16:44:32 2009
   9
  10 $ Start of Compile
  11 #Thu Oct 29 16:44:32 2009
  12
  13 Synopsys VHDL Compiler, version comp400rc, Build 020R, built May 20 2009
  14 Copyright (C) 1994-2009, Synopsys Inc.  All Rights Reserved
  15
  16 @N: CD720 :"/opt/synplify/fpga_c200906/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ns
  17 @N:"/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_ent.vhd":38:7:38:9|Top entity is set to vga.
  18 @E: CD169 :"/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_control_arc.vhd":43:2:43:16|Illegal declaration
  19 1 error parsing file /homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_control_arc.vhd
  20 @END
  21 1 error parsing file /homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_driver_arc.vhd
  22 @END
  23 @E|Parse errors encountered - exiting
  24 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
  25 # Thu Oct 29 16:44:32 2009
  26
  27 ###########################################################]