1 # Copyright (C) 1991-2006 Altera Corporation
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2 # Your use of Altera Corporation's design tools, logic functions
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3 # and other software and tools, and its AMPP partner logic
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4 # functions, and any output files any of the foregoing
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5 # (including device programming or simulation files), and any
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6 # associated documentation or information are expressly subject
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7 # to the terms and conditions of the Altera Program License
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8 # Subscription Agreement, Altera MegaCore Function License
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9 # Agreement, or other applicable license agreement, including,
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10 # without limitation, that your use is for the sole purpose of
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11 # programming logic devices manufactured by Altera and sold by
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12 # Altera or its authorized distributors. Please refer to the
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13 # applicable agreement for further details.
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15 # Quartus II: Generate Tcl File for Project
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17 # Generated on: Fri Sep 29 09:31:24 2006
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19 # Load Quartus II Tcl Project package
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20 package require ::quartus::project
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21 package require ::quartus::flow
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23 set need_to_close_project 0
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24 set make_assignments 1
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26 # Check that the right project is open
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27 if {[is_project_open]} {
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28 if {[string compare $quartus(project) "vga_pll"]} {
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29 puts "Project vga_pll is not open"
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30 set make_assignments 0
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33 # Only open if not already open
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34 if {[project_exists vga_pll]} {
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35 project_open -cmp vga_pll vga_pll
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37 project_new -cmp vga_pll vga_pll
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39 set need_to_close_project 1
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43 if {$make_assignments} {
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44 catch { set_global_assignment -name FAMILY Stratix } result
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45 catch { set_global_assignment -name DEVICE EP1S25F672C6 } result
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46 catch { set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0 } result
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47 catch { set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:04:10 SEPTEMBER 29, 2006" } result
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48 catch { set_global_assignment -name LAST_QUARTUS_VERSION 6.0 } result
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49 catch { set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Synplify Pro" } result
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50 catch { set_global_assignment -name EDA_LMF_FILE synplcty.lmf -section_id eda_design_synthesis } result
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51 catch { set_global_assignment -name EDA_INPUT_DATA_FORMAT VQM -section_id eda_design_synthesis } result
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52 catch { set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" } result
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53 catch { set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation } result
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54 catch { set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation } result
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55 catch { set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA } result
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56 catch { set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 } result
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57 catch { set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 } result
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58 catch { set_global_assignment -name BSF_FILE ../../src/vpll.bsf } result
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59 catch { set_global_assignment -name VHDL_FILE ../../src/vpll.vhd } result
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60 catch { set_global_assignment -name BDF_FILE ../../src/vga_pll.bdf } result
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61 catch { set_global_assignment -name VQM_FILE ../../syn/rev_1/vga.vqm } result
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63 set_location_assignment PIN_E24 -to b0_pin
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64 set_location_assignment PIN_T6 -to b1_pin
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65 set_location_assignment PIN_N3 -to board_clk
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66 set_location_assignment PIN_E23 -to g0_pin
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67 set_location_assignment PIN_T5 -to g1_pin
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68 set_location_assignment PIN_T24 -to g2_pin
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69 set_location_assignment PIN_F1 -to hsync_pin
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70 set_location_assignment PIN_E22 -to r0_pin
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71 set_location_assignment PIN_T4 -to r1_pin
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72 set_location_assignment PIN_T7 -to r2_pin
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73 set_location_assignment PIN_A5 -to reset
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74 set_location_assignment PIN_F2 -to vsync_pin
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75 set_location_assignment PIN_Y5 -to d_hsync_state[0]
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76 set_location_assignment PIN_F19 -to d_hsync_state[1]
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77 set_location_assignment PIN_F17 -to d_hsync_state[2]
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78 set_location_assignment PIN_Y2 -to d_hsync_state[3]
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79 set_location_assignment PIN_F10 -to d_hsync_state[4]
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80 set_location_assignment PIN_F9 -to d_hsync_state[5]
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81 set_location_assignment PIN_F6 -to d_hsync_state[6]
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82 set_location_assignment PIN_H4 -to d_hsync_counter[0]
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83 set_location_assignment PIN_G25 -to d_hsync_counter[7]
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84 set_location_assignment PIN_G22 -to d_hsync_counter[8]
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85 set_location_assignment PIN_G18 -to d_hsync_counter[9]
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86 set_location_assignment PIN_F5 -to d_vsync_state[0]
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87 set_location_assignment PIN_F4 -to d_vsync_state[1]
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88 set_location_assignment PIN_F3 -to d_vsync_state[2]
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89 set_location_assignment PIN_M19 -to d_vsync_state[3]
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90 set_location_assignment PIN_M18 -to d_vsync_state[4]
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91 set_location_assignment PIN_M7 -to d_vsync_state[5]
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92 set_location_assignment PIN_M4 -to d_vsync_state[6]
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93 set_location_assignment PIN_G9 -to d_vsync_counter[0]
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94 set_location_assignment PIN_G6 -to d_vsync_counter[7]
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95 set_location_assignment PIN_G4 -to d_vsync_counter[8]
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96 set_location_assignment PIN_G2 -to d_vsync_counter[9]
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97 set_location_assignment PIN_K6 -to d_line_counter[0]
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98 set_location_assignment PIN_K4 -to d_line_counter[1]
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99 set_location_assignment PIN_J22 -to d_line_counter[2]
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100 set_location_assignment PIN_M9 -to d_line_counter[3]
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101 set_location_assignment PIN_M8 -to d_line_counter[4]
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102 set_location_assignment PIN_M6 -to d_line_counter[5]
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103 set_location_assignment PIN_M5 -to d_line_counter[6]
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104 set_location_assignment PIN_L24 -to d_line_counter[7]
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105 set_location_assignment PIN_L25 -to d_line_counter[8]
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106 set_location_assignment PIN_L23 -to d_column_counter[0]
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107 set_location_assignment PIN_L22 -to d_column_counter[1]
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108 set_location_assignment PIN_L21 -to d_column_counter[2]
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109 set_location_assignment PIN_L20 -to d_column_counter[3]
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110 set_location_assignment PIN_L6 -to d_column_counter[4]
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111 set_location_assignment PIN_L4 -to d_column_counter[5]
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112 set_location_assignment PIN_L2 -to d_column_counter[6]
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113 set_location_assignment PIN_K23 -to d_column_counter[7]
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114 set_location_assignment PIN_K19 -to d_column_counter[8]
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115 set_location_assignment PIN_K5 -to d_column_counter[9]
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116 set_location_assignment PIN_L7 -to d_hsync
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117 set_location_assignment PIN_L5 -to d_vsync
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118 set_location_assignment PIN_F26 -to d_set_hsync_counter
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119 set_location_assignment PIN_F24 -to d_set_vsync_counter
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120 set_location_assignment PIN_F21 -to d_set_line_counter
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121 set_location_assignment PIN_Y23 -to d_set_column_counter
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122 set_location_assignment PIN_L3 -to d_r
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123 set_location_assignment PIN_K24 -to d_g
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124 set_location_assignment PIN_K20 -to d_b
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125 set_location_assignment PIN_H18 -to d_v_enable
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126 set_location_assignment PIN_J21 -to d_h_enable
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127 set_location_assignment PIN_R8 -to seven_seg_pin[0]
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128 set_location_assignment PIN_R9 -to seven_seg_pin[1]
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129 set_location_assignment PIN_R19 -to seven_seg_pin[2]
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130 set_location_assignment PIN_R20 -to seven_seg_pin[3]
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131 set_location_assignment PIN_R21 -to seven_seg_pin[4]
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132 set_location_assignment PIN_R22 -to seven_seg_pin[5]
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133 set_location_assignment PIN_R23 -to seven_seg_pin[6]
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134 set_location_assignment PIN_Y11 -to seven_seg_pin[7]
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135 set_location_assignment PIN_N7 -to seven_seg_pin[8]
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136 set_location_assignment PIN_N8 -to seven_seg_pin[9]
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137 set_location_assignment PIN_R4 -to seven_seg_pin[10]
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138 set_location_assignment PIN_R6 -to seven_seg_pin[11]
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139 set_location_assignment PIN_AA11 -to seven_seg_pin[12]
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140 set_location_assignment PIN_T2 -to seven_seg_pin[13]
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141 set_location_assignment PIN_K3 -to d_state_clk
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142 set_location_assignment PIN_H3 -to d_toggle
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143 set_location_assignment PIN_H26 -to d_toggle_counter[0]
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144 set_location_assignment PIN_G24 -to d_toggle_counter[15]
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145 set_location_assignment PIN_G23 -to d_toggle_counter[16]
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146 set_location_assignment PIN_G21 -to d_toggle_counter[17]
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147 set_location_assignment PIN_G20 -to d_toggle_counter[18]
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148 set_location_assignment PIN_G5 -to d_toggle_counter[19]
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149 set_location_assignment PIN_G3 -to d_toggle_counter[20]
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150 set_location_assignment PIN_G1 -to d_toggle_counter[21]
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151 set_location_assignment PIN_F25 -to d_toggle_counter[22]
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152 set_location_assignment PIN_F23 -to d_toggle_counter[23]
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153 set_location_assignment PIN_T19 -to d_toggle_counter[24]
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154 set_instance_assignment -name SLOW_SLEW_RATE ON -to d_column_counter
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155 set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter
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156 set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[1]
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157 set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[2]
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158 set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[3]
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159 set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[4]
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160 set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[5]
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161 set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[6]
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162 set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_state
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163 set_instance_assignment -name SLOW_SLEW_RATE ON -to d_line_counter
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164 set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter
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165 set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[1]
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166 set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[2]
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167 set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[3]
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168 set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[4]
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169 set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[5]
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170 set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[6]
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171 set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_state
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172 set_instance_assignment -name SLOW_SLEW_RATE ON -to seven_seg_pin
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175 # Commit assignments
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178 execute_flow -compile
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181 if {$need_to_close_project} {
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