bsp2/Designflow/ppr/download/vga_pll.flow.rpt

   1 Flow report for vga_pll
   2 Wed Oct 28 14:55:41 2009
   3 Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version
   4
   5
   6 ---------------------
   7 ; Table of Contents ;
   8 ---------------------
   9   1. Legal Notice
  10   2. Flow Summary
  11   3. Flow Settings
  12   4. Flow Non-Default Global Settings
  13   5. Flow Elapsed Time
  14   6. Flow OS Summary
  15   7. Flow Log
  16
  17
  18
  19 ----------------
  20 ; Legal Notice ;
  21 ----------------
  22 Copyright (C) 1991-2009 Altera Corporation
  23 Your use of Altera Corporation's design tools, logic functions
  24 and other software and tools, and its AMPP partner logic
  25 functions, and any output files from any of the foregoing
  26 (including device programming or simulation files), and any
  27 associated documentation or information are expressly subject
  28 to the terms and conditions of the Altera Program License
  29 Subscription Agreement, Altera MegaCore Function License
  30 Agreement, or other applicable license agreement, including,
  31 without limitation, that your use is for the sole purpose of
  32 programming logic devices manufactured by Altera and sold by
  33 Altera or its authorized distributors.  Please refer to the
  34 applicable agreement for further details.
  35
  36
  37
  38 +---------------------------------------------------------------------+
  39 ; Flow Summary                                                        ;
  40 +--------------------------+------------------------------------------+
  41 ; Flow Status              ; Successful - Wed Oct 28 14:55:41 2009    ;
  42 ; Quartus II Version       ; 9.0 Build 132 02/25/2009 SJ Full Version ;
  43 ; Revision Name            ; vga_pll                                  ;
  44 ; Top-level Entity Name    ; vga_pll                                  ;
  45 ; Family                   ; Stratix                                  ;
  46 ; Device                   ; EP1S25F672C6                             ;
  47 ; Timing Models            ; Final                                    ;
  48 ; Met timing requirements  ; Yes                                      ;
  49 ; Total logic elements     ; 173 / 25,660 ( < 1 % )                   ;
  50 ; Total pins               ; 117 / 474 ( 25 % )                       ;
  51 ; Total virtual pins       ; 0                                        ;
  52 ; Total memory bits        ; 0 / 1,944,576 ( 0 % )                    ;
  53 ; DSP block 9-bit elements ; 0 / 80 ( 0 % )                           ;
  54 ; Total PLLs               ; 1 / 6 ( 17 % )                           ;
  55 ; Total DLLs               ; 0 / 2 ( 0 % )                            ;
  56 +--------------------------+------------------------------------------+
  57
  58
  59 +-----------------------------------------+
  60 ; Flow Settings                           ;
  61 +-------------------+---------------------+
  62 ; Option            ; Setting             ;
  63 +-------------------+---------------------+
  64 ; Start date & time ; 10/28/2009 14:54:36 ;
  65 ; Main task         ; Compilation         ;
  66 ; Revision Name     ; vga_pll             ;
  67 +-------------------+---------------------+
  68
  69
  70 +-----------------------------------------------------------------------------------------------------------------------+
  71 ; Flow Non-Default Global Settings                                                                                      ;
  72 +------------------------------------+-----------------------------+---------------+-------------+----------------------+
  73 ; Assignment Name                    ; Value                       ; Default Value ; Entity Name ; Section Id           ;
  74 +------------------------------------+-----------------------------+---------------+-------------+----------------------+
  75 ; COMPILER_SIGNATURE_ID              ; 91815332912.125673807629382 ; --            ; --          ; --                   ;
  76 ; EDA_DESIGN_ENTRY_SYNTHESIS_TOOL    ; Synplify Pro                ; <None>        ; --          ; --                   ;
  77 ; EDA_INPUT_DATA_FORMAT              ; Vqm                         ; --            ; --          ; eda_design_synthesis ;
  78 ; EDA_LMF_FILE                       ; synplcty.lmf                ; --            ; --          ; eda_design_synthesis ;
  79 ; EDA_OUTPUT_DATA_FORMAT             ; Verilog                     ; --            ; --          ; eda_simulation       ;
  80 ; EDA_SIMULATION_TOOL                ; ModelSim-Altera (Verilog)   ; <None>        ; --          ; --                   ;
  81 ; EDA_TIME_SCALE                     ; 1 ps                        ; --            ; --          ; eda_simulation       ;
  82 ; MAX_CORE_JUNCTION_TEMP             ; 85                          ; --            ; --          ; --                   ;
  83 ; MIN_CORE_JUNCTION_TEMP             ; 0                           ; --            ; --          ; --                   ;
  84 ; PARTITION_COLOR                    ; 16764057                    ; --            ; --          ; Top                  ;
  85 ; PARTITION_NETLIST_TYPE             ; SOURCE                      ; --            ; --          ; Top                  ;
  86 ; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off                         ; --            ; --          ; eda_blast_fpga       ;
  87 +------------------------------------+-----------------------------+---------------+-------------+----------------------+
  88
  89
  90 +-----------------------------------------------------------------------------------------------------------------------------+
  91 ; Flow Elapsed Time                                                                                                           ;
  92 +-------------------------+--------------+-------------------------+---------------------+------------------------------------+
  93 ; Module Name             ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
  94 +-------------------------+--------------+-------------------------+---------------------+------------------------------------+
  95 ; Analysis & Synthesis    ; 00:00:07     ; 1.0                     ; --                  ; 00:00:03                           ;
  96 ; Fitter                  ; 00:00:29     ; 1.0                     ; --                  ; 00:00:29                           ;
  97 ; Assembler               ; 00:00:18     ; 1.0                     ; --                  ; 00:00:18                           ;
  98 ; Classic Timing Analyzer ; 00:00:00     ; 1.0                     ; --                  ; 00:00:00                           ;
  99 ; EDA Netlist Writer      ; 00:00:01     ; 1.0                     ; --                  ; 00:00:01                           ;
 100 ; Total                   ; 00:00:55     ; --                      ; --                  ; 00:00:51                           ;
 101 +-------------------------+--------------+-------------------------+---------------------+------------------------------------+
 102
 103
 104 +------------------------------------------------------------------------------------+
 105 ; Flow OS Summary                                                                    ;
 106 +-------------------------+------------------+---------+------------+----------------+
 107 ; Module Name             ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
 108 +-------------------------+------------------+---------+------------+----------------+
 109 ; Analysis & Synthesis    ; ti15             ; Red Hat ; 5          ; x86_64         ;
 110 ; Fitter                  ; ti15             ; Red Hat ; 5          ; x86_64         ;
 111 ; Assembler               ; ti15             ; Red Hat ; 5          ; x86_64         ;
 112 ; Classic Timing Analyzer ; ti15             ; Red Hat ; 5          ; x86_64         ;
 113 ; EDA Netlist Writer      ; ti15             ; Red Hat ; 5          ; x86_64         ;
 114 +-------------------------+------------------+---------+------------+----------------+
 115
 116
 117 ------------
 118 ; Flow Log ;
 119 ------------
 120 quartus_map --read_settings_files=on --write_settings_files=off vga_pll -c vga_pll
 121 quartus_fit --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll
 122 quartus_asm --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll
 123 quartus_tan --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll --timing_analysis_only
 124 quartus_eda --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll
 125
 126
 127