Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26
-rw-r--r-- 203 .gitignore
-rw-r--r-- 17987 COPYING
-rw-r--r-- 8915 Makefile
-rw-r--r-- 10328 Makefile.inc
-rw-r--r-- 2998 README
drwxr-xr-x - documentation
drwxr-xr-x - payloads
drwxr-xr-x - src
drwxr-xr-x - util