select HAVE_DEBUG_CAR
select SET_FIDVID
-config AMD_CIMX_SB800
- bool
- default y
-
config MAINBOARD_DIR
string
default advansus/a785e-i
#romstage-y += reset.c #FIXME romstage have include test_rest.c
-romstage-y += pmio.c
ramstage-y += reset.c
-ramstage-y += pmio.c
#SB800 CIMx share AGESA V5 lib code
ifneq ($(CONFIG_AMD_AGESA),y)
#include <arch/acpi.h>
#include <arch/io.h>
#include <device/device.h>
-#include "pmio.h"
-
-/*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
-/* pm_base should be got from bar2 of rs780. Here I compact ACPI
- * registers into 32 bytes limit.
- * */
-
-#define ACPI_PM_EVT_BLK (pm_base + 0x00) /* 4 bytes */
-#define ACPI_PM1_CNT_BLK (pm_base + 0x04) /* 2 bytes */
-#define ACPI_PMA_CNT_BLK (pm_base + 0x0F) /* 1 byte */
-#define ACPI_PM_TMR_BLK (pm_base + 0x18) /* 4 bytes */
-#define ACPI_GPE0_BLK (pm_base + 0x10) /* 8 bytes */
-#define ACPI_CPU_CONTORL (pm_base + 0x08) /* 6 bytes */
+#include "SBPLATFORM.h"
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{
+ u16 val;
acpi_header_t *header = &(fadt->header);
- pm_base &= 0xFFFF;
- printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
+ printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE);
/* Prepare the header */
memset((void *)fadt, 0, sizeof(acpi_fadt_t));
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = 0xe2;
- pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF);
- pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8);
- pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF);
- pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8);
- pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF);
- pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8);
- pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF);
- pm_iowrite(0x69, ACPI_GPE0_BLK >> 8);
+ val = PM1_EVT_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG60, AccWidthUint16, &val);
+ val = PM1_CNT_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG62, AccWidthUint16, &val);
+ val = PM1_TMR_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG64, AccWidthUint16, &val);
+ val = GPE0_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val);
/* CpuControl is in \_PR.CPU0, 6 bytes */
- pm_iowrite(0x66, ACPI_CPU_CONTORL & 0xFF);
- pm_iowrite(0x67, ACPI_CPU_CONTORL >> 8);
-
- pm_iowrite(0x6A, 0); /* AcpiSmiCmdLo */
- pm_iowrite(0x6B, 0); /* AcpiSmiCmdHi */
-
- pm_iowrite(0x6C, ACPI_PMA_CNT_BLK & 0xFF);
- pm_iowrite(0x6D, ACPI_PMA_CNT_BLK >> 8);
+ val = CPU_CNT_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val);
+ val = 0;
+ WritePMIO(SB_PMIOA_REG6A, AccWidthUint16, &val);
+ val = ACPI_PMA_CNT_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG6C, AccWidthUint16, &val);
+
+ /* AcpiDecodeEnable, When set, SB uses the contents of the
+ * PM registers at index 60-6B to decode ACPI I/O address.
+ * AcpiSmiEn & SmiCmdEn*/
+ val = BIT0 | BIT1 | BIT2 | BIT4;
+ WritePMIO(SB_PMIOA_REG74, AccWidthUint16, &val);
- pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses
- * the contents of the PM registers at
- * index 60-6B to decode ACPI I/O address.
- * AcpiSmiEn & SmiCmdEn*/
/* RTC_En_En, TMR_En_En, GBL_EN_EN */
- outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
+ outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */
- fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
+ fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS;
fadt->pm1b_evt_blk = 0x0000;
- fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
+ fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS;
fadt->pm1b_cnt_blk = 0x0000;
- fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
- fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
- fadt->gpe0_blk = ACPI_GPE0_BLK;
+ fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS;
+ fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS;
+ fadt->gpe0_blk = GPE0_BLK_ADDRESS;
fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */
fadt->pm1_evt_len = 4;
fadt->x_pm1a_evt_blk.bit_width = 32;
fadt->x_pm1a_evt_blk.bit_offset = 0;
fadt->x_pm1a_evt_blk.resv = 0;
- fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
+ fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS;
fadt->x_pm1a_evt_blk.addrh = 0x0;
fadt->x_pm1b_evt_blk.space_id = 1;
fadt->x_pm1a_cnt_blk.bit_width = 16;
fadt->x_pm1a_cnt_blk.bit_offset = 0;
fadt->x_pm1a_cnt_blk.resv = 0;
- fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
+ fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS;
fadt->x_pm1a_cnt_blk.addrh = 0x0;
fadt->x_pm1b_cnt_blk.space_id = 1;
fadt->x_pm2_cnt_blk.bit_width = 0;
fadt->x_pm2_cnt_blk.bit_offset = 0;
fadt->x_pm2_cnt_blk.resv = 0;
- fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
+ fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS;
fadt->x_pm2_cnt_blk.addrh = 0x0;
fadt->x_pm_tmr_blk.space_id = 1;
fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.resv = 0;
- fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
+ fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS;
fadt->x_pm_tmr_blk.addrh = 0x0;
fadt->x_gpe0_blk.space_id = 1;
fadt->x_gpe0_blk.bit_width = 32;
fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.resv = 0;
- fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
+ fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS;
fadt->x_gpe0_blk.addrh = 0x0;
fadt->x_gpe1_blk.space_id = 1;
#include <cpu/amd/multicore.h>
#endif
#include <cpu/amd/amdfam10_sysconf.h>
+#if CONFIG_AMD_SB_CIMX
+#include <sb_cimx.h>
+#endif
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
#endif
apicid_sb800 = apicid_base + 0;
+
+#if CONFIG_AMD_SB_CIMX
+ sb_Late_Post();
+#endif
}
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-//#include <southbridge/amd/sb800/sb800.h>
-#include "pmio.h"
+#include "SBPLATFORM.h"
#include "chip.h"
uint64_t uma_memory_base, uma_memory_size;
/* GPIO6. */
void enable_int_gfx(void)
{
- u8 byte;
-
volatile u8 *gpio_reg;
- pm_iowrite(0xEA, 0x01); /* diable the PCIB */
- /* Disable Gec */
- byte = pm_ioread(0xF6);
- byte |= 1;
- pm_iowrite(0xF6, byte);
- /* make sure the fed80000 is accessible */
- byte = pm_ioread(0x24);
- byte |= 1;
- pm_iowrite(0x24, byte);
+#ifdef UNUSED_CODE
+ RWPMIO(SB_PMIOA_REGEA, AccWidthUint8, ~(BIT0), BIT0); /* Disable the PCIB */
+ RWPMIO(SB_PMIOA_REGF6, AccWidthUint8, ~(BIT0), BIT0); /* Disable Gec */
+#endif
+ /* make sure the Acpi MMIO(fed80000) is accessible */
+ RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
- gpio_reg = (volatile u8 *)0xFED80000 + 0xD00; /* IoMux Register */
+ gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0xD00; /* IoMux Register */
*(gpio_reg + 0x6) = 0x1; /* Int_vga_en */
*(gpio_reg + 170) = 0x1; /* gpio_gate */
- gpio_reg = (volatile u8 *)0xFED80000 + 0x100; /* GPIO Registers */
+ gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0x100; /* GPIO Registers */
*(gpio_reg + 0x6) = 0x8;
*(gpio_reg + 170) = 0x0;
#include <arch/io.h>
#include <string.h>
#include <stdint.h>
-#include "pmio.h"
#include <cpu/amd/amdfam10_sysconf.h>
+#include <SBPLATFORM.h>
extern int bus_isa;
extern u8 bus_rs780[11];
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
-
- dword = 0;
- dword = pm_ioread(0x34) & 0xF0;
- dword |= (pm_ioread(0x35) & 0xFF) << 8;
- dword |= (pm_ioread(0x36) & 0xFF) << 16;
- dword |= (pm_ioread(0x37) & 0xFF) << 24;
+ ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
+ dword &= 0xFFFFFFF0;
smp_write_ioapic(mc, apicid_sb800, 0x11, dword);
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#ifndef _A785E_I_CFG_H_
+#define _A785E_I_CFG_H_
+
+/**
+ * @def BIOS_SIZE_1M
+ * @def BIOS_SIZE_2M
+ * @def BIOS_SIZE_4M
+ * @def BIOS_SIZE_8M
+ */
+#define BIOS_SIZE_1M 0
+#define BIOS_SIZE_2M 1
+#define BIOS_SIZE_4M 3
+#define BIOS_SIZE_8M 7
+
+/* In SB800, default ROM size is 1M Bytes, if your platform ROM
+ * bigger than 1M you have to set the ROM size outside CIMx module and
+ * before AGESA module get call.
+ */
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+ #define BIOS_SIZE BIOS_SIZE_1M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
+ #define BIOS_SIZE BIOS_SIZE_2M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
+ #define BIOS_SIZE BIOS_SIZE_4M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
+ #define BIOS_SIZE BIOS_SIZE_8M
+#endif
+
+/**
+ * @def SPREAD_SPECTRUM
+ * @brief
+ * 0 - Disable Spread Spectrum function
+ * 1 - Enable Spread Spectrum function
+ */
+#define SPREAD_SPECTRUM 0
+
+/**
+ * @def SB_HPET_TIMER
+ * @breif
+ * 0 - Disable hpet
+ * 1 - Enable hpet
+ */
+#define HPET_TIMER 1
+
+/**
+ * @def USB_CONFIG
+ * @brief bit[0-6] used to control USB
+ * 0 - Disable
+ * 1 - Enable
+ * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
+ * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
+ * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
+ * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
+ * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
+ * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
+ * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
+ */
+#define USB_CONFIG 0x7F
+
+/**
+ * @def PCI_CLOCK_CTRL
+ * @breif bit[0-4] used for PCI Slots Clock Control,
+ * 0 - disable
+ * 1 - enable
+ * PCI SLOT 0 define at BIT0
+ * PCI SLOT 1 define at BIT1
+ * PCI SLOT 2 define at BIT2
+ * PCI SLOT 3 define at BIT3
+ * PCI SLOT 4 define at BIT4
+ */
+#define PCI_CLOCK_CTRL 0x1F
+
+/**
+ * @def SATA_CONTROLLER
+ * @breif INCHIP Sata Controller
+ */
+#define SATA_CONTROLLER CIMX_OPTION_ENABLED
+
+/**
+ * @def SATA_MODE
+ * @breif INCHIP Sata Controller Mode
+ * NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#define SATA_MODE NATIVE_IDE_MODE
+
+/**
+ * @breif INCHIP Sata IDE Controller Mode
+ */
+#define IDE_LEGACY_MODE 0
+#define IDE_NATIVE_MODE 1
+
+/**
+ * @def SATA_IDE_MODE
+ * @breif INCHIP Sata IDE Controller Mode
+ * NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#define SATA_IDE_MODE IDE_LEGACY_MODE
+
+/**
+ * @def EXTERNAL_CLOCK
+ * @brief 00/10: Reference clock from crystal oscillator via
+ * PAD_XTALI and PAD_XTALO
+ *
+ * @def INTERNAL_CLOCK
+ * @brief 01/11: Reference clock from internal clock through
+ * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
+ */
+#define EXTERNAL_CLOCK 0x00
+#define INTERNAL_CLOCK 0x01
+
+/* NOTE: inagua have to using internal clock,
+ * otherwise can not detect sata drive
+ */
+#define SATA_CLOCK_SOURCE INTERNAL_CLOCK
+
+/**
+ * @def SATA_PORT_MULT_CAP_RESERVED
+ * @brief 1 ON, 0 0FF
+ */
+#define SATA_PORT_MULT_CAP_RESERVED 1
+
+
+/**
+ * @def AZALIA_AUTO
+ * @brief Detect Azalia controller automatically.
+ *
+ * @def AZALIA_DISABLE
+ * @brief Disable Azalia controller.
+
+ * @def AZALIA_ENABLE
+ * @brief Enable Azalia controller.
+ */
+#define AZALIA_AUTO 0
+#define AZALIA_DISABLE 1
+#define AZALIA_ENABLE 2
+
+/**
+ * @breif INCHIP HDA controller
+ */
+#define AZALIA_CONTROLLER AZALIA_AUTO
+
+/**
+ * @def AZALIA_PIN_CONFIG
+ * @brief
+ * 0 - disable
+ * 1 - enable
+ */
+#define AZALIA_PIN_CONFIG 1
+
+/**
+ * @def AZALIA_SDIN_PIN
+ * @brief
+ * SDIN0 is define at BIT0 & BIT1
+ * 00 - GPIO PIN
+ * 01 - Reserved
+ * 10 - As a Azalia SDIN pin
+ * SDIN1 is define at BIT2 & BIT3
+ * SDIN2 is define at BIT4 & BIT5
+ * SDIN3 is define at BIT6 & BIT7
+ */
+//#define AZALIA_SDIN_PIN 0xAA
+#define AZALIA_SDIN_PIN 0x2A
+
+/**
+ * @def GPP_CONTROLLER
+ */
+#define GPP_CONTROLLER CIMX_OPTION_ENABLED
+
+/**
+ * @def GPP_CFGMODE
+ * @brief GPP Link Configuration
+ * four possible configuration:
+ * GPP_CFGMODE_X4000
+ * GPP_CFGMODE_X2200
+ * GPP_CFGMODE_X2110
+ * GPP_CFGMODE_X1111
+ */
+#define GPP_CFGMODE GPP_CFGMODE_X1111
+
+/**
+ * @def NB_SB_GEN2
+ * 0 - Disable
+ * 1 - Enable
+ */
+#define NB_SB_GEN2 TRUE
+
+/**
+ * @def SB_GEN2
+ * 0 - Disable
+ * 1 - Enable
+ */
+#define SB_GPP_GEN2 TRUE
+
+
+/**
+ * @def GEC_CONFIG
+ * 0 - Enable
+ * 1 - Disable
+ */
+#define GEC_CONFIG 0
+
+#endif
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "pmio.h"
-
-static void pmio_write_index(u16 port_base, u8 reg, u8 value)
-{
- outb(reg, port_base);
- outb(value, port_base + 1);
-}
-
-static u8 pmio_read_index(u16 port_base, u8 reg)
-{
- outb(reg, port_base);
- return inb(port_base + 1);
-}
-
-void pm_iowrite(u8 reg, u8 value)
-{
- pmio_write_index(PM_INDEX, reg, value);
-}
-
-u8 pm_ioread(u8 reg)
-{
- return pmio_read_index(PM_INDEX, reg);
-}
-
-void pm2_iowrite(u8 reg, u8 value)
-{
- pmio_write_index(PM2_INDEX, reg, value);
-}
-
-u8 pm2_ioread(u8 reg)
-{
- return pmio_read_index(PM2_INDEX, reg);
-}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _PMIO_H_
-#define _PMIO_H_
-
-#define PM_INDEX 0xCD6
-#define PM_DATA 0xCD7
-#define PM2_INDEX 0xCD0
-#define PM2_DATA 0xCD1
-
-void pm_iowrite(u8 reg, u8 value);
-u8 pm_ioread(u8 reg);
-void pm2_iowrite(u8 reg, u8 value);
-u8 pm2_ioread(u8 reg);
-
-#endif
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
-#include <SbEarly.h>
+#include <sb_cimx.h>
#include <SBPLATFORM.h> /* SB OEM constants */
#include <southbridge/amd/cimx/sb800/smbus.h>
#include "northbridge/amd/amdfam10/debug.c"
outb(0x06, 0x0cf9);
}
-//FIXME copyed from sb800
-#include <pmio.h>
-static void sb800_clk_output_48Mhz(void)
-{
- /* AcpiMMioDecodeEn */
- u8 reg8;
- reg8 = pm_ioread(0x24);
- reg8 |= 1;
- reg8 &= ~(1 << 1);
- pm_iowrite(0x24, reg8);
-
- *(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
- *(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */
-}
-
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
enumerate_ht_chain();
//enable port80 decoding and southbridge poweron init
- sb_poweron_init();
+ sb_Poweron_Init();
}
post_code(0x30);
bool
default y
-config AMD_CIMX_SB800
- bool
- default y
-
config MAINBOARD_DIR
string
default amd/inagua
ramstage-y += PlatformGnbPcie.c
ramstage-y += reset.c
-ramstage-y += pmio.c
AGESA_ROOT ?= src/vendorcode/amd/agesa/f14
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += ../../../../$(AGESA_ROOT)
-#subdirs-$(CONFIG_AMD_CIMX) += ../../../vendorcode/amd/cimx
+#subdirs-$(CONFIG_AMD_SB_CIMX) += ../../../vendorcode/amd/cimx
#include <arch/acpi.h>
#include <arch/io.h>
#include <device/device.h>
-//#include "../../../southbridge/amd/sb800/sb800.h"
-
-/*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
-/* pm_base should be got from bar2 of sb800. Here I compact ACPI
- * registers into 32 bytes limit.
- * */
-
-#define ACPI_PM_EVT_BLK (pm_base + 0x00) /* 4 bytes */
-#define ACPI_PM1_CNT_BLK (pm_base + 0x04) /* 2 bytes */
-#define ACPI_PMA_CNT_BLK (pm_base + 0x0F) /* 1 byte */
-#define ACPI_PM_TMR_BLK (pm_base + 0x18) /* 4 bytes */
-#define ACPI_GPE0_BLK (pm_base + 0x10) /* 8 bytes */
-#define ACPI_CPU_CONTORL (pm_base + 0x08) /* 6 bytes */
+#include "SBPLATFORM.h"
+
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{
+ u16 val = 0;
acpi_header_t *header = &(fadt->header);
- pm_base &= 0xFFFF;
- printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
-
+ printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE);
/* Prepare the header */
memset((void *)fadt, 0, sizeof(acpi_fadt_t));
memcpy(header->signature, "FACP", 4);
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = 0xe2;
- pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF);
- pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8);
- pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF);
- pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8);
- pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF);
- pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8);
- pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF);
- pm_iowrite(0x69, ACPI_GPE0_BLK >> 8);
+ val = PM1_EVT_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG60, AccWidthUint16, &val);
+ val = PM1_CNT_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG62, AccWidthUint16, &val);
+ val = PM1_TMR_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG64, AccWidthUint16, &val);
+ val = GPE0_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val);
/* CpuControl is in \_PR.CPU0, 6 bytes */
- pm_iowrite(0x66, ACPI_CPU_CONTORL & 0xFF);
- pm_iowrite(0x67, ACPI_CPU_CONTORL >> 8);
-
- pm_iowrite(0x6A, 0); /* AcpiSmiCmdLo */
- pm_iowrite(0x6B, 0); /* AcpiSmiCmdHi */
-
- pm_iowrite(0x6C, ACPI_PMA_CNT_BLK & 0xFF);
- pm_iowrite(0x6D, ACPI_PMA_CNT_BLK >> 8);
+ val = CPU_CNT_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val);
+ val = 0;
+ WritePMIO(SB_PMIOA_REG6A, AccWidthUint16, &val);
+ val = ACPI_PMA_CNT_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG6C, AccWidthUint16, &val);
+
+ /* AcpiDecodeEnable, When set, SB uses the contents of the
+ * PM registers at index 60-6B to decode ACPI I/O address.
+ * AcpiSmiEn & SmiCmdEn*/
+ val = BIT0 | BIT1 | BIT2 | BIT4;
+ WritePMIO(SB_PMIOA_REG74, AccWidthUint16, &val);
- pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses
- * the contents of the PM registers at
- * index 60-6B to decode ACPI I/O address.
- * AcpiSmiEn & SmiCmdEn*/
/* RTC_En_En, TMR_En_En, GBL_EN_EN */
- outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
- fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
+ outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */
+ fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS;
fadt->pm1b_evt_blk = 0x0000;
- fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
+ fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS;
fadt->pm1b_cnt_blk = 0x0000;
- fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
- fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
- fadt->gpe0_blk = ACPI_GPE0_BLK;
+ fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS;
+ fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS;
+ fadt->gpe0_blk = GPE0_BLK_ADDRESS;
fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */
fadt->pm1_evt_len = 4;
fadt->x_pm1a_evt_blk.bit_width = 32;
fadt->x_pm1a_evt_blk.bit_offset = 0;
fadt->x_pm1a_evt_blk.resv = 0;
- fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
+ fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS;
fadt->x_pm1a_evt_blk.addrh = 0x0;
fadt->x_pm1b_evt_blk.space_id = 1;
fadt->x_pm1a_cnt_blk.bit_width = 16;
fadt->x_pm1a_cnt_blk.bit_offset = 0;
fadt->x_pm1a_cnt_blk.resv = 0;
- fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
+ fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS;
fadt->x_pm1a_cnt_blk.addrh = 0x0;
fadt->x_pm1b_cnt_blk.space_id = 1;
fadt->x_pm2_cnt_blk.bit_width = 0;
fadt->x_pm2_cnt_blk.bit_offset = 0;
fadt->x_pm2_cnt_blk.resv = 0;
- fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
+ fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS;
fadt->x_pm2_cnt_blk.addrh = 0x0;
fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.resv = 0;
- fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
+ fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS;
fadt->x_pm_tmr_blk.addrh = 0x0;
fadt->x_gpe0_blk.bit_width = 32;
fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.resv = 0;
- fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
+ fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS;
fadt->x_gpe0_blk.addrh = 0x0;
#include <stdint.h>
#include <stdlib.h>
#include <cpu/amd/amdfam14.h>
+#if CONFIG_AMD_SB_CIMX
+#include <sb_cimx.h>
+#endif
/* Global variables for MB layouts and these will be shared by irqtable mptable
/* I/O APICs: APIC ID Version State Address */
bus_isa = 10;
+
+#if CONFIG_AMD_SB_CIMX
+ sb_Late_Post();
+#endif
}
#include <stdint.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
+#include <SBPLATFORM.h>
#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1
extern u8 bus_sb800[2];
u32 dword;
u8 byte;
- dword = 0;
- dword = pm_ioread(0x34) & 0xF0;
- dword |= (pm_ioread(0x35) & 0xFF) << 8;
- dword |= (pm_ioread(0x36) & 0xFF) << 16;
- dword |= (pm_ioread(0x37) & 0xFF) << 24;
+ ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
+ dword &= 0xFFFFFFF0;
/* Set IO APIC ID onto IO_APIC_ID */
write32 (dword, 0x00);
write32 (dword + 0x10, IO_APIC_ID << 24);
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#ifndef _INAGUA_CFG_H_
+#define _INAGUA_CFG_H_
+
+/**
+ * @def BIOS_SIZE_1M
+ * @def BIOS_SIZE_2M
+ * @def BIOS_SIZE_4M
+ * @def BIOS_SIZE_8M
+ */
+#define BIOS_SIZE_1M 0
+#define BIOS_SIZE_2M 1
+#define BIOS_SIZE_4M 3
+#define BIOS_SIZE_8M 7
+
+/* In SB800, default ROM size is 1M Bytes, if your platform ROM
+ * bigger than 1M you have to set the ROM size outside CIMx module and
+ * before AGESA module get call.
+ */
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+ #define BIOS_SIZE BIOS_SIZE_1M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
+ #define BIOS_SIZE BIOS_SIZE_2M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
+ #define BIOS_SIZE BIOS_SIZE_4M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
+ #define BIOS_SIZE BIOS_SIZE_8M
+#endif
+
+/**
+ * @def SPREAD_SPECTRUM
+ * @brief
+ * 0 - Disable Spread Spectrum function
+ * 1 - Enable Spread Spectrum function
+ */
+#define SPREAD_SPECTRUM 0
+
+/**
+ * @def SB_HPET_TIMER
+ * @breif
+ * 0 - Disable hpet
+ * 1 - Enable hpet
+ */
+#define HPET_TIMER 1
+
+/**
+ * @def USB_CONFIG
+ * @brief bit[0-6] used to control USB
+ * 0 - Disable
+ * 1 - Enable
+ * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
+ * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
+ * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
+ * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
+ * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
+ * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
+ * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
+ */
+#define USB_CONFIG 0x7F
+
+/**
+ * @def PCI_CLOCK_CTRL
+ * @breif bit[0-4] used for PCI Slots Clock Control,
+ * 0 - disable
+ * 1 - enable
+ * PCI SLOT 0 define at BIT0
+ * PCI SLOT 1 define at BIT1
+ * PCI SLOT 2 define at BIT2
+ * PCI SLOT 3 define at BIT3
+ * PCI SLOT 4 define at BIT4
+ */
+#define PCI_CLOCK_CTRL 0x1F
+
+/**
+ * @def SATA_CONTROLLER
+ * @breif INCHIP Sata Controller
+ */
+#define SATA_CONTROLLER CIMX_OPTION_ENABLED
+
+/**
+ * @def SATA_MODE
+ * @breif INCHIP Sata Controller Mode
+ * NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#define SATA_MODE NATIVE_IDE_MODE
+
+/**
+ * @breif INCHIP Sata IDE Controller Mode
+ */
+#define IDE_LEGACY_MODE 0
+#define IDE_NATIVE_MODE 1
+
+/**
+ * @def SATA_IDE_MODE
+ * @breif INCHIP Sata IDE Controller Mode
+ * NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#define SATA_IDE_MODE IDE_LEGACY_MODE
+
+/**
+ * @def EXTERNAL_CLOCK
+ * @brief 00/10: Reference clock from crystal oscillator via
+ * PAD_XTALI and PAD_XTALO
+ *
+ * @def INTERNAL_CLOCK
+ * @brief 01/11: Reference clock from internal clock through
+ * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
+ */
+#define EXTERNAL_CLOCK 0x00
+#define INTERNAL_CLOCK 0x01
+
+/* NOTE: inagua have to using internal clock,
+ * otherwise can not detect sata drive
+ */
+#define SATA_CLOCK_SOURCE INTERNAL_CLOCK
+
+/**
+ * @def SATA_PORT_MULT_CAP_RESERVED
+ * @brief 1 ON, 0 0FF
+ */
+#define SATA_PORT_MULT_CAP_RESERVED 1
+
+
+/**
+ * @def AZALIA_AUTO
+ * @brief Detect Azalia controller automatically.
+ *
+ * @def AZALIA_DISABLE
+ * @brief Disable Azalia controller.
+
+ * @def AZALIA_ENABLE
+ * @brief Enable Azalia controller.
+ */
+#define AZALIA_AUTO 0
+#define AZALIA_DISABLE 1
+#define AZALIA_ENABLE 2
+
+/**
+ * @breif INCHIP HDA controller
+ */
+#define AZALIA_CONTROLLER AZALIA_AUTO
+
+/**
+ * @def AZALIA_PIN_CONFIG
+ * @brief
+ * 0 - disable
+ * 1 - enable
+ */
+#define AZALIA_PIN_CONFIG 1
+
+/**
+ * @def AZALIA_SDIN_PIN
+ * @brief
+ * SDIN0 is define at BIT0 & BIT1
+ * 00 - GPIO PIN
+ * 01 - Reserved
+ * 10 - As a Azalia SDIN pin
+ * SDIN1 is define at BIT2 & BIT3
+ * SDIN2 is define at BIT4 & BIT5
+ * SDIN3 is define at BIT6 & BIT7
+ */
+//#define AZALIA_SDIN_PIN 0xAA
+#define AZALIA_SDIN_PIN 0x2A
+
+/**
+ * @def GPP_CONTROLLER
+ */
+#define GPP_CONTROLLER CIMX_OPTION_ENABLED
+
+/**
+ * @def GPP_CFGMODE
+ * @brief GPP Link Configuration
+ * four possible configuration:
+ * GPP_CFGMODE_X4000
+ * GPP_CFGMODE_X2200
+ * GPP_CFGMODE_X2110
+ * GPP_CFGMODE_X1111
+ */
+#define GPP_CFGMODE GPP_CFGMODE_X1111
+
+/**
+ * @def NB_SB_GEN2
+ * 0 - Disable
+ * 1 - Enable
+ */
+#define NB_SB_GEN2 TRUE
+
+/**
+ * @def SB_GEN2
+ * 0 - Disable
+ * 1 - Enable
+ */
+#define SB_GPP_GEN2 TRUE
+
+
+/**
+ * @def GEC_CONFIG
+ * 0 - Enable
+ * 1 - Disable
+ */
+#define GEC_CONFIG 0
+
+#endif
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-#include <arch/io.h> /*inb, outb*/
-#include "pmio.h"
-
-static void pmio_write_index(u16 port_base, u8 reg, u8 value)
-{
- outb(reg, port_base);
- outb(value, port_base + 1);
-}
-
-static u8 pmio_read_index(u16 port_base, u8 reg)
-{
- outb(reg, port_base);
- return inb(port_base + 1);
-}
-
-void pm_iowrite(u8 reg, u8 value)
-{
- pmio_write_index(PM_INDEX, reg, value);
-}
-
-u8 pm_ioread(u8 reg)
-{
- return pmio_read_index(PM_INDEX, reg);
-}
-
-void pm2_iowrite(u8 reg, u8 value)
-{
- pmio_write_index(PM2_INDEX, reg, value);
-}
-
-u8 pm2_ioread(u8 reg)
-{
- return pmio_read_index(PM2_INDEX, reg);
-}
-
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-#ifndef _PMIO_H_
-#define _PMIO_H_
-
-#define PM_INDEX 0xCD6
-#define PM_DATA 0xCD7
-#define PM2_INDEX 0xCD0
-#define PM2_DATA 0xCD1
-
-void pm_iowrite(u8 reg, u8 value);
-u8 pm_ioread(u8 reg);
-void pm2_iowrite(u8 reg, u8 value);
-u8 pm2_ioread(u8 reg);
-
-#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "pc80/i8254.c"
#include "pc80/i8259.c"
-#include "SbEarly.h"
+#include "sb_cimx.h"
#include "SBPLATFORM.h"
#include <arch/cpu.h>
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
- sb_poweron_init();
+ sb_Poweron_Init();
post_code(0x31);
kbc1100_early_init(CONFIG_SIO_PORT);
bool
default y
-config AMD_CIMX_SB800
- bool
- default y
-
config MAINBOARD_DIR
string
default amd/persimmon
ramstage-y += PlatformGnbPcie.c
ramstage-y += reset.c
-ramstage-y += pmio.c
subdirs-$(CONFIG_AMD_AGESA) += ../../../vendorcode/amd/agesa/f14
#include <arch/acpi.h>
#include <arch/io.h>
#include <device/device.h>
-//#include "../../../southbridge/amd/sb800/sb800.h"
-
-/*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
-/* pm_base should be got from bar2 of sb800. Here I compact ACPI
- * registers into 32 bytes limit.
- * */
-
-#define ACPI_PM_EVT_BLK (pm_base + 0x00) /* 4 bytes */
-#define ACPI_PM1_CNT_BLK (pm_base + 0x04) /* 2 bytes */
-#define ACPI_PMA_CNT_BLK (pm_base + 0x0F) /* 1 byte */
-#define ACPI_PM_TMR_BLK (pm_base + 0x18) /* 4 bytes */
-#define ACPI_GPE0_BLK (pm_base + 0x10) /* 8 bytes */
-#define ACPI_CPU_CONTORL (pm_base + 0x08) /* 6 bytes */
+#include "SBPLATFORM.h"
+
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{
+ u16 val = 0;
acpi_header_t *header = &(fadt->header);
- pm_base &= 0xFFFF;
- printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
-
+ printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE);
/* Prepare the header */
memset((void *)fadt, 0, sizeof(acpi_fadt_t));
memcpy(header->signature, "FACP", 4);
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = 0xe2;
- pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF);
- pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8);
- pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF);
- pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8);
- pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF);
- pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8);
- pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF);
- pm_iowrite(0x69, ACPI_GPE0_BLK >> 8);
+ val = PM1_EVT_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG60, AccWidthUint16, &val);
+ val = PM1_CNT_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG62, AccWidthUint16, &val);
+ val = PM1_TMR_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG64, AccWidthUint16, &val);
+ val = GPE0_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val);
/* CpuControl is in \_PR.CPU0, 6 bytes */
- pm_iowrite(0x66, ACPI_CPU_CONTORL & 0xFF);
- pm_iowrite(0x67, ACPI_CPU_CONTORL >> 8);
-
- pm_iowrite(0x6A, 0); /* AcpiSmiCmdLo */
- pm_iowrite(0x6B, 0); /* AcpiSmiCmdHi */
-
- pm_iowrite(0x6C, ACPI_PMA_CNT_BLK & 0xFF);
- pm_iowrite(0x6D, ACPI_PMA_CNT_BLK >> 8);
+ val = CPU_CNT_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val);
+ val = 0;
+ WritePMIO(SB_PMIOA_REG6A, AccWidthUint16, &val);
+ val = ACPI_PMA_CNT_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG6C, AccWidthUint16, &val);
+
+ /* AcpiDecodeEnable, When set, SB uses the contents of the
+ * PM registers at index 60-6B to decode ACPI I/O address.
+ * AcpiSmiEn & SmiCmdEn*/
+ val = BIT0 | BIT1 | BIT2 | BIT4;
+ WritePMIO(SB_PMIOA_REG74, AccWidthUint16, &val);
- pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses
- * the contents of the PM registers at
- * index 60-6B to decode ACPI I/O address.
- * AcpiSmiEn & SmiCmdEn*/
/* RTC_En_En, TMR_En_En, GBL_EN_EN */
- outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
- fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
+ outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */
+ fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS;
fadt->pm1b_evt_blk = 0x0000;
- fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
+ fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS;
fadt->pm1b_cnt_blk = 0x0000;
- fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
- fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
- fadt->gpe0_blk = ACPI_GPE0_BLK;
+ fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS;
+ fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS;
+ fadt->gpe0_blk = GPE0_BLK_ADDRESS;
fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */
fadt->pm1_evt_len = 4;
fadt->x_pm1a_evt_blk.bit_width = 32;
fadt->x_pm1a_evt_blk.bit_offset = 0;
fadt->x_pm1a_evt_blk.resv = 0;
- fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
+ fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS;
fadt->x_pm1a_evt_blk.addrh = 0x0;
fadt->x_pm1b_evt_blk.space_id = 1;
fadt->x_pm1a_cnt_blk.bit_width = 16;
fadt->x_pm1a_cnt_blk.bit_offset = 0;
fadt->x_pm1a_cnt_blk.resv = 0;
- fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
+ fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS;
fadt->x_pm1a_cnt_blk.addrh = 0x0;
fadt->x_pm1b_cnt_blk.space_id = 1;
fadt->x_pm2_cnt_blk.bit_width = 0;
fadt->x_pm2_cnt_blk.bit_offset = 0;
fadt->x_pm2_cnt_blk.resv = 0;
- fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
+ fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS;
fadt->x_pm2_cnt_blk.addrh = 0x0;
fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.resv = 0;
- fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
+ fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS;
fadt->x_pm_tmr_blk.addrh = 0x0;
fadt->x_gpe0_blk.bit_width = 32;
fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.resv = 0;
- fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
+ fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS;
fadt->x_gpe0_blk.addrh = 0x0;
#include <stdint.h>
#include <stdlib.h>
#include <cpu/amd/amdfam14.h>
+#if CONFIG_AMD_SB_CIMX
+#include <sb_cimx.h>
+#endif
/* Global variables for MB layouts and these will be shared by irqtable mptable
bus_isa = 10;
apicid_base = CONFIG_MAX_CPUS;
apicid_sb800 = apicid_base;
+
+#if CONFIG_AMD_SB_CIMX
+ sb_Late_Post();
+#endif
}
#include <arch/io.h>
#include <string.h>
#include <stdint.h>
+#include <SBPLATFORM.h>
extern u8 bus_sb800[2];
u32 dword;
u8 byte;
- dword = 0;
- dword = pm_ioread(0x34) & 0xF0;
- dword |= (pm_ioread(0x35) & 0xFF) << 8;
- dword |= (pm_ioread(0x36) & 0xFF) << 16;
- dword |= (pm_ioread(0x37) & 0xFF) << 24;
+ ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
+ dword &= 0xFFFFFFF0;
smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#ifndef _PERSIMMON_CFG_H_
+#define _PERSIMMON_CFG_H_
+
+/**
+ * @def BIOS_SIZE_1M
+ * @def BIOS_SIZE_2M
+ * @def BIOS_SIZE_4M
+ * @def BIOS_SIZE_8M
+ */
+#define BIOS_SIZE_1M 0
+#define BIOS_SIZE_2M 1
+#define BIOS_SIZE_4M 3
+#define BIOS_SIZE_8M 7
+
+/* In SB800, default ROM size is 1M Bytes, if your platform ROM
+ * bigger than 1M you have to set the ROM size outside CIMx module and
+ * before AGESA module get call.
+ */
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+ #define BIOS_SIZE BIOS_SIZE_1M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
+ #define BIOS_SIZE BIOS_SIZE_2M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
+ #define BIOS_SIZE BIOS_SIZE_4M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
+ #define BIOS_SIZE BIOS_SIZE_8M
+#endif
+
+/**
+ * @def SPREAD_SPECTRUM
+ * @brief
+ * 0 - Disable Spread Spectrum function
+ * 1 - Enable Spread Spectrum function
+ */
+#define SPREAD_SPECTRUM 0
+
+/**
+ * @def SB_HPET_TIMER
+ * @breif
+ * 0 - Disable hpet
+ * 1 - Enable hpet
+ */
+#define HPET_TIMER 1
+
+/**
+ * @def USB_CONFIG
+ * @brief bit[0-6] used to control USB
+ * 0 - Disable
+ * 1 - Enable
+ * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
+ * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
+ * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
+ * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
+ * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
+ * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
+ * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
+ */
+#define USB_CONFIG 0x7F
+
+/**
+ * @def PCI_CLOCK_CTRL
+ * @breif bit[0-4] used for PCI Slots Clock Control,
+ * 0 - disable
+ * 1 - enable
+ * PCI SLOT 0 define at BIT0
+ * PCI SLOT 1 define at BIT1
+ * PCI SLOT 2 define at BIT2
+ * PCI SLOT 3 define at BIT3
+ * PCI SLOT 4 define at BIT4
+ */
+#define PCI_CLOCK_CTRL 0x1F
+
+/**
+ * @def SATA_CONTROLLER
+ * @breif INCHIP Sata Controller
+ */
+#define SATA_CONTROLLER CIMX_OPTION_ENABLED
+
+/**
+ * @def SATA_MODE
+ * @breif INCHIP Sata Controller Mode
+ * NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#define SATA_MODE NATIVE_IDE_MODE
+
+/**
+ * @breif INCHIP Sata IDE Controller Mode
+ */
+#define IDE_LEGACY_MODE 0
+#define IDE_NATIVE_MODE 1
+
+/**
+ * @def SATA_IDE_MODE
+ * @breif INCHIP Sata IDE Controller Mode
+ * NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#define SATA_IDE_MODE IDE_LEGACY_MODE
+
+/**
+ * @def EXTERNAL_CLOCK
+ * @brief 00/10: Reference clock from crystal oscillator via
+ * PAD_XTALI and PAD_XTALO
+ *
+ * @def INTERNAL_CLOCK
+ * @brief 01/11: Reference clock from internal clock through
+ * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
+ */
+#define EXTERNAL_CLOCK 0x00
+#define INTERNAL_CLOCK 0x01
+
+/* NOTE: inagua have to using internal clock,
+ * otherwise can not detect sata drive
+ */
+#define SATA_CLOCK_SOURCE INTERNAL_CLOCK
+
+/**
+ * @def SATA_PORT_MULT_CAP_RESERVED
+ * @brief 1 ON, 0 0FF
+ */
+#define SATA_PORT_MULT_CAP_RESERVED 1
+
+
+/**
+ * @def AZALIA_AUTO
+ * @brief Detect Azalia controller automatically.
+ *
+ * @def AZALIA_DISABLE
+ * @brief Disable Azalia controller.
+
+ * @def AZALIA_ENABLE
+ * @brief Enable Azalia controller.
+ */
+#define AZALIA_AUTO 0
+#define AZALIA_DISABLE 1
+#define AZALIA_ENABLE 2
+
+/**
+ * @breif INCHIP HDA controller
+ */
+#define AZALIA_CONTROLLER AZALIA_AUTO
+
+/**
+ * @def AZALIA_PIN_CONFIG
+ * @brief
+ * 0 - disable
+ * 1 - enable
+ */
+#define AZALIA_PIN_CONFIG 1
+
+/**
+ * @def AZALIA_SDIN_PIN
+ * @brief
+ * SDIN0 is define at BIT0 & BIT1
+ * 00 - GPIO PIN
+ * 01 - Reserved
+ * 10 - As a Azalia SDIN pin
+ * SDIN1 is define at BIT2 & BIT3
+ * SDIN2 is define at BIT4 & BIT5
+ * SDIN3 is define at BIT6 & BIT7
+ */
+//#define AZALIA_SDIN_PIN 0xAA
+#define AZALIA_SDIN_PIN 0x2A
+
+/**
+ * @def GPP_CONTROLLER
+ */
+#define GPP_CONTROLLER CIMX_OPTION_ENABLED
+
+/**
+ * @def GPP_CFGMODE
+ * @brief GPP Link Configuration
+ * four possible configuration:
+ * GPP_CFGMODE_X4000
+ * GPP_CFGMODE_X2200
+ * GPP_CFGMODE_X2110
+ * GPP_CFGMODE_X1111
+ */
+#define GPP_CFGMODE GPP_CFGMODE_X1111
+
+/**
+ * @def NB_SB_GEN2
+ * 0 - Disable
+ * 1 - Enable
+ */
+#define NB_SB_GEN2 TRUE
+
+/**
+ * @def SB_GEN2
+ * 0 - Disable
+ * 1 - Enable
+ */
+#define SB_GPP_GEN2 TRUE
+
+
+/**
+ * @def GEC_CONFIG
+ * 0 - Enable
+ * 1 - Disable
+ */
+#define GEC_CONFIG 0
+
+#endif
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-#include <arch/io.h> /*inb, outb*/
-#include "pmio.h"
-
-static void pmio_write_index(u16 port_base, u8 reg, u8 value)
-{
- outb(reg, port_base);
- outb(value, port_base + 1);
-}
-
-static u8 pmio_read_index(u16 port_base, u8 reg)
-{
- outb(reg, port_base);
- return inb(port_base + 1);
-}
-
-void pm_iowrite(u8 reg, u8 value)
-{
- pmio_write_index(PM_INDEX, reg, value);
-}
-
-u8 pm_ioread(u8 reg)
-{
- return pmio_read_index(PM_INDEX, reg);
-}
-
-void pm2_iowrite(u8 reg, u8 value)
-{
- pmio_write_index(PM2_INDEX, reg, value);
-}
-
-u8 pm2_ioread(u8 reg)
-{
- return pmio_read_index(PM2_INDEX, reg);
-}
-
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-#ifndef _PMIO_H_
-#define _PMIO_H_
-
-#define PM_INDEX 0xCD6
-#define PM_DATA 0xCD7
-#define PM2_INDEX 0xCD0
-#define PM2_DATA 0xCD1
-
-void pm_iowrite(u8 reg, u8 value);
-u8 pm_ioread(u8 reg);
-void pm2_iowrite(u8 reg, u8 value);
-u8 pm2_ioread(u8 reg);
-
-#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "pc80/i8254.c"
#include "pc80/i8259.c"
-#include "SbEarly.h"
+#include "sb_cimx.h"
#include "SBPLATFORM.h"
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
- sb_poweron_init();
+ sb_Poweron_Init();
post_code(0x31);
f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
UINT32 GpioMmioAddr;
UINT8 Data8;
UINT16 Data16;
- UINT8 TempData8;
FcnData = Data;
MemData = ConfigPtr;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
if (ResetInfo->ResetControl == DeassertSlotReset) {
- if (ResetInfo->ResetId & BIT2+BIT3) { //de-assert
+ if (ResetInfo->ResetId & (BIT2+BIT3)) { //de-assert
// [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG45);
if (Data8 & BIT7) {
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28);
while (!(Data8 & BIT7)) {
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28);
- }
+ }
// GPIO44: PE_GPIO0 MXM Reset
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44);
Data8 |= BIT6 ;
bool
default y
-config AMD_CIMX_SB900
- bool
- default y
-
config MAINBOARD_DIR
string
default amd/torpedo
romstage-y += dimmSpd.c
romstage-y += BiosCallOuts.c
romstage-y += PlatformGnbPcie.c
-romstage-y += cfg.c
romstage-y += gpio.c
ramstage-y += buildOpts.c
ramstage-y += dimmSpd.c
ramstage-y += BiosCallOuts.c
ramstage-y += PlatformGnbPcie.c
-ramstage-y += cfg.c
ramstage-y += reset.c
ramstage-y += pmio.c
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-#include <string.h>
-#include "SbPlatform.h"
-#include "cfg.h"
-#include <console/console.h> /* printk */
-
-
-/**
- * @brief South Bridge CIMx configuration
- *
- * should be called before exeucte CIMx function.
- * this function will be called in romstage and ramstage.
- */
-void sb900_cimx_config(AMDSBCFG *sb_config)
-{
- if (!sb_config) {
- printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - No sb_config.\n");
- return;
- }
- printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - Start.\n");
- memset(sb_config, 0, sizeof(AMDSBCFG));
-
- /* static Build Parameters */
- sb_config->BuildParameters.BiosSize = BIOS_SIZE;
- sb_config->BuildParameters.LegacyFree = LEGACY_FREE;
- sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS; // Board Level
- sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS; // Board Level
- sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS; // Board Level
- sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS; // Board Level
- sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS; // Board Level
- sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS; // Board Level
- sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS; // Board Level
- sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS; // Board Level
- sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; // Board Level
- sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS; // Board Level
-
- /* Turn on CDROM and HDD Power */
- sb_config->SATAMODE.SataMode.SataClkMode = SATA_CLK_RESERVED;
-
- // header
- sb_config->StdHeader.PcieBasePtr = PCIEX_BASE_ADDRESS;
-
- // Build Parameters
- sb_config->BuildParameters.ImcEnableOverWrite = IMC_ENABLE_OVER_WRITE; // Internal Option
- sb_config->BuildParameters.UsbMsi = USB_MSI; // Internal Option
- sb_config->BuildParameters.HdAudioMsi = HDAUDIO_MSI; // Internal Option
- sb_config->BuildParameters.LpcMsi = LPC_MSI; // Internal Option
- sb_config->BuildParameters.PcibMsi = PCIB_MSI; // Internal Option
- sb_config->BuildParameters.AbMsi = AB_MSI; // Internal Option
- sb_config->BuildParameters.GecShadowRomBase = GEC_SHADOWROM_BASE; // Board Level
- sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS; // Board Level
- sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID; // Board Level
- sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID; // Board Level
- sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID; // Board Level
- sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID; // Board Level
- sb_config->BuildParameters.OhciSsid = OHCI_SSID; // Board Level
- sb_config->BuildParameters.EhciSsid = EHCI_SSID; // Board Level
- sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID; // Board Level
- sb_config->BuildParameters.SmbusSsid = SMBUS_SSID; // Board Level
- sb_config->BuildParameters.IdeSsid = IDE_SSID; // Board Level
- sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID; // Board Level
- sb_config->BuildParameters.LpcSsid = LPC_SSID; // Board Level
- // sb_config->BuildParameters.PCIBSsid = PCIB_SSID; // Field Retired
-
- //
- // Common Function
- //
- sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER; // External Option
- sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = SATA_IDE_COMBMD_PRISEC_OPT; // External Option
- sb_config->SATAMODE.SataMode.SataIdeCombinedMode = SATA_IDECOMBINED_MODE; // External Option
- sb_config->S3Resume = 0; // CIMx Internal Used
- sb_config->SpreadSpectrum = INCHIP_SPREAD_SPECTRUM; // Board Level
- sb_config->NbSbGen2 = INCHIP_NB_SB_GEN2; // External Option
- sb_config->GppGen2 = INCHIP_GPP_GEN2; // External Option
- sb_config->GppMemWrImprove = INCHIP_GPP_MEMORY_WRITE_IMPROVE; // Internal Option
- sb_config->S4Resume = 0; // CIMx Internal Used
- sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; // INCHIP_SATA_MODE // External Option
- sb_config->SataIdeMode = INCHIP_IDE_MODE; // External Option
- sb_config->sdConfig = SB_SD_CONFIG; // External Option
- sb_config->sdSpeed = SB_SD_SPEED; // Internal Option
- sb_config->sdBitwidth = SB_SD_BITWIDTH; // Internal Option
- sb_config->SataDisUnusedIdePChannel = SATA_DISUNUSED_IDE_P_CHANNEL; // External Option
- sb_config->SataDisUnusedIdeSChannel = SATA_DISUNUSED_IDE_S_CHANNEL; // External Option
- sb_config->IdeDisUnusedIdePChannel = IDE_DISUNUSED_IDE_P_CHANNEL; // External Option
- sb_config->IdeDisUnusedIdeSChannel = IDE_DISUNUSED_IDE_S_CHANNEL; // External Option
- sb_config->SATAESPPORT.SataEspPort.PORT0 = SATA_ESP_PORT0; // Board Level
- sb_config->SATAESPPORT.SataEspPort.PORT1 = SATA_ESP_PORT1; // Board Level
- sb_config->SATAESPPORT.SataEspPort.PORT2 = SATA_ESP_PORT2; // Board Level
- sb_config->SATAESPPORT.SataEspPort.PORT3 = SATA_ESP_PORT3; // Board Level
- sb_config->SATAESPPORT.SataEspPort.PORT4 = SATA_ESP_PORT4; // Board Level
- sb_config->SATAESPPORT.SataEspPort.PORT5 = SATA_ESP_PORT5; // Board Level
- sb_config->SATAESPPORT.SataEspPort.PORT6 = SATA_ESP_PORT6; // Board Level
- sb_config->SATAESPPORT.SataEspPort.PORT7 = SATA_ESP_PORT7; // Board Level
- sb_config->SATAPORTPOWER.SataPortPower.PORT0 = SATA_PORT_POWER_PORT0; // Board Level
- sb_config->SATAPORTPOWER.SataPortPower.PORT1 = SATA_PORT_POWER_PORT1; // Board Level
- sb_config->SATAPORTPOWER.SataPortPower.PORT2 = SATA_PORT_POWER_PORT2; // Board Level
- sb_config->SATAPORTPOWER.SataPortPower.PORT3 = SATA_PORT_POWER_PORT3; // Board Level
- sb_config->SATAPORTPOWER.SataPortPower.PORT4 = SATA_PORT_POWER_PORT4; // Board Level
- sb_config->SATAPORTPOWER.SataPortPower.PORT5 = SATA_PORT_POWER_PORT5; // Board Level
- sb_config->SATAPORTPOWER.SataPortPower.PORT6 = SATA_PORT_POWER_PORT6; // Board Level
- sb_config->SATAPORTPOWER.SataPortPower.PORT7 = SATA_PORT_POWER_PORT7; // Board Level
- sb_config->SATAPORTMODE.SataPortMd.PORT0 = SATA_PORTMODE_PORT0; // Board Level
- sb_config->SATAPORTMODE.SataPortMd.PORT1 = SATA_PORTMODE_PORT1; // Board Level
- sb_config->SATAPORTMODE.SataPortMd.PORT2 = SATA_PORTMODE_PORT2; // Board Level
- sb_config->SATAPORTMODE.SataPortMd.PORT3 = SATA_PORTMODE_PORT3; // Board Level
- sb_config->SATAPORTMODE.SataPortMd.PORT4 = SATA_PORTMODE_PORT4; // Board Level
- sb_config->SATAPORTMODE.SataPortMd.PORT5 = SATA_PORTMODE_PORT5; // Board Level
- sb_config->SATAPORTMODE.SataPortMd.PORT6 = SATA_PORTMODE_PORT6; // Board Level
- sb_config->SATAPORTMODE.SataPortMd.PORT7 = SATA_PORTMODE_PORT7; // Board Level
- sb_config->SataAggrLinkPmCap = INCHIP_SATA_AGGR_LINK_PM_CAP; // Internal Option
- sb_config->SataPortMultCap = INCHIP_SATA_PORT_MULT_CAP; // Internal Option
- sb_config->SataClkAutoOff = INCHIP_SATA_CLK_AUTO_OFF; // External Option
- sb_config->SataPscCap = INCHIP_SATA_PSC_CAP; // External Option
- sb_config->SataFisBasedSwitching = INCHIP_SATA_FIS_BASE_SW; // External Option
- sb_config->SataCccSupport = INCHIP_SATA_CCC_SUPPORT; // External Option
- sb_config->SataSscCap = INCHIP_SATA_SSC_CAP; // External Option
- sb_config->SataMsiCapability = INCHIP_SATA_MSI_CAP; // Internal Option
- sb_config->SataForceRaid = INCHIP_SATA_FORCE_RAID5; // Internal Option
- sb_config->SataTargetSupport8Device = CIMXSB_SATA_TARGET_8DEVICE_CAP; // External Option
- sb_config->SataDisableGenericMode = SATA_DISABLE_GENERIC_MODE_CAP;// External Option
- sb_config->SataAhciEnclosureManagement = SATA_AHCI_ENCLOSURE_CAP; // Internal Option
- sb_config->SataSgpio0 = SATA_GPIO_0_CAP; // External Option
- sb_config->SataSgpio1 = SATA_GPIO_1_CAP; // External Option
- sb_config->SataPhyPllShutDown = SATA_PHY_PLL_SHUTDOWN; // External Option
- sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT0 = SATA_HOTREMOVEL_ENH_PORT0; // Board Level
- sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT1 = SATA_HOTREMOVEL_ENH_PORT1; // Board Level
- sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT2 = SATA_HOTREMOVEL_ENH_PORT2; // Board Level
- sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT3 = SATA_HOTREMOVEL_ENH_PORT3; // Board Level
- sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT4 = SATA_HOTREMOVEL_ENH_PORT4; // Board Level
- sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT5 = SATA_HOTREMOVEL_ENH_PORT5; // Board Level
- sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT6 = SATA_HOTREMOVEL_ENH_PORT6; // Board Level
- sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT7 = SATA_HOTREMOVEL_ENH_PORT7; // Board Level
- // USB
- sb_config->USBMODE.UsbMode.Ohci1 = INCHIP_USB_OHCI1_CINFIG; // External Option
- sb_config->USBMODE.UsbMode.Ehci1 = INCHIP_USB_EHCI1_CINFIG; // Internal Option*
- sb_config->USBMODE.UsbMode.Ohci2 = INCHIP_USB_OHCI2_CINFIG; // External Option
- sb_config->USBMODE.UsbMode.Ehci2 = INCHIP_USB_EHCI2_CINFIG; // Internal Option*
- sb_config->USBMODE.UsbMode.Ohci3 = INCHIP_USB_OHCI3_CINFIG; // External Option
- sb_config->USBMODE.UsbMode.Ehci3 = INCHIP_USB_EHCI3_CINFIG; // Internal Option*
- sb_config->USBMODE.UsbMode.Ohci4 = INCHIP_USB_OHCI4_CINFIG; // External Option
- // GEC
- sb_config->GecConfig = INCHIP_GEC_CONTROLLER; // External Option
- sb_config->IrConfig = SB_IR_CONTROLLER; // External Option
- sb_config->XhciSwitch = SB_XHCI_SWITCH; // External Option
- // Azalia
- sb_config->AzaliaController = INCHIP_AZALIA_CONTROLLER; // External Option
- sb_config->AzaliaPinCfg = INCHIP_AZALIA_PIN_CONFIG; // Board Level
- sb_config->FrontPanelDetected = INCHIP_FRONT_PANEL_DETECTED; // Board Level
- sb_config->AZALIACONFIG.AzaliaSdinPin = AZALIA_PIN_CONFIG; // Board Level
- sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr = NULL; // Board Level
- sb_config->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr = NULL; // Board Level
- sb_config->AnyHT200MhzLink = INCHIP_ANY_HT_200MHZ_LINK; // Internal Option
- sb_config->HpetTimer = SB_HPET_TIMER; // External Option
- sb_config->AzaliaSnoop = INCHIP_AZALIA_SNOOP; // Internal Option*
- // Generic
- sb_config->NativePcieSupport = INCHIP_NATIVE_PCIE_SUPPOORT; // External Option
- // USB
- sb_config->UsbPhyPowerDown = INCHIP_USB_PHY_POWER_DOWN; // External Option
- sb_config->PcibClkStopOverride = INCHIP_PCIB_CLK_STOP_OVERRIDE;// Internal Option
- // sb_config->HpetMsiDis = 0; // Field Retired
- // sb_config->ResetCpuOnSyncFlood = 0; // Field Retired
- // sb_config->PcibAutoClkCtr = 0; // Field Retired
- sb_config->OEMPROGTBL.OemProgrammingTablePtr = NULL; // Board Level
- sb_config->PORTCONFIG[0].PortCfg.PortPresent = SB_GPP_PORT0; // Board Level
- sb_config->PORTCONFIG[0].PortCfg.PortDetected = 0; // CIMx Internal Used
- sb_config->PORTCONFIG[0].PortCfg.PortIsGen2 = 0; // CIMx Internal Used
- sb_config->PORTCONFIG[0].PortCfg.PortHotPlug = 0; // CIMx Internal Used
- // sb_config->PORTCONFIG[0].PortCfg.PortIntxMap = 0; // Field Retired
- sb_config->PORTCONFIG[1].PortCfg.PortPresent = SB_GPP_PORT1; // Board Level
- sb_config->PORTCONFIG[1].PortCfg.PortDetected = 0; // CIMx Internal Used
- sb_config->PORTCONFIG[1].PortCfg.PortIsGen2 = 0; // CIMx Internal Used
- sb_config->PORTCONFIG[1].PortCfg.PortHotPlug = 0; // CIMx Internal Used
- // sb_config->PORTCONFIG[0].PortCfg.PortIntxMap = 0; // Field Retired
- sb_config->PORTCONFIG[2].PortCfg.PortPresent = SB_GPP_PORT2; // Board Level
- sb_config->PORTCONFIG[2].PortCfg.PortDetected = 0; // CIMx Internal Used
- sb_config->PORTCONFIG[2].PortCfg.PortIsGen2 = 0; // CIMx Internal Used
- sb_config->PORTCONFIG[2].PortCfg.PortHotPlug = 0; // CIMx Internal Used
- // sb_config->PORTCONFIG[0].PortCfg.PortIntxMap = 0; // Field Retired
- sb_config->PORTCONFIG[3].PortCfg.PortPresent = SB_GPP_PORT3; // Board Level
- sb_config->PORTCONFIG[3].PortCfg.PortDetected = 0; // CIMx Internal Used
- sb_config->PORTCONFIG[3].PortCfg.PortIsGen2 = 0; // CIMx Internal Used
- sb_config->PORTCONFIG[3].PortCfg.PortHotPlug = 0; // CIMx Internal Used
- // sb_config->PORTCONFIG[0].PortCfg.PortIntxMap = 0; // Field Retired
- sb_config->GppLinkConfig = INCHIP_GPP_LINK_CONFIG; // External Option
- sb_config->GppFoundGfxDev = 0; // CIMx Internal Used
- sb_config->GppFunctionEnable = SB_GPP_CONTROLLER; // External Option
- sb_config->GppUnhidePorts = INCHIP_GPP_UNHIDE_PORTS; // Internal Option
- sb_config->GppPortAspm = INCHIP_GPP_PORT_ASPM; // Internal Option
- sb_config->GppLaneReversal = INCHIP_GPP_LANEREVERSAL; // External Option
- sb_config->AlinkPhyPllPowerDown = INCHIP_ALINK_PHY_PLL_POWER_DOWN; // External Option
- sb_config->GppPhyPllPowerDown = INCHIP_GPP_PHY_PLL_POWER_DOWN;// External Option
- sb_config->GppDynamicPowerSaving = INCHIP_GPP_DYNAMIC_POWER_SAVING; // External Option
- sb_config->PcieAER = INCHIP_PCIE_AER; // External Option
- sb_config->PcieRAS = INCHIP_PCIE_RAS; // External Option
- sb_config->GppHardwareDowngrade = INCHIP_GPP_HARDWARE_DOWNGRADE;// Internal Option
- sb_config->GppToggleReset = INCHIP_GPP_TOGGLE_RESET; // External Option
- sb_config->sdbEnable = 0; // CIMx Internal Used
- sb_config->TempMMIO = NULL; // CIMx Internal Used
- // sb_config->GecPhyStatus = INCHIP_GEC_PHY_STATUS; // Field Retired
- sb_config->SBGecPwr = INCHIP_GEC_POWER_POLICY; // Internal Option
- sb_config->SBGecDebugBus = INCHIP_GEC_DEBUGBUS; // Internal Option
- sb_config->SbPcieOrderRule = INCHIP_SB_PCIE_ORDER_RULE; // External Option
- sb_config->AcDcMsg = INCHIP_ACDC_MSG; // Internal Option
- sb_config->TimerTickTrack = INCHIP_TIMER_TICK_TRACK; // Internal Option
- sb_config->ClockInterruptTag = INCHIP_CLOCK_INTERRUPT_TAG; // Internal Option
- sb_config->OhciTrafficHanding = INCHIP_OHCI_TRAFFIC_HANDING; // Internal Option
- sb_config->EhciTrafficHanding = INCHIP_EHCI_TRAFFIC_HANDING; // Internal Option
- sb_config->FusionMsgCMultiCore = INCHIP_FUSION_MSGC_MULTICORE; // Internal Option
- sb_config->FusionMsgCStage = INCHIP_FUSION_MSGC_STAGE; // Internal Option
- sb_config->ALinkClkGateOff = INCHIP_ALINK_CLK_GATE_OFF; // External Option
- sb_config->BLinkClkGateOff = INCHIP_BLINK_CLK_GATE_OFF; // External Option
- // sb_config->sdb = 0; // Field Retired
- sb_config->GppGen2Strap = 0; // CIMx Internal Used
- sb_config->SlowSpeedABlinkClock = INCHIP_SLOW_SPEED_ABLINK_CLOCK; // Internal Option
- sb_config->DYNAMICGECROM.DynamicGecRomAddress_Ptr = NULL; // Board Level
- sb_config->AbClockGating = INCHIP_AB_CLOCK_GATING; // External Option
- sb_config->GppClockGating = INCHIP_GPP_CLOCK_GATING; // External Option
- sb_config->L1TimerOverwrite = INCHIP_L1_TIMER_OVERWRITE; // Internal Option
- // sb_config->UmiLinkWidth = 0; // Field Retired
- sb_config->UmiDynamicSpeedChange = INCHIP_UMI_DYNAMIC_SPEED_CHANGE; // Internal Option
- // sb_config->PcieRefClockOverclocking = 0; // Field Retired
- sb_config->SbAlinkGppTxDriverStrength = INCHIP_ALINK_GPP_TX_DRV_STRENGTH; // Internal Option
- sb_config->PwrFailShadow = 0x02; // Board Level
- sb_config->StressResetMode = INCHIP_STRESS_RESET_MODE; // Internal Option
- sb_config->hwm.fanSampleFreqDiv = 0x03; // Board Level
- sb_config->hwm.hwmSbtsiAutoPoll = 1; // Board Level
-
- /* General */
- sb_config->PciClks = SB_PCI_CLOCK_RESERVED;
- sb_config->hwm.hwmEnable = 0x0;
-
-#ifndef __PRE_RAM__
- /* ramstage cimx config here */
- if (!sb_config->StdHeader.CALLBACK.CalloutPtr) {
- sb_config->StdHeader.CALLBACK.CalloutPtr = sb900_callout_entry;
- }
-
- //sb_config->
-#endif //!__PRE_RAM__
- printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - End.\n");
-}
-
-void SbPowerOnInit_Config(AMDSBCFG *sb_config)
-{
- if (!sb_config) {
- printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - No sb_config.\n");
- return;
- }
- printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - Start.\n");
- memset(sb_config, 0, sizeof(AMDSBCFG));
-
- // Set the build parameters
- sb_config->BuildParameters.BiosSize = BIOS_SIZE; // Field Retired
- sb_config->BuildParameters.LegacyFree = SBCIMx_LEGACY_FREE; // Board Level
- sb_config->BuildParameters.SpiSpeed = SBCIMX_SPI_SPEED; // Internal Option
- sb_config->BuildParameters.SpiFastSpeed = SBCIMX_SPI_FASTSPEED; // Internal Option
- // sb_config->BuildParameters.SpiWriteSpeed = 0; // Field Retired
- sb_config->BuildParameters.SpiMode = SBCIMX_SPI_MODE; // Internal Option
- sb_config->BuildParameters.SpiBurstWrite = SBCIMX_SPI_BURST_WRITE; // Internla Option
- sb_config->BuildParameters.EcKbd = INCHIP_EC_KBD; // Board Level
- sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; // Board Level
- sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS; // Board Level
- sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS; // Board Level
- sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS; // Board Level
- sb_config->BuildParameters.GecShadowRomBase = GEC_ROM_SHADOW_ADDRESS; // Board Level
- sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS; // Board Level
- sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS; // Board Level
- sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS; // Board Level
- sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS; // Board Level
- sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS; // Board Level
- sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS; // Board Level
- sb_config->BuildParameters.SmiCmdPortAddr = SMI_CMD_PORT; // Board Level
- sb_config->BuildParameters.AcpiPmaCntBlkAddr = ACPI_PMA_CNT_BLK_ADDRESS; // Board Level
- sb_config->SATAMODE.SataMode.SataController = INCHIP_SATA_CONTROLLER; // External Option
- sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = SATA_COMBINE_MODE_CHANNEL;// External Option
- sb_config->SATAMODE.SataMode.SataSetMaxGen2 = SATA_MAX_GEN2_MODE; // External Option
- sb_config->SATAMODE.SataMode.SataIdeCombinedMode= SATA_COMBINE_MODE; // External Option
- sb_config->SATAMODE.SataMode.SataClkMode = SATA_CLK_RESERVED; // Internal Option
- sb_config->NbSbGen2 = NB_SB_GEN2; // External Option
- sb_config->SataInternal100Spread = INCHIP_SATA_INTERNAL_100_SPREAD; // External Option
- sb_config->OEMPROGTBL.OemProgrammingTablePtr = NULL; // Board Level
- sb_config->sdbEnable = 0; // CIMx Internal Used
- sb_config->Cg2Pll = INCHIP_CG2_PLL; // Internal Option
-
- printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - End.\n");
-}
-
-
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-#ifndef _SB900_CFG_H_
-#define _SB900_CFG_H_
-
-#include <stdint.h>
-
-
-/**
- * @section BIOSSize BIOSSize
- * @li <b>0</b> - 1M
- * @li <b>1</b> - 2M
- * @li <b>3</b> - 4M
- * @li <b>7</b> - 8M
- * In Hudson-2, default ROM size is 1M Bytes, if your platform
- * ROM bigger then 1M you have to set the ROM size outside CIMx
- * module and before AGESA module get call.
- */
-#define BIOS_SIZE_1M 0
-#define BIOS_SIZE_2M 1
-#define BIOS_SIZE_4M 3
-#define BIOS_SIZE_8M 7
-
-#ifndef BIOS_SIZE
-#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
- #define BIOS_SIZE BIOS_SIZE_1M
-#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
- #define BIOS_SIZE BIOS_SIZE_2M
-#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
- #define BIOS_SIZE BIOS_SIZE_4M
-#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
- #define BIOS_SIZE BIOS_SIZE_8M
-#endif
-#endif
-
-/**
- * @section SBCIMx_LEGACY_FREE SBCIMx_LEGACY_FREE
- * @li <b>1</b> - Legacy free enable
- * @li <b>0</b> - Legacy free disable
- */
-#ifndef SBCIMx_LEGACY_FREE
- #define SBCIMx_LEGACY_FREE 0
-#endif
-
-/**
- * @section SpiSpeed
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#ifndef SBCIMX_SPI_SPEED
- #define SBCIMX_SPI_SPEED 0
-#endif
-
-/**
- * @section SpiFastSpeed
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#ifndef SBCIMX_SPI_FASTSPEED
- #define SBCIMX_SPI_FASTSPEED 0
-#endif
-
-/**
- * @section SpiMode
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#ifndef SBCIMX_SPI_MODE
- #define SBCIMX_SPI_MODE 0
-#endif
-
-/**
- * @section SpiBurstWrite
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#ifndef SBCIMX_SPI_BURST_WRITE
- #define SBCIMX_SPI_BURST_WRITE 0
-#endif
-
-/**
- * @section INCHIP_EC_KBD INCHIP_EC_KBD
- * @li <b>0</b> - Use SIO PS/2 function.
- * @li <b>1</b> - Use EC PS/2 function.
- */
-#ifndef INCHIP_EC_KBD
- #define INCHIP_EC_KBD 0
-#endif
-
-/**
- * @section INCHIP_EC_CHANNEL10 INCHIP_EC_CHANNEL10
- * @li <b>0</b> - EC controller NOT support Channel10
- * @li <b>1</b> - EC controller support Channel10.
- */
-#ifndef INCHIP_EC_CHANNEL10
- #define INCHIP_EC_CHANNEL10 1
-#endif
-
-/**
- * @section Smbus0BaseAddress
- */
-// #ifndef SMBUS0_BASE_ADDRESS
-// #define SMBUS0_BASE_ADDRESS 0xB00
-// #endif
-
-/**
- * @section Smbus1BaseAddress
- */
-// #ifndef SMBUS1_BASE_ADDRESS
-// #define SMBUS1_BASE_ADDRESS 0xB21
-// #endif
-
-/**
- * @section SioPmeBaseAddress
- */
-// #ifndef SIO_PME_BASE_ADDRESS
-// #define SIO_PME_BASE_ADDRESS 0xE00
-// #endif
-
-/**
- * @section WatchDogTimerBase
- */
-// #ifndef WATCHDOG_TIMER_BASE_ADDRESS
-// #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC00000
-// #endif
-
-/**
- * @section GecShadowRomBase
- */
-#ifndef GEC_ROM_SHADOW_ADDRESS
- #define GEC_ROM_SHADOW_ADDRESS 0xFED61000
-#endif
-
-/**
- * @section SpiRomBaseAddress
- */
-// #ifndef SPI_BASE_ADDRESS
-// #define SPI_BASE_ADDRESS 0xFEC10000
-// #endif
-
-/**
- * @section AcpiPm1EvtBlkAddr
- */
-// #ifndef PM1_EVT_BLK_ADDRESS
-// #define PM1_EVT_BLK_ADDRESS 0x400
-// #endif
-
-/**
- * @section AcpiPm1CntBlkAddr
- */
-// #ifndef PM1_CNT_BLK_ADDRESS
-// #define PM1_CNT_BLK_ADDRESS 0x404
-// #endif
-
-/**
- * @section AcpiPmTmrBlkAddr
- */
-// #ifndef PM1_TMR_BLK_ADDRESS
-// #define PM1_TMR_BLK_ADDRESS 0x408
-// #endif
-
-/**
- * @section CpuControlBlkAddr
- */
-// #ifndef CPU_CNT_BLK_ADDRESS
-// #define CPU_CNT_BLK_ADDRESS 0x410
-// #endif
-
-/**
- * @section AcpiGpe0BlkAddr
- */
-// #ifndef GPE0_BLK_ADDRESS
-// #define GPE0_BLK_ADDRESS 0x420
-// #endif
-
-/**
- * @section SmiCmdPortAddr
- */
-// #ifndef SMI_CMD_PORT
-// #define SMI_CMD_PORT 0xB0
-// #endif
-
-/**
- * @section AcpiPmaCntBlkAddr
- */
-// #ifndef ACPI_PMA_CNT_BLK_ADDRESS
-// #define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
-// #endif
-
-/**
- * @section SataController
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#ifndef INCHIP_SATA_CONTROLLER
- #define INCHIP_SATA_CONTROLLER 1
-#endif
-
-/**
- * @section SataIdeCombMdPriSecOpt
- * @li <b>0</b> - Primary
- * @li <b>1</b> - Secondary<TD></TD>
- * Sata Controller set as primary or
- * secondary while Combined Mode is enabled
- */
-#ifndef SATA_COMBINE_MODE_CHANNEL
- #define SATA_COMBINE_MODE_CHANNEL 0
-#endif
-
-/**
- * @section SataSetMaxGen2
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- * SataController Set to Max Gen2 mode
- */
-#ifndef SATA_MAX_GEN2_MODE
- #define SATA_MAX_GEN2_MODE 0
-#endif
-
-/**
- * @section SataIdeCombinedMode
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- * Sata IDE Controller set to Combined Mode
- */
-#ifndef SATA_COMBINE_MODE
- #define SATA_COMBINE_MODE 0
-#endif
-
-#define SATA_CLK_RESERVED 9
-
-/**
- * @section NbSbGen2
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#ifndef NB_SB_GEN2
- #define NB_SB_GEN2 1
-#endif
-
-/**
- * @section SataInternal100Spread
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#ifndef INCHIP_SATA_INTERNAL_100_SPREAD
- #define INCHIP_SATA_INTERNAL_100_SPREAD 0
-#endif
-
-/**
- * @section Cg2Pll
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#ifndef INCHIP_CG2_PLL
- #define INCHIP_CG2_PLL 0
-#endif
-
-
-
-
-/**
- * @section SpreadSpectrum
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- * Spread Spectrum function
- */
-#define INCHIP_SPREAD_SPECTRUM 1
-
-/**
- * @section INCHIP_USB_CINFIG INCHIP_USB_CINFIG
- *
- * - Usb Ohci1 Contoller is define at BIT0
- * 0:Disable 1:Enable
- * (Bus 0 Dev 18 Func0)
- * - Usb Ehci1 Contoller is define at BIT1
- * 0:Disable 1:Enable
- * (Bus 0 Dev 18 Func2)
- * - Usb Ohci2 Contoller is define at BIT2
- * 0:Disable 1:Enable
- * (Bus 0 Dev 19 Func0)
- * - Usb Ehci2 Contoller is define at BIT3
- * 0:Disable 1:Enable
- * (Bus 0 Dev 19 Func2)
- * - Usb Ohci3 Contoller is define at BIT4
- * 0:Disable 1:Enable
- * (Bus 0 Dev 22 Func0)
- * - Usb Ehci3 Contoller is define at BIT5
- * 0:Disable 1:Enable
- * (Bus 0 Dev 22 Func2)
- * - Usb Ohci4 Contoller is define at BIT6
- * 0:Disable 1:Enable
- * (Bus 0 Dev 20 Func5)
- */
-#define INCHIP_USB_CINFIG 0x7F
-#define INCHIP_USB_OHCI1_CINFIG 0x01
-#define INCHIP_USB_OHCI2_CINFIG 0x01
-#if CONFIG_ONBOARD_USB30 == 1
-#define INCHIP_USB_OHCI3_CINFIG 0x00
-#else
-#define INCHIP_USB_OHCI3_CINFIG 0x01
-#endif
-#define INCHIP_USB_OHCI4_CINFIG 0x01
-#define INCHIP_USB_EHCI1_CINFIG 0x01
-#define INCHIP_USB_EHCI2_CINFIG 0x01
-#define INCHIP_USB_EHCI3_CINFIG 0x01
-
-/**
- * @section INCHIP_SATA_MODE INCHIP_SATA_MODE
- * @li <b>000</b> - Native IDE mode
- * @li <b>001</b> - RAID mode
- * @li <b>010</b> - AHCI mode
- * @li <b>011</b> - Legacy IDE mode
- * @li <b>100</b> - IDE->AHCI mode
- * @li <b>101</b> - AHCI mode as 7804 ID (AMD driver)
- * @li <b>110</b> - IDE->AHCI mode as 7804 ID (AMD driver)
- */
-#define INCHIP_SATA_MODE 0
-
-/**
- * @section INCHIP_IDE_MODE INCHIP_IDE_MODE
- * @li <b>0</b> - Legacy IDE mode
- * @li <b>1</b> - Native IDE mode<TD></TD>
- * ** DO NOT ALLOW SATA & IDE use same mode **
- */
-#define INCHIP_IDE_MODE 1
-
-#define SATA_PORT_MULT_CAP_RESERVED 1
-
-/**
- * @section INCHIP_AZALIA_CONTROLLER INCHIP_AZALIA_CONTROLLER
- * @li <b>0</b> - Auto : Detect Azalia controller automatically.
- * @li <b>1</b> - Diable : Disable Azalia controller.
- * @li <b>2</b> - Enable : Enable Azalia controller.
- */
-#define INCHIP_AZALIA_CONTROLLER 2
-#define AZALIA_AUTO 0
-#define AZALIA_DISABLE 1
-#define AZALIA_ENABLE 2
-
-/**
- * @section INCHIP_AZALIA_PIN_CONFIG INCHIP_AZALIA_PIN_CONFIG
- * @li <b>0</b> - disable
- * @li <b>1</b> - enable
- */
-#define INCHIP_AZALIA_PIN_CONFIG 1
-
-/**
- * @section AZALIA_PIN_CONFIG AZALIA_PIN_CONFIG
- *
- * SDIN0 is define at BIT0 & BIT1
- * - 00: GPIO PIN
- * - 01: Reserved
- * - 10: As a Azalia SDIN pin<TD></TD>
- * SDIN1 is define at BIT2 & BIT3
- * - 00: GPIO PIN
- * - 01: Reserved
- * - 10: As a Azalia SDIN pin<TD></TD>
- * SDIN2 is define at BIT4 & BIT5
- * - 00: GPIO PIN
- * - 01: Reserved
- * - 10: As a Azalia SDIN pin<TD></TD>
- * SDIN3 is define at BIT6 & BIT7
- * - 00: GPIO PIN
- * - 01: Reserved
- * - 10: As a Azalia SDIN pin
- */
-#define AZALIA_PIN_CONFIG 0x2A
-
-/**
- * @section AzaliaSnoop
- * @li <b>0</b> - disable
- * @li <b>1</b> - enable *
- */
-#define INCHIP_AZALIA_SNOOP 0x01
-
-/**
- * @section NCHIP_GEC_CONTROLLER
- * @li <b>0</b> - Enable *
- * @li <b>1</b> - Disable
- */
-#define INCHIP_GEC_CONTROLLER 0x00
-
-/**
- * @section SB_HPET_TIMER SB_HPET_TIMER
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SB_HPET_TIMER 1
-
-/**
- * @section SB_GPP_CONTROLLER SB_GPP_CONTROLLER
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SB_GPP_CONTROLLER 1
-
-/**
- * @section GPP_LINK_CONFIG GPP_LINK_CONFIG
- * @li <b>0000</b> - Port ABCD -> 4:0:0:0
- * @li <b>0001</b> - N/A
- * @li <b>0010</b> - Port ABCD -> 2:2:0:0
- * @li <b>0011</b> - Port ABCD -> 2:1:1:0
- * @li <b>0100</b> - Port ABCD -> 1:1:1:1
- */
-#define GPP_LINK_CONFIG 4
-
-/**
- * @section SB_GPP_PORT0 SB_GPP_PORT0
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SB_GPP_PORT0 1
-
-/**
- * @section SB_GPP_PORT1 SB_GPP_PORT1
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SB_GPP_PORT1 1
-
-/**
- * @section SB_GPP_PORT2 SB_GPP_PORT2
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SB_GPP_PORT2 1
-
-/**
- * @section SB_GPP_PORT3 SB_GPP_PORT3
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SB_GPP_PORT3 1
-
-/**
- * @section SB_IR_CONTROLLER
- * @li <b>00 </b> - disable
- * @li <b>01 </b> - Rx and Tx0
- * @li <b>10 </b> - Rx and Tx1
- * @li <b>11 </b> - Rx and both Tx0,Tx1
- */
-#define SB_IR_CONTROLLER 3
-
-/**
- * @section INCHIP_USB_PHY_POWER_DOWN
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_USB_PHY_POWER_DOWN 0
-
-/**
- * @section INCHIP_NATIVE_PCIE_SUPPOORT
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_NATIVE_PCIE_SUPPOORT 1
-
-/**
- * @section INCHIP_NB_SB_GEN2
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_NB_SB_GEN2 1
-
-/**
- * @section INCHIP_GPP_GEN2
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_GPP_GEN2 1
-
-/**
- * @section INCHIP_GPP_MEMORY_WRITE_IMPROVE
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_GPP_MEMORY_WRITE_IMPROVE 1
-
-/**
- * @section INCHIP_GEC_PHY_STATUS
- * @li <b>0</b> - Gb PHY Mode *
- * @li <b>1</b> - 100/10 PHY Mode
- */
-#define INCHIP_GEC_PHY_STATUS 0
-
-/**
- * @section INCHIP_GEC_POWER_POLICY
- * @li <b>0</b> - S3/S5
- * @li <b>1</b> - S5
- * @li <b>2</b> - S3
- * @li <b>3</b> - Never power down *
- */
-#define INCHIP_GEC_POWER_POLICY 3
-
-/**
- * @section INCHIP_GEC_DEBUGBUS
- * @li <b>0</b> - Disable *
- * @li <b>1</b> - Enable
- */
-#define INCHIP_GEC_DEBUGBUS 0
-
-/**
- * @section SATA_MAX_GEN2_MODE SATA_MAX_GEN2_MODE
- * @li <b>0</b> - Disable *
- * @li <b>1</b> - Enable
- * SataController Set to Max Gen2 mode
- */
-#define SATA_MAX_GEN2_MODE 0
-
-/**
- * @section INCHIP_SATA_AGGR_LINK_PM_CAP
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable *
- * SataController Set to aggressive link PM capability
- */
-#define INCHIP_SATA_AGGR_LINK_PM_CAP 0
-
-/**
- * @section INCHIP_SATA_PORT_MULT_CAP
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable *
- * SataController Set to Port Multiple capability
- */
-#define INCHIP_SATA_PORT_MULT_CAP 1
-
-/**
- * @section INCHIP_SATA_PSC_CAP
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable *
-*/
-#define INCHIP_SATA_PSC_CAP 0
-
-/**
- * @section INCHIP_SATA_SSC_CAP
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable *
- */
-#define INCHIP_SATA_SSC_CAP 0
-
-/**
- * @section INCHIP_SATA_CLK_AUTO_OFF
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable *
- */
-#define INCHIP_SATA_CLK_AUTO_OFF 1
-
-/**
- * @section INCHIP_SATA_FIS_BASE_SW
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable *
- */
-#define INCHIP_SATA_FIS_BASE_SW 1
-
-/**
- * @section INCHIP_SATA_CCC_SUPPORT
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable *
- */
-#define INCHIP_SATA_CCC_SUPPORT 1
-
-/**
- * @section INCHIP_SATA_MSI_CAP
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable *
- */
-#define INCHIP_SATA_MSI_CAP 1
-
-/**
- * @section CIMXSB_SATA_TARGET_8DEVICE_CAP
- * @li <b>0</b> - Disable *
- * @li <b>1</b> - Enable
- */
-#define CIMXSB_SATA_TARGET_8DEVICE_CAP 0
-
-/**
- * @section SATA_DISABLE_GENERIC_MODE
- * @li <b>0</b> - Disable *
- * @li <b>1</b> - Enable
- */
-#define SATA_DISABLE_GENERIC_MODE_CAP 0
-
-/**
- * @section SATA_AHCI_ENCLOSURE_CAP
- * @li <b>0</b> - Disable *
- * @li <b>1</b> - Enable
- */
-#define SATA_AHCI_ENCLOSURE_CAP 0
-
-/**
- * @section SataForceRaid (RISD5 mode)
- * @li <b>0</b> - Disable *
- * @li <b>1</b> - Enable
- */
-#define INCHIP_SATA_FORCE_RAID5 0
-
-/**
- * @section SATA_GPIO_0_CAP
- * @li <b>0</b> - Disable *
- * @li <b>1</b> - Enable
- */
-#define SATA_GPIO_0_CAP 0
-
-/**
- * @section SATA_GPIO_1_CAP
- * @li <b>0</b> - Disable *
- * @li <b>1</b> - Enable
- */
-#define SATA_GPIO_1_CAP 0
-
-/**
- * @section SataPhyPllShutDown
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable *
- */
-#define SATA_PHY_PLL_SHUTDOWN 1
-
-/**
- * @section ImcEnableOverWrite
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define IMC_ENABLE_OVER_WRITE 0
-
-/**
- * @section UsbMsi
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define USB_MSI 0
-
-/**
- * @section HdAudioMsi
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define HDAUDIO_MSI 0
-
-/**
- * @section LpcMsi
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define LPC_MSI 0
-
-/**
- * @section PcibMsi
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define PCIB_MSI 0
-
-/**
- * @section AbMsi
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define AB_MSI 0
-
-/**
- * @section GecShadowRomBase
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable *
- */
-#define GEC_SHADOWROM_BASE 0xFED61000
-
-/**
- * @section SataController
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable *
- */
-#define SATA_CONTROLLER 1
-
-/**
- * @section SataIdeCombMdPriSecOpt
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_IDE_COMBMD_PRISEC_OPT 0
-
-/**
- * @section SataIdeCombinedMode
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_IDECOMBINED_MODE 0
-
-/**
- * @section sdConfig
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable *
- */
-#define SB_SD_CONFIG 1
-
-/**
- * @section sdSpeed
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable *
- */
-#define SB_SD_SPEED 1
-
-/**
- * @section sdBitwidth
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable *
- */
-#define SB_SD_BITWIDTH 1
-
-/**
- * @section SataDisUnusedIdePChannel
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_DISUNUSED_IDE_P_CHANNEL 0
-
-/**
- * @section SataDisUnusedIdeSChannel
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_DISUNUSED_IDE_S_CHANNEL 0
-
-/**
- * @section IdeDisUnusedIdePChannel
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define IDE_DISUNUSED_IDE_P_CHANNEL 0
-
-/**
- * @section IdeDisUnusedIdeSChannel
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define IDE_DISUNUSED_IDE_S_CHANNEL 0
-
-/**
- * @section IdeDisUnusedIdeSChannel
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-
-/**
- * @section SataEspPort0
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_ESP_PORT0 0
-
-/**
- * @section SataEspPort1
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_ESP_PORT1 0
-
-/**
- * @section SataEspPort2
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_ESP_PORT2 0
-
-/**
- * @section SataEspPort3
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_ESP_PORT3 0
-
-/**
- * @section SataEspPort4
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_ESP_PORT4 0
-
-/**
- * @section SataEspPort5
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_ESP_PORT5 0
-
-/**
- * @section SataEspPort6
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_ESP_PORT6 0
-
-/**
- * @section SataEspPort7
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_ESP_PORT7 0
-
-/**
- * @section SataPortPower0
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_PORT_POWER_PORT0 0
-
-/**
- * @section SataPortPower1
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_PORT_POWER_PORT1 0
-
-/**
- * @section SataPortPower2
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_PORT_POWER_PORT2 0
-
-/**
- * @section SataPortPower3
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_PORT_POWER_PORT3 0
-
-/**
- * @section SataPortPower4
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_PORT_POWER_PORT4 0
-
-/**
- * @section SataPortPower5
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_PORT_POWER_PORT5 0
-
-/**
- * @section SataPortPower6
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_PORT_POWER_PORT6 0
-
-/**
- * @section SataPortPower7
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_PORT_POWER_PORT7 0
-
-/**
- * @section SataPortMd0
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_PORTMODE_PORT0 3
-
-/**
- * @section SataPortMd1
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_PORTMODE_PORT1 3
-
-/**
- * @section SataPortMd2
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_PORTMODE_PORT2 3
-
-/**
- * @section SataPortMd3
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_PORTMODE_PORT3 3
-
-/**
- * @section SataPortMd4
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_PORTMODE_PORT4 0
-
-/**
- * @section SataPortMd5
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_PORTMODE_PORT5 0
-
-/**
- * @section SataPortMd6
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_PORTMODE_PORT6 0
-
-/**
- * @section SataPortMd7
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_PORTMODE_PORT7 0
-
-/**
- * @section SataHotRemovelEnh0
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_HOTREMOVEL_ENH_PORT0 0
-
-/**
- * @section SataHotRemovelEnh1
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_HOTREMOVEL_ENH_PORT1 0
-
-/**
- * @section SataHotRemovelEnh2
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_HOTREMOVEL_ENH_PORT2 0
-
-/**
- * @section SataHotRemovelEnh3
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_HOTREMOVEL_ENH_PORT3 0
-
-/**
- * @section SataHotRemovelEnh4
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_HOTREMOVEL_ENH_PORT4 0
-
-/**
- * @section SataHotRemovelEnh5
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_HOTREMOVEL_ENH_PORT5 0
-
-/**
- * @section SataHotRemovelEnh6
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_HOTREMOVEL_ENH_PORT6 0
-
-/**
- * @section SataHotRemovelEnh7
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define SATA_HOTREMOVEL_ENH_PORT7 0
-
-/**
- * @section XhciSwitch
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#if CONFIG_ONBOARD_USB30 == 1
- #define SB_XHCI_SWITCH 0
-#else
-#define SB_XHCI_SWITCH 1
-#endif
-
-/**
- * @section FrontPanelDetected
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_FRONT_PANEL_DETECTED 0
-
-/**
- * @section AnyHT200MhzLink
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_ANY_HT_200MHZ_LINK 0
-
-/**
- * @section PcibClkStopOverride
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_PCIB_CLK_STOP_OVERRIDE 0
-
-/**
- * @section GppLinkConfig
- * @li <b>0000</b> - Port ABCD -> 4:0:0:0
- * @li <b>0001</b> - N/A
- * @li <b>0010</b> - Port ABCD -> 2:2:0:0
- * @li <b>0011</b> - Port ABCD -> 2:1:1:0
- * @li <b>0100</b> - Port ABCD -> 1:1:1:1
- */
-#define INCHIP_GPP_LINK_CONFIG 4
-
-/**
- * @section GppUnhidePorts
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_GPP_UNHIDE_PORTS 0
-
-/**
- * @section GppPortAspm
- * @li <b>01</b> - Disabled
- * @li <b>01</b> - L0s
- * @li <b>10</b> - L1
- * @li <b>11</b> - L0s + L1
- */
-#define INCHIP_GPP_PORT_ASPM 3
-
-/**
- * @section GppLaneReversal
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_GPP_LANEREVERSAL 0
-
-/**
- * @section AlinkPhyPllPowerDown
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_ALINK_PHY_PLL_POWER_DOWN 1
-
-/**
- * @section GppPhyPllPowerDown
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_GPP_PHY_PLL_POWER_DOWN 1
-
-/**
- * @section GppDynamicPowerSaving
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_GPP_DYNAMIC_POWER_SAVING 1
-
-/**
- * @section PcieAER
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_PCIE_AER 0
-
-/**
- * @section PcieRAS
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_PCIE_RAS 0
-
-/**
- * @section GppHardwareDowngrade
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_GPP_HARDWARE_DOWNGRADE 0
-
-/**
- * @section GppToggleReset
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_GPP_TOGGLE_RESET 0
-
-/**
- * @section SbPcieOrderRule
- * @li <b>00</b> - Disable
- * @li <b>01</b> - Rule 1
- * @li <b>10</b> - Rule 2
- */
-#define INCHIP_SB_PCIE_ORDER_RULE 2
-
-/**
- * @section AcDcMsg
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_ACDC_MSG 0
-
-/**
- * @section TimerTickTrack
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_TIMER_TICK_TRACK 1
-
-/**
- * @section ClockInterruptTag
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_CLOCK_INTERRUPT_TAG 1
-
-/**
- * @section OhciTrafficHanding
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_OHCI_TRAFFIC_HANDING 0
-
-/**
- * @section EhciTrafficHanding
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_EHCI_TRAFFIC_HANDING 0
-
-/**
- * @section FusionMsgCMultiCore
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_FUSION_MSGC_MULTICORE 0
-
-/**
- * @section FusionMsgCStage
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_FUSION_MSGC_STAGE 0
-
-/**
- * @section ALinkClkGateOff
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_ALINK_CLK_GATE_OFF 0
-
-/**
- * @section BLinkClkGateOff
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_BLINK_CLK_GATE_OFF 0
-
-/**
- * @section SlowSpeedABlinkClock
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_SLOW_SPEED_ABLINK_CLOCK 0
-
-/**
- * @section AbClockGating
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_AB_CLOCK_GATING 1
-
-/**
- * @section GppClockGating
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_GPP_CLOCK_GATING 1
-
-/**
- * @section L1TimerOverwrite
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_L1_TIMER_OVERWRITE 0
-
-/**
- * @section UmiDynamicSpeedChange
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_UMI_DYNAMIC_SPEED_CHANGE 0
-
-/**
- * @section SbAlinkGppTxDriverStrength
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_ALINK_GPP_TX_DRV_STRENGTH 0
-
-/**
- * @section StressResetMode
- * @li <b>0</b> - Disable
- * @li <b>1</b> - Enable
- */
-#define INCHIP_STRESS_RESET_MODE 0
-
-#ifndef SB_PCI_CLOCK_RESERVED
- #define SB_PCI_CLOCK_RESERVED 0x0 //according to CIMx change 0x1F
-#endif
-
-/**
- * @brief South Bridge CIMx configuration
- *
- */
-void sb900_cimx_config(AMDSBCFG *sb_cfg);
-void SbPowerOnInit_Config(AMDSBCFG *sb_cfg);
-
-/**
- * @brief Entry point of Southbridge CIMx callout
- *
- * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)
- *
- * @param[in] func Southbridge CIMx Function ID.
- * @param[in] data Southbridge Input Data.
- * @param[in] sb_cfg Southbridge configuration structure pointer.
- *
- */
-u32 sb900_callout_entry(u32 func, u32 data, void* sb_cfg);
-
-#endif
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#ifndef _SB900_CFG_H_
+#define _SB900_CFG_H_
+
+#include <stdint.h>
+
+
+/**
+ * @section BIOSSize BIOSSize
+ * @li <b>0</b> - 1M
+ * @li <b>1</b> - 2M
+ * @li <b>3</b> - 4M
+ * @li <b>7</b> - 8M
+ * In Hudson-2, default ROM size is 1M Bytes, if your platform
+ * ROM bigger then 1M you have to set the ROM size outside CIMx
+ * module and before AGESA module get call.
+ */
+#define BIOS_SIZE_1M 0
+#define BIOS_SIZE_2M 1
+#define BIOS_SIZE_4M 3
+#define BIOS_SIZE_8M 7
+
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+ #define BIOS_SIZE BIOS_SIZE_1M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
+ #define BIOS_SIZE BIOS_SIZE_2M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
+ #define BIOS_SIZE BIOS_SIZE_4M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
+ #define BIOS_SIZE BIOS_SIZE_8M
+#endif
+
+/**
+ * @section SBCIMx_LEGACY_FREE SBCIMx_LEGACY_FREE
+ * @li <b>1</b> - Legacy free enable
+ * @li <b>0</b> - Legacy free disable
+ */
+#ifndef SBCIMx_LEGACY_FREE
+ #define SBCIMx_LEGACY_FREE 0
+#endif
+
+/**
+ * @section SpiSpeed
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#ifndef SBCIMX_SPI_SPEED
+ #define SBCIMX_SPI_SPEED 0
+#endif
+
+/**
+ * @section SpiFastSpeed
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#ifndef SBCIMX_SPI_FASTSPEED
+ #define SBCIMX_SPI_FASTSPEED 0
+#endif
+
+/**
+ * @section SpiMode
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#ifndef SBCIMX_SPI_MODE
+ #define SBCIMX_SPI_MODE 0
+#endif
+
+/**
+ * @section SpiBurstWrite
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#ifndef SBCIMX_SPI_BURST_WRITE
+ #define SBCIMX_SPI_BURST_WRITE 0
+#endif
+
+/**
+ * @section INCHIP_EC_KBD INCHIP_EC_KBD
+ * @li <b>0</b> - Use SIO PS/2 function.
+ * @li <b>1</b> - Use EC PS/2 function.
+ */
+#ifndef INCHIP_EC_KBD
+ #define INCHIP_EC_KBD 0
+#endif
+
+/**
+ * @section INCHIP_EC_CHANNEL10 INCHIP_EC_CHANNEL10
+ * @li <b>0</b> - EC controller NOT support Channel10
+ * @li <b>1</b> - EC controller support Channel10.
+ */
+#ifndef INCHIP_EC_CHANNEL10
+ #define INCHIP_EC_CHANNEL10 1
+#endif
+
+/**
+ * @section Smbus0BaseAddress
+ */
+// #ifndef SMBUS0_BASE_ADDRESS
+// #define SMBUS0_BASE_ADDRESS 0xB00
+// #endif
+
+/**
+ * @section Smbus1BaseAddress
+ */
+// #ifndef SMBUS1_BASE_ADDRESS
+// #define SMBUS1_BASE_ADDRESS 0xB21
+// #endif
+
+/**
+ * @section SioPmeBaseAddress
+ */
+// #ifndef SIO_PME_BASE_ADDRESS
+// #define SIO_PME_BASE_ADDRESS 0xE00
+// #endif
+
+/**
+ * @section WatchDogTimerBase
+ */
+// #ifndef WATCHDOG_TIMER_BASE_ADDRESS
+// #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC00000
+// #endif
+
+/**
+ * @section GecShadowRomBase
+ */
+#ifndef GEC_ROM_SHADOW_ADDRESS
+ #define GEC_ROM_SHADOW_ADDRESS 0xFED61000
+#endif
+
+/**
+ * @section SpiRomBaseAddress
+ */
+// #ifndef SPI_BASE_ADDRESS
+// #define SPI_BASE_ADDRESS 0xFEC10000
+// #endif
+
+/**
+ * @section AcpiPm1EvtBlkAddr
+ */
+// #ifndef PM1_EVT_BLK_ADDRESS
+// #define PM1_EVT_BLK_ADDRESS 0x400
+// #endif
+
+/**
+ * @section AcpiPm1CntBlkAddr
+ */
+// #ifndef PM1_CNT_BLK_ADDRESS
+// #define PM1_CNT_BLK_ADDRESS 0x404
+// #endif
+
+/**
+ * @section AcpiPmTmrBlkAddr
+ */
+// #ifndef PM1_TMR_BLK_ADDRESS
+// #define PM1_TMR_BLK_ADDRESS 0x408
+// #endif
+
+/**
+ * @section CpuControlBlkAddr
+ */
+// #ifndef CPU_CNT_BLK_ADDRESS
+// #define CPU_CNT_BLK_ADDRESS 0x410
+// #endif
+
+/**
+ * @section AcpiGpe0BlkAddr
+ */
+// #ifndef GPE0_BLK_ADDRESS
+// #define GPE0_BLK_ADDRESS 0x420
+// #endif
+
+/**
+ * @section SmiCmdPortAddr
+ */
+// #ifndef SMI_CMD_PORT
+// #define SMI_CMD_PORT 0xB0
+// #endif
+
+/**
+ * @section AcpiPmaCntBlkAddr
+ */
+// #ifndef ACPI_PMA_CNT_BLK_ADDRESS
+// #define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
+// #endif
+
+/**
+ * @section SataController
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#ifndef INCHIP_SATA_CONTROLLER
+ #define INCHIP_SATA_CONTROLLER 1
+#endif
+
+/**
+ * @section SataIdeCombMdPriSecOpt
+ * @li <b>0</b> - Primary
+ * @li <b>1</b> - Secondary<TD></TD>
+ * Sata Controller set as primary or
+ * secondary while Combined Mode is enabled
+ */
+#ifndef SATA_COMBINE_MODE_CHANNEL
+ #define SATA_COMBINE_MODE_CHANNEL 0
+#endif
+
+/**
+ * @section SataSetMaxGen2
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ * SataController Set to Max Gen2 mode
+ */
+#ifndef SATA_MAX_GEN2_MODE
+ #define SATA_MAX_GEN2_MODE 0
+#endif
+
+/**
+ * @section SataIdeCombinedMode
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ * Sata IDE Controller set to Combined Mode
+ */
+#ifndef SATA_COMBINE_MODE
+ #define SATA_COMBINE_MODE 0
+#endif
+
+#define SATA_CLK_RESERVED 9
+
+/**
+ * @section NbSbGen2
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#ifndef NB_SB_GEN2
+ #define NB_SB_GEN2 1
+#endif
+
+/**
+ * @section SataInternal100Spread
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#ifndef INCHIP_SATA_INTERNAL_100_SPREAD
+ #define INCHIP_SATA_INTERNAL_100_SPREAD 0
+#endif
+
+/**
+ * @section Cg2Pll
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#ifndef INCHIP_CG2_PLL
+ #define INCHIP_CG2_PLL 0
+#endif
+
+
+
+
+/**
+ * @section SpreadSpectrum
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ * Spread Spectrum function
+ */
+#define INCHIP_SPREAD_SPECTRUM 1
+
+/**
+ * @section INCHIP_USB_CINFIG INCHIP_USB_CINFIG
+ *
+ * - Usb Ohci1 Contoller is define at BIT0
+ * 0:Disable 1:Enable
+ * (Bus 0 Dev 18 Func0)
+ * - Usb Ehci1 Contoller is define at BIT1
+ * 0:Disable 1:Enable
+ * (Bus 0 Dev 18 Func2)
+ * - Usb Ohci2 Contoller is define at BIT2
+ * 0:Disable 1:Enable
+ * (Bus 0 Dev 19 Func0)
+ * - Usb Ehci2 Contoller is define at BIT3
+ * 0:Disable 1:Enable
+ * (Bus 0 Dev 19 Func2)
+ * - Usb Ohci3 Contoller is define at BIT4
+ * 0:Disable 1:Enable
+ * (Bus 0 Dev 22 Func0)
+ * - Usb Ehci3 Contoller is define at BIT5
+ * 0:Disable 1:Enable
+ * (Bus 0 Dev 22 Func2)
+ * - Usb Ohci4 Contoller is define at BIT6
+ * 0:Disable 1:Enable
+ * (Bus 0 Dev 20 Func5)
+ */
+#define INCHIP_USB_CINFIG 0x7F
+#define INCHIP_USB_OHCI1_CINFIG 0x01
+#define INCHIP_USB_OHCI2_CINFIG 0x01
+#if CONFIG_ONBOARD_USB30 == 1
+#define INCHIP_USB_OHCI3_CINFIG 0x00
+#else
+#define INCHIP_USB_OHCI3_CINFIG 0x01
+#endif
+#define INCHIP_USB_OHCI4_CINFIG 0x01
+#define INCHIP_USB_EHCI1_CINFIG 0x01
+#define INCHIP_USB_EHCI2_CINFIG 0x01
+#define INCHIP_USB_EHCI3_CINFIG 0x01
+
+/**
+ * @section INCHIP_SATA_MODE INCHIP_SATA_MODE
+ * @li <b>000</b> - Native IDE mode
+ * @li <b>001</b> - RAID mode
+ * @li <b>010</b> - AHCI mode
+ * @li <b>011</b> - Legacy IDE mode
+ * @li <b>100</b> - IDE->AHCI mode
+ * @li <b>101</b> - AHCI mode as 7804 ID (AMD driver)
+ * @li <b>110</b> - IDE->AHCI mode as 7804 ID (AMD driver)
+ */
+#define INCHIP_SATA_MODE 0
+
+/**
+ * @section INCHIP_IDE_MODE INCHIP_IDE_MODE
+ * @li <b>0</b> - Legacy IDE mode
+ * @li <b>1</b> - Native IDE mode<TD></TD>
+ * ** DO NOT ALLOW SATA & IDE use same mode **
+ */
+#define INCHIP_IDE_MODE 1
+
+#define SATA_PORT_MULT_CAP_RESERVED 1
+
+/**
+ * @section INCHIP_AZALIA_CONTROLLER INCHIP_AZALIA_CONTROLLER
+ * @li <b>0</b> - Auto : Detect Azalia controller automatically.
+ * @li <b>1</b> - Diable : Disable Azalia controller.
+ * @li <b>2</b> - Enable : Enable Azalia controller.
+ */
+#define INCHIP_AZALIA_CONTROLLER 2
+#define AZALIA_AUTO 0
+#define AZALIA_DISABLE 1
+#define AZALIA_ENABLE 2
+
+/**
+ * @section INCHIP_AZALIA_PIN_CONFIG INCHIP_AZALIA_PIN_CONFIG
+ * @li <b>0</b> - disable
+ * @li <b>1</b> - enable
+ */
+#define INCHIP_AZALIA_PIN_CONFIG 1
+
+/**
+ * @section AZALIA_PIN_CONFIG AZALIA_PIN_CONFIG
+ *
+ * SDIN0 is define at BIT0 & BIT1
+ * - 00: GPIO PIN
+ * - 01: Reserved
+ * - 10: As a Azalia SDIN pin<TD></TD>
+ * SDIN1 is define at BIT2 & BIT3
+ * - 00: GPIO PIN
+ * - 01: Reserved
+ * - 10: As a Azalia SDIN pin<TD></TD>
+ * SDIN2 is define at BIT4 & BIT5
+ * - 00: GPIO PIN
+ * - 01: Reserved
+ * - 10: As a Azalia SDIN pin<TD></TD>
+ * SDIN3 is define at BIT6 & BIT7
+ * - 00: GPIO PIN
+ * - 01: Reserved
+ * - 10: As a Azalia SDIN pin
+ */
+#define AZALIA_PIN_CONFIG 0x2A
+
+/**
+ * @section AzaliaSnoop
+ * @li <b>0</b> - disable
+ * @li <b>1</b> - enable *
+ */
+#define INCHIP_AZALIA_SNOOP 0x01
+
+/**
+ * @section NCHIP_GEC_CONTROLLER
+ * @li <b>0</b> - Enable *
+ * @li <b>1</b> - Disable
+ */
+#define INCHIP_GEC_CONTROLLER 0x00
+
+/**
+ * @section SB_HPET_TIMER SB_HPET_TIMER
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SB_HPET_TIMER 1
+
+/**
+ * @section SB_GPP_CONTROLLER SB_GPP_CONTROLLER
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SB_GPP_CONTROLLER 1
+
+/**
+ * @section GPP_LINK_CONFIG GPP_LINK_CONFIG
+ * @li <b>0000</b> - Port ABCD -> 4:0:0:0
+ * @li <b>0001</b> - N/A
+ * @li <b>0010</b> - Port ABCD -> 2:2:0:0
+ * @li <b>0011</b> - Port ABCD -> 2:1:1:0
+ * @li <b>0100</b> - Port ABCD -> 1:1:1:1
+ */
+#define GPP_LINK_CONFIG 4
+
+/**
+ * @section SB_GPP_PORT0 SB_GPP_PORT0
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SB_GPP_PORT0 1
+
+/**
+ * @section SB_GPP_PORT1 SB_GPP_PORT1
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SB_GPP_PORT1 1
+
+/**
+ * @section SB_GPP_PORT2 SB_GPP_PORT2
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SB_GPP_PORT2 1
+
+/**
+ * @section SB_GPP_PORT3 SB_GPP_PORT3
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SB_GPP_PORT3 1
+
+/**
+ * @section SB_IR_CONTROLLER
+ * @li <b>00 </b> - disable
+ * @li <b>01 </b> - Rx and Tx0
+ * @li <b>10 </b> - Rx and Tx1
+ * @li <b>11 </b> - Rx and both Tx0,Tx1
+ */
+#define SB_IR_CONTROLLER 3
+
+/**
+ * @section INCHIP_USB_PHY_POWER_DOWN
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_USB_PHY_POWER_DOWN 0
+
+/**
+ * @section INCHIP_NATIVE_PCIE_SUPPOORT
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_NATIVE_PCIE_SUPPOORT 1
+
+/**
+ * @section INCHIP_NB_SB_GEN2
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_NB_SB_GEN2 1
+
+/**
+ * @section INCHIP_GPP_GEN2
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_GPP_GEN2 1
+
+/**
+ * @section INCHIP_GPP_MEMORY_WRITE_IMPROVE
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_GPP_MEMORY_WRITE_IMPROVE 1
+
+/**
+ * @section INCHIP_GEC_PHY_STATUS
+ * @li <b>0</b> - Gb PHY Mode *
+ * @li <b>1</b> - 100/10 PHY Mode
+ */
+#define INCHIP_GEC_PHY_STATUS 0
+
+/**
+ * @section INCHIP_GEC_POWER_POLICY
+ * @li <b>0</b> - S3/S5
+ * @li <b>1</b> - S5
+ * @li <b>2</b> - S3
+ * @li <b>3</b> - Never power down *
+ */
+#define INCHIP_GEC_POWER_POLICY 3
+
+/**
+ * @section INCHIP_GEC_DEBUGBUS
+ * @li <b>0</b> - Disable *
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_GEC_DEBUGBUS 0
+
+/**
+ * @section SATA_MAX_GEN2_MODE SATA_MAX_GEN2_MODE
+ * @li <b>0</b> - Disable *
+ * @li <b>1</b> - Enable
+ * SataController Set to Max Gen2 mode
+ */
+#define SATA_MAX_GEN2_MODE 0
+
+/**
+ * @section INCHIP_SATA_AGGR_LINK_PM_CAP
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable *
+ * SataController Set to aggressive link PM capability
+ */
+#define INCHIP_SATA_AGGR_LINK_PM_CAP 0
+
+/**
+ * @section INCHIP_SATA_PORT_MULT_CAP
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable *
+ * SataController Set to Port Multiple capability
+ */
+#define INCHIP_SATA_PORT_MULT_CAP 1
+
+/**
+ * @section INCHIP_SATA_PSC_CAP
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable *
+*/
+#define INCHIP_SATA_PSC_CAP 0
+
+/**
+ * @section INCHIP_SATA_SSC_CAP
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable *
+ */
+#define INCHIP_SATA_SSC_CAP 0
+
+/**
+ * @section INCHIP_SATA_CLK_AUTO_OFF
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable *
+ */
+#define INCHIP_SATA_CLK_AUTO_OFF 1
+
+/**
+ * @section INCHIP_SATA_FIS_BASE_SW
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable *
+ */
+#define INCHIP_SATA_FIS_BASE_SW 1
+
+/**
+ * @section INCHIP_SATA_CCC_SUPPORT
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable *
+ */
+#define INCHIP_SATA_CCC_SUPPORT 1
+
+/**
+ * @section INCHIP_SATA_MSI_CAP
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable *
+ */
+#define INCHIP_SATA_MSI_CAP 1
+
+/**
+ * @section CIMXSB_SATA_TARGET_8DEVICE_CAP
+ * @li <b>0</b> - Disable *
+ * @li <b>1</b> - Enable
+ */
+#define CIMXSB_SATA_TARGET_8DEVICE_CAP 0
+
+/**
+ * @section SATA_DISABLE_GENERIC_MODE
+ * @li <b>0</b> - Disable *
+ * @li <b>1</b> - Enable
+ */
+#define SATA_DISABLE_GENERIC_MODE_CAP 0
+
+/**
+ * @section SATA_AHCI_ENCLOSURE_CAP
+ * @li <b>0</b> - Disable *
+ * @li <b>1</b> - Enable
+ */
+#define SATA_AHCI_ENCLOSURE_CAP 0
+
+/**
+ * @section SataForceRaid (RISD5 mode)
+ * @li <b>0</b> - Disable *
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_SATA_FORCE_RAID5 0
+
+/**
+ * @section SATA_GPIO_0_CAP
+ * @li <b>0</b> - Disable *
+ * @li <b>1</b> - Enable
+ */
+#define SATA_GPIO_0_CAP 0
+
+/**
+ * @section SATA_GPIO_1_CAP
+ * @li <b>0</b> - Disable *
+ * @li <b>1</b> - Enable
+ */
+#define SATA_GPIO_1_CAP 0
+
+/**
+ * @section SataPhyPllShutDown
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable *
+ */
+#define SATA_PHY_PLL_SHUTDOWN 1
+
+/**
+ * @section ImcEnableOverWrite
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define IMC_ENABLE_OVER_WRITE 0
+
+/**
+ * @section UsbMsi
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define USB_MSI 0
+
+/**
+ * @section HdAudioMsi
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define HDAUDIO_MSI 0
+
+/**
+ * @section LpcMsi
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define LPC_MSI 0
+
+/**
+ * @section PcibMsi
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define PCIB_MSI 0
+
+/**
+ * @section AbMsi
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define AB_MSI 0
+
+/**
+ * @section GecShadowRomBase
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable *
+ */
+#define GEC_SHADOWROM_BASE 0xFED61000
+
+/**
+ * @section SataController
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable *
+ */
+#define SATA_CONTROLLER 1
+
+/**
+ * @section SataIdeCombMdPriSecOpt
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_IDE_COMBMD_PRISEC_OPT 0
+
+/**
+ * @section SataIdeCombinedMode
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_IDECOMBINED_MODE 0
+
+/**
+ * @section sdConfig
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable *
+ */
+#define SB_SD_CONFIG 1
+
+/**
+ * @section sdSpeed
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable *
+ */
+#define SB_SD_SPEED 1
+
+/**
+ * @section sdBitwidth
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable *
+ */
+#define SB_SD_BITWIDTH 1
+
+/**
+ * @section SataDisUnusedIdePChannel
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_DISUNUSED_IDE_P_CHANNEL 0
+
+/**
+ * @section SataDisUnusedIdeSChannel
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_DISUNUSED_IDE_S_CHANNEL 0
+
+/**
+ * @section IdeDisUnusedIdePChannel
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define IDE_DISUNUSED_IDE_P_CHANNEL 0
+
+/**
+ * @section IdeDisUnusedIdeSChannel
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define IDE_DISUNUSED_IDE_S_CHANNEL 0
+
+/**
+ * @section IdeDisUnusedIdeSChannel
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+
+/**
+ * @section SataEspPort0
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_ESP_PORT0 0
+
+/**
+ * @section SataEspPort1
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_ESP_PORT1 0
+
+/**
+ * @section SataEspPort2
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_ESP_PORT2 0
+
+/**
+ * @section SataEspPort3
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_ESP_PORT3 0
+
+/**
+ * @section SataEspPort4
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_ESP_PORT4 0
+
+/**
+ * @section SataEspPort5
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_ESP_PORT5 0
+
+/**
+ * @section SataEspPort6
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_ESP_PORT6 0
+
+/**
+ * @section SataEspPort7
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_ESP_PORT7 0
+
+/**
+ * @section SataPortPower0
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_PORT_POWER_PORT0 0
+
+/**
+ * @section SataPortPower1
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_PORT_POWER_PORT1 0
+
+/**
+ * @section SataPortPower2
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_PORT_POWER_PORT2 0
+
+/**
+ * @section SataPortPower3
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_PORT_POWER_PORT3 0
+
+/**
+ * @section SataPortPower4
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_PORT_POWER_PORT4 0
+
+/**
+ * @section SataPortPower5
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_PORT_POWER_PORT5 0
+
+/**
+ * @section SataPortPower6
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_PORT_POWER_PORT6 0
+
+/**
+ * @section SataPortPower7
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_PORT_POWER_PORT7 0
+
+/**
+ * @section SataPortMd0
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_PORTMODE_PORT0 3
+
+/**
+ * @section SataPortMd1
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_PORTMODE_PORT1 3
+
+/**
+ * @section SataPortMd2
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_PORTMODE_PORT2 3
+
+/**
+ * @section SataPortMd3
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_PORTMODE_PORT3 3
+
+/**
+ * @section SataPortMd4
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_PORTMODE_PORT4 0
+
+/**
+ * @section SataPortMd5
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_PORTMODE_PORT5 0
+
+/**
+ * @section SataPortMd6
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_PORTMODE_PORT6 0
+
+/**
+ * @section SataPortMd7
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_PORTMODE_PORT7 0
+
+/**
+ * @section SataHotRemovelEnh0
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_HOTREMOVEL_ENH_PORT0 0
+
+/**
+ * @section SataHotRemovelEnh1
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_HOTREMOVEL_ENH_PORT1 0
+
+/**
+ * @section SataHotRemovelEnh2
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_HOTREMOVEL_ENH_PORT2 0
+
+/**
+ * @section SataHotRemovelEnh3
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_HOTREMOVEL_ENH_PORT3 0
+
+/**
+ * @section SataHotRemovelEnh4
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_HOTREMOVEL_ENH_PORT4 0
+
+/**
+ * @section SataHotRemovelEnh5
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_HOTREMOVEL_ENH_PORT5 0
+
+/**
+ * @section SataHotRemovelEnh6
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_HOTREMOVEL_ENH_PORT6 0
+
+/**
+ * @section SataHotRemovelEnh7
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define SATA_HOTREMOVEL_ENH_PORT7 0
+
+/**
+ * @section XhciSwitch
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#if CONFIG_ONBOARD_USB30 == 1
+ #define SB_XHCI_SWITCH 0
+#else
+#define SB_XHCI_SWITCH 1
+#endif
+
+/**
+ * @section FrontPanelDetected
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_FRONT_PANEL_DETECTED 0
+
+/**
+ * @section AnyHT200MhzLink
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_ANY_HT_200MHZ_LINK 0
+
+/**
+ * @section PcibClkStopOverride
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_PCIB_CLK_STOP_OVERRIDE 0
+
+/**
+ * @section GppLinkConfig
+ * @li <b>0000</b> - Port ABCD -> 4:0:0:0
+ * @li <b>0001</b> - N/A
+ * @li <b>0010</b> - Port ABCD -> 2:2:0:0
+ * @li <b>0011</b> - Port ABCD -> 2:1:1:0
+ * @li <b>0100</b> - Port ABCD -> 1:1:1:1
+ */
+#define INCHIP_GPP_LINK_CONFIG 4
+
+/**
+ * @section GppUnhidePorts
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_GPP_UNHIDE_PORTS 0
+
+/**
+ * @section GppPortAspm
+ * @li <b>01</b> - Disabled
+ * @li <b>01</b> - L0s
+ * @li <b>10</b> - L1
+ * @li <b>11</b> - L0s + L1
+ */
+#define INCHIP_GPP_PORT_ASPM 3
+
+/**
+ * @section GppLaneReversal
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_GPP_LANEREVERSAL 0
+
+/**
+ * @section AlinkPhyPllPowerDown
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_ALINK_PHY_PLL_POWER_DOWN 1
+
+/**
+ * @section GppPhyPllPowerDown
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_GPP_PHY_PLL_POWER_DOWN 1
+
+/**
+ * @section GppDynamicPowerSaving
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_GPP_DYNAMIC_POWER_SAVING 1
+
+/**
+ * @section PcieAER
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_PCIE_AER 0
+
+/**
+ * @section PcieRAS
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_PCIE_RAS 0
+
+/**
+ * @section GppHardwareDowngrade
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_GPP_HARDWARE_DOWNGRADE 0
+
+/**
+ * @section GppToggleReset
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_GPP_TOGGLE_RESET 0
+
+/**
+ * @section SbPcieOrderRule
+ * @li <b>00</b> - Disable
+ * @li <b>01</b> - Rule 1
+ * @li <b>10</b> - Rule 2
+ */
+#define INCHIP_SB_PCIE_ORDER_RULE 2
+
+/**
+ * @section AcDcMsg
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_ACDC_MSG 0
+
+/**
+ * @section TimerTickTrack
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_TIMER_TICK_TRACK 1
+
+/**
+ * @section ClockInterruptTag
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_CLOCK_INTERRUPT_TAG 1
+
+/**
+ * @section OhciTrafficHanding
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_OHCI_TRAFFIC_HANDING 0
+
+/**
+ * @section EhciTrafficHanding
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_EHCI_TRAFFIC_HANDING 0
+
+/**
+ * @section FusionMsgCMultiCore
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_FUSION_MSGC_MULTICORE 0
+
+/**
+ * @section FusionMsgCStage
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_FUSION_MSGC_STAGE 0
+
+/**
+ * @section ALinkClkGateOff
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_ALINK_CLK_GATE_OFF 0
+
+/**
+ * @section BLinkClkGateOff
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_BLINK_CLK_GATE_OFF 0
+
+/**
+ * @section SlowSpeedABlinkClock
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_SLOW_SPEED_ABLINK_CLOCK 0
+
+/**
+ * @section AbClockGating
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_AB_CLOCK_GATING 1
+
+/**
+ * @section GppClockGating
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_GPP_CLOCK_GATING 1
+
+/**
+ * @section L1TimerOverwrite
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_L1_TIMER_OVERWRITE 0
+
+/**
+ * @section UmiDynamicSpeedChange
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_UMI_DYNAMIC_SPEED_CHANGE 0
+
+/**
+ * @section SbAlinkGppTxDriverStrength
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_ALINK_GPP_TX_DRV_STRENGTH 0
+
+/**
+ * @section StressResetMode
+ * @li <b>0</b> - Disable
+ * @li <b>1</b> - Enable
+ */
+#define INCHIP_STRESS_RESET_MODE 0
+
+#ifndef SB_PCI_CLOCK_RESERVED
+ #define SB_PCI_CLOCK_RESERVED 0x0 //according to CIMx change 0x1F
+#endif
+
+/**
+ * @brief South Bridge CIMx configuration
+ *
+ */
+void sb900_cimx_config(AMDSBCFG *sb_cfg);
+void SbPowerOnInit_Config(AMDSBCFG *sb_cfg);
+
+/**
+ * @brief Entry point of Southbridge CIMx callout
+ *
+ * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)
+ *
+ * @param[in] func Southbridge CIMx Function ID.
+ * @param[in] data Southbridge Input Data.
+ * @param[in] sb_cfg Southbridge configuration structure pointer.
+ *
+ */
+u32 sb900_callout_entry(u32 func, u32 data, void* sb_cfg);
+
+#endif
bool
default y
-config AMD_CIMX_SB800
- bool
- default y
-
config MAINBOARD_DIR
string
default asrock/e350m1
ramstage-y += PlatformGnbPcie.c
ramstage-y += reset.c
-ramstage-y += pmio.c
subdirs-$(CONFIG_AMD_AGESA) += ../../../vendorcode/amd/agesa/f14
#include <arch/acpi.h>
#include <arch/io.h>
#include <device/device.h>
-//#include "../../../southbridge/amd/sb800/sb800.h"
-
-/*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
-/* pm_base should be got from bar2 of sb800. Here I compact ACPI
- * registers into 32 bytes limit.
- * */
-
-#define ACPI_PM_EVT_BLK (pm_base + 0x00) /* 4 bytes */
-#define ACPI_PM1_CNT_BLK (pm_base + 0x04) /* 2 bytes */
-#define ACPI_PMA_CNT_BLK (pm_base + 0x0F) /* 1 byte */
-#define ACPI_PM_TMR_BLK (pm_base + 0x18) /* 4 bytes */
-#define ACPI_GPE0_BLK (pm_base + 0x10) /* 8 bytes */
-#define ACPI_CPU_CONTORL (pm_base + 0x08) /* 6 bytes */
+#include "SBPLATFORM.h"
+
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{
+ u16 val = 0;
acpi_header_t *header = &(fadt->header);
- pm_base &= 0xFFFF;
- printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
-
+ printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE);
/* Prepare the header */
memset((void *)fadt, 0, sizeof(acpi_fadt_t));
memcpy(header->signature, "FACP", 4);
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = 0xe2;
- pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF);
- pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8);
- pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF);
- pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8);
- pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF);
- pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8);
- pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF);
- pm_iowrite(0x69, ACPI_GPE0_BLK >> 8);
+ val = PM1_EVT_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG60, AccWidthUint16, &val);
+ val = PM1_CNT_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG62, AccWidthUint16, &val);
+ val = PM1_TMR_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG64, AccWidthUint16, &val);
+ val = GPE0_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val);
/* CpuControl is in \_PR.CPU0, 6 bytes */
- pm_iowrite(0x66, ACPI_CPU_CONTORL & 0xFF);
- pm_iowrite(0x67, ACPI_CPU_CONTORL >> 8);
-
- pm_iowrite(0x6A, 0); /* AcpiSmiCmdLo */
- pm_iowrite(0x6B, 0); /* AcpiSmiCmdHi */
-
- pm_iowrite(0x6C, ACPI_PMA_CNT_BLK & 0xFF);
- pm_iowrite(0x6D, ACPI_PMA_CNT_BLK >> 8);
+ val = CPU_CNT_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val);
+ val = 0;
+ WritePMIO(SB_PMIOA_REG6A, AccWidthUint16, &val);
+ val = ACPI_PMA_CNT_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG6C, AccWidthUint16, &val);
+
+ /* AcpiDecodeEnable, When set, SB uses the contents of the
+ * PM registers at index 60-6B to decode ACPI I/O address.
+ * AcpiSmiEn & SmiCmdEn*/
+ val = BIT0 | BIT1 | BIT2 | BIT4;
+ WritePMIO(SB_PMIOA_REG74, AccWidthUint16, &val);
- pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses
- * the contents of the PM registers at
- * index 60-6B to decode ACPI I/O address.
- * AcpiSmiEn & SmiCmdEn*/
/* RTC_En_En, TMR_En_En, GBL_EN_EN */
- outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
- fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
+ outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */
+ fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS;
fadt->pm1b_evt_blk = 0x0000;
- fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
+ fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS;
fadt->pm1b_cnt_blk = 0x0000;
- fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
- fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
- fadt->gpe0_blk = ACPI_GPE0_BLK;
+ fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS;
+ fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS;
+ fadt->gpe0_blk = GPE0_BLK_ADDRESS;
fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */
fadt->pm1_evt_len = 4;
fadt->x_pm1a_evt_blk.bit_width = 32;
fadt->x_pm1a_evt_blk.bit_offset = 0;
fadt->x_pm1a_evt_blk.resv = 0;
- fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
+ fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS;
fadt->x_pm1a_evt_blk.addrh = 0x0;
fadt->x_pm1b_evt_blk.space_id = 1;
fadt->x_pm1a_cnt_blk.bit_width = 16;
fadt->x_pm1a_cnt_blk.bit_offset = 0;
fadt->x_pm1a_cnt_blk.resv = 0;
- fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
+ fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS;
fadt->x_pm1a_cnt_blk.addrh = 0x0;
fadt->x_pm1b_cnt_blk.space_id = 1;
fadt->x_pm2_cnt_blk.bit_width = 0;
fadt->x_pm2_cnt_blk.bit_offset = 0;
fadt->x_pm2_cnt_blk.resv = 0;
- fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
+ fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS;
fadt->x_pm2_cnt_blk.addrh = 0x0;
fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.resv = 0;
- fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
+ fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS;
fadt->x_pm_tmr_blk.addrh = 0x0;
fadt->x_gpe0_blk.bit_width = 32;
fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.resv = 0;
- fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
+ fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS;
fadt->x_gpe0_blk.addrh = 0x0;
#include <stdint.h>
#include <stdlib.h>
#include <cpu/amd/amdfam14.h>
+#if CONFIG_AMD_SB_CIMX
+#include "sb_cimx.h"
+#endif
/* Global variables for MB layouts and these will be shared by irqtable mptable
bus_isa = 10;
apicid_base = CONFIG_MAX_CPUS;
apicid_sb800 = apicid_base;
+
+#if CONFIG_AMD_SB_CIMX
+ sb_Late_Post();
+#endif
}
#include <arch/io.h>
#include <string.h>
#include <stdint.h>
+#include <SBPLATFORM.h>
extern u8 bus_sb800[2];
u32 dword;
u8 byte;
- dword = 0;
- dword = pm_ioread(0x34) & 0xF0;
- dword |= (pm_ioread(0x35) & 0xFF) << 8;
- dword |= (pm_ioread(0x36) & 0xFF) << 16;
- dword |= (pm_ioread(0x37) & 0xFF) << 24;
+ ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
+ dword &= 0xFFFFFFF0;
smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#ifndef _E350M1_CFG_H_
+#define _E350M1_CFG_H_
+
+/**
+ * @def BIOS_SIZE_1M
+ * @def BIOS_SIZE_2M
+ * @def BIOS_SIZE_4M
+ * @def BIOS_SIZE_8M
+ */
+#define BIOS_SIZE_1M 0
+#define BIOS_SIZE_2M 1
+#define BIOS_SIZE_4M 3
+#define BIOS_SIZE_8M 7
+
+/* In SB800, default ROM size is 1M Bytes, if your platform ROM
+ * bigger than 1M you have to set the ROM size outside CIMx module and
+ * before AGESA module get call.
+ */
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+ #define BIOS_SIZE BIOS_SIZE_1M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
+ #define BIOS_SIZE BIOS_SIZE_2M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
+ #define BIOS_SIZE BIOS_SIZE_4M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
+ #define BIOS_SIZE BIOS_SIZE_8M
+#endif
+
+/**
+ * @def SPREAD_SPECTRUM
+ * @brief
+ * 0 - Disable Spread Spectrum function
+ * 1 - Enable Spread Spectrum function
+ */
+#define SPREAD_SPECTRUM 0
+
+/**
+ * @def SB_HPET_TIMER
+ * @breif
+ * 0 - Disable hpet
+ * 1 - Enable hpet
+ */
+#define HPET_TIMER 1
+
+/**
+ * @def USB_CONFIG
+ * @brief bit[0-6] used to control USB
+ * 0 - Disable
+ * 1 - Enable
+ * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
+ * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
+ * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
+ * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
+ * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
+ * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
+ * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
+ */
+#define USB_CONFIG 0x7F
+
+/**
+ * @def PCI_CLOCK_CTRL
+ * @breif bit[0-4] used for PCI Slots Clock Control,
+ * 0 - disable
+ * 1 - enable
+ * PCI SLOT 0 define at BIT0
+ * PCI SLOT 1 define at BIT1
+ * PCI SLOT 2 define at BIT2
+ * PCI SLOT 3 define at BIT3
+ * PCI SLOT 4 define at BIT4
+ */
+#define PCI_CLOCK_CTRL 0x1F
+
+/**
+ * @def SATA_CONTROLLER
+ * @breif INCHIP Sata Controller
+ */
+#define SATA_CONTROLLER CIMX_OPTION_ENABLED
+
+/**
+ * @def SATA_MODE
+ * @breif INCHIP Sata Controller Mode
+ * NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#define SATA_MODE NATIVE_IDE_MODE
+
+/**
+ * @breif INCHIP Sata IDE Controller Mode
+ */
+#define IDE_LEGACY_MODE 0
+#define IDE_NATIVE_MODE 1
+
+/**
+ * @def SATA_IDE_MODE
+ * @breif INCHIP Sata IDE Controller Mode
+ * NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#define SATA_IDE_MODE IDE_LEGACY_MODE
+
+/**
+ * @def EXTERNAL_CLOCK
+ * @brief 00/10: Reference clock from crystal oscillator via
+ * PAD_XTALI and PAD_XTALO
+ *
+ * @def INTERNAL_CLOCK
+ * @brief 01/11: Reference clock from internal clock through
+ * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
+ */
+#define EXTERNAL_CLOCK 0x00
+#define INTERNAL_CLOCK 0x01
+
+/* NOTE: inagua have to using internal clock,
+ * otherwise can not detect sata drive
+ */
+#define SATA_CLOCK_SOURCE INTERNAL_CLOCK
+
+/**
+ * @def SATA_PORT_MULT_CAP_RESERVED
+ * @brief 1 ON, 0 0FF
+ */
+#define SATA_PORT_MULT_CAP_RESERVED 1
+
+
+/**
+ * @def AZALIA_AUTO
+ * @brief Detect Azalia controller automatically.
+ *
+ * @def AZALIA_DISABLE
+ * @brief Disable Azalia controller.
+
+ * @def AZALIA_ENABLE
+ * @brief Enable Azalia controller.
+ */
+#define AZALIA_AUTO 0
+#define AZALIA_DISABLE 1
+#define AZALIA_ENABLE 2
+
+/**
+ * @breif INCHIP HDA controller
+ */
+#define AZALIA_CONTROLLER AZALIA_AUTO
+
+/**
+ * @def AZALIA_PIN_CONFIG
+ * @brief
+ * 0 - disable
+ * 1 - enable
+ */
+#define AZALIA_PIN_CONFIG 1
+
+/**
+ * @def AZALIA_SDIN_PIN
+ * @brief
+ * SDIN0 is define at BIT0 & BIT1
+ * 00 - GPIO PIN
+ * 01 - Reserved
+ * 10 - As a Azalia SDIN pin
+ * SDIN1 is define at BIT2 & BIT3
+ * SDIN2 is define at BIT4 & BIT5
+ * SDIN3 is define at BIT6 & BIT7
+ */
+//#define AZALIA_SDIN_PIN 0xAA
+#define AZALIA_SDIN_PIN 0x2A
+
+/**
+ * @def GPP_CONTROLLER
+ */
+#define GPP_CONTROLLER CIMX_OPTION_ENABLED
+
+/**
+ * @def GPP_CFGMODE
+ * @brief GPP Link Configuration
+ * four possible configuration:
+ * GPP_CFGMODE_X4000
+ * GPP_CFGMODE_X2200
+ * GPP_CFGMODE_X2110
+ * GPP_CFGMODE_X1111
+ */
+#define GPP_CFGMODE GPP_CFGMODE_X1111
+
+/**
+ * @def NB_SB_GEN2
+ * 0 - Disable
+ * 1 - Enable
+ */
+#define NB_SB_GEN2 TRUE
+
+/**
+ * @def SB_GEN2
+ * 0 - Disable
+ * 1 - Enable
+ */
+#define SB_GPP_GEN2 TRUE
+
+
+/**
+ * @def GEC_CONFIG
+ * 0 - Enable
+ * 1 - Disable
+ */
+#define GEC_CONFIG 0
+
+#endif
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-#include <arch/io.h> /*inb, outb*/
-#include "pmio.h"
-
-static void pmio_write_index(u16 port_base, u8 reg, u8 value)
-{
- outb(reg, port_base);
- outb(value, port_base + 1);
-}
-
-static u8 pmio_read_index(u16 port_base, u8 reg)
-{
- outb(reg, port_base);
- return inb(port_base + 1);
-}
-
-void pm_iowrite(u8 reg, u8 value)
-{
- pmio_write_index(PM_INDEX, reg, value);
-}
-
-u8 pm_ioread(u8 reg)
-{
- return pmio_read_index(PM_INDEX, reg);
-}
-
-void pm2_iowrite(u8 reg, u8 value)
-{
- pmio_write_index(PM2_INDEX, reg, value);
-}
-
-u8 pm2_ioread(u8 reg)
-{
- return pmio_read_index(PM2_INDEX, reg);
-}
-
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-#ifndef _PMIO_H_
-#define _PMIO_H_
-
-#define PM_INDEX 0xCD6
-#define PM_DATA 0xCD7
-#define PM2_INDEX 0xCD0
-#define PM2_DATA 0xCD1
-
-void pm_iowrite(u8 reg, u8 value);
-u8 pm_ioread(u8 reg);
-void pm2_iowrite(u8 reg, u8 value);
-u8 pm2_ioread(u8 reg);
-
-#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "pc80/i8254.c"
#include "pc80/i8259.c"
-#include "SbEarly.h"
+#include "sb_cimx.h"
#include "SBPLATFORM.h"
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
- sb_poweron_init();
+ sb_Poweron_Init();
post_code(0x31);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
#include "chip.h"
#include "northbridge.h"
+#if CONFIG_AMD_SB_CIMX
+#include <sb_cimx.h>
+#endif
//#define FX_DEVS NODE_NUMS
static void domain_enable_resources(device_t dev)
{
u32 val;
+
+#if CONFIG_AMD_SB_CIMX
+ sb_After_Pci_Init();
+ sb_Mid_Post_Init();
+#endif
+
/* Must be called after PCI enumeration and resource allocation */
printk(BIOS_DEBUG, "\nFam14h - domain_enable_resources: AmdInitMid.\n");
val = agesawrapper_amdinitmid ();
#endif
#include <cpu/amd/amdfam10_sysconf.h>
+#if CONFIG_AMD_SB_CIMX
+#include <sb_cimx.h>
+#endif
struct amdfam10_sysconf_t sysconf;
static void cpu_bus_init(device_t dev)
{
initialize_cpus(dev->link_list);
+#if CONFIG_AMD_SB_CIMX
+ sb_After_Pci_Init();
+ sb_Mid_Post_Init();
+#endif
}
static void cpu_bus_noop(device_t dev)
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5530) += cs5530
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5535) += cs5535
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5536) += cs5536
-subdirs-$(CONFIG_AMD_CIMX_SB800) += cimx
-subdirs-$(CONFIG_AMD_CIMX_SB900) += cimx
+subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx
+subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
+config AMD_SB_CIMX
+ bool
+ default n
+
source src/southbridge/amd/cimx/sb800/Kconfig
source src/southbridge/amd/cimx/sb900/Kconfig
#define ILLEGAL_SBDFO 0xFFFFFFFF
/// CPUID data received registers format
-typedef struct _SB_CPUID_DATA {
+typedef struct _CPUID_DATA {
IN OUT unsigned int EAX_Reg; ///< CPUID instruction result in EAX
IN OUT unsigned int EBX_Reg; ///< CPUID instruction result in EBX
IN OUT unsigned int ECX_Reg; ///< CPUID instruction result in ECX
config SOUTHBRIDGE_AMD_CIMX_SB800
bool
+ default n
select IOAPIC
+ select AMD_SB_CIMX
if SOUTHBRIDGE_AMD_CIMX_SB800
config BOOTBLOCK_SOUTHBRIDGE_INIT
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
-subdirs-$(CONFIG_AMD_CIMX_SB800) += ../../../../../src/vendorcode/amd/cimx/sb800
+subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += ../../../../../src/vendorcode/amd/cimx/sb800
# SB800 Platform Files
#endif
#define FIXUP_PTR(ptr) ptr
+#include <console/console.h>
#include "AmdSbLib.h"
#include "Amd.h"
#include "SB800.h"
#include "SBDEF.h"
#include "AMDSBLIB.h"
#include "SBSUBFUN.h"
-#include "OEM.h"
+#include "platform_cfg.h" /* mainboard specific configuration */
+#include "OEM.h" /* platform default configuration */
#include "AMD.h"
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-#ifndef _CIMX_SB_EARLY_H_
-#define _CIMX_SB_EARLY_H_
-
-/**
- * @brief Get SouthBridge device number, called by finalize_node_setup()
- * @param[in] bus target bus number
- * @return southbridge device number
- */
-u32 get_sbdn(u32 bus);
-
-/**
- * South Bridge CIMx romstage entry, sbPowerOnInit entry point wrapper.
- */
-void sb_poweron_init(void);
-//void sb_before_pci_init(void);
-
-#endif
void sb800_cimx_config(AMDSBCFG *sb_config)
{
if (!sb_config) {
+ printk(BIOS_DEBUG, "SB800 - Cfg.c - sb800_cimx_config - No sb_config.\n");
return;
}
+ printk(BIOS_INFO, "SB800 - Cfg.c - sb800_cimx_config - Start.\n");
//memset(sb_config, 0, sizeof(AMDSBCFG));
/* header */
sb_config->HpetTimer = HPET_TIMER;
/* USB */
- sb_config->USBMODE.UsbModeReg = USB_CINFIG;
+ sb_config->USBMODE.UsbModeReg = USB_CONFIG;
sb_config->SbUsbPll = 0;
/* SATA */
sb_config->GppFunctionEnable = GPP_CONTROLLER;
sb_config->GppLinkConfig = GPP_CFGMODE;
//sb_config->PORTCONFIG[0].PortCfg.PortHotPlug = TRUE;
+ sb_config->PORTCONFIG[0].PortCfg.PortPresent = CIMX_OPTION_ENABLED;
+ sb_config->PORTCONFIG[1].PortCfg.PortPresent = CIMX_OPTION_ENABLED;
+ sb_config->PORTCONFIG[2].PortCfg.PortPresent = CIMX_OPTION_ENABLED;
+ sb_config->PORTCONFIG[3].PortCfg.PortPresent = CIMX_OPTION_ENABLED;
sb_config->GppUnhidePorts = TRUE; //visable always, even port empty
- //sb_config->NbSbGen2 = TRUE;
- //sb_config->GppGen2 = TRUE;
+ sb_config->NbSbGen2 = NB_SB_GEN2;
+ sb_config->GppGen2 = SB_GPP_GEN2;
//cimx BTS fix
sb_config->GppMemWrImprove = TRUE;
sb_config->SbPcieOrderRule = TRUE;
sb_config->AlinkPhyPllPowerDown = TRUE;
sb_config->GppPhyPllPowerDown = TRUE; //GPP power saving
- sb_config->SBGecPwr = 0x03;//11b << 5, rpr BDF: 00:20:06, PLATFORM.H default define 0x11 was wrong
- sb_config->GecConfig = 0; //ENABLE GEC controller
+ sb_config->SBGecPwr = 0x03;//11b << 5, rpr BDF: 00:20:06
+ sb_config->GecConfig = GEC_CONFIG;
#ifndef __PRE_RAM__
/* ramstage cimx config here */
if (!sb_config->StdHeader.CALLBACK.CalloutPtr) {
sb_config->StdHeader.CALLBACK.CalloutPtr = sb800_callout_entry;
}
-
- //sb_config->
#endif //!__PRE_RAM__
+ printk(BIOS_INFO, "SB800 - Cfg.c - sb800_cimx_config - End.\n");
}
#include <stdint.h>
-
-/**
- * @def BIOS_SIZE_1M
- * @def BIOS_SIZE_2M
- * @def BIOS_SIZE_4M
- * @def BIOS_SIZE_8M
- */
-#define BIOS_SIZE_1M 0
-#define BIOS_SIZE_2M 1
-#define BIOS_SIZE_4M 3
-#define BIOS_SIZE_8M 7
-
-/* In SB800, default ROM size is 1M Bytes, if your platform ROM
- * bigger than 1M you have to set the ROM size outside CIMx module and
- * before AGESA module get call.
- */
-#ifndef BIOS_SIZE
-#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
- #define BIOS_SIZE BIOS_SIZE_1M
-#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
- #define BIOS_SIZE BIOS_SIZE_2M
-#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
- #define BIOS_SIZE BIOS_SIZE_4M
-#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
- #define BIOS_SIZE BIOS_SIZE_8M
-#endif
-#endif
-
-/**
- * @def SPREAD_SPECTRUM
- * @brief
- * 0 - Disable Spread Spectrum function
- * 1 - Enable Spread Spectrum function
- */
-#define SPREAD_SPECTRUM 0
-
-/**
- * @def SB_HPET_TIMER
- * @breif
- * 0 - Disable hpet
- * 1 - Enable hpet
- */
-#define HPET_TIMER 1
-
-/**
- * @def USB_CONFIG
- * @brief bit[0-6] used to control USB
- * 0 - Disable
- * 1 - Enable
- * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
- * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
- * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
- * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
- * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
- * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
- * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
- */
-#define USB_CINFIG 0x7F
-
-/**
- * @def PCI_CLOCK_CTRL
- * @breif bit[0-4] used for PCI Slots Clock Control,
- * 0 - disable
- * 1 - enable
- * PCI SLOT 0 define at BIT0
- * PCI SLOT 1 define at BIT1
- * PCI SLOT 2 define at BIT2
- * PCI SLOT 3 define at BIT3
- * PCI SLOT 4 define at BIT4
- */
-#define PCI_CLOCK_CTRL 0x1F
-
-/**
- * @def SATA_CONTROLLER
- * @breif INCHIP Sata Controller
- */
-#ifndef SATA_CONTROLLER
- #define SATA_CONTROLLER CIMX_OPTION_ENABLED
-#endif
-
-/**
- * @def SATA_MODE
- * @breif INCHIP Sata Controller Mode
- * NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#ifndef SATA_MODE
- #define SATA_MODE NATIVE_IDE_MODE
-#endif
-
-/**
- * @breif INCHIP Sata IDE Controller Mode
- */
-#define IDE_LEGACY_MODE 0
-#define IDE_NATIVE_MODE 1
-
-/**
- * @def SATA_IDE_MODE
- * @breif INCHIP Sata IDE Controller Mode
- * NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#ifndef SATA_IDE_MODE
- #define SATA_IDE_MODE IDE_LEGACY_MODE
-#endif
-
-/**
- * @def EXTERNAL_CLOCK
- * @brief 00/10: Reference clock from crystal oscillator via
- * PAD_XTALI and PAD_XTALO
- *
- * @def INTERNAL_CLOCK
- * @brief 01/11: Reference clock from internal clock through
- * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
- */
-#define EXTERNAL_CLOCK 0x00
-#define INTERNAL_CLOCK 0x01
-
-/* NOTE: inagua have to using internal clock,
- * otherwise can not detect sata drive
- */
-#define SATA_CLOCK_SOURCE INTERNAL_CLOCK
-
-/**
- * @def SATA_PORT_MULT_CAP_RESERVED
- * @brief 1 ON, 0 0FF
- */
-#define SATA_PORT_MULT_CAP_RESERVED 1
-
-
-/**
- * @def AZALIA_AUTO
- * @brief Detect Azalia controller automatically.
- *
- * @def AZALIA_DISABLE
- * @brief Disable Azalia controller.
-
- * @def AZALIA_ENABLE
- * @brief Enable Azalia controller.
- */
-#define AZALIA_AUTO 0
-#define AZALIA_DISABLE 1
-#define AZALIA_ENABLE 2
-
-/**
- * @breif INCHIP HDA controller
- */
-#ifndef AZALIA_CONTROLLER
- #define AZALIA_CONTROLLER AZALIA_AUTO
-#endif
-
-/**
- * @def AZALIA_PIN_CONFIG
- * @brief
- * 0 - disable
- * 1 - enable
- */
-#ifndef AZALIA_PIN_CONFIG
- #define AZALIA_PIN_CONFIG 1
-#endif
-
-/**
- * @def AZALIA_SDIN_PIN
- * @brief
- * SDIN0 is define at BIT0 & BIT1
- * 00 - GPIO PIN
- * 01 - Reserved
- * 10 - As a Azalia SDIN pin
- * SDIN1 is define at BIT2 & BIT3
- * SDIN2 is define at BIT4 & BIT5
- * SDIN3 is define at BIT6 & BIT7
- */
-#ifndef AZALIA_SDIN_PIN
- //#define AZALIA_SDIN_PIN 0xAA
- #define AZALIA_SDIN_PIN 0x2A
-#endif
-
-/**
- * @def GPP_CONTROLLER
- */
-#ifndef GPP_CONTROLLER
- #define GPP_CONTROLLER CIMX_OPTION_ENABLED
-#endif
-
-/**
- * @def GPP_CFGMODE
- * @brief GPP Link Configuration
- * four possible configuration:
- * GPP_CFGMODE_X4000
- * GPP_CFGMODE_X2200
- * GPP_CFGMODE_X2110
- * GPP_CFGMODE_X1111
- */
-#ifndef GPP_CFGMODE
- #define GPP_CFGMODE GPP_CFGMODE_X1111
-#endif
-
-
/**
* @brief South Bridge CIMx configuration
*
#include <arch/io.h> /* inl, outl */
#include <arch/romcc_io.h> /* device_t */
#include "SBPLATFORM.h"
-#include "SbEarly.h"
+#include "sb_cimx.h"
#include "cfg.h" /*sb800_cimx_config*/
+#if CONFIG_RAMINIT_SYSINFO == 1
/**
* @brief Get SouthBridge device number
* @param[in] bus target bus number
{
device_t dev;
+ printk(BIOS_DEBUG, "SB800 - %s - %s - Start.\n", __FILE__, __func__);
//dev = PCI_DEV(bus, 0x14, 0);
dev = pci_locate_device_on_bus(
PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB800_SM),
bus);
+ printk(BIOS_DEBUG, "SB800 - %s - %s - End.\n", __FILE__, __func__);
return (dev >> 15) & 0x1f;
}
+#endif
/**
* @brief South Bridge CIMx romstage entry,
* wrapper of sbPowerOnInit entry point.
*/
-void sb_poweron_init(void)
+void sb_Poweron_Init(void)
{
AMDSBCFG sb_early_cfg;
// VerifyImage() will fail, LocateImage() take minitues to find the image.
sbPowerOnInit(&sb_early_cfg);
}
+
+/**
+ * CIMX not set the clock to 48Mhz until sbBeforePciInit,
+ * coreboot may need to set this even more earlier
+ */
+void sb800_clk_output_48Mhz(void)
+{
+ /* AcpiMMioDecodeEn */
+ RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0 + BIT1), BIT0);
+
+ *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
+ *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */
+}
+
#include "SBPLATFORM.h" /* Platfrom Specific Definitions */
#include "cfg.h" /* sb800 Cimx configuration */
#include "chip.h" /* struct southbridge_amd_cimx_sb800_config */
+#include "sb_cimx.h" /* AMD CIMX wrapper entries */
/*implement in mainboard.c*/
-//void set_pcie_assert(void);
-//void set_pcie_deassert(void);
void set_pcie_reset(void);
void set_pcie_dereset(void);
-#ifndef _RAMSTAGE_
-#define _RAMSTAGE_
-#endif
static AMDSBCFG sb_late_cfg; //global, init in sb800_cimx_config
static AMDSBCFG *sb_config = &sb_late_cfg;
u32 sb800_callout_entry(u32 func, u32 data, void* config)
{
u32 ret = 0;
-
+ printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__);
switch (func) {
case CB_SBGPP_RESET_ASSERT:
- //set_pcie_assert();
set_pcie_reset();
break;
case CB_SBGPP_RESET_DEASSERT:
- //set_pcie_deassert();
set_pcie_dereset();
break;
break;
}
+ printk(BIOS_DEBUG, "SB800 - Late.c - %s - End.\n", __func__);
return ret;
}
static struct pci_operations lops_pci = {
- .set_subsystem = 0,
+ .set_subsystem = pci_dev_set_subsystem,
};
-static void lpc_enable_resources(device_t dev)
-{
-
- pci_dev_enable_resources(dev);
- //lpc_enable_childrens_resources(dev);
-}
-
-static void lpc_init(device_t dev)
-{
- /* SB Configure HPET base and enable bit */
- hpetInit(sb_config, &(sb_config->BuildParameters));
-}
-
static struct device_operations lpc_ops = {
.read_resources = lpc_read_resources,
.set_resources = lpc_set_resources,
- .enable_resources = lpc_enable_resources,
- .init = lpc_init,
+ .enable_resources = pci_dev_enable_resources,
+ .init = 0,
.scan_bus = scan_static_bus,
.ops_pci = &lops_pci,
};
.device = PCI_DEVICE_ID_ATI_SB800_LPC,
};
-
-static void sata_enable_resources(struct device *dev)
-{
- sataInitAfterPciEnum(sb_config);
- pci_dev_enable_resources(dev);
-}
-
-static void sata_init(struct device *dev)
-{
- sb_config->StdHeader.Func = SB_MID_POST_INIT;
- AmdSbDispatcher(sb_config); //sataInitMidPost only
- commonInitLateBoot(sb_config);
- sataInitLatePost(sb_config);
-}
-
static struct device_operations sata_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
- .enable_resources = sata_enable_resources, //pci_dev_enable_resources,
- .init = sata_init,
+ .enable_resources = pci_dev_enable_resources,
+ .init = 0,
.scan_bus = 0,
.ops_pci = &lops_pci,
};
.device = PCI_DEVICE_ID_ATI_SB800_SATA_AHCI,
};
-#if CONFIG_USBDEBUG
+#if CONFIG_USBDEBUG == 1
static void usb_set_resources(struct device *dev)
{
struct resource *res;
u32 base;
u32 old_debug;
+ printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__);
old_debug = get_ehci_debug();
set_ehci_debug(0);
base = res->base;
set_ehci_base(base);
report_resource_stored(dev, res, "");
+ printk(BIOS_DEBUG, "SB800 - Late.c - %s - End.\n", __func__);
}
#endif
-static void usb_init(struct device *dev)
-{
- usbInitAfterPciInit(sb_config);
- commonInitLateBoot(sb_config);
-}
-
static struct device_operations usb_ops = {
.read_resources = pci_dev_read_resources,
#if CONFIG_USBDEBUG
.set_resources = pci_dev_set_resources,
#endif
.enable_resources = pci_dev_enable_resources,
- .init = usb_init,
+ .init = 0,
.scan_bus = 0,
.ops_pci = &lops_pci,
};
};
-static void azalia_init(struct device *dev)
-{
- azaliaInitAfterPciEnum(sb_config); //Detect and configure High Definition Audio
-}
-
static struct device_operations azalia_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
- .init = azalia_init,
+ .init = 0,
.scan_bus = 0,
.ops_pci = &lops_pci,
};
};
-static void gec_init(struct device *dev)
-{
- gecInitAfterPciEnum(sb_config);
- gecInitLatePost(sb_config);
- printk(BIOS_DEBUG, "gec hda enabled\n");
-}
-
static struct device_operations gec_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
- .init = gec_init,
+ .init = 0,
.scan_bus = 0,
.ops_pci = &lops_pci,
};
RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 0);
}
-static void pcie_init(device_t dev)
-{
- sbPcieGppLateInit(sb_config);
-}
static struct device_operations pci_ops = {
.read_resources = pci_bus_read_resources,
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_bus_enable_resources,
- .init = pcie_init,
+ .init = 0,
.scan_bus = pci_scan_bridge,
.enable = 0,
.reset_bus = pci_bus_reset,
};
+/**
+ * South Bridge CIMx ramstage entry point wrapper.
+ */
+void sb_Before_Pci_Init(void)
+{
+ sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT;
+ AmdSbDispatcher(sb_config);
+}
+
+void sb_After_Pci_Init(void)
+{
+ sb_config->StdHeader.Func = SB_AFTER_PCI_INIT;
+ AmdSbDispatcher(sb_config);
+}
+
+void sb_Mid_Post_Init(void)
+{
+ sb_config->StdHeader.Func = SB_MID_POST_INIT;
+ AmdSbDispatcher(sb_config);
+}
+
+void sb_Late_Post(void)
+{
+ sb_config->StdHeader.Func = SB_LATE_POST_INIT;
+ AmdSbDispatcher(sb_config);
+}
+
+
/**
* @brief SB Cimx entry point sbBeforePciInit wrapper
*/
struct southbridge_amd_cimx_sb800_config *sb_chip =
(struct southbridge_amd_cimx_sb800_config *)(dev->chip_info);
- sb800_cimx_config(sb_config);
printk(BIOS_DEBUG, "sb800_enable() ");
- /* Config SouthBridge SMBUS/ACPI/IDE/LPC/PCIB.*/
- commonInitEarlyBoot(sb_config);
- commonInitEarlyPost(sb_config);
-
switch (dev->path.pci.devfn) {
case (0x11 << 3) | 0: /* 0:11.0 SATA */
+ /* the first sb800 device */
+ sb800_cimx_config(sb_config);
+
if (dev->enabled) {
sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED;
if (1 == sb_chip->boot_switch_sata_ide)
} else {
sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED;
}
-
- sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
- break;
-
- case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
- case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */
- case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */
- case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */
- case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */
- case (0x16 << 3) | 0: /* 0:16:0 OHCI-USB3 */
- case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */
- usbInitBeforePciEnum(sb_config); // USB POST TIME Only
break;
case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
- {
- u32 ioapic_base;
-
- printk(BIOS_INFO, "sm_init().\n");
- ioapic_base = IO_APIC_ADDR;
- clear_ioapic(ioapic_base);
- /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
- #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16)
- /* Assign the ioapic ID the next available number after the processor core local APIC IDs */
- setup_ioapic(ioapic_base, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS);
- #elif (CONFIG_APIC_ID_OFFSET > 0)
- /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */
- setup_ioapic(ioapic_base, 0);
- #else
- #error "The processor APIC IDs must be lifted to make room for the I/O APIC ID"
- #endif
- }
-
+ printk(BIOS_INFO, "sm_init().\n");
+ clear_ioapic(IO_APIC_ADDR);
+ /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
+#if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16)
+ /* Assign the ioapic ID the next available number after the processor core local APIC IDs */
+ setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS);
+#elif (CONFIG_APIC_ID_OFFSET > 0)
+ /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */
+ setup_ioapic(IO_APIC_ADDR, 0);
+#else
+#error "The processor APIC IDs must be lifted to make room for the I/O APIC ID"
+#endif
break;
case (0x14 << 3) | 1: /* 0:14:1 IDE */
} else {
sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_DISABLED;
}
- sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
break;
case (0x14 << 3) | 2: /* 0:14:2 HDA */
sb_config->AzaliaController = AZALIA_DISABLE;
printk(BIOS_DEBUG, "hda disabled\n");
}
- azaliaInitBeforePciEnum(sb_config); // Detect and configure High Definition Audio
break;
sb_config->GecConfig = 1;
printk(BIOS_DEBUG, "gec disabled\n");
}
- gecInitBeforePciEnum(sb_config); // Init GEC
break;
case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
{
- device_t device;
- for (device = dev; device; device = device->next) {
- if (dev->path.type != DEVICE_PATH_PCI) continue;
- if ((device->path.pci.devfn & ~7) != PCI_DEVFN(0x15,0)) break;
- sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled;
+ device_t device;
+ for (device = dev; device; device = device->next) {
+ if (dev->path.type != DEVICE_PATH_PCI) continue;
+ if ((device->path.pci.devfn & ~7) != PCI_DEVFN(0x15,0)) break;
+ sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled;
+ }
+
+ /*
+ * GPP_CFGMODE_X4000: PortA Lanes[3:0]
+ * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2]
+ * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3
+ * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
+ */
+ sb_config->GppLinkConfig = sb_chip->gpp_configuration;
}
+ break;
- /*
- * GPP_CFGMODE_X4000: PortA Lanes[3:0]
- * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2]
- * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3
- * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
- */
- sb_config->GppLinkConfig = sb_chip->gpp_configuration;
- sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT;
- AmdSbDispatcher(sb_config);
+ case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
+ sb_config->USBMODE.UsbMode.Ohci1 = dev->enabled;
+ break;
+ case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */
+ sb_config->USBMODE.UsbMode.Ehci1 = dev->enabled;
+ break;
+ case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */
+ sb_config->USBMODE.UsbMode.Ohci2 = dev->enabled;
+ break;
+ case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */
+ sb_config->USBMODE.UsbMode.Ehci2 = dev->enabled;
+ break;
+ case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */
+ sb_config->USBMODE.UsbMode.Ohci4 = dev->enabled;
+ break;
+ case (0x16 << 3) | 0: /* 0:16:0 OHCI-USB3 */
+ sb_config->USBMODE.UsbMode.Ohci3 = dev->enabled;
+ break;
+ case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */
+ sb_config->USBMODE.UsbMode.Ehci3 = dev->enabled;
+
+ /* the last sb800 device */
+ sb_Before_Pci_Init();
break;
- }
default:
break;
}
-
}
struct chip_operations southbridge_amd_cimx_sb800_ops = {
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <console/console.h>
#include <device/pci.h>
#include "lpc.h"
{
struct resource *res;
+ printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_read_resources - Start.\n");
/* Get the normal pci resources of this device */
pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
compact_resources(dev);
+ printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_read_resources - End.\n");
}
void lpc_set_resources(struct device *dev)
{
struct resource *res;
+ printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_set_resources - Start.\n");
pci_dev_set_resources(dev);
/* Specical case. SPI Base Address. The SpiRomEnable should be set. */
res = find_resource(dev, SPIROM_BASE_ADDRESS);
pci_write_config32(dev, SPIROM_BASE_ADDRESS, res->base | 1 << 1);
-
+ printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_set_resources - End.\n");
}
/**
int var_num = 0;
u16 reg_var[3];
+ printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_enable_childrens_resources - Start.\n");
reg = pci_read_config32(dev, 0x44);
reg_x = pci_read_config32(dev, 0x48);
//pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata
break;
}
+ printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_enable_childrens_resources - End.\n");
}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#ifndef _CIMX_H_
+#define _CIMX_H_
+
+/**
+ * AMD South Bridge CIMx entry point wrapper
+ */
+void sb_Poweron_Init(void);
+void sb_Before_Pci_Init(void);
+void sb_After_Pci_Init(void);
+void sb_Mid_Post_Init(void);
+void sb_Late_Post(void);
+
+/**
+ * CIMX not set the clock to 48Mhz until sbBeforePciInit,
+ * coreboot may need to set this even more earlier
+ */
+void sb800_clk_output_48Mhz(void);
+
+#if CONFIG_RAMINIT_SYSINFO == 1
+/**
+ * @brief Get SouthBridge device number, called by finalize_node_setup()
+ * @param[in] bus target bus number
+ * @return southbridge device number
+ */
+u32 get_sbdn(u32 bus);
+#endif
+#endif
#include <arch/io.h>
#include "smbus.h"
+#include <console/console.h> /* printk */
static inline void smbus_delay(void)
{
u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - smbus not ready.\n");
return -2; /* not ready */
}
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - Start.\n");
/* set the device I'm talking too */
outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
/* read results of transaction */
byte = inb(smbus_io_base + SMBHSTCMD);
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - End.\n");
return byte;
}
u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - smbus not ready.\n");
return -2; /* not ready */
}
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - Start.\n");
/* set the command... */
outb(val, smbus_io_base + SMBHSTCMD);
return -3; /* timeout or error */
}
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - End.\n");
return 0;
}
u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - smbus not ready.\n");
return -2; /* not ready */
}
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - Start.\n");
/* set the command/address... */
outb(address & 0xff, smbus_io_base + SMBHSTCMD);
/* read results of transaction */
byte = inb(smbus_io_base + SMBHSTDAT0);
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - End.\n");
return byte;
}
u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - smbus not ready.\n");
return -2; /* not ready */
}
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - Start.\n");
/* set the command/address... */
outb(address & 0xff, smbus_io_base + SMBHSTCMD);
return -3; /* timeout or error */
}
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - End.\n");
return 0;
}
{
u32 tmp;
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_ab_indx - Start.\n");
outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX);
tmp = inl(AB_DATA);
/* rpr 4.2
outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we dont have to do it again. */
outl(tmp, AB_DATA);
outl(0, AB_INDX);
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_ab_indx - End.\n");
}
void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val)
{
u32 tmp;
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_rc_indx - Start.\n");
outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX);
tmp = inl(AB_DATA);
/* rpr 4.2
outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we dont have to do it again. */
outl(tmp, AB_DATA);
outl(0, AB_INDX);
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_rc_indx - End.\n");
}
/* space = 0: AX_INDXC, AX_DATAC
{
u32 tmp;
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_ax_indx - Start.\n");
/* read axindc to tmp */
outl(space << 29 | space << 3 | 0x30, AB_INDX);
outl(axindc, AB_DATA);
outl(space << 29 | space << 3 | 0x34, AB_INDX);
outl(tmp, AB_DATA);
outl(0, AB_INDX);
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_ax_indx - End.\n");
}
config SOUTHBRIDGE_AMD_CIMX_SB900
bool
+ default n
select IOAPIC
+ select AMD_SB_CIMX
if SOUTHBRIDGE_AMD_CIMX_SB900
config SATA_CONTROLLER_MODE
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
-subdirs-$(CONFIG_AMD_CIMX_SB900) += ../../../../../src/vendorcode/amd/cimx/sb900
+subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += ../../../../../src/vendorcode/amd/cimx/sb900
# SB900 Platform Files
+romstage-y += cfg.c
romstage-y += early.c
romstage-y += smbus.c
-ramstage-y += late.c
+ramstage-y += cfg.c
ramstage-y += early.c
+ramstage-y += late.c
driver-y += smbus.c
driver-y += lpc.c
#endif
#define FIXUP_PTR(ptr) ptr
+#include <console/console.h>
#include "AmdSbLib.h"
#include "Amd.h"
#include "Hudson-2.h"
#include "SbDef.h"
#include "AmdSbLib.h"
#include "SbSubFun.h"
-#include "Oem.h"
+#include "platform_cfg.h" /* mainboard specific configuration */
+#include "Oem.h" /* platform default configuration */
#include "AMD.h"
#include "SbBiosRamUsage.h"
#include "EcFan.h"
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#include <string.h>
+#include "SbPlatform.h"
+#include "platform_cfg.h"
+
+
+/**
+ * @brief South Bridge CIMx configuration
+ *
+ * should be called before exeucte CIMx function.
+ * this function will be called in romstage and ramstage.
+ */
+void sb900_cimx_config(AMDSBCFG *sb_config)
+{
+ if (!sb_config) {
+ printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - No sb_config.\n");
+ return;
+ }
+ printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - Start.\n");
+ memset(sb_config, 0, sizeof(AMDSBCFG));
+
+ /* static Build Parameters */
+ sb_config->BuildParameters.BiosSize = BIOS_SIZE;
+ sb_config->BuildParameters.LegacyFree = LEGACY_FREE;
+ sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS; // Board Level
+ sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS; // Board Level
+ sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS; // Board Level
+ sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS; // Board Level
+ sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS; // Board Level
+ sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS; // Board Level
+ sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS; // Board Level
+ sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS; // Board Level
+ sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; // Board Level
+ sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS; // Board Level
+
+ /* Turn on CDROM and HDD Power */
+ sb_config->SATAMODE.SataMode.SataClkMode = SATA_CLK_RESERVED;
+
+ // header
+ sb_config->StdHeader.PcieBasePtr = PCIEX_BASE_ADDRESS;
+
+ // Build Parameters
+ sb_config->BuildParameters.ImcEnableOverWrite = IMC_ENABLE_OVER_WRITE; // Internal Option
+ sb_config->BuildParameters.UsbMsi = USB_MSI; // Internal Option
+ sb_config->BuildParameters.HdAudioMsi = HDAUDIO_MSI; // Internal Option
+ sb_config->BuildParameters.LpcMsi = LPC_MSI; // Internal Option
+ sb_config->BuildParameters.PcibMsi = PCIB_MSI; // Internal Option
+ sb_config->BuildParameters.AbMsi = AB_MSI; // Internal Option
+ sb_config->BuildParameters.GecShadowRomBase = GEC_SHADOWROM_BASE; // Board Level
+ sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS; // Board Level
+ sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID; // Board Level
+ sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID; // Board Level
+ sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID; // Board Level
+ sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID; // Board Level
+ sb_config->BuildParameters.OhciSsid = OHCI_SSID; // Board Level
+ sb_config->BuildParameters.EhciSsid = EHCI_SSID; // Board Level
+ sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID; // Board Level
+ sb_config->BuildParameters.SmbusSsid = SMBUS_SSID; // Board Level
+ sb_config->BuildParameters.IdeSsid = IDE_SSID; // Board Level
+ sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID; // Board Level
+ sb_config->BuildParameters.LpcSsid = LPC_SSID; // Board Level
+ // sb_config->BuildParameters.PCIBSsid = PCIB_SSID; // Field Retired
+
+ //
+ // Common Function
+ //
+ sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER; // External Option
+ sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = SATA_IDE_COMBMD_PRISEC_OPT; // External Option
+ sb_config->SATAMODE.SataMode.SataIdeCombinedMode = SATA_IDECOMBINED_MODE; // External Option
+ sb_config->S3Resume = 0; // CIMx Internal Used
+ sb_config->SpreadSpectrum = INCHIP_SPREAD_SPECTRUM; // Board Level
+ sb_config->NbSbGen2 = INCHIP_NB_SB_GEN2; // External Option
+ sb_config->GppGen2 = INCHIP_GPP_GEN2; // External Option
+ sb_config->GppMemWrImprove = INCHIP_GPP_MEMORY_WRITE_IMPROVE; // Internal Option
+ sb_config->S4Resume = 0; // CIMx Internal Used
+ sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; // INCHIP_SATA_MODE // External Option
+ sb_config->SataIdeMode = INCHIP_IDE_MODE; // External Option
+ sb_config->sdConfig = SB_SD_CONFIG; // External Option
+ sb_config->sdSpeed = SB_SD_SPEED; // Internal Option
+ sb_config->sdBitwidth = SB_SD_BITWIDTH; // Internal Option
+ sb_config->SataDisUnusedIdePChannel = SATA_DISUNUSED_IDE_P_CHANNEL; // External Option
+ sb_config->SataDisUnusedIdeSChannel = SATA_DISUNUSED_IDE_S_CHANNEL; // External Option
+ sb_config->IdeDisUnusedIdePChannel = IDE_DISUNUSED_IDE_P_CHANNEL; // External Option
+ sb_config->IdeDisUnusedIdeSChannel = IDE_DISUNUSED_IDE_S_CHANNEL; // External Option
+ sb_config->SATAESPPORT.SataEspPort.PORT0 = SATA_ESP_PORT0; // Board Level
+ sb_config->SATAESPPORT.SataEspPort.PORT1 = SATA_ESP_PORT1; // Board Level
+ sb_config->SATAESPPORT.SataEspPort.PORT2 = SATA_ESP_PORT2; // Board Level
+ sb_config->SATAESPPORT.SataEspPort.PORT3 = SATA_ESP_PORT3; // Board Level
+ sb_config->SATAESPPORT.SataEspPort.PORT4 = SATA_ESP_PORT4; // Board Level
+ sb_config->SATAESPPORT.SataEspPort.PORT5 = SATA_ESP_PORT5; // Board Level
+ sb_config->SATAESPPORT.SataEspPort.PORT6 = SATA_ESP_PORT6; // Board Level
+ sb_config->SATAESPPORT.SataEspPort.PORT7 = SATA_ESP_PORT7; // Board Level
+ sb_config->SATAPORTPOWER.SataPortPower.PORT0 = SATA_PORT_POWER_PORT0; // Board Level
+ sb_config->SATAPORTPOWER.SataPortPower.PORT1 = SATA_PORT_POWER_PORT1; // Board Level
+ sb_config->SATAPORTPOWER.SataPortPower.PORT2 = SATA_PORT_POWER_PORT2; // Board Level
+ sb_config->SATAPORTPOWER.SataPortPower.PORT3 = SATA_PORT_POWER_PORT3; // Board Level
+ sb_config->SATAPORTPOWER.SataPortPower.PORT4 = SATA_PORT_POWER_PORT4; // Board Level
+ sb_config->SATAPORTPOWER.SataPortPower.PORT5 = SATA_PORT_POWER_PORT5; // Board Level
+ sb_config->SATAPORTPOWER.SataPortPower.PORT6 = SATA_PORT_POWER_PORT6; // Board Level
+ sb_config->SATAPORTPOWER.SataPortPower.PORT7 = SATA_PORT_POWER_PORT7; // Board Level
+ sb_config->SATAPORTMODE.SataPortMd.PORT0 = SATA_PORTMODE_PORT0; // Board Level
+ sb_config->SATAPORTMODE.SataPortMd.PORT1 = SATA_PORTMODE_PORT1; // Board Level
+ sb_config->SATAPORTMODE.SataPortMd.PORT2 = SATA_PORTMODE_PORT2; // Board Level
+ sb_config->SATAPORTMODE.SataPortMd.PORT3 = SATA_PORTMODE_PORT3; // Board Level
+ sb_config->SATAPORTMODE.SataPortMd.PORT4 = SATA_PORTMODE_PORT4; // Board Level
+ sb_config->SATAPORTMODE.SataPortMd.PORT5 = SATA_PORTMODE_PORT5; // Board Level
+ sb_config->SATAPORTMODE.SataPortMd.PORT6 = SATA_PORTMODE_PORT6; // Board Level
+ sb_config->SATAPORTMODE.SataPortMd.PORT7 = SATA_PORTMODE_PORT7; // Board Level
+ sb_config->SataAggrLinkPmCap = INCHIP_SATA_AGGR_LINK_PM_CAP; // Internal Option
+ sb_config->SataPortMultCap = INCHIP_SATA_PORT_MULT_CAP; // Internal Option
+ sb_config->SataClkAutoOff = INCHIP_SATA_CLK_AUTO_OFF; // External Option
+ sb_config->SataPscCap = INCHIP_SATA_PSC_CAP; // External Option
+ sb_config->SataFisBasedSwitching = INCHIP_SATA_FIS_BASE_SW; // External Option
+ sb_config->SataCccSupport = INCHIP_SATA_CCC_SUPPORT; // External Option
+ sb_config->SataSscCap = INCHIP_SATA_SSC_CAP; // External Option
+ sb_config->SataMsiCapability = INCHIP_SATA_MSI_CAP; // Internal Option
+ sb_config->SataForceRaid = INCHIP_SATA_FORCE_RAID5; // Internal Option
+ sb_config->SataTargetSupport8Device = CIMXSB_SATA_TARGET_8DEVICE_CAP; // External Option
+ sb_config->SataDisableGenericMode = SATA_DISABLE_GENERIC_MODE_CAP;// External Option
+ sb_config->SataAhciEnclosureManagement = SATA_AHCI_ENCLOSURE_CAP; // Internal Option
+ sb_config->SataSgpio0 = SATA_GPIO_0_CAP; // External Option
+ sb_config->SataSgpio1 = SATA_GPIO_1_CAP; // External Option
+ sb_config->SataPhyPllShutDown = SATA_PHY_PLL_SHUTDOWN; // External Option
+ sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT0 = SATA_HOTREMOVEL_ENH_PORT0; // Board Level
+ sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT1 = SATA_HOTREMOVEL_ENH_PORT1; // Board Level
+ sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT2 = SATA_HOTREMOVEL_ENH_PORT2; // Board Level
+ sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT3 = SATA_HOTREMOVEL_ENH_PORT3; // Board Level
+ sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT4 = SATA_HOTREMOVEL_ENH_PORT4; // Board Level
+ sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT5 = SATA_HOTREMOVEL_ENH_PORT5; // Board Level
+ sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT6 = SATA_HOTREMOVEL_ENH_PORT6; // Board Level
+ sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT7 = SATA_HOTREMOVEL_ENH_PORT7; // Board Level
+ // USB
+ sb_config->USBMODE.UsbMode.Ohci1 = INCHIP_USB_OHCI1_CINFIG; // External Option
+ sb_config->USBMODE.UsbMode.Ehci1 = INCHIP_USB_EHCI1_CINFIG; // Internal Option*
+ sb_config->USBMODE.UsbMode.Ohci2 = INCHIP_USB_OHCI2_CINFIG; // External Option
+ sb_config->USBMODE.UsbMode.Ehci2 = INCHIP_USB_EHCI2_CINFIG; // Internal Option*
+ sb_config->USBMODE.UsbMode.Ohci3 = INCHIP_USB_OHCI3_CINFIG; // External Option
+ sb_config->USBMODE.UsbMode.Ehci3 = INCHIP_USB_EHCI3_CINFIG; // Internal Option*
+ sb_config->USBMODE.UsbMode.Ohci4 = INCHIP_USB_OHCI4_CINFIG; // External Option
+ // GEC
+ sb_config->GecConfig = INCHIP_GEC_CONTROLLER; // External Option
+ sb_config->IrConfig = SB_IR_CONTROLLER; // External Option
+ sb_config->XhciSwitch = SB_XHCI_SWITCH; // External Option
+ // Azalia
+ sb_config->AzaliaController = INCHIP_AZALIA_CONTROLLER; // External Option
+ sb_config->AzaliaPinCfg = INCHIP_AZALIA_PIN_CONFIG; // Board Level
+ sb_config->FrontPanelDetected = INCHIP_FRONT_PANEL_DETECTED; // Board Level
+ sb_config->AZALIACONFIG.AzaliaSdinPin = AZALIA_PIN_CONFIG; // Board Level
+ sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr = NULL; // Board Level
+ sb_config->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr = NULL; // Board Level
+ sb_config->AnyHT200MhzLink = INCHIP_ANY_HT_200MHZ_LINK; // Internal Option
+ sb_config->HpetTimer = SB_HPET_TIMER; // External Option
+ sb_config->AzaliaSnoop = INCHIP_AZALIA_SNOOP; // Internal Option*
+ // Generic
+ sb_config->NativePcieSupport = INCHIP_NATIVE_PCIE_SUPPOORT; // External Option
+ // USB
+ sb_config->UsbPhyPowerDown = INCHIP_USB_PHY_POWER_DOWN; // External Option
+ sb_config->PcibClkStopOverride = INCHIP_PCIB_CLK_STOP_OVERRIDE;// Internal Option
+ // sb_config->HpetMsiDis = 0; // Field Retired
+ // sb_config->ResetCpuOnSyncFlood = 0; // Field Retired
+ // sb_config->PcibAutoClkCtr = 0; // Field Retired
+ sb_config->OEMPROGTBL.OemProgrammingTablePtr = NULL; // Board Level
+ sb_config->PORTCONFIG[0].PortCfg.PortPresent = SB_GPP_PORT0; // Board Level
+ sb_config->PORTCONFIG[0].PortCfg.PortDetected = 0; // CIMx Internal Used
+ sb_config->PORTCONFIG[0].PortCfg.PortIsGen2 = 0; // CIMx Internal Used
+ sb_config->PORTCONFIG[0].PortCfg.PortHotPlug = 0; // CIMx Internal Used
+ // sb_config->PORTCONFIG[0].PortCfg.PortIntxMap = 0; // Field Retired
+ sb_config->PORTCONFIG[1].PortCfg.PortPresent = SB_GPP_PORT1; // Board Level
+ sb_config->PORTCONFIG[1].PortCfg.PortDetected = 0; // CIMx Internal Used
+ sb_config->PORTCONFIG[1].PortCfg.PortIsGen2 = 0; // CIMx Internal Used
+ sb_config->PORTCONFIG[1].PortCfg.PortHotPlug = 0; // CIMx Internal Used
+ // sb_config->PORTCONFIG[0].PortCfg.PortIntxMap = 0; // Field Retired
+ sb_config->PORTCONFIG[2].PortCfg.PortPresent = SB_GPP_PORT2; // Board Level
+ sb_config->PORTCONFIG[2].PortCfg.PortDetected = 0; // CIMx Internal Used
+ sb_config->PORTCONFIG[2].PortCfg.PortIsGen2 = 0; // CIMx Internal Used
+ sb_config->PORTCONFIG[2].PortCfg.PortHotPlug = 0; // CIMx Internal Used
+ // sb_config->PORTCONFIG[0].PortCfg.PortIntxMap = 0; // Field Retired
+ sb_config->PORTCONFIG[3].PortCfg.PortPresent = SB_GPP_PORT3; // Board Level
+ sb_config->PORTCONFIG[3].PortCfg.PortDetected = 0; // CIMx Internal Used
+ sb_config->PORTCONFIG[3].PortCfg.PortIsGen2 = 0; // CIMx Internal Used
+ sb_config->PORTCONFIG[3].PortCfg.PortHotPlug = 0; // CIMx Internal Used
+ // sb_config->PORTCONFIG[0].PortCfg.PortIntxMap = 0; // Field Retired
+ sb_config->GppLinkConfig = INCHIP_GPP_LINK_CONFIG; // External Option
+ sb_config->GppFoundGfxDev = 0; // CIMx Internal Used
+ sb_config->GppFunctionEnable = SB_GPP_CONTROLLER; // External Option
+ sb_config->GppUnhidePorts = INCHIP_GPP_UNHIDE_PORTS; // Internal Option
+ sb_config->GppPortAspm = INCHIP_GPP_PORT_ASPM; // Internal Option
+ sb_config->GppLaneReversal = INCHIP_GPP_LANEREVERSAL; // External Option
+ sb_config->AlinkPhyPllPowerDown = INCHIP_ALINK_PHY_PLL_POWER_DOWN; // External Option
+ sb_config->GppPhyPllPowerDown = INCHIP_GPP_PHY_PLL_POWER_DOWN;// External Option
+ sb_config->GppDynamicPowerSaving = INCHIP_GPP_DYNAMIC_POWER_SAVING; // External Option
+ sb_config->PcieAER = INCHIP_PCIE_AER; // External Option
+ sb_config->PcieRAS = INCHIP_PCIE_RAS; // External Option
+ sb_config->GppHardwareDowngrade = INCHIP_GPP_HARDWARE_DOWNGRADE;// Internal Option
+ sb_config->GppToggleReset = INCHIP_GPP_TOGGLE_RESET; // External Option
+ sb_config->sdbEnable = 0; // CIMx Internal Used
+ sb_config->TempMMIO = NULL; // CIMx Internal Used
+ // sb_config->GecPhyStatus = INCHIP_GEC_PHY_STATUS; // Field Retired
+ sb_config->SBGecPwr = INCHIP_GEC_POWER_POLICY; // Internal Option
+ sb_config->SBGecDebugBus = INCHIP_GEC_DEBUGBUS; // Internal Option
+ sb_config->SbPcieOrderRule = INCHIP_SB_PCIE_ORDER_RULE; // External Option
+ sb_config->AcDcMsg = INCHIP_ACDC_MSG; // Internal Option
+ sb_config->TimerTickTrack = INCHIP_TIMER_TICK_TRACK; // Internal Option
+ sb_config->ClockInterruptTag = INCHIP_CLOCK_INTERRUPT_TAG; // Internal Option
+ sb_config->OhciTrafficHanding = INCHIP_OHCI_TRAFFIC_HANDING; // Internal Option
+ sb_config->EhciTrafficHanding = INCHIP_EHCI_TRAFFIC_HANDING; // Internal Option
+ sb_config->FusionMsgCMultiCore = INCHIP_FUSION_MSGC_MULTICORE; // Internal Option
+ sb_config->FusionMsgCStage = INCHIP_FUSION_MSGC_STAGE; // Internal Option
+ sb_config->ALinkClkGateOff = INCHIP_ALINK_CLK_GATE_OFF; // External Option
+ sb_config->BLinkClkGateOff = INCHIP_BLINK_CLK_GATE_OFF; // External Option
+ // sb_config->sdb = 0; // Field Retired
+ sb_config->GppGen2Strap = 0; // CIMx Internal Used
+ sb_config->SlowSpeedABlinkClock = INCHIP_SLOW_SPEED_ABLINK_CLOCK; // Internal Option
+ sb_config->DYNAMICGECROM.DynamicGecRomAddress_Ptr = NULL; // Board Level
+ sb_config->AbClockGating = INCHIP_AB_CLOCK_GATING; // External Option
+ sb_config->GppClockGating = INCHIP_GPP_CLOCK_GATING; // External Option
+ sb_config->L1TimerOverwrite = INCHIP_L1_TIMER_OVERWRITE; // Internal Option
+ // sb_config->UmiLinkWidth = 0; // Field Retired
+ sb_config->UmiDynamicSpeedChange = INCHIP_UMI_DYNAMIC_SPEED_CHANGE; // Internal Option
+ // sb_config->PcieRefClockOverclocking = 0; // Field Retired
+ sb_config->SbAlinkGppTxDriverStrength = INCHIP_ALINK_GPP_TX_DRV_STRENGTH; // Internal Option
+ sb_config->PwrFailShadow = 0x02; // Board Level
+ sb_config->StressResetMode = INCHIP_STRESS_RESET_MODE; // Internal Option
+ sb_config->hwm.fanSampleFreqDiv = 0x03; // Board Level
+ sb_config->hwm.hwmSbtsiAutoPoll = 1; // Board Level
+
+ /* General */
+ sb_config->PciClks = SB_PCI_CLOCK_RESERVED;
+ sb_config->hwm.hwmEnable = 0x0;
+
+#ifndef __PRE_RAM__
+ /* ramstage cimx config here */
+ if (!sb_config->StdHeader.CALLBACK.CalloutPtr) {
+ sb_config->StdHeader.CALLBACK.CalloutPtr = sb900_callout_entry;
+ }
+
+ //sb_config->
+#endif //!__PRE_RAM__
+ printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - End.\n");
+}
+
+void SbPowerOnInit_Config(AMDSBCFG *sb_config)
+{
+ if (!sb_config) {
+ printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - No sb_config.\n");
+ return;
+ }
+ printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - Start.\n");
+ memset(sb_config, 0, sizeof(AMDSBCFG));
+
+ // Set the build parameters
+ sb_config->BuildParameters.BiosSize = BIOS_SIZE; // Field Retired
+ sb_config->BuildParameters.LegacyFree = SBCIMx_LEGACY_FREE; // Board Level
+ sb_config->BuildParameters.SpiSpeed = SBCIMX_SPI_SPEED; // Internal Option
+ sb_config->BuildParameters.SpiFastSpeed = SBCIMX_SPI_FASTSPEED; // Internal Option
+ // sb_config->BuildParameters.SpiWriteSpeed = 0; // Field Retired
+ sb_config->BuildParameters.SpiMode = SBCIMX_SPI_MODE; // Internal Option
+ sb_config->BuildParameters.SpiBurstWrite = SBCIMX_SPI_BURST_WRITE; // Internla Option
+ sb_config->BuildParameters.EcKbd = INCHIP_EC_KBD; // Board Level
+ sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; // Board Level
+ sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS; // Board Level
+ sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS; // Board Level
+ sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS; // Board Level
+ sb_config->BuildParameters.GecShadowRomBase = GEC_ROM_SHADOW_ADDRESS; // Board Level
+ sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS; // Board Level
+ sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS; // Board Level
+ sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS; // Board Level
+ sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS; // Board Level
+ sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS; // Board Level
+ sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS; // Board Level
+ sb_config->BuildParameters.SmiCmdPortAddr = SMI_CMD_PORT; // Board Level
+ sb_config->BuildParameters.AcpiPmaCntBlkAddr = ACPI_PMA_CNT_BLK_ADDRESS; // Board Level
+ sb_config->SATAMODE.SataMode.SataController = INCHIP_SATA_CONTROLLER; // External Option
+ sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = SATA_COMBINE_MODE_CHANNEL;// External Option
+ sb_config->SATAMODE.SataMode.SataSetMaxGen2 = SATA_MAX_GEN2_MODE; // External Option
+ sb_config->SATAMODE.SataMode.SataIdeCombinedMode= SATA_COMBINE_MODE; // External Option
+ sb_config->SATAMODE.SataMode.SataClkMode = SATA_CLK_RESERVED; // Internal Option
+ sb_config->NbSbGen2 = NB_SB_GEN2; // External Option
+ sb_config->SataInternal100Spread = INCHIP_SATA_INTERNAL_100_SPREAD; // External Option
+ sb_config->OEMPROGTBL.OemProgrammingTablePtr = NULL; // Board Level
+ sb_config->sdbEnable = 0; // CIMx Internal Used
+ sb_config->Cg2Pll = INCHIP_CG2_PLL; // Internal Option
+
+ printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - End.\n");
+}
+
+
#include <arch/romcc_io.h> /* device_t */
#include "SbPlatform.h"
#include "SbEarly.h"
-#include "cfg.h" /*sb900_cimx_config*/
#include <console/console.h>
#include <console/loglevel.h>
#include "smbus.h"
#include <console/console.h> /* printk */
#include "lpc.h" /* lpc_read_resources */
#include "SbPlatform.h" /* Platfrom Specific Definitions */
-#include "cfg.h" /* sb900 Cimx configuration */
#include "chip.h" /* struct southbridge_amd_cimx_sb900_config */
void WriteIo8(IN unsigned short Address, IN unsigned char Data);
void WriteIo16(IN unsigned short Address, IN unsigned short Data);
void WriteIo32(IN unsigned short Address, IN unsigned int Data);
-void CpuidRead(IN unsigned int CpuidFcnAddress, OUT CPUID_DATA *Value);
+//void CpuidRead(IN unsigned int CpuidFcnAddress, OUT CPUID_DATA *Value);
+void CpuidRead(unsigned int CpuidFcnAddress, CPUID_DATA *Value);
unsigned char ReadNumberOfCpuCores(void);
*
*/
-#define BIOS_SIZE 0x04 //04 - 1MB
+#ifndef BIOS_SIZE
+ #define BIOS_SIZE 0x04 //04 - 1MB
+#endif
#define LEGACY_FREE 0x00
//#define ACPI_SLEEP_TRAP 0x01
//#define SPREAD_SPECTRUM_EPROM_LOAD 0x01
;
;*********************************************************************************/
-#define BIOS_SIZE 0x04 //04 - 1MB
+#ifndef BIOS_SIZE
+ #define BIOS_SIZE 0x04 //04 - 1MB
+#endif
#define LEGACY_FREE 0x00
#define ACPI_SLEEP_TRAP 0x01
//#define SPREAD_SPECTRUM_EPROM_LOAD 0x01
projects / coreboot.git / commitdiff