The rev 4099 broke ECC boards, they need to have tidy the ECC tags. Myles reverted...

I think we can return the 4099 back under HAVE_ACPI_RESUME define to make everyone happy (and booting ;).

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4252 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/cpu/amd/car/clear_init_ram.c b/src/cpu/amd/car/clear_init_ram.c
index ff05f0d439387c03baa796a65a7bb8eb7126e803..8b97129ec6ccc6bd717f8435b4880cd996283c34 100644 (file)
--- a/src/cpu/amd/car/clear_init_ram.c
+++ b/src/cpu/amd/car/clear_init_ram.c
@@ -6,8 +6,13 @@ static void __attribute__((noinline)) clear_init_ram(void)
        // gcc 3.4.5 will inline the copy_and_run and clear_init_ram in post_cache_as_ram
        // will reuse %edi as 0 from clear_memory for copy_and_run part, actually it is increased already
        // so noline clear_init_ram
-        clear_memory(0,  ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE));
 
+#if HAVE_ACPI_RESUME == 1
+       /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */
+       clear_memory( _RAMBASE,  (CONFIG_LB_MEM_TOPK << 10) -  _RAMBASE - DCACHE_RAM_SIZE);
+#else
+        clear_memory(0,  ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE));
+#endif
 }
 
 /* be warned, this file will be used by core other than core 0/node 0 or core0/node0 when cpu_reset*/