-/*\r
- * $Header: /home/cvs/BIR/ca-cpu/freebios/src/include/assert.h,v 1.1 2005/07/11 16:03:54 smagnani Exp $\r
- *\r
- * assert.h: Debugging macros\r
- *\r
- * Copyright (C) 2005 Digital Design Corporation\r
- *\r
- * This program is free software; you can redistribute it and/or modify\r
- * it under the terms of the GNU General Public License as published by\r
- * the Free Software Foundation; either version 2 of the License, or\r
- * (at your option) any later version.\r
- *\r
- * This program is distributed in the hope that it will be useful,\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- * GNU General Public License for more details.\r
- *\r
- * You should have received a copy of the GNU General Public License\r
- * along with this program; if not, write to the Free Software\r
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
- *\r
- * $Log: assert.h,v $\r
- * Revision 1.1 2005/07/11 16:03:54 smagnani\r
- * Initial revision.\r
- *\r
- *\r
- */\r
-\r
-#ifndef __ASSERT_H_DEFINED\r
-#define __ASSERT_H_DEFINED\r
-\r
-// ROMCC doesn't support __FILE__ or __LINE__ :^{\r
-\r
-#if DEBUG\r
-#ifdef __ROMCC__\r
-#define ASSERT(x) { if (!(x)) die("ASSERT failure!\r\n"); }\r
-#else\r
-#define ASSERT(x) { \\r
- if (!(x)) \\r
- { \\r
- printk_emerg("ASSERT failure: file '%s', line %d\n", __FILE__, __LINE__); \\r
- die(""); \\r
- } \\r
- }\r
-#endif // __ROMCC__\r
-#else // !DEBUG\r
-#define ASSERT(x) { }\r
-#endif\r
-\r
-#ifdef __ROMCC__\r
-#define BUG() { die("BUG encountered: system halted\r\n"); }\r
-#else\r
-#define BUG() { \\r
- printk_emerg("BUG: file '%s', line %d\n", __FILE__, __LINE__); \\r
- die(""); \\r
- }\r
-#endif\r
- \r
-#endif // __ASSERT_H_DEFINED\r
+/*
+ * assert.h: Debugging macros
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __ASSERT_H_DEFINED
+#define __ASSERT_H_DEFINED
+
+// ROMCC doesn't support __FILE__ or __LINE__ :^{
+
+#if DEBUG
+#ifdef __ROMCC__
+#define ASSERT(x) { if (!(x)) die("ASSERT failure!\r\n"); }
+#else
+#define ASSERT(x) { \
+ if (!(x)) \
+ { \
+ printk_emerg("ASSERT failure: file '%s', line %d\n", __FILE__, __LINE__); \
+ die(""); \
+ } \
+ }
+#endif // __ROMCC__
+#else // !DEBUG
+#define ASSERT(x) { }
+#endif
+
+#ifdef __ROMCC__
+#define BUG() { die("BUG encountered: system halted\r\n"); }
+#else
+#define BUG() { \
+ printk_emerg("BUG: file '%s', line %d\n", __FILE__, __LINE__); \
+ die(""); \
+ }
+#endif
+
+#endif // __ASSERT_H_DEFINED
-/*\r
- * $Header: /home/cvs/BIR/ca-cpu/freebios/src/include/sdram_mode.h,v 1.1 2005/07/11 16:03:54 smagnani Exp $\r
- *\r
- * sdram_mode.h: Definitions for SDRAM Mode Register and Extended Mode Register\r
- * \r
- *\r
- * Copyright (C) 2005 Digital Design Corporation\r
- *\r
- * This program is free software; you can redistribute it and/or modify\r
- * it under the terms of the GNU General Public License as published by\r
- * the Free Software Foundation; either version 2 of the License, or\r
- * (at your option) any later version.\r
- *\r
- * This program is distributed in the hope that it will be useful,\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- * GNU General Public License for more details.\r
- *\r
- * You should have received a copy of the GNU General Public License\r
- * along with this program; if not, write to the Free Software\r
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
- *\r
- * $Log: sdram_mode.h,v $\r
- * Revision 1.1 2005/07/11 16:03:54 smagnani\r
- * Initial revision.\r
- *\r
- *\r
- */\r
-\r
-#ifndef __SDRAMMODE_H_DEFINED\r
-#define __SDRAMMODE_H_DEFINED\r
-\r
-// SDRAM Mode Register definitions, per JESD79D\r
-// These are transmitted via A0-A13\r
-\r
-// Burst length\r
-#define SDRAM_BURST_2 (1<<0)\r
-#define SDRAM_BURST_4 (2<<0)\r
-#define SDRAM_BURST_8 (3<<0)\r
-\r
-#define SDRAM_BURST_SEQUENTIAL (0<<3)\r
-#define SDRAM_BURST_INTERLEAVED (1<<3)\r
-\r
-#define SDRAM_CAS_2_0 (2<<4)\r
-#define SDRAM_CAS_3_0 (3<<4) /* Optional for DDR 200-333 */\r
-#define SDRAM_CAS_1_5 (5<<4) /* Optional */\r
-#define SDRAM_CAS_2_5 (6<<4)\r
-#define SDRAM_CAS_MASK (7<<4)\r
-\r
-#define SDRAM_MODE_NORMAL (0 << 7)\r
-#define SDRAM_MODE_TEST (1 << 7)\r
-#define SDRAM_MODE_DLL_RESET (2 << 7)\r
-\r
-// Extended Mode Register\r
-\r
-#define SDRAM_EXTMODE_DLL_ENABLE (0 << 0)\r
-#define SDRAM_EXTMODE_DLL_DISABLE (1 << 0)\r
-\r
-#define SDRAM_EXTMODE_DRIVE_NORMAL (0 << 1)\r
-#define SDRAM_EXTMODE_DRIVE_WEAK (1 << 1) /* Optional */\r
-\r
-#endif // __SDRAMMODE_H_DEFINED\r
+/*
+ * sdram_mode.h: Definitions for SDRAM Mode Register and Extended Mode Register
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __SDRAMMODE_H_DEFINED
+#define __SDRAMMODE_H_DEFINED
+
+// SDRAM Mode Register definitions, per JESD79D
+// These are transmitted via A0-A13
+
+// Burst length
+#define SDRAM_BURST_2 (1<<0)
+#define SDRAM_BURST_4 (2<<0)
+#define SDRAM_BURST_8 (3<<0)
+
+#define SDRAM_BURST_SEQUENTIAL (0<<3)
+#define SDRAM_BURST_INTERLEAVED (1<<3)
+
+#define SDRAM_CAS_2_0 (2<<4)
+#define SDRAM_CAS_3_0 (3<<4) /* Optional for DDR 200-333 */
+#define SDRAM_CAS_1_5 (5<<4) /* Optional */
+#define SDRAM_CAS_2_5 (6<<4)
+#define SDRAM_CAS_MASK (7<<4)
+
+#define SDRAM_MODE_NORMAL (0 << 7)
+#define SDRAM_MODE_TEST (1 << 7)
+#define SDRAM_MODE_DLL_RESET (2 << 7)
+
+// Extended Mode Register
+
+#define SDRAM_EXTMODE_DLL_ENABLE (0 << 0)
+#define SDRAM_EXTMODE_DLL_DISABLE (1 << 0)
+
+#define SDRAM_EXTMODE_DRIVE_NORMAL (0 << 1)
+#define SDRAM_EXTMODE_DRIVE_WEAK (1 << 1) /* Optional */
+
+#endif // __SDRAMMODE_H_DEFINED
-/*\r
- * $Header: /home/cvs/BIR/ca-cpu/freebios/src/include/spd.h,v 1.1 2005/07/11 16:03:54 smagnani Exp $\r
- *\r
- * spd.h: Definitions for Serial Presence Detect (SPD) data\r
- * stored on SDRAM modules\r
- *\r
- * Copyright (C) 2005 Digital Design Corporation\r
- *\r
- * This program is free software; you can redistribute it and/or modify\r
- * it under the terms of the GNU General Public License as published by\r
- * the Free Software Foundation; either version 2 of the License, or\r
- * (at your option) any later version.\r
- *\r
- * This program is distributed in the hope that it will be useful,\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- * GNU General Public License for more details.\r
- *\r
- * You should have received a copy of the GNU General Public License\r
- * along with this program; if not, write to the Free Software\r
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
- *\r
- * $Log: spd.h,v $\r
- * Revision 1.1 2005/07/11 16:03:54 smagnani\r
- * Initial revision.\r
- *\r
- *\r
- */\r
-\r
-#ifndef __SPD_H_DEFINED\r
-#define __SPD_H_DEFINED\r
-\r
-// Byte numbers\r
-#define SPD_MEMORY_TYPE 2\r
-#define SPD_NUM_ROWS 3\r
-#define SPD_NUM_COLUMNS 4\r
-#define SPD_NUM_DIMM_BANKS 5\r
-#define SPD_MODULE_DATA_WIDTH_LSB 6\r
-#define SPD_MODULE_DATA_WIDTH_MSB 7\r
-#define SPD_MODULE_VOLTAGE 8\r
-#define SPD_MIN_CYCLE_TIME_AT_CAS_MAX 9\r
-#define SPD_DIMM_CONFIG_TYPE 11\r
-#define SPD_REFRESH 12\r
-#define SPD_PRIMARY_DRAM_WIDTH 13\r
-#define SPD_SUPPORTED_BURST_LENGTHS 16\r
-#define SPD_NUM_BANKS_PER_DRAM 17\r
-#define SPD_ACCEPTABLE_CAS_LATENCIES 18\r
-#define SPD_MODULE_ATTRIBUTES 21\r
-#define SPD_MIN_CYCLE_TIME_AT_CAS_REDUCED_05 23\r
-#define SPD_MIN_CYCLE_TIME_AT_CAS_REDUCED_10 25\r
-#define SPD_MIN_ROW_PRECHARGE_TIME 27\r
-#define SPD_MIN_RAS_TO_CAS_DELAY 29\r
-#define SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY 30\r
-#define SPD_ADDRESS_CMD_HOLD 33\r
-\r
-\r
-// SPD_MEMORY_TYPE values\r
-#define MEMORY_TYPE_SDRAM_DDR 7\r
-\r
-// SPD_MODULE_VOLTAGE values\r
-#define SPD_VOLTAGE_SSTL2 4\r
-\r
-// SPD_DIMM_CONFIG_TYPE values\r
-#define ERROR_SCHEME_NONE 0\r
-#define ERROR_SCHEME_PARITY 1\r
-#define ERROR_SCHEME_ECC 2\r
-\r
-// SPD_ACCEPTABLE_CAS_LATENCIES values\r
-#define SPD_CAS_LATENCY_1_0 0x01\r
-#define SPD_CAS_LATENCY_1_5 0x02\r
-#define SPD_CAS_LATENCY_2_0 0x04\r
-#define SPD_CAS_LATENCY_2_5 0x08\r
-#define SPD_CAS_LATENCY_3_0 0x10\r
-#define SPD_CAS_LATENCY_3_5 0x20\r
-#define SPD_CAS_LATENCY_4_0 0x40\r
-\r
-// SPD_SUPPORTED_BURST_LENGTHS values\r
-#define SPD_BURST_LENGTH_1 1\r
-#define SPD_BURST_LENGTH_2 2\r
-#define SPD_BURST_LENGTH_4 4\r
-#define SPD_BURST_LENGTH_8 8\r
-#define SPD_BURST_LENGTH_PAGE (1<<7)\r
-\r
-\r
-// SPD_MODULE_ATTRIBUTES values\r
-#define MODULE_BUFFERED 1\r
-#define MODULE_REGISTERED 2\r
-\r
-#endif // __SPD_H_DEFINED\r
+/*
+ * spd.h: Definitions for Serial Presence Detect (SPD) data
+ * stored on SDRAM modules
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __SPD_H_DEFINED
+#define __SPD_H_DEFINED
+
+// Byte numbers
+#define SPD_MEMORY_TYPE 2
+#define SPD_NUM_ROWS 3
+#define SPD_NUM_COLUMNS 4
+#define SPD_NUM_DIMM_BANKS 5
+#define SPD_MODULE_DATA_WIDTH_LSB 6
+#define SPD_MODULE_DATA_WIDTH_MSB 7
+#define SPD_MODULE_VOLTAGE 8
+#define SPD_MIN_CYCLE_TIME_AT_CAS_MAX 9
+#define SPD_DIMM_CONFIG_TYPE 11
+#define SPD_REFRESH 12
+#define SPD_PRIMARY_DRAM_WIDTH 13
+#define SPD_SUPPORTED_BURST_LENGTHS 16
+#define SPD_NUM_BANKS_PER_DRAM 17
+#define SPD_ACCEPTABLE_CAS_LATENCIES 18
+#define SPD_MODULE_ATTRIBUTES 21
+#define SPD_MIN_CYCLE_TIME_AT_CAS_REDUCED_05 23
+#define SPD_MIN_CYCLE_TIME_AT_CAS_REDUCED_10 25
+#define SPD_MIN_ROW_PRECHARGE_TIME 27
+#define SPD_MIN_RAS_TO_CAS_DELAY 29
+#define SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY 30
+#define SPD_ADDRESS_CMD_HOLD 33
+
+
+// SPD_MEMORY_TYPE values
+#define MEMORY_TYPE_SDRAM_DDR 7
+
+// SPD_MODULE_VOLTAGE values
+#define SPD_VOLTAGE_SSTL2 4
+
+// SPD_DIMM_CONFIG_TYPE values
+#define ERROR_SCHEME_NONE 0
+#define ERROR_SCHEME_PARITY 1
+#define ERROR_SCHEME_ECC 2
+
+// SPD_ACCEPTABLE_CAS_LATENCIES values
+#define SPD_CAS_LATENCY_1_0 0x01
+#define SPD_CAS_LATENCY_1_5 0x02
+#define SPD_CAS_LATENCY_2_0 0x04
+#define SPD_CAS_LATENCY_2_5 0x08
+#define SPD_CAS_LATENCY_3_0 0x10
+#define SPD_CAS_LATENCY_3_5 0x20
+#define SPD_CAS_LATENCY_4_0 0x40
+
+// SPD_SUPPORTED_BURST_LENGTHS values
+#define SPD_BURST_LENGTH_1 1
+#define SPD_BURST_LENGTH_2 2
+#define SPD_BURST_LENGTH_4 4
+#define SPD_BURST_LENGTH_8 8
+#define SPD_BURST_LENGTH_PAGE (1<<7)
+
+
+// SPD_MODULE_ATTRIBUTES values
+#define MODULE_BUFFERED 1
+#define MODULE_REGISTERED 2
+
+#endif // __SPD_H_DEFINED
/*
- * $Header$
- *
* e7501.h: PCI configuration space for the Intel E7501 memory controller
*
* Copyright (C) 2005 Digital Design Corporation
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- *
- * $Log$
- *
*/
-//kind of cmos_err for ich3\r
-\r
-#include "i82801ca.h"\r
+//kind of cmos_err for ich3
+
+#include "i82801ca.h"
static void check_cmos_failed(void)
-{\r
+{
#if HAVE_OPTION_TABLE
- uint8_t byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3);\r
+ uint8_t byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3);
if( byte & RTC_BATTERY_DEAD) {
- // Set boot_option and last_boot to 'Fallback',\r
+ // Set boot_option and last_boot to 'Fallback',
// clear reboot_bits
byte = cmos_read(RTC_BOOT_BYTE);
byte &= 0x0c;
byte |= MAX_REBOOT_CNT << 4;
cmos_write(byte, RTC_BOOT_BYTE);
- }\r
+ }
#endif
}
void i82801ca_enable(device_t dev)
{
- unsigned int index = 0;\r
- uint8_t bHasDisableBit = 0;\r
+ unsigned int index = 0;
+ uint8_t bHasDisableBit = 0;
uint16_t cur_disable_mask, new_disable_mask;
// all 82801ca devices are in bus 0
// Calculate disable bit position for specified device:function
// NOTE: For ICH-3, only the following devices can be disabled:
- // D31:F1, D31:F3, D31:F5, D31:F6, \r
- // D29:F0, D29:F1, D29:F2\r
+ // D31:F1, D31:F3, D31:F5, D31:F6,
+ // D29:F0, D29:F1, D29:F2
if (PCI_SLOT(dev->path.u.pci.devfn) == 31) {
- index = PCI_FUNC(dev->path.u.pci.devfn);\r
-\r
- if ((index == 1) || (index == 3) || (index == 5) || (index == 6))\r
- bHasDisableBit = 1;\r
+ index = PCI_FUNC(dev->path.u.pci.devfn);
+
+ if ((index == 1) || (index == 3) || (index == 5) || (index == 6))
+ bHasDisableBit = 1;
} else if (PCI_SLOT(dev->path.u.pci.devfn) == 29) {
- index = 8 + PCI_FUNC(dev->path.u.pci.devfn);\r
-\r
- if (PCI_FUNC(dev->path.u.pci.devfn) < 3)\r
+ index = 8 + PCI_FUNC(dev->path.u.pci.devfn);
+
+ if (PCI_FUNC(dev->path.u.pci.devfn) < 3)
bHasDisableBit = 1;
}
-\r
+
if (bHasDisableBit) {
cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS);
new_disable_mask = cur_disable_mask & ~(1<<index); // enable it
}
if (new_disable_mask != cur_disable_mask) {
pci_write_config16(lpc_dev, FUNC_DIS, new_disable_mask);
- }\r
+ }
}
}
#ifndef I82801CA_H
#define I82801CA_H
-\r
-#ifndef __ROMCC__\r
+
+#ifndef __ROMCC__
#include "chip.h"
-extern void i82801ca_enable(device_t dev);\r
-#endif\r
+extern void i82801ca_enable(device_t dev);
+#endif
#define PCI_DMA_CFG 0x90
#define FUNC_DIS 0xF2
// GEN_PMCON_3 bits
-#define RTC_BATTERY_DEAD (1<<2)\r
-#define RTC_POWER_FAILED (1<<1)\r
+#define RTC_BATTERY_DEAD (1<<2)
+#define RTC_POWER_FAILED (1<<1)
#define SLEEP_AFTER_POWER_FAIL (1<<0)
-\r
-/********************************************************************/\r
-/* IDE Controller */\r
-/********************************************************************/\r
-\r
-// PCI Configuration Space (D31:F1)\r
-#define IDE_TIM_PRI 0x40 // IDE timings, primary\r
-#define IDE_TIM_SEC 0x42 // IDE timings, secondary\r
-\r
-\r
-// IDE_TIM bits\r
-#define IDE_DECODE_ENABLE (1<<15)\r
-\r
-/********************************************************************/\r
-/* SMBus */\r
-/********************************************************************/\r
-\r
-// PCI Configuration Space (D31:F3)\r
+
+/********************************************************************/
+/* IDE Controller */
+/********************************************************************/
+
+// PCI Configuration Space (D31:F1)
+#define IDE_TIM_PRI 0x40 // IDE timings, primary
+#define IDE_TIM_SEC 0x42 // IDE timings, secondary
+
+
+// IDE_TIM bits
+#define IDE_DECODE_ENABLE (1<<15)
+
+/********************************************************************/
+/* SMBus */
+/********************************************************************/
+
+// PCI Configuration Space (D31:F3)
#define SMB_BASE 0x20
-#define HOSTC 0x40\r
-\r
-// HOSTC bits\r
-#define I2C_EN (1<<2)\r
-#define SMB_SMI_EN (1<<1)\r
-#define HST_EN (1<<0)\r
+#define HOSTC 0x40
+
+// HOSTC bits
+#define I2C_EN (1<<2)
+#define SMB_SMI_EN (1<<1)
+#define HST_EN (1<<0)
#define SMBUS_IO_BASE 0x1000
-\r
+
// I/O registers (relative to SMBUS_IO_BASE)
#define SMBHSTSTAT 0
#define SMBHSTCTL 2
#define SMBSLVDATA 10
#define SMLINK_PIN_CTL 14
#define SMBUS_PIN_CTL 15
-\r
+
/* Between 1-10 seconds, We should never timeout normally
* Longer than this is just painful when a timeout condition occurs.
*/
#include <device/pci_ids.h>
-#include "i82801ca.h"\r
+#include "i82801ca.h"
static void enable_smbus(void)
{
{
/* Enable ide devices so the linux ide driver will work */
uint16_t ideTimingConfig;
- int enable_primary = 1;\r
+ int enable_primary = 1;
int enable_secondary = 1;
ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI);
/*
* (C) 2003 Linux Networx, SuSE Linux AG
* (C) 2004 Tyan Computer
- * (c) 2005 Digital Design Corporation\r
+ * (c) 2005 Digital Design Corporation
*/
#include <console/console.h>
#include <device/device.h>
#include "i82801ca.h"
#define NMI_OFF 0
-\r
-#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL\r
-#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON\r
-#endif\r
-\r
-#define MAINBOARD_POWER_OFF 0\r
-#define MAINBOARD_POWER_ON 1\r
-\r
+
+#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
+#endif
+
+#define MAINBOARD_POWER_OFF 0
+#define MAINBOARD_POWER_ON 1
+
void i82801ca_enable_ioapic( struct device *dev)
{
pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0));
}
-//----------------------------------------------------------------------------------\r
-// Function: i82801ca_lpc_route_dma\r
+//----------------------------------------------------------------------------------
+// Function: i82801ca_lpc_route_dma
// Parameters: dev
// mask - identifies whether each channel should be used for PCI DMA
// (bit = 0) or LPC DMA (bit = 1). The LSb controls channel 0.
-// Channel 4 is not used (reserved). \r
-// Return Value: None\r
-// Description: Route all DMA channels to either PCI or LPC.\r
-//\r
+// Channel 4 is not used (reserved).
+// Return Value: None
+// Description: Route all DMA channels to either PCI or LPC.
+//
void i82801ca_lpc_route_dma( struct device *dev, uint8_t mask)
{
uint16_t dmaConfig;
int channelIndex;
-\r
+
dmaConfig = pci_read_config16(dev, PCI_DMA_CFG);
dmaConfig &= 0x300; // Preserve reserved bits
for(channelIndex = 0; channelIndex < 8; channelIndex++) {
void i82801ca_rtc_init(struct device *dev)
{
uint32_t dword;
- int rtc_failed;\r
- int pwr_on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;\r
- uint8_t pmcon3 = pci_read_config8(dev, GEN_PMCON_3);\r
+ int rtc_failed;
+ int pwr_on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ uint8_t pmcon3 = pci_read_config8(dev, GEN_PMCON_3);
rtc_failed = pmcon3 & RTC_BATTERY_DEAD;
if (rtc_failed) {
// Clear the RTC_BATTERY_DEAD bit, but preserve
- // the RTC_POWER_FAILED, G3 state, and reserved bits\r
+ // the RTC_POWER_FAILED, G3 state, and reserved bits
// NOTE: RTC_BATTERY_DEAD and RTC_POWER_FAILED are "write-1-clear" bits
pmcon3 &= ~RTC_POWER_FAILED;
- }\r
-\r
- get_option(&pwr_on, "power_on_after_fail");\r
- pmcon3 &= ~SLEEP_AFTER_POWER_FAIL;\r
- if (!pwr_on) {\r
- pmcon3 |= SLEEP_AFTER_POWER_FAIL;\r
- }\r
- pci_write_config8(dev, GEN_PMCON_3, pmcon3);\r
- printk_info("set power %s after power fail\n", \r
- pwr_on ? "on" : "off");\r
+ }
+
+ get_option(&pwr_on, "power_on_after_fail");
+ pmcon3 &= ~SLEEP_AFTER_POWER_FAIL;
+ if (!pwr_on) {
+ pmcon3 |= SLEEP_AFTER_POWER_FAIL;
+ }
+ pci_write_config8(dev, GEN_PMCON_3, pmcon3);
+ printk_info("set power %s after power fail\n",
+ pwr_on ? "on" : "off");
// See if the Safe Mode jumper is set
dword = pci_read_config32(dev, GEN_STS);
// Enable access to the upper 128 byte bank of CMOS RAM
pci_write_config8(dev, RTC_CONF, 0x04);
- // Decode 0x3F8-0x3FF (COM1) for COMA port,\r
+ // Decode 0x3F8-0x3FF (COM1) for COMA port,
// 0x2F8-0x2FF (COM2) for COMB
pci_write_config8(dev, COM_DEC, 0x10);
-\r
- // LPT decode defaults to 0x378-0x37F and 0x778-0x77F\r
- // Floppy decode defaults to 0x3F0-0x3F5, 0x3F7\r
- // Enable COMA, COMB, LPT, floppy; \r
+ // LPT decode defaults to 0x378-0x37F and 0x778-0x77F
+ // Floppy decode defaults to 0x3F0-0x3F5, 0x3F7
+
+ // Enable COMA, COMB, LPT, floppy;
// disable microcontroller, Super I/O, sound, gameport
pci_write_config16(dev, LPC_EN, 0x000F);
}
pci_write_config8(dev, GEN_PMCON_3, byte);
printk_info("set power %s after power fail\n", pwr_on?"on":"off");
- /* Set up NMI on errors */\r
- byte = inb(0x61);\r
- byte &= ~(1 << 3); /* IOCHK# NMI Enable */\r
- byte &= ~(1 << 2); /* PCI SERR# Enable */\r
- outb(byte, 0x61);\r
- byte = inb(0x70);\r
- nmi_option = NMI_OFF;\r
- get_option(&nmi_option, "nmi");\r
- if (nmi_option) { \r
- byte &= ~(1 << 7); /* set NMI */\r
- outb(byte, 0x70);\r
- }\r
+ /* Set up NMI on errors */
+ byte = inb(0x61);
+ byte &= ~(1 << 3); /* IOCHK# NMI Enable */
+ byte &= ~(1 << 2); /* PCI SERR# Enable */
+ outb(byte, 0x61);
+ byte = inb(0x70);
+ nmi_option = NMI_OFF;
+ get_option(&nmi_option, "nmi");
+ if (nmi_option) {
+ byte &= ~(1 << 7); /* set NMI */
+ outb(byte, 0x70);
+ }
/* Initialize the real time clock */
i82801ca_rtc_init(dev);
#include <smbus.h>
#include <pci.h>
#include <arch/io.h>
-#include "i82801ca.h"\r
+#include "i82801ca.h"
#define PM_BUS 0
#define PM_DEVFN PCI_DEVFN(0x1f,3)
void smbus_enable(void)
{
/* iobase addr */
- pcibios_write_config_dword(PM_BUS, PM_DEVFN, SMB_BASE, \r
+ pcibios_write_config_dword(PM_BUS, PM_DEVFN, SMB_BASE,
SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
/* smbus enable */
pcibios_write_config_byte(PM_BUS, PM_DEVFN, HOSTC, HST_EN);
-/*\r
- * $Header$\r
- *\r
- * lpc47b272_early_serial.c: Pre-RAM driver for SMSC LPC47B272 Super I/O chip\r
- *\r
- * Copyright (C) 2005 Digital Design Corporation\r
- *\r
- * This program is free software; you can redistribute it and/or modify\r
- * it under the terms of the GNU General Public License as published by\r
- * the Free Software Foundation; either version 2 of the License, or\r
- * (at your option) any later version.\r
- *\r
- * This program is distributed in the hope that it will be useful,\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- * GNU General Public License for more details.\r
- *\r
- * You should have received a copy of the GNU General Public License\r
- * along with this program; if not, write to the Free Software\r
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
- *\r
- * $Log$\r
- *\r
- */\r
+/*
+ * lpc47b272_early_serial.c: Pre-RAM driver for SMSC LPC47B272 Super I/O chip
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
#include <arch/romcc_io.h>
#include "lpc47b272.h"
-//----------------------------------------------------------------------------------\r
-// Function: pnp_enter_conf_state\r
-// Parameters: dev - high 8 bits = Super I/O port\r
-// Return Value: None\r
-// Description: Enable access to the LPC47B272's configuration registers.\r
-//\r
+//----------------------------------------------------------------------------------
+// Function: pnp_enter_conf_state
+// Parameters: dev - high 8 bits = Super I/O port
+// Return Value: None
+// Description: Enable access to the LPC47B272's configuration registers.
+//
static inline void pnp_enter_conf_state(device_t dev) {
unsigned port = dev>>8;
outb(0x55, port);
-}\r
+}
-//----------------------------------------------------------------------------------\r
-// Function: pnp_exit_conf_state\r
-// Parameters: dev - high 8 bits = Super I/O port\r
-// Return Value: None\r
-// Description: Disable access to the LPC47B272's configuration registers.\r
-//\r
+//----------------------------------------------------------------------------------
+// Function: pnp_exit_conf_state
+// Parameters: dev - high 8 bits = Super I/O port
+// Return Value: None
+// Description: Disable access to the LPC47B272's configuration registers.
+//
static void pnp_exit_conf_state(device_t dev) {
unsigned port = dev>>8;
outb(0xaa, port);
}
-//----------------------------------------------------------------------------------\r
-// Function: lpc47b272_enable_serial\r
-// Parameters: dev - high 8 bits = Super I/O port, \r
-// low 8 bits = logical device number (per lpc47b272.h)\r
-// iobase - processor I/O port address to assign to this serial device\r
-// Return Value: bool\r
-// Description: Configure the base I/O port of the specified serial device\r
-// and enable the serial device.\r
-//\r
+//----------------------------------------------------------------------------------
+// Function: lpc47b272_enable_serial
+// Parameters: dev - high 8 bits = Super I/O port,
+// low 8 bits = logical device number (per lpc47b272.h)
+// iobase - processor I/O port address to assign to this serial device
+// Return Value: bool
+// Description: Configure the base I/O port of the specified serial device
+// and enable the serial device.
+//
static void lpc47b272_enable_serial(device_t dev, unsigned iobase)
{
pnp_enter_conf_state(dev);
-/*\r
- * $Header$\r
- *\r
- * superio.c: RAM driver for SMSC LPC47B272 Super I/O chip\r
- *\r
+/*
+ * superio.c: RAM driver for SMSC LPC47B272 Super I/O chip
+ *
* Copyright 2000 AG Electronics Ltd.
* Copyright 2003-2004 Linux Networx
* Copyright 2004 Tyan
- * Copyright (C) 2005 Digital Design Corporation\r
- *\r
- * This program is free software; you can redistribute it and/or modify\r
- * it under the terms of the GNU General Public License as published by\r
- * the Free Software Foundation; either version 2 of the License, or\r
- * (at your option) any later version.\r
- *\r
- * This program is distributed in the hope that it will be useful,\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- * GNU General Public License for more details.\r
- *\r
- * You should have received a copy of the GNU General Public License\r
- * along with this program; if not, write to the Free Software\r
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
- *\r
- * $Log$\r
- *\r
- */\r
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
#include <arch/io.h>
#include <device/device.h>
#include "chip.h"
#include "lpc47b272.h"
-// Forward declarations\r
-static void enable_dev(device_t dev);\r
+// Forward declarations
+static void enable_dev(device_t dev);
void lpc47b272_pnp_set_resources(device_t dev);
void lpc47b272_pnp_set_resources(device_t dev);
void lpc47b272_pnp_enable_resources(device_t dev);
void lpc47b272_pnp_enable(device_t dev);
static void lpc47b272_init(device_t dev);
-static void pnp_enter_conf_state(device_t dev);\r
-static void pnp_exit_conf_state(device_t dev);\r
+static void pnp_enter_conf_state(device_t dev);
+static void pnp_exit_conf_state(device_t dev);
static void dump_pnp_device(device_t dev);
{ &ops, LPC47B272_RT, PNP_IO0, { 0x780, 0 }, },
};
-/**********************************************************************************/\r
-/* PUBLIC INTERFACE */\r
-/**********************************************************************************/\r
-\r
-//----------------------------------------------------------------------------------\r
-// Function: enable_dev\r
-// Parameters: dev - pointer to structure describing a Super I/O device \r
-// Return Value: None\r
-// Description: Create device structures and allocate resources to devices \r
-// specified in the pnp_dev_info array (above).\r
-//\r
-static void enable_dev(device_t dev)\r
-{\r
- pnp_enable_devices(dev, &pnp_ops, \r
- sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), \r
- pnp_dev_info);\r
-}\r
-
-//----------------------------------------------------------------------------------\r
-// Function: lpc47b272_pnp_set_resources\r
-// Parameters: dev - pointer to structure describing a Super I/O device \r
-// Return Value: None\r
-// Description: Configure the specified Super I/O device with the resources\r
-// (I/O space, etc.) that have been allocated for it.\r
+/**********************************************************************************/
+/* PUBLIC INTERFACE */
+/**********************************************************************************/
+
+//----------------------------------------------------------------------------------
+// Function: enable_dev
+// Parameters: dev - pointer to structure describing a Super I/O device
+// Return Value: None
+// Description: Create device structures and allocate resources to devices
+// specified in the pnp_dev_info array (above).
+//
+static void enable_dev(device_t dev)
+{
+ pnp_enable_devices(dev, &pnp_ops,
+ sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]),
+ pnp_dev_info);
+}
+
+//----------------------------------------------------------------------------------
+// Function: lpc47b272_pnp_set_resources
+// Parameters: dev - pointer to structure describing a Super I/O device
+// Return Value: None
+// Description: Configure the specified Super I/O device with the resources
+// (I/O space, etc.) that have been allocated for it.
//
void lpc47b272_pnp_set_resources(device_t dev)
{
pnp_exit_conf_state(dev);
}
-//----------------------------------------------------------------------------------\r
-// Function: lpc47b272_init\r
-// Parameters: dev - pointer to structure describing a Super I/O device \r
-// Return Value: None\r
-// Description: Initialize the specified Super I/O device.\r
+//----------------------------------------------------------------------------------
+// Function: lpc47b272_init
+// Parameters: dev - pointer to structure describing a Super I/O device
+// Return Value: None
+// Description: Initialize the specified Super I/O device.
// Devices other than COM ports and the keyboard controller are
-// ignored. For COM ports, we configure the baud rate. \r
-//\r
+// ignored. For COM ports, we configure the baud rate.
+//
static void lpc47b272_init(device_t dev)
{
struct superio_smsc_lpc47b272_config *conf = dev->chip_info;
break;
}
}
-\r
-/**********************************************************************************/\r
-/* PRIVATE FUNCTIONS */\r
-/**********************************************************************************/\r
-
-//----------------------------------------------------------------------------------\r
-// Function: pnp_enter_conf_state\r
-// Parameters: dev - pointer to structure describing a Super I/O device \r
-// Return Value: None\r
-// Description: Enable access to the LPC47B272's configuration registers.\r
-//\r
-static void pnp_enter_conf_state(device_t dev) \r
+
+/**********************************************************************************/
+/* PRIVATE FUNCTIONS */
+/**********************************************************************************/
+
+//----------------------------------------------------------------------------------
+// Function: pnp_enter_conf_state
+// Parameters: dev - pointer to structure describing a Super I/O device
+// Return Value: None
+// Description: Enable access to the LPC47B272's configuration registers.
+//
+static void pnp_enter_conf_state(device_t dev)
{
outb(0x55, dev->path.u.pnp.port);
-}\r
-
-//----------------------------------------------------------------------------------\r
-// Function: pnp_exit_conf_state\r
-// Parameters: dev - pointer to structure describing a Super I/O device \r
-// Return Value: None\r
-// Description: Disable access to the LPC47B272's configuration registers.\r
-//\r
-static void pnp_exit_conf_state(device_t dev) \r
+}
+
+//----------------------------------------------------------------------------------
+// Function: pnp_exit_conf_state
+// Parameters: dev - pointer to structure describing a Super I/O device
+// Return Value: None
+// Description: Disable access to the LPC47B272's configuration registers.
+//
+static void pnp_exit_conf_state(device_t dev)
{
outb(0xaa, dev->path.u.pnp.port);
}
#if 0
-//----------------------------------------------------------------------------------\r
-// Function: dump_pnp_device\r
-// Parameters: dev - pointer to structure describing a Super I/O device \r
-// Return Value: None\r
-// Description: Print the values of all of the LPC47B272's configuration registers.\r
-// NOTE: The LPC47B272 must be in configuration mode when this\r
-// function is called.\r
-//\r
+//----------------------------------------------------------------------------------
+// Function: dump_pnp_device
+// Parameters: dev - pointer to structure describing a Super I/O device
+// Return Value: None
+// Description: Print the values of all of the LPC47B272's configuration registers.
+// NOTE: The LPC47B272 must be in configuration mode when this
+// function is called.
+//
static void dump_pnp_device(device_t dev)
{
int register_index;
print_debug("\r\n");
for(register_index = 0; register_index <= LPC47B272_MAX_CONFIG_REGISTER; register_index++) {
- uint8_t register_value;\r
+ uint8_t register_value;
if ((register_index & 0x0f) == 0) {
print_debug_hex8(register_index);
print_debug_char(':');
- }\r
-\r
+ }
+
// Skip over 'register' that would cause exit from configuration mode
if (register_index == 0xaa)
- register_value = 0xaa;\r
+ register_value = 0xaa;
else
- register_value = pnp_read_config(dev, register_index);\r
-\r
+ register_value = pnp_read_config(dev, register_index);
+
print_debug_char(' ');
print_debug_hex8(register_value);
if ((register_index & 0x0f) == 0x0f) {
print_debug("\r\n");
}
- }\r
-\r
- print_debug("\r\n");\r
+ }
+
+ print_debug("\r\n");
}
#endif
-/*\r
- * $Header$\r
- *\r
- * lpc47m10x_early_serial.c: Pre-RAM driver for SMSC LPC47M10X2 Super I/O chip\r
+/*
+ * lpc47m10x_early_serial.c: Pre-RAM driver for SMSC LPC47M10X2 Super I/O chip
* derived from lpc47n217
- *\r
- * Copyright (C) 2005 Digital Design Corporation\r
- *\r
- * This program is free software; you can redistribute it and/or modify\r
- * it under the terms of the GNU General Public License as published by\r
- * the Free Software Foundation; either version 2 of the License, or\r
- * (at your option) any later version.\r
- *\r
- * This program is distributed in the hope that it will be useful,\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- * GNU General Public License for more details.\r
- *\r
- * You should have received a copy of the GNU General Public License\r
- * along with this program; if not, write to the Free Software\r
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
- *\r
- * $Log$\r
- *\r
- */\r
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
#include <arch/romcc_io.h>
#include "lpc47m10x.h"
-//----------------------------------------------------------------------------------\r
-// Function: pnp_enter_conf_state\r
-// Parameters: dev - high 8 bits = Super I/O port\r
-// Return Value: None\r
-// Description: Enable access to the LPC47M10X2's configuration registers.\r
-//\r
+//----------------------------------------------------------------------------------
+// Function: pnp_enter_conf_state
+// Parameters: dev - high 8 bits = Super I/O port
+// Return Value: None
+// Description: Enable access to the LPC47M10X2's configuration registers.
+//
static inline void pnp_enter_conf_state(device_t dev) {
unsigned port = dev>>8;
outb(0x55, port);
-}\r
+}
-//----------------------------------------------------------------------------------\r
-// Function: pnp_exit_conf_state\r
-// Parameters: dev - high 8 bits = Super I/O port\r
-// Return Value: None\r
-// Description: Disable access to the LPC47M10X2's configuration registers.\r
-//\r
+//----------------------------------------------------------------------------------
+// Function: pnp_exit_conf_state
+// Parameters: dev - high 8 bits = Super I/O port
+// Return Value: None
+// Description: Disable access to the LPC47M10X2's configuration registers.
+//
static void pnp_exit_conf_state(device_t dev) {
unsigned port = dev>>8;
outb(0xaa, port);
}
-//----------------------------------------------------------------------------------\r
-// Function: lpc47b272_enable_serial\r
-// Parameters: dev - high 8 bits = Super I/O port, \r
-// low 8 bits = logical device number (per lpc47b272.h)\r
-// iobase - processor I/O port address to assign to this serial device\r
-// Return Value: bool\r
-// Description: Configure the base I/O port of the specified serial device\r
-// and enable the serial device.\r
-//\r
+//----------------------------------------------------------------------------------
+// Function: lpc47b272_enable_serial
+// Parameters: dev - high 8 bits = Super I/O port,
+// low 8 bits = logical device number (per lpc47b272.h)
+// iobase - processor I/O port address to assign to this serial device
+// Return Value: bool
+// Description: Configure the base I/O port of the specified serial device
+// and enable the serial device.
+//
static void lpc47b272_enable_serial(device_t dev, unsigned iobase)
{
pnp_enter_conf_state(dev);
/*
- * $Header$
- *
* superio.c: RAM driver for SMSC LPC47M10X2 Super I/O chip
*
* Copyright 2000 AG Electronics Ltd.
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- *
- * $Log$
- *
*/
#include <arch/io.h>
-/*\r
- * $Header: /home/cvs/BIR/ca-cpu/freebios/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c,v 1.1.1.1 2005/07/11 15:28:51 smagnani Exp $\r
- *\r
- * lpc47n217_early_serial.c: Pre-RAM driver for SMSC LPC47N217 Super I/O chip\r
- *\r
- * Copyright (C) 2005 Digital Design Corporation\r
- *\r
- * This program is free software; you can redistribute it and/or modify\r
- * it under the terms of the GNU General Public License as published by\r
- * the Free Software Foundation; either version 2 of the License, or\r
- * (at your option) any later version.\r
- *\r
- * This program is distributed in the hope that it will be useful,\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- * GNU General Public License for more details.\r
- *\r
- * You should have received a copy of the GNU General Public License\r
- * along with this program; if not, write to the Free Software\r
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
- *\r
- * $Log: lpc47n217_early_serial.c,v $\r
- * Revision 1.1.1.1 2005/07/11 15:28:51 smagnani\r
- * Initial revision.\r
- *\r
- *\r
- */\r
-\r
-#include <arch/romcc_io.h>\r
-#include <assert.h>\r
-#include "lpc47n217.h"\r
-\r
-//----------------------------------------------------------------------------------\r
-// Function: pnp_enter_conf_state\r
-// Parameters: dev - high 8 bits = Super I/O port\r
-// Return Value: None\r
-// Description: Enable access to the LPC47N217's configuration registers.\r
-//\r
-static inline void pnp_enter_conf_state(device_t dev) {\r
- unsigned port = dev>>8;\r
- outb(0x55, port);\r
-}\r
-\r
-//----------------------------------------------------------------------------------\r
-// Function: pnp_exit_conf_state\r
-// Parameters: dev - high 8 bits = Super I/O port\r
-// Return Value: None\r
-// Description: Disable access to the LPC47N217's configuration registers.\r
-//\r
-static void pnp_exit_conf_state(device_t dev) {\r
- unsigned port = dev>>8;\r
- outb(0xaa, port);\r
-}\r
-\r
-//----------------------------------------------------------------------------------\r
-// Function: lpc47n217_pnp_set_iobase\r
-// Parameters: dev - high 8 bits = Super I/O port, \r
-// low 8 bits = logical device number (per lpc47n217.h)\r
-// iobase - base I/O port for the logical device\r
-// Return Value: None\r
-// Description: Program the base I/O port for the specified logical device.\r
-//\r
-void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase)\r
-{\r
- // LPC47N217 requires base ports to be a multiple of 4\r
- ASSERT(!(iobase & 0x3));\r
-\r
- switch(dev & 0xFF) {\r
- case LPC47N217_PP: \r
- pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);\r
- break;\r
- \r
- case LPC47N217_SP1: \r
- pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);\r
- break;\r
- \r
- case LPC47N217_SP2:\r
- pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);\r
- break;\r
- \r
- default:\r
- break;\r
- }\r
-}\r
-\r
-//----------------------------------------------------------------------------------\r
-// Function: lpc47n217_pnp_set_enable\r
-// Parameters: dev - high 8 bits = Super I/O port, \r
-// low 8 bits = logical device number (per lpc47n217.h)\r
-// enable - 0 to disable, anythig else to enable\r
-// Return Value: None\r
-// Description: Enable or disable the specified logical device.\r
-// Technically, a full disable requires setting the device's base\r
-// I/O port below 0x100. We don't do that here, because we don't\r
-// have access to a data structure that specifies what the 'real'\r
-// base port is (when asked to enable the device). Also the function\r
-// is used only to disable the device while its true base port is\r
-// programmed (see lpc47n217_enable_serial() below).\r
-//\r
-void lpc47n217_pnp_set_enable(device_t dev, int enable)\r
-{\r
- uint8_t power_register = 0;\r
- uint8_t power_mask = 0;\r
- uint8_t current_power;\r
- uint8_t new_power;\r
- \r
- switch(dev & 0xFF) {\r
- case LPC47N217_PP: \r
- power_register = 0x01;\r
- power_mask = 0x04;\r
- break;\r
- \r
- case LPC47N217_SP1: \r
- power_register = 0x02;\r
- power_mask = 0x08;\r
- break;\r
- \r
- case LPC47N217_SP2:\r
- power_register = 0x02;\r
- power_mask = 0x80;\r
- break;\r
- \r
- default:\r
- return;\r
- }\r
-\r
- current_power = pnp_read_config(dev, power_register);\r
- new_power = current_power & ~power_mask; // disable by default\r
-\r
- if (enable)\r
- new_power |= power_mask; // Enable\r
-\r
- pnp_write_config(dev, power_register, new_power);\r
-}\r
-\r
-//----------------------------------------------------------------------------------\r
-// Function: lpc47n217_enable_serial\r
-// Parameters: dev - high 8 bits = Super I/O port, \r
-// low 8 bits = logical device number (per lpc47n217.h)\r
-// iobase - processor I/O port address to assign to this serial device\r
-// Return Value: bool\r
-// Description: Configure the base I/O port of the specified serial device\r
-// and enable the serial device.\r
-//\r
-static void lpc47n217_enable_serial(device_t dev, unsigned iobase)\r
-{\r
- // NOTE: Cannot use pnp_set_XXX() here because they assume chip\r
- // support for logical devices, which the LPC47N217 doesn't have\r
- \r
- pnp_enter_conf_state(dev);\r
- lpc47n217_pnp_set_enable(dev, 0);\r
- lpc47n217_pnp_set_iobase(dev, iobase);\r
- lpc47n217_pnp_set_enable(dev, 1);\r
- pnp_exit_conf_state(dev);\r
-}\r
+/*
+ * lpc47n217_early_serial.c: Pre-RAM driver for SMSC LPC47N217 Super I/O chip
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include <assert.h>
+#include "lpc47n217.h"
+
+//----------------------------------------------------------------------------------
+// Function: pnp_enter_conf_state
+// Parameters: dev - high 8 bits = Super I/O port
+// Return Value: None
+// Description: Enable access to the LPC47N217's configuration registers.
+//
+static inline void pnp_enter_conf_state(device_t dev) {
+ unsigned port = dev>>8;
+ outb(0x55, port);
+}
+
+//----------------------------------------------------------------------------------
+// Function: pnp_exit_conf_state
+// Parameters: dev - high 8 bits = Super I/O port
+// Return Value: None
+// Description: Disable access to the LPC47N217's configuration registers.
+//
+static void pnp_exit_conf_state(device_t dev) {
+ unsigned port = dev>>8;
+ outb(0xaa, port);
+}
+
+//----------------------------------------------------------------------------------
+// Function: lpc47n217_pnp_set_iobase
+// Parameters: dev - high 8 bits = Super I/O port,
+// low 8 bits = logical device number (per lpc47n217.h)
+// iobase - base I/O port for the logical device
+// Return Value: None
+// Description: Program the base I/O port for the specified logical device.
+//
+void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase)
+{
+ // LPC47N217 requires base ports to be a multiple of 4
+ ASSERT(!(iobase & 0x3));
+
+ switch(dev & 0xFF) {
+ case LPC47N217_PP:
+ pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
+ break;
+
+ case LPC47N217_SP1:
+ pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
+ break;
+
+ case LPC47N217_SP2:
+ pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
+ break;
+
+ default:
+ break;
+ }
+}
+
+//----------------------------------------------------------------------------------
+// Function: lpc47n217_pnp_set_enable
+// Parameters: dev - high 8 bits = Super I/O port,
+// low 8 bits = logical device number (per lpc47n217.h)
+// enable - 0 to disable, anythig else to enable
+// Return Value: None
+// Description: Enable or disable the specified logical device.
+// Technically, a full disable requires setting the device's base
+// I/O port below 0x100. We don't do that here, because we don't
+// have access to a data structure that specifies what the 'real'
+// base port is (when asked to enable the device). Also the function
+// is used only to disable the device while its true base port is
+// programmed (see lpc47n217_enable_serial() below).
+//
+void lpc47n217_pnp_set_enable(device_t dev, int enable)
+{
+ uint8_t power_register = 0;
+ uint8_t power_mask = 0;
+ uint8_t current_power;
+ uint8_t new_power;
+
+ switch(dev & 0xFF) {
+ case LPC47N217_PP:
+ power_register = 0x01;
+ power_mask = 0x04;
+ break;
+
+ case LPC47N217_SP1:
+ power_register = 0x02;
+ power_mask = 0x08;
+ break;
+
+ case LPC47N217_SP2:
+ power_register = 0x02;
+ power_mask = 0x80;
+ break;
+
+ default:
+ return;
+ }
+
+ current_power = pnp_read_config(dev, power_register);
+ new_power = current_power & ~power_mask; // disable by default
+
+ if (enable)
+ new_power |= power_mask; // Enable
+
+ pnp_write_config(dev, power_register, new_power);
+}
+
+//----------------------------------------------------------------------------------
+// Function: lpc47n217_enable_serial
+// Parameters: dev - high 8 bits = Super I/O port,
+// low 8 bits = logical device number (per lpc47n217.h)
+// iobase - processor I/O port address to assign to this serial device
+// Return Value: bool
+// Description: Configure the base I/O port of the specified serial device
+// and enable the serial device.
+//
+static void lpc47n217_enable_serial(device_t dev, unsigned iobase)
+{
+ // NOTE: Cannot use pnp_set_XXX() here because they assume chip
+ // support for logical devices, which the LPC47N217 doesn't have
+
+ pnp_enter_conf_state(dev);
+ lpc47n217_pnp_set_enable(dev, 0);
+ lpc47n217_pnp_set_iobase(dev, iobase);
+ lpc47n217_pnp_set_enable(dev, 1);
+ pnp_exit_conf_state(dev);
+}
-/*\r
- * $Header: /home/cvs/BIR/ca-cpu/freebios/src/superio/smsc/lpc47n217/superio.c,v 1.1.1.1 2005/07/11 15:28:51 smagnani Exp $\r
- *\r
- * superio.c: RAM-based driver for SMSC LPC47N217 Super I/O chip\r
- *\r
- * Based on LinuxBIOS code for SMSC 47B397:\r
- * Copyright 2000 AG Electronics Ltd.\r
- * Copyright 2003-2004 Linux Networx\r
- * Copyright 2004 Tyan \r
- *\r
- * Copyright (C) 2005 Digital Design Corporation\r
- *\r
- * This program is free software; you can redistribute it and/or modify\r
- * it under the terms of the GNU General Public License as published by\r
- * the Free Software Foundation; either version 2 of the License, or\r
- * (at your option) any later version.\r
- *\r
- * This program is distributed in the hope that it will be useful,\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- * GNU General Public License for more details.\r
- *\r
- * You should have received a copy of the GNU General Public License\r
- * along with this program; if not, write to the Free Software\r
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
- *\r
- * $Log: superio.c,v $\r
- * Revision 1.1.1.1 2005/07/11 15:28:51 smagnani\r
- * Initial revision.\r
- *\r
- *\r
- */\r
-\r
-#include <arch/io.h>\r
-#include <device/device.h>\r
-#include <device/pnp.h>\r
-#include <console/console.h>\r
-#include <device/smbus.h>\r
-#include <string.h>\r
-#include <bitops.h>\r
-#include <uart8250.h>\r
-#include <assert.h>\r
-#include "chip.h"\r
-#include "lpc47n217.h"\r
-\r
-// Forward declarations\r
-static void enable_dev(device_t dev);\r
-void lpc47n217_pnp_set_resources(device_t dev);\r
-void lpc47n217_pnp_enable_resources(device_t dev);\r
-void lpc47n217_pnp_enable(device_t dev);\r
-static void lpc47n217_init(device_t dev);\r
-\r
-static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource);\r
-void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase);\r
-void lpc47n217_pnp_set_drq(device_t dev, unsigned drq);\r
-void lpc47n217_pnp_set_irq(device_t dev, unsigned irq);\r
-void lpc47n217_pnp_set_enable(device_t dev, int enable);\r
-\r
-static void pnp_enter_conf_state(device_t dev);\r
-static void pnp_exit_conf_state(device_t dev);\r
-\r
-\r
-struct chip_operations superio_smsc_lpc47n217_ops = {\r
- CHIP_NAME("smsc lpc47n217")\r
- .enable_dev = enable_dev,\r
-};\r
-\r
-static struct device_operations ops = {\r
- .read_resources = pnp_read_resources,\r
- .set_resources = lpc47n217_pnp_set_resources,\r
- .enable_resources = lpc47n217_pnp_enable_resources,\r
- .enable = lpc47n217_pnp_enable,\r
- .init = lpc47n217_init,\r
-};\r
-\r
-static struct pnp_info pnp_dev_info[] = {\r
- { &ops, LPC47N217_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },\r
- { &ops, LPC47N217_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },\r
- { &ops, LPC47N217_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }\r
-};\r
-\r
-/**********************************************************************************/\r
-/* PUBLIC INTERFACE */\r
-/**********************************************************************************/\r
-\r
-//----------------------------------------------------------------------------------\r
-// Function: enable_dev\r
-// Parameters: dev - pointer to structure describing a Super I/O device \r
-// Return Value: None\r
-// Description: Create device structures and allocate resources to devices \r
-// specified in the pnp_dev_info array (above).\r
-//\r
-static void enable_dev(device_t dev)\r
-{\r
- pnp_enable_devices(dev, &pnp_ops, \r
- sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), \r
- pnp_dev_info);\r
-}\r
-\r
-//----------------------------------------------------------------------------------\r
-// Function: lpc47n217_pnp_set_resources\r
-// Parameters: dev - pointer to structure describing a Super I/O device \r
-// Return Value: None\r
-// Description: Configure the specified Super I/O device with the resources\r
-// (I/O space, etc.) that have been allocate for it.\r
-//\r
-void lpc47n217_pnp_set_resources(device_t dev)\r
-{\r
- int i;\r
- \r
- pnp_enter_conf_state(dev); \r
-\r
- // NOTE: Cannot use pnp_set_resources() here because it assumes chip\r
- // support for logical devices, which the LPC47N217 doesn't have\r
- for(i = 0; i < dev->resources; i++)\r
- lpc47n217_pnp_set_resource(dev, &dev->resource[i]);\r
-\r
-// dump_pnp_device(dev);\r
- \r
- pnp_exit_conf_state(dev); \r
-} \r
-\r
-void lpc47n217_pnp_enable_resources(device_t dev)\r
-{ \r
- pnp_enter_conf_state(dev);\r
-\r
- // NOTE: Cannot use pnp_enable_resources() here because it assumes chip\r
- // support for logical devices, which the LPC47N217 doesn't have\r
- lpc47n217_pnp_set_enable(dev, 1);\r
-\r
- pnp_exit_conf_state(dev);\r
-}\r
-\r
-void lpc47n217_pnp_enable(device_t dev)\r
-{\r
- pnp_enter_conf_state(dev); \r
-\r
- // NOTE: Cannot use pnp_set_enable() here because it assumes chip\r
- // support for logical devices, which the LPC47N217 doesn't have\r
-\r
- if(dev->enabled) {\r
- lpc47n217_pnp_set_enable(dev, 1);\r
- }\r
- else {\r
- lpc47n217_pnp_set_enable(dev, 0);\r
- }\r
-\r
- pnp_exit_conf_state(dev); \r
-}\r
-\r
-//----------------------------------------------------------------------------------\r
-// Function: lpc47n217_init\r
-// Parameters: dev - pointer to structure describing a Super I/O device \r
-// Return Value: None\r
-// Description: Initialize the specified Super I/O device.\r
-// Devices other than COM ports are ignored.\r
-// For COM ports, we configure the baud rate. \r
-//\r
-static void lpc47n217_init(device_t dev)\r
-{\r
- struct superio_smsc_lpc47n217_config* conf = dev->chip_info;\r
- struct resource *res0;\r
-\r
- if (!dev->enabled)\r
- return;\r
-\r
- switch(dev->path.u.pnp.device) {\r
- case LPC47N217_SP1: \r
- res0 = find_resource(dev, PNP_IDX_IO0);\r
- init_uart8250(res0->base, &conf->com1);\r
- break;\r
-\r
- case LPC47N217_SP2:\r
- res0 = find_resource(dev, PNP_IDX_IO0);\r
- init_uart8250(res0->base, &conf->com2);\r
- break;\r
- }\r
-}\r
-\r
-\r
-/**********************************************************************************/\r
-/* PRIVATE FUNCTIONS */\r
-/**********************************************************************************/\r
-\r
-static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource)\r
-{\r
- if (!(resource->flags & IORESOURCE_ASSIGNED)) {\r
- printk_err("ERROR: %s %02x not allocated\n",\r
- dev_path(dev), resource->index);\r
- return;\r
- }\r
-\r
- /* Now store the resource */\r
- // NOTE: Cannot use pnp_set_XXX() here because they assume chip\r
- // support for logical devices, which the LPC47N217 doesn't have\r
-\r
- if (resource->flags & IORESOURCE_IO) {\r
- lpc47n217_pnp_set_iobase(dev, resource->base);\r
- }\r
- else if (resource->flags & IORESOURCE_DRQ) {\r
- lpc47n217_pnp_set_drq(dev, resource->base);\r
- }\r
- else if (resource->flags & IORESOURCE_IRQ) {\r
- lpc47n217_pnp_set_irq(dev, resource->base);\r
- }\r
- else {\r
- printk_err("ERROR: %s %02x unknown resource type\n",\r
- dev_path(dev), resource->index);\r
- return;\r
- }\r
- resource->flags |= IORESOURCE_STORED;\r
-\r
- report_resource_stored(dev, resource, "");\r
-}\r
-\r
-void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase)\r
-{\r
- ASSERT(!(iobase & 0x3));\r
- \r
- switch(dev->path.u.pnp.device) {\r
- case LPC47N217_PP: \r
- pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);\r
- break;\r
- \r
- case LPC47N217_SP1: \r
- pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);\r
- break;\r
- \r
- case LPC47N217_SP2:\r
- pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);\r
- break;\r
- \r
- default:\r
- BUG();\r
- break;\r
- }\r
-}\r
-\r
-void lpc47n217_pnp_set_drq(device_t dev, unsigned drq)\r
-{\r
- if (dev->path.u.pnp.device == LPC47N217_PP) {\r
- const uint8_t PP_DMA_MASK = 0x0F;\r
- const uint8_t PP_DMA_SELECTION_REGISTER = 0x26;\r
- uint8_t current_config = pnp_read_config(dev, PP_DMA_SELECTION_REGISTER);\r
- uint8_t new_config;\r
-\r
- ASSERT(!(drq & ~PP_DMA_MASK)); // DRQ out of range?? \r
- new_config = (current_config & ~PP_DMA_MASK) | drq;\r
- pnp_write_config(dev, PP_DMA_SELECTION_REGISTER, new_config);\r
- } else {\r
- BUG();\r
- }\r
-}\r
-\r
-void lpc47n217_pnp_set_irq(device_t dev, unsigned irq)\r
-{\r
- uint8_t irq_config_register = 0;\r
- uint8_t irq_config_mask = 0;\r
- uint8_t current_config;\r
- uint8_t new_config;\r
- \r
- switch(dev->path.u.pnp.device) {\r
- case LPC47N217_PP: \r
- irq_config_register = 0x27;\r
- irq_config_mask = 0x0F;\r
- break;\r
- \r
- case LPC47N217_SP1: \r
- irq_config_register = 0x28;\r
- irq_config_mask = 0xF0;\r
- irq <<= 4;\r
- break;\r
- \r
- case LPC47N217_SP2:\r
- irq_config_register = 0x28;\r
- irq_config_mask = 0x0F;\r
- break;\r
- \r
- default:\r
- BUG();\r
- return;\r
- }\r
-\r
- ASSERT(!(irq & ~irq_config_mask)); // IRQ out of range??\r
- \r
- current_config = pnp_read_config(dev, irq_config_register);\r
- new_config = (current_config & ~irq_config_mask) | irq;\r
- pnp_write_config(dev, irq_config_register, new_config);\r
-}\r
-\r
-void lpc47n217_pnp_set_enable(device_t dev, int enable)\r
-{\r
- uint8_t power_register = 0;\r
- uint8_t power_mask = 0;\r
- uint8_t current_power;\r
- uint8_t new_power;\r
- \r
- switch(dev->path.u.pnp.device) {\r
- case LPC47N217_PP: \r
- power_register = 0x01;\r
- power_mask = 0x04;\r
- break;\r
- \r
- case LPC47N217_SP1: \r
- power_register = 0x02;\r
- power_mask = 0x08;\r
- break;\r
- \r
- case LPC47N217_SP2:\r
- power_register = 0x02;\r
- power_mask = 0x80;\r
- break;\r
- \r
- default:\r
- BUG();\r
- return;\r
- }\r
-\r
- current_power = pnp_read_config(dev, power_register);\r
- new_power = current_power & ~power_mask; // disable by default\r
-\r
- if (enable) {\r
- struct resource* ioport_resource = find_resource(dev, PNP_IDX_IO0);\r
- lpc47n217_pnp_set_iobase(dev, ioport_resource->base);\r
- \r
- new_power |= power_mask; // Enable\r
- \r
- } else {\r
- lpc47n217_pnp_set_iobase(dev, 0);\r
- }\r
- pnp_write_config(dev, power_register, new_power);\r
-}\r
-\r
-\r
-//----------------------------------------------------------------------------------\r
-// Function: pnp_enter_conf_state\r
-// Parameters: dev - pointer to structure describing a Super I/O device \r
-// Return Value: None\r
-// Description: Enable access to the LPC47N217's configuration registers.\r
-//\r
-static void pnp_enter_conf_state(device_t dev) \r
-{\r
- outb(0x55, dev->path.u.pnp.port);\r
-}\r
-\r
-//----------------------------------------------------------------------------------\r
-// Function: pnp_exit_conf_state\r
-// Parameters: dev - pointer to structure describing a Super I/O device \r
-// Return Value: None\r
-// Description: Disable access to the LPC47N217's configuration registers.\r
-//\r
-static void pnp_exit_conf_state(device_t dev) \r
-{\r
- outb(0xaa, dev->path.u.pnp.port);\r
-}\r
-\r
-#if 0\r
-//----------------------------------------------------------------------------------\r
-// Function: dump_pnp_device\r
-// Parameters: dev - pointer to structure describing a Super I/O device \r
-// Return Value: None\r
-// Description: Print the values of all of the LPC47N217's configuration registers.\r
-// NOTE: The LPC47N217 must be in configuration mode when this\r
-// function is called.\r
-//\r
-static void dump_pnp_device(device_t dev)\r
-{\r
- int register_index;\r
- print_debug("\r\n");\r
-\r
- for(register_index = 0; register_index <= LPC47N217_MAX_CONFIG_REGISTER; register_index++) {\r
- uint8_t register_value;\r
-\r
- if ((register_index & 0x0f) == 0) {\r
- print_debug_hex8(register_index);\r
- print_debug_char(':');\r
- }\r
-\r
- // Skip over 'register' that would cause exit from configuration mode\r
- if (register_index == 0xaa)\r
- register_value = 0xaa;\r
- else\r
- register_value = pnp_read_config(dev, register_index);\r
-\r
- print_debug_char(' ');\r
- print_debug_hex8(register_value);\r
- if ((register_index & 0x0f) == 0x0f) {\r
- print_debug("\r\n");\r
- }\r
- }\r
-\r
- print_debug("\r\n");\r
-}\r
-#endif\r
+/*
+ * superio.c: RAM-based driver for SMSC LPC47N217 Super I/O chip
+ *
+ * Based on LinuxBIOS code for SMSC 47B397:
+ * Copyright 2000 AG Electronics Ltd.
+ * Copyright 2003-2004 Linux Networx
+ * Copyright 2004 Tyan
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <device/smbus.h>
+#include <string.h>
+#include <bitops.h>
+#include <uart8250.h>
+#include <assert.h>
+#include "chip.h"
+#include "lpc47n217.h"
+
+// Forward declarations
+static void enable_dev(device_t dev);
+void lpc47n217_pnp_set_resources(device_t dev);
+void lpc47n217_pnp_enable_resources(device_t dev);
+void lpc47n217_pnp_enable(device_t dev);
+static void lpc47n217_init(device_t dev);
+
+static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource);
+void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase);
+void lpc47n217_pnp_set_drq(device_t dev, unsigned drq);
+void lpc47n217_pnp_set_irq(device_t dev, unsigned irq);
+void lpc47n217_pnp_set_enable(device_t dev, int enable);
+
+static void pnp_enter_conf_state(device_t dev);
+static void pnp_exit_conf_state(device_t dev);
+
+
+struct chip_operations superio_smsc_lpc47n217_ops = {
+ CHIP_NAME("smsc lpc47n217")
+ .enable_dev = enable_dev,
+};
+
+static struct device_operations ops = {
+ .read_resources = pnp_read_resources,
+ .set_resources = lpc47n217_pnp_set_resources,
+ .enable_resources = lpc47n217_pnp_enable_resources,
+ .enable = lpc47n217_pnp_enable,
+ .init = lpc47n217_init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { &ops, LPC47N217_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+ { &ops, LPC47N217_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &ops, LPC47N217_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }
+};
+
+/**********************************************************************************/
+/* PUBLIC INTERFACE */
+/**********************************************************************************/
+
+//----------------------------------------------------------------------------------
+// Function: enable_dev
+// Parameters: dev - pointer to structure describing a Super I/O device
+// Return Value: None
+// Description: Create device structures and allocate resources to devices
+// specified in the pnp_dev_info array (above).
+//
+static void enable_dev(device_t dev)
+{
+ pnp_enable_devices(dev, &pnp_ops,
+ sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]),
+ pnp_dev_info);
+}
+
+//----------------------------------------------------------------------------------
+// Function: lpc47n217_pnp_set_resources
+// Parameters: dev - pointer to structure describing a Super I/O device
+// Return Value: None
+// Description: Configure the specified Super I/O device with the resources
+// (I/O space, etc.) that have been allocate for it.
+//
+void lpc47n217_pnp_set_resources(device_t dev)
+{
+ int i;
+
+ pnp_enter_conf_state(dev);
+
+ // NOTE: Cannot use pnp_set_resources() here because it assumes chip
+ // support for logical devices, which the LPC47N217 doesn't have
+ for(i = 0; i < dev->resources; i++)
+ lpc47n217_pnp_set_resource(dev, &dev->resource[i]);
+
+// dump_pnp_device(dev);
+
+ pnp_exit_conf_state(dev);
+}
+
+void lpc47n217_pnp_enable_resources(device_t dev)
+{
+ pnp_enter_conf_state(dev);
+
+ // NOTE: Cannot use pnp_enable_resources() here because it assumes chip
+ // support for logical devices, which the LPC47N217 doesn't have
+ lpc47n217_pnp_set_enable(dev, 1);
+
+ pnp_exit_conf_state(dev);
+}
+
+void lpc47n217_pnp_enable(device_t dev)
+{
+ pnp_enter_conf_state(dev);
+
+ // NOTE: Cannot use pnp_set_enable() here because it assumes chip
+ // support for logical devices, which the LPC47N217 doesn't have
+
+ if(dev->enabled) {
+ lpc47n217_pnp_set_enable(dev, 1);
+ }
+ else {
+ lpc47n217_pnp_set_enable(dev, 0);
+ }
+
+ pnp_exit_conf_state(dev);
+}
+
+//----------------------------------------------------------------------------------
+// Function: lpc47n217_init
+// Parameters: dev - pointer to structure describing a Super I/O device
+// Return Value: None
+// Description: Initialize the specified Super I/O device.
+// Devices other than COM ports are ignored.
+// For COM ports, we configure the baud rate.
+//
+static void lpc47n217_init(device_t dev)
+{
+ struct superio_smsc_lpc47n217_config* conf = dev->chip_info;
+ struct resource *res0;
+
+ if (!dev->enabled)
+ return;
+
+ switch(dev->path.u.pnp.device) {
+ case LPC47N217_SP1:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ init_uart8250(res0->base, &conf->com1);
+ break;
+
+ case LPC47N217_SP2:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ init_uart8250(res0->base, &conf->com2);
+ break;
+ }
+}
+
+
+/**********************************************************************************/
+/* PRIVATE FUNCTIONS */
+/**********************************************************************************/
+
+static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource)
+{
+ if (!(resource->flags & IORESOURCE_ASSIGNED)) {
+ printk_err("ERROR: %s %02x not allocated\n",
+ dev_path(dev), resource->index);
+ return;
+ }
+
+ /* Now store the resource */
+ // NOTE: Cannot use pnp_set_XXX() here because they assume chip
+ // support for logical devices, which the LPC47N217 doesn't have
+
+ if (resource->flags & IORESOURCE_IO) {
+ lpc47n217_pnp_set_iobase(dev, resource->base);
+ }
+ else if (resource->flags & IORESOURCE_DRQ) {
+ lpc47n217_pnp_set_drq(dev, resource->base);
+ }
+ else if (resource->flags & IORESOURCE_IRQ) {
+ lpc47n217_pnp_set_irq(dev, resource->base);
+ }
+ else {
+ printk_err("ERROR: %s %02x unknown resource type\n",
+ dev_path(dev), resource->index);
+ return;
+ }
+ resource->flags |= IORESOURCE_STORED;
+
+ report_resource_stored(dev, resource, "");
+}
+
+void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase)
+{
+ ASSERT(!(iobase & 0x3));
+
+ switch(dev->path.u.pnp.device) {
+ case LPC47N217_PP:
+ pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
+ break;
+
+ case LPC47N217_SP1:
+ pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
+ break;
+
+ case LPC47N217_SP2:
+ pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
+ break;
+
+ default:
+ BUG();
+ break;
+ }
+}
+
+void lpc47n217_pnp_set_drq(device_t dev, unsigned drq)
+{
+ if (dev->path.u.pnp.device == LPC47N217_PP) {
+ const uint8_t PP_DMA_MASK = 0x0F;
+ const uint8_t PP_DMA_SELECTION_REGISTER = 0x26;
+ uint8_t current_config = pnp_read_config(dev, PP_DMA_SELECTION_REGISTER);
+ uint8_t new_config;
+
+ ASSERT(!(drq & ~PP_DMA_MASK)); // DRQ out of range??
+ new_config = (current_config & ~PP_DMA_MASK) | drq;
+ pnp_write_config(dev, PP_DMA_SELECTION_REGISTER, new_config);
+ } else {
+ BUG();
+ }
+}
+
+void lpc47n217_pnp_set_irq(device_t dev, unsigned irq)
+{
+ uint8_t irq_config_register = 0;
+ uint8_t irq_config_mask = 0;
+ uint8_t current_config;
+ uint8_t new_config;
+
+ switch(dev->path.u.pnp.device) {
+ case LPC47N217_PP:
+ irq_config_register = 0x27;
+ irq_config_mask = 0x0F;
+ break;
+
+ case LPC47N217_SP1:
+ irq_config_register = 0x28;
+ irq_config_mask = 0xF0;
+ irq <<= 4;
+ break;
+
+ case LPC47N217_SP2:
+ irq_config_register = 0x28;
+ irq_config_mask = 0x0F;
+ break;
+
+ default:
+ BUG();
+ return;
+ }
+
+ ASSERT(!(irq & ~irq_config_mask)); // IRQ out of range??
+
+ current_config = pnp_read_config(dev, irq_config_register);
+ new_config = (current_config & ~irq_config_mask) | irq;
+ pnp_write_config(dev, irq_config_register, new_config);
+}
+
+void lpc47n217_pnp_set_enable(device_t dev, int enable)
+{
+ uint8_t power_register = 0;
+ uint8_t power_mask = 0;
+ uint8_t current_power;
+ uint8_t new_power;
+
+ switch(dev->path.u.pnp.device) {
+ case LPC47N217_PP:
+ power_register = 0x01;
+ power_mask = 0x04;
+ break;
+
+ case LPC47N217_SP1:
+ power_register = 0x02;
+ power_mask = 0x08;
+ break;
+
+ case LPC47N217_SP2:
+ power_register = 0x02;
+ power_mask = 0x80;
+ break;
+
+ default:
+ BUG();
+ return;
+ }
+
+ current_power = pnp_read_config(dev, power_register);
+ new_power = current_power & ~power_mask; // disable by default
+
+ if (enable) {
+ struct resource* ioport_resource = find_resource(dev, PNP_IDX_IO0);
+ lpc47n217_pnp_set_iobase(dev, ioport_resource->base);
+
+ new_power |= power_mask; // Enable
+
+ } else {
+ lpc47n217_pnp_set_iobase(dev, 0);
+ }
+ pnp_write_config(dev, power_register, new_power);
+}
+
+
+//----------------------------------------------------------------------------------
+// Function: pnp_enter_conf_state
+// Parameters: dev - pointer to structure describing a Super I/O device
+// Return Value: None
+// Description: Enable access to the LPC47N217's configuration registers.
+//
+static void pnp_enter_conf_state(device_t dev)
+{
+ outb(0x55, dev->path.u.pnp.port);
+}
+
+//----------------------------------------------------------------------------------
+// Function: pnp_exit_conf_state
+// Parameters: dev - pointer to structure describing a Super I/O device
+// Return Value: None
+// Description: Disable access to the LPC47N217's configuration registers.
+//
+static void pnp_exit_conf_state(device_t dev)
+{
+ outb(0xaa, dev->path.u.pnp.port);
+}
+
+#if 0
+//----------------------------------------------------------------------------------
+// Function: dump_pnp_device
+// Parameters: dev - pointer to structure describing a Super I/O device
+// Return Value: None
+// Description: Print the values of all of the LPC47N217's configuration registers.
+// NOTE: The LPC47N217 must be in configuration mode when this
+// function is called.
+//
+static void dump_pnp_device(device_t dev)
+{
+ int register_index;
+ print_debug("\r\n");
+
+ for(register_index = 0; register_index <= LPC47N217_MAX_CONFIG_REGISTER; register_index++) {
+ uint8_t register_value;
+
+ if ((register_index & 0x0f) == 0) {
+ print_debug_hex8(register_index);
+ print_debug_char(':');
+ }
+
+ // Skip over 'register' that would cause exit from configuration mode
+ if (register_index == 0xaa)
+ register_value = 0xaa;
+ else
+ register_value = pnp_read_config(dev, register_index);
+
+ print_debug_char(' ');
+ print_debug_hex8(register_value);
+ if ((register_index & 0x0f) == 0x0f) {
+ print_debug("\r\n");
+ }
+ }
+
+ print_debug("\r\n");
+}
+#endif
projects / coreboot.git / commitdiff