--- /dev/null
+config chip.h
+object superio.o
--- /dev/null
+#ifndef SIO_COM1
+#define SIO_COM1_BASE 0x3F8
+#endif
+#ifndef SIO_COM2
+#define SIO_COM2_BASE 0x2F8
+#endif
+
+struct chip_operations;
+extern struct chip_operations superio_smsc_lpc47b272_ops;
+
+#include <pc80/keyboard.h>
+#include <uart8250.h>
+
+struct superio_smsc_lpc47b272_config {
+ struct uart8250 com1, com2;
+ struct pc_keyboard keyboard;
+};
--- /dev/null
+#define LPC47B272_FDC 0 /* Floppy */
+#define LPC47B272_PP 3 /* Parallel Port */
+#define LPC47B272_SP1 4 /* Com1 */
+#define LPC47B272_SP2 5 /* Com2 */
+#define LPC47B272_KBC 7 /* Keyboard & Mouse */
+#define LPC47B272_RT 10 /* Runtime reg*/
+
+#define LPC47B272_MAX_CONFIG_REGISTER 0x5F
--- /dev/null
+/*\r
+ * $Header$\r
+ *\r
+ * lpc47b272_early_serial.c: Pre-RAM driver for SMSC LPC47B272 Super I/O chip\r
+ *\r
+ * Copyright (C) 2005 Digital Design Corporation\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; either version 2 of the License, or\r
+ * (at your option) any later version.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+ *\r
+ * $Log$\r
+ *\r
+ */\r
+
+#include <arch/romcc_io.h>
+#include "lpc47b272.h"
+
+//----------------------------------------------------------------------------------\r
+// Function: pnp_enter_conf_state\r
+// Parameters: dev - high 8 bits = Super I/O port\r
+// Return Value: None\r
+// Description: Enable access to the LPC47B272's configuration registers.\r
+//\r
+static inline void pnp_enter_conf_state(device_t dev) {
+ unsigned port = dev>>8;
+ outb(0x55, port);
+}\r
+
+//----------------------------------------------------------------------------------\r
+// Function: pnp_exit_conf_state\r
+// Parameters: dev - high 8 bits = Super I/O port\r
+// Return Value: None\r
+// Description: Disable access to the LPC47B272's configuration registers.\r
+//\r
+static void pnp_exit_conf_state(device_t dev) {
+ unsigned port = dev>>8;
+ outb(0xaa, port);
+}
+
+//----------------------------------------------------------------------------------\r
+// Function: lpc47b272_enable_serial\r
+// Parameters: dev - high 8 bits = Super I/O port, \r
+// low 8 bits = logical device number (per lpc47b272.h)\r
+// iobase - processor I/O port address to assign to this serial device\r
+// Return Value: bool\r
+// Description: Configure the base I/O port of the specified serial device\r
+// and enable the serial device.\r
+//\r
+static void lpc47b272_enable_serial(device_t dev, unsigned iobase)
+{
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_conf_state(dev);
+}
--- /dev/null
+/*\r
+ * $Header$\r
+ *\r
+ * superio.c: RAM driver for SMSC LPC47B272 Super I/O chip\r
+ *\r
+ * Copyright 2000 AG Electronics Ltd.
+ * Copyright 2003-2004 Linux Networx
+ * Copyright 2004 Tyan
+ * Copyright (C) 2005 Digital Design Corporation\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; either version 2 of the License, or\r
+ * (at your option) any later version.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+ *\r
+ * $Log$\r
+ *\r
+ */\r
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <device/smbus.h>
+#include <string.h>
+#include <bitops.h>
+#include <uart8250.h>
+#include <pc80/keyboard.h>
+#include "chip.h"
+#include "lpc47b272.h"
+
+// Forward declarations\r
+static void enable_dev(device_t dev);\r
+void lpc47b272_pnp_set_resources(device_t dev);
+void lpc47b272_pnp_set_resources(device_t dev);
+void lpc47b272_pnp_enable_resources(device_t dev);
+void lpc47b272_pnp_enable(device_t dev);
+static void lpc47b272_init(device_t dev);
+
+static void pnp_enter_conf_state(device_t dev);\r
+static void pnp_exit_conf_state(device_t dev);\r
+static void dump_pnp_device(device_t dev);
+
+
+struct chip_operations superio_smsc_lpc47b272_ops = {
+ CHIP_NAME("smsc lpc47b272")
+ .enable_dev = enable_dev
+};
+
+static struct device_operations ops = {
+ .read_resources = pnp_read_resources,
+ .set_resources = lpc47b272_pnp_set_resources,
+ .enable_resources = lpc47b272_pnp_enable_resources,
+ .enable = lpc47b272_pnp_enable,
+ .init = lpc47b272_init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { &ops, LPC47B272_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+ { &ops, LPC47B272_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+ { &ops, LPC47B272_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &ops, LPC47B272_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &ops, LPC47B272_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
+ { &ops, LPC47B272_RT, PNP_IO0, { 0x780, 0 }, },
+};
+
+/**********************************************************************************/\r
+/* PUBLIC INTERFACE */\r
+/**********************************************************************************/\r
+\r
+//----------------------------------------------------------------------------------\r
+// Function: enable_dev\r
+// Parameters: dev - pointer to structure describing a Super I/O device \r
+// Return Value: None\r
+// Description: Create device structures and allocate resources to devices \r
+// specified in the pnp_dev_info array (above).\r
+//\r
+static void enable_dev(device_t dev)\r
+{\r
+ pnp_enable_devices(dev, &pnp_ops, \r
+ sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), \r
+ pnp_dev_info);\r
+}\r
+
+//----------------------------------------------------------------------------------\r
+// Function: lpc47b272_pnp_set_resources\r
+// Parameters: dev - pointer to structure describing a Super I/O device \r
+// Return Value: None\r
+// Description: Configure the specified Super I/O device with the resources\r
+// (I/O space, etc.) that have been allocated for it.\r
+//
+void lpc47b272_pnp_set_resources(device_t dev)
+{
+ pnp_enter_conf_state(dev);
+ pnp_set_resources(dev);
+ pnp_exit_conf_state(dev);
+}
+
+void lpc47b272_pnp_enable_resources(device_t dev)
+{
+ pnp_enter_conf_state(dev);
+ pnp_enable_resources(dev);
+ pnp_exit_conf_state(dev);
+}
+
+void lpc47b272_pnp_enable(device_t dev)
+{
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+
+ if(dev->enabled) {
+ pnp_set_enable(dev, 1);
+ }
+ else {
+ pnp_set_enable(dev, 0);
+ }
+ pnp_exit_conf_state(dev);
+}
+
+//----------------------------------------------------------------------------------\r
+// Function: lpc47b272_init\r
+// Parameters: dev - pointer to structure describing a Super I/O device \r
+// Return Value: None\r
+// Description: Initialize the specified Super I/O device.\r
+// Devices other than COM ports and the keyboard controller are
+// ignored. For COM ports, we configure the baud rate. \r
+//\r
+static void lpc47b272_init(device_t dev)
+{
+ struct superio_smsc_lpc47b272_config *conf = dev->chip_info;
+ struct resource *res0, *res1;
+
+ if (!dev->enabled)
+ return;
+
+ switch(dev->path.u.pnp.device) {
+ case LPC47B272_SP1:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ init_uart8250(res0->base, &conf->com1);
+ break;
+
+ case LPC47B272_SP2:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ init_uart8250(res0->base, &conf->com2);
+ break;
+
+ case LPC47B272_KBC:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ res1 = find_resource(dev, PNP_IDX_IO1);
+ init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
+ break;
+ }
+}
+\r
+/**********************************************************************************/\r
+/* PRIVATE FUNCTIONS */\r
+/**********************************************************************************/\r
+
+//----------------------------------------------------------------------------------\r
+// Function: pnp_enter_conf_state\r
+// Parameters: dev - pointer to structure describing a Super I/O device \r
+// Return Value: None\r
+// Description: Enable access to the LPC47B272's configuration registers.\r
+//\r
+static void pnp_enter_conf_state(device_t dev) \r
+{
+ outb(0x55, dev->path.u.pnp.port);
+}\r
+
+//----------------------------------------------------------------------------------\r
+// Function: pnp_exit_conf_state\r
+// Parameters: dev - pointer to structure describing a Super I/O device \r
+// Return Value: None\r
+// Description: Disable access to the LPC47B272's configuration registers.\r
+//\r
+static void pnp_exit_conf_state(device_t dev) \r
+{
+ outb(0xaa, dev->path.u.pnp.port);
+}
+
+#if 0
+//----------------------------------------------------------------------------------\r
+// Function: dump_pnp_device\r
+// Parameters: dev - pointer to structure describing a Super I/O device \r
+// Return Value: None\r
+// Description: Print the values of all of the LPC47B272's configuration registers.\r
+// NOTE: The LPC47B272 must be in configuration mode when this\r
+// function is called.\r
+//\r
+static void dump_pnp_device(device_t dev)
+{
+ int register_index;
+ print_debug("\r\n");
+
+ for(register_index = 0; register_index <= LPC47B272_MAX_CONFIG_REGISTER; register_index++) {
+ uint8_t register_value;\r
+
+ if ((register_index & 0x0f) == 0) {
+ print_debug_hex8(register_index);
+ print_debug_char(':');
+ }\r
+\r
+ // Skip over 'register' that would cause exit from configuration mode
+ if (register_index == 0xaa)
+ register_value = 0xaa;\r
+ else
+ register_value = pnp_read_config(dev, register_index);\r
+\r
+ print_debug_char(' ');
+ print_debug_hex8(register_value);
+ if ((register_index & 0x0f) == 0x0f) {
+ print_debug("\r\n");
+ }
+ }\r
+\r
+ print_debug("\r\n");\r
+}
+#endif
--- /dev/null
+config chip.h\r
+object superio.o\r
--- /dev/null
+#ifndef SIO_COM1\r
+#define SIO_COM1_BASE 0x3F8\r
+#endif\r
+#ifndef SIO_COM2\r
+#define SIO_COM2_BASE 0x2F8\r
+#endif\r
+\r
+struct chip_operations;\r
+extern struct chip_operations superio_smsc_lpc47n217_ops;\r
+\r
+#include <uart8250.h>\r
+\r
+struct superio_smsc_lpc47n217_config {\r
+ struct uart8250 com1, com2;\r
+};\r
--- /dev/null
+// These are arbitrary, but must match declarations in the mainboard config file.\r
+// Values chosen to match SMSC 47B37x.\r
+\r
+#define LPC47N217_PP 3 /* Parallel Port */\r
+#define LPC47N217_SP1 4 /* Com1 */\r
+#define LPC47N217_SP2 5 /* Com2 */\r
+\r
+#define LPC47N217_MAX_CONFIG_REGISTER 0x39\r
--- /dev/null
+/*\r
+ * $Header: /home/cvs/BIR/ca-cpu/freebios/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c,v 1.1.1.1 2005/07/11 15:28:51 smagnani Exp $\r
+ *\r
+ * lpc47n217_early_serial.c: Pre-RAM driver for SMSC LPC47N217 Super I/O chip\r
+ *\r
+ * Copyright (C) 2005 Digital Design Corporation\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; either version 2 of the License, or\r
+ * (at your option) any later version.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+ *\r
+ * $Log: lpc47n217_early_serial.c,v $\r
+ * Revision 1.1.1.1 2005/07/11 15:28:51 smagnani\r
+ * Initial revision.\r
+ *\r
+ *\r
+ */\r
+\r
+#include <arch/romcc_io.h>\r
+#include <assert.h>\r
+#include "lpc47n217.h"\r
+\r
+//----------------------------------------------------------------------------------\r
+// Function: pnp_enter_conf_state\r
+// Parameters: dev - high 8 bits = Super I/O port\r
+// Return Value: None\r
+// Description: Enable access to the LPC47N217's configuration registers.\r
+//\r
+static inline void pnp_enter_conf_state(device_t dev) {\r
+ unsigned port = dev>>8;\r
+ outb(0x55, port);\r
+}\r
+\r
+//----------------------------------------------------------------------------------\r
+// Function: pnp_exit_conf_state\r
+// Parameters: dev - high 8 bits = Super I/O port\r
+// Return Value: None\r
+// Description: Disable access to the LPC47N217's configuration registers.\r
+//\r
+static void pnp_exit_conf_state(device_t dev) {\r
+ unsigned port = dev>>8;\r
+ outb(0xaa, port);\r
+}\r
+\r
+//----------------------------------------------------------------------------------\r
+// Function: lpc47n217_pnp_set_iobase\r
+// Parameters: dev - high 8 bits = Super I/O port, \r
+// low 8 bits = logical device number (per lpc47n217.h)\r
+// iobase - base I/O port for the logical device\r
+// Return Value: None\r
+// Description: Program the base I/O port for the specified logical device.\r
+//\r
+void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase)\r
+{\r
+ // LPC47N217 requires base ports to be a multiple of 4\r
+ ASSERT(!(iobase & 0x3));\r
+\r
+ switch(dev & 0xFF) {\r
+ case LPC47N217_PP: \r
+ pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);\r
+ break;\r
+ \r
+ case LPC47N217_SP1: \r
+ pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);\r
+ break;\r
+ \r
+ case LPC47N217_SP2:\r
+ pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+//----------------------------------------------------------------------------------\r
+// Function: lpc47n217_pnp_set_enable\r
+// Parameters: dev - high 8 bits = Super I/O port, \r
+// low 8 bits = logical device number (per lpc47n217.h)\r
+// enable - 0 to disable, anythig else to enable\r
+// Return Value: None\r
+// Description: Enable or disable the specified logical device.\r
+// Technically, a full disable requires setting the device's base\r
+// I/O port below 0x100. We don't do that here, because we don't\r
+// have access to a data structure that specifies what the 'real'\r
+// base port is (when asked to enable the device). Also the function\r
+// is used only to disable the device while its true base port is\r
+// programmed (see lpc47n217_enable_serial() below).\r
+//\r
+void lpc47n217_pnp_set_enable(device_t dev, int enable)\r
+{\r
+ uint8_t power_register = 0;\r
+ uint8_t power_mask = 0;\r
+ uint8_t current_power;\r
+ uint8_t new_power;\r
+ \r
+ switch(dev & 0xFF) {\r
+ case LPC47N217_PP: \r
+ power_register = 0x01;\r
+ power_mask = 0x04;\r
+ break;\r
+ \r
+ case LPC47N217_SP1: \r
+ power_register = 0x02;\r
+ power_mask = 0x08;\r
+ break;\r
+ \r
+ case LPC47N217_SP2:\r
+ power_register = 0x02;\r
+ power_mask = 0x80;\r
+ break;\r
+ \r
+ default:\r
+ return;\r
+ }\r
+\r
+ current_power = pnp_read_config(dev, power_register);\r
+ new_power = current_power & ~power_mask; // disable by default\r
+\r
+ if (enable)\r
+ new_power |= power_mask; // Enable\r
+\r
+ pnp_write_config(dev, power_register, new_power);\r
+}\r
+\r
+//----------------------------------------------------------------------------------\r
+// Function: lpc47n217_enable_serial\r
+// Parameters: dev - high 8 bits = Super I/O port, \r
+// low 8 bits = logical device number (per lpc47n217.h)\r
+// iobase - processor I/O port address to assign to this serial device\r
+// Return Value: bool\r
+// Description: Configure the base I/O port of the specified serial device\r
+// and enable the serial device.\r
+//\r
+static void lpc47n217_enable_serial(device_t dev, unsigned iobase)\r
+{\r
+ // NOTE: Cannot use pnp_set_XXX() here because they assume chip\r
+ // support for logical devices, which the LPC47N217 doesn't have\r
+ \r
+ pnp_enter_conf_state(dev);\r
+ lpc47n217_pnp_set_enable(dev, 0);\r
+ lpc47n217_pnp_set_iobase(dev, iobase);\r
+ lpc47n217_pnp_set_enable(dev, 1);\r
+ pnp_exit_conf_state(dev);\r
+}\r
--- /dev/null
+/*\r
+ * $Header: /home/cvs/BIR/ca-cpu/freebios/src/superio/smsc/lpc47n217/superio.c,v 1.1.1.1 2005/07/11 15:28:51 smagnani Exp $\r
+ *\r
+ * superio.c: RAM-based driver for SMSC LPC47N217 Super I/O chip\r
+ *\r
+ * Based on LinuxBIOS code for SMSC 47B397:\r
+ * Copyright 2000 AG Electronics Ltd.\r
+ * Copyright 2003-2004 Linux Networx\r
+ * Copyright 2004 Tyan \r
+ *\r
+ * Copyright (C) 2005 Digital Design Corporation\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; either version 2 of the License, or\r
+ * (at your option) any later version.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+ *\r
+ * $Log: superio.c,v $\r
+ * Revision 1.1.1.1 2005/07/11 15:28:51 smagnani\r
+ * Initial revision.\r
+ *\r
+ *\r
+ */\r
+\r
+#include <arch/io.h>\r
+#include <device/device.h>\r
+#include <device/pnp.h>\r
+#include <console/console.h>\r
+#include <device/smbus.h>\r
+#include <string.h>\r
+#include <bitops.h>\r
+#include <uart8250.h>\r
+#include <assert.h>\r
+#include "chip.h"\r
+#include "lpc47n217.h"\r
+\r
+// Forward declarations\r
+static void enable_dev(device_t dev);\r
+void lpc47n217_pnp_set_resources(device_t dev);\r
+void lpc47n217_pnp_enable_resources(device_t dev);\r
+void lpc47n217_pnp_enable(device_t dev);\r
+static void lpc47n217_init(device_t dev);\r
+\r
+static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource);\r
+void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase);\r
+void lpc47n217_pnp_set_drq(device_t dev, unsigned drq);\r
+void lpc47n217_pnp_set_irq(device_t dev, unsigned irq);\r
+void lpc47n217_pnp_set_enable(device_t dev, int enable);\r
+\r
+static void pnp_enter_conf_state(device_t dev);\r
+static void pnp_exit_conf_state(device_t dev);\r
+\r
+\r
+struct chip_operations superio_smsc_lpc47n217_ops = {\r
+ CHIP_NAME("smsc lpc47n217")\r
+ .enable_dev = enable_dev,\r
+};\r
+\r
+static struct device_operations ops = {\r
+ .read_resources = pnp_read_resources,\r
+ .set_resources = lpc47n217_pnp_set_resources,\r
+ .enable_resources = lpc47n217_pnp_enable_resources,\r
+ .enable = lpc47n217_pnp_enable,\r
+ .init = lpc47n217_init,\r
+};\r
+\r
+static struct pnp_info pnp_dev_info[] = {\r
+ { &ops, LPC47N217_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },\r
+ { &ops, LPC47N217_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },\r
+ { &ops, LPC47N217_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }\r
+};\r
+\r
+/**********************************************************************************/\r
+/* PUBLIC INTERFACE */\r
+/**********************************************************************************/\r
+\r
+//----------------------------------------------------------------------------------\r
+// Function: enable_dev\r
+// Parameters: dev - pointer to structure describing a Super I/O device \r
+// Return Value: None\r
+// Description: Create device structures and allocate resources to devices \r
+// specified in the pnp_dev_info array (above).\r
+//\r
+static void enable_dev(device_t dev)\r
+{\r
+ pnp_enable_devices(dev, &pnp_ops, \r
+ sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), \r
+ pnp_dev_info);\r
+}\r
+\r
+//----------------------------------------------------------------------------------\r
+// Function: lpc47n217_pnp_set_resources\r
+// Parameters: dev - pointer to structure describing a Super I/O device \r
+// Return Value: None\r
+// Description: Configure the specified Super I/O device with the resources\r
+// (I/O space, etc.) that have been allocate for it.\r
+//\r
+void lpc47n217_pnp_set_resources(device_t dev)\r
+{\r
+ int i;\r
+ \r
+ pnp_enter_conf_state(dev); \r
+\r
+ // NOTE: Cannot use pnp_set_resources() here because it assumes chip\r
+ // support for logical devices, which the LPC47N217 doesn't have\r
+ for(i = 0; i < dev->resources; i++)\r
+ lpc47n217_pnp_set_resource(dev, &dev->resource[i]);\r
+\r
+// dump_pnp_device(dev);\r
+ \r
+ pnp_exit_conf_state(dev); \r
+} \r
+\r
+void lpc47n217_pnp_enable_resources(device_t dev)\r
+{ \r
+ pnp_enter_conf_state(dev);\r
+\r
+ // NOTE: Cannot use pnp_enable_resources() here because it assumes chip\r
+ // support for logical devices, which the LPC47N217 doesn't have\r
+ lpc47n217_pnp_set_enable(dev, 1);\r
+\r
+ pnp_exit_conf_state(dev);\r
+}\r
+\r
+void lpc47n217_pnp_enable(device_t dev)\r
+{\r
+ pnp_enter_conf_state(dev); \r
+\r
+ // NOTE: Cannot use pnp_set_enable() here because it assumes chip\r
+ // support for logical devices, which the LPC47N217 doesn't have\r
+\r
+ if(dev->enabled) {\r
+ lpc47n217_pnp_set_enable(dev, 1);\r
+ }\r
+ else {\r
+ lpc47n217_pnp_set_enable(dev, 0);\r
+ }\r
+\r
+ pnp_exit_conf_state(dev); \r
+}\r
+\r
+//----------------------------------------------------------------------------------\r
+// Function: lpc47n217_init\r
+// Parameters: dev - pointer to structure describing a Super I/O device \r
+// Return Value: None\r
+// Description: Initialize the specified Super I/O device.\r
+// Devices other than COM ports are ignored.\r
+// For COM ports, we configure the baud rate. \r
+//\r
+static void lpc47n217_init(device_t dev)\r
+{\r
+ struct superio_smsc_lpc47n217_config* conf = dev->chip_info;\r
+ struct resource *res0;\r
+\r
+ if (!dev->enabled)\r
+ return;\r
+\r
+ switch(dev->path.u.pnp.device) {\r
+ case LPC47N217_SP1: \r
+ res0 = find_resource(dev, PNP_IDX_IO0);\r
+ init_uart8250(res0->base, &conf->com1);\r
+ break;\r
+\r
+ case LPC47N217_SP2:\r
+ res0 = find_resource(dev, PNP_IDX_IO0);\r
+ init_uart8250(res0->base, &conf->com2);\r
+ break;\r
+ }\r
+}\r
+\r
+\r
+/**********************************************************************************/\r
+/* PRIVATE FUNCTIONS */\r
+/**********************************************************************************/\r
+\r
+static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource)\r
+{\r
+ if (!(resource->flags & IORESOURCE_ASSIGNED)) {\r
+ printk_err("ERROR: %s %02x not allocated\n",\r
+ dev_path(dev), resource->index);\r
+ return;\r
+ }\r
+\r
+ /* Now store the resource */\r
+ // NOTE: Cannot use pnp_set_XXX() here because they assume chip\r
+ // support for logical devices, which the LPC47N217 doesn't have\r
+\r
+ if (resource->flags & IORESOURCE_IO) {\r
+ lpc47n217_pnp_set_iobase(dev, resource->base);\r
+ }\r
+ else if (resource->flags & IORESOURCE_DRQ) {\r
+ lpc47n217_pnp_set_drq(dev, resource->base);\r
+ }\r
+ else if (resource->flags & IORESOURCE_IRQ) {\r
+ lpc47n217_pnp_set_irq(dev, resource->base);\r
+ }\r
+ else {\r
+ printk_err("ERROR: %s %02x unknown resource type\n",\r
+ dev_path(dev), resource->index);\r
+ return;\r
+ }\r
+ resource->flags |= IORESOURCE_STORED;\r
+\r
+ report_resource_stored(dev, resource, "");\r
+}\r
+\r
+void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase)\r
+{\r
+ ASSERT(!(iobase & 0x3));\r
+ \r
+ switch(dev->path.u.pnp.device) {\r
+ case LPC47N217_PP: \r
+ pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);\r
+ break;\r
+ \r
+ case LPC47N217_SP1: \r
+ pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);\r
+ break;\r
+ \r
+ case LPC47N217_SP2:\r
+ pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);\r
+ break;\r
+ \r
+ default:\r
+ BUG();\r
+ break;\r
+ }\r
+}\r
+\r
+void lpc47n217_pnp_set_drq(device_t dev, unsigned drq)\r
+{\r
+ if (dev->path.u.pnp.device == LPC47N217_PP) {\r
+ const uint8_t PP_DMA_MASK = 0x0F;\r
+ const uint8_t PP_DMA_SELECTION_REGISTER = 0x26;\r
+ uint8_t current_config = pnp_read_config(dev, PP_DMA_SELECTION_REGISTER);\r
+ uint8_t new_config;\r
+\r
+ ASSERT(!(drq & ~PP_DMA_MASK)); // DRQ out of range?? \r
+ new_config = (current_config & ~PP_DMA_MASK) | drq;\r
+ pnp_write_config(dev, PP_DMA_SELECTION_REGISTER, new_config);\r
+ } else {\r
+ BUG();\r
+ }\r
+}\r
+\r
+void lpc47n217_pnp_set_irq(device_t dev, unsigned irq)\r
+{\r
+ uint8_t irq_config_register = 0;\r
+ uint8_t irq_config_mask = 0;\r
+ uint8_t current_config;\r
+ uint8_t new_config;\r
+ \r
+ switch(dev->path.u.pnp.device) {\r
+ case LPC47N217_PP: \r
+ irq_config_register = 0x27;\r
+ irq_config_mask = 0x0F;\r
+ break;\r
+ \r
+ case LPC47N217_SP1: \r
+ irq_config_register = 0x28;\r
+ irq_config_mask = 0xF0;\r
+ irq <<= 4;\r
+ break;\r
+ \r
+ case LPC47N217_SP2:\r
+ irq_config_register = 0x28;\r
+ irq_config_mask = 0x0F;\r
+ break;\r
+ \r
+ default:\r
+ BUG();\r
+ return;\r
+ }\r
+\r
+ ASSERT(!(irq & ~irq_config_mask)); // IRQ out of range??\r
+ \r
+ current_config = pnp_read_config(dev, irq_config_register);\r
+ new_config = (current_config & ~irq_config_mask) | irq;\r
+ pnp_write_config(dev, irq_config_register, new_config);\r
+}\r
+\r
+void lpc47n217_pnp_set_enable(device_t dev, int enable)\r
+{\r
+ uint8_t power_register = 0;\r
+ uint8_t power_mask = 0;\r
+ uint8_t current_power;\r
+ uint8_t new_power;\r
+ \r
+ switch(dev->path.u.pnp.device) {\r
+ case LPC47N217_PP: \r
+ power_register = 0x01;\r
+ power_mask = 0x04;\r
+ break;\r
+ \r
+ case LPC47N217_SP1: \r
+ power_register = 0x02;\r
+ power_mask = 0x08;\r
+ break;\r
+ \r
+ case LPC47N217_SP2:\r
+ power_register = 0x02;\r
+ power_mask = 0x80;\r
+ break;\r
+ \r
+ default:\r
+ BUG();\r
+ return;\r
+ }\r
+\r
+ current_power = pnp_read_config(dev, power_register);\r
+ new_power = current_power & ~power_mask; // disable by default\r
+\r
+ if (enable) {\r
+ struct resource* ioport_resource = find_resource(dev, PNP_IDX_IO0);\r
+ lpc47n217_pnp_set_iobase(dev, ioport_resource->base);\r
+ \r
+ new_power |= power_mask; // Enable\r
+ \r
+ } else {\r
+ lpc47n217_pnp_set_iobase(dev, 0);\r
+ }\r
+ pnp_write_config(dev, power_register, new_power);\r
+}\r
+\r
+\r
+//----------------------------------------------------------------------------------\r
+// Function: pnp_enter_conf_state\r
+// Parameters: dev - pointer to structure describing a Super I/O device \r
+// Return Value: None\r
+// Description: Enable access to the LPC47N217's configuration registers.\r
+//\r
+static void pnp_enter_conf_state(device_t dev) \r
+{\r
+ outb(0x55, dev->path.u.pnp.port);\r
+}\r
+\r
+//----------------------------------------------------------------------------------\r
+// Function: pnp_exit_conf_state\r
+// Parameters: dev - pointer to structure describing a Super I/O device \r
+// Return Value: None\r
+// Description: Disable access to the LPC47N217's configuration registers.\r
+//\r
+static void pnp_exit_conf_state(device_t dev) \r
+{\r
+ outb(0xaa, dev->path.u.pnp.port);\r
+}\r
+\r
+#if 0\r
+//----------------------------------------------------------------------------------\r
+// Function: dump_pnp_device\r
+// Parameters: dev - pointer to structure describing a Super I/O device \r
+// Return Value: None\r
+// Description: Print the values of all of the LPC47N217's configuration registers.\r
+// NOTE: The LPC47N217 must be in configuration mode when this\r
+// function is called.\r
+//\r
+static void dump_pnp_device(device_t dev)\r
+{\r
+ int register_index;\r
+ print_debug("\r\n");\r
+\r
+ for(register_index = 0; register_index <= LPC47N217_MAX_CONFIG_REGISTER; register_index++) {\r
+ uint8_t register_value;\r
+\r
+ if ((register_index & 0x0f) == 0) {\r
+ print_debug_hex8(register_index);\r
+ print_debug_char(':');\r
+ }\r
+\r
+ // Skip over 'register' that would cause exit from configuration mode\r
+ if (register_index == 0xaa)\r
+ register_value = 0xaa;\r
+ else\r
+ register_value = pnp_read_config(dev, register_index);\r
+\r
+ print_debug_char(' ');\r
+ print_debug_hex8(register_value);\r
+ if ((register_index & 0x0f) == 0x0f) {\r
+ print_debug("\r\n");\r
+ }\r
+ }\r
+\r
+ print_debug("\r\n");\r
+}\r
+#endif\r
projects / coreboot.git / commitdiff