config DCACHE_RAM_BASE
hex
- default 0xc0000
+ default 0xc8000
depends on CPU_AMD_GX2
config DCACHE_RAM_SIZE
hex
- default 0x01000
+ default 0x04000
depends on CPU_AMD_GX2
config GEODE_VSA
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
+
driver-y += model_gx2_init.o
obj-y += cpubug.o
+
+cpu_incs += $(src)/cpu/amd/model_gx2/cache_as_ram.inc
-
-/* ***************************************************************************/
-/* **/
-/* * BIST */
-/* **/
-/* * GX2 BISTs need to be run before BTB or caches are enabled.*/
-/* * BIST result left in registers on failure to be checked with FS2.*/
-/* **/
-/* ***************************************************************************/
-static void
-BIST(void){
- int msrnum;
- msr_t msr;
-
- /* DM*/
- msrnum = CPU_DM_CONFIG0;
- msr = rdmsr(msrnum);
- msr.lo |= DM_CONFIG0_LOWER_DCDIS_SET;
- wrmsr(msrnum, msr);
-
- msr.lo = 0x00000003F;
- msr.hi = 0x000000000;
- msrnum = CPU_DM_BIST;
- wrmsr(msrnum, msr);
-
- outb(POST_CPU_DM_BIST_FAILURE, 0x80); /* 0x29*/
- msr = rdmsr(msrnum); /* read back for pass fail*/
- msr.lo &= 0x0F3FF0000;
- if (msr.lo != 0xfeff0000)
- goto BISTFail;
-
- msrnum = CPU_DM_CONFIG0;
- msr = rdmsr(msrnum);
- msr.lo &= ~ DM_CONFIG0_LOWER_DCDIS_SET;
- wrmsr(msrnum, msr);
-
- /* FPU*/
- msr.lo = 0x000000131;
- msr.hi = 0;
- msrnum = CPU_FP_UROM_BIST;
- wrmsr(msrnum, msr);
-
- outb(POST_CPU_FPU_BIST_FAILURE, 0x80); /* 0x89*/
- inb(0x80); /* IO delay*/
- msr = rdmsr(msrnum); /* read back for pass fail*/
- while ((msr.lo&0x884) != 0x884)
- msr = rdmsr(msrnum); /* Endless loop if BIST is broken*/
- if ((msr.lo&0x642) != 0x642)
- goto BISTFail;
-
- msr.lo = msr.hi = 0; /* clear FPU BIST bits*/
- msrnum = CPU_FP_UROM_BIST;
- wrmsr(msrnum, msr);
-
-
- /* BTB*/
- msr.lo = 0x000000303;
- msr.hi = 0x000000000;
- msrnum = CPU_PF_BTBRMA_BIST;
- wrmsr(msrnum, msr);
-
- outb(POST_CPU_BTB_BIST_FAILURE , 0x80); /* 0x8A*/
- msr = rdmsr(msrnum); /* read back for pass fail*/
- if ((msr.lo & 0x3030) != 0x3030)
- goto BISTFail;
-
- return;
-
-BISTFail:
- print_err("BIST failed!\n");
- while(1);
-}
/* ***************************************************************************/
/* * cpuRegInit*/
/* ***************************************************************************/
-void
-cpuRegInit (void){
+void cpuRegInit (void)
+{
int msrnum;
msr_t msr;
/* Turn on BTM for early debug based on setup. */
msr.lo |= 0x08;
wrmsr(msrnum, msr);
-
-/* */
-/* BIST*/
-/* */
- /*if (getnvram( TOKEN_BIST_ENABLE) & == TVALUE_DISABLE) {*/
- {
-// BIST();
- }
-
-
/* */
/* Enable BTB*/
/* */
}
#endif
}
-
-
-
-
-/* ***************************************************************************/
-/* **/
-/* * MTestPinCheckBX*/
-/* **/
-/* * Set MTEST pins to expected values from OPTIONS.INC/NVRAM*/
-/* * This version is called when there isn't a stack available*/
-/* **/
-/* ***************************************************************************/
-static void
-MTestPinCheckBX (void){
- int msrnum;
- msr_t msr;
-
- /*if (getnvram( TOKEN_MTEST_ENABLE) ==TVALUE_DISABLE ) {*/
- /* return ; */
- /* } */
-
- /* Turn on MTEST*/
- msrnum = MC_CFCLK_DBUG;
- msr = rdmsr(msrnum);
- msr.hi |= CFCLK_UPPER_MTST_B2B_DIS_SET | CFCLK_UPPER_MTEST_EN_SET;
- wrmsr(msrnum, msr);
-
- msrnum = GLCP_SYS_RSTPLL /* Get SDR/DDR mode from GLCP*/;
- msr = rdmsr(msrnum);
- msr.lo >>= RSTPPL_LOWER_SDRMODE_SHIFT;
- if (msr.lo & 1) {
- msrnum = MC_CFCLK_DBUG; /* Turn on SDR MTEST stuff*/
- msr = rdmsr(msrnum);
- msr.lo |= CFCLK_LOWER_SDCLK_SET;
- msr.hi |= CFCLK_UPPER_MTST_DQS_EN_SET;
- wrmsr(msrnum, msr);
- }
-
- /* Lock the cache down here.*/
- __asm__("wbinvd\n");
-
-}
/* * Destroys: Al,*/
/* **/
/* ***************************************************************************/
-static void
-StartTimer1(void)
+static void StartTimer1(void)
{
outb(0x56, 0x43);
outb(0x12, 0x41);
}
-void
-SystemPreInit(void)
+void SystemPreInit(void)
{
/* they want a jump ... */
- __asm__("jmp .+2\ninvd\njmp.+2\n");
+#ifndef CONFIG_USE_DCACHE_RAM
+ __asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n");
+#endif
StartTimer1();
}
#define VIP_GLD_MSR_CAP (MSR_VIP + 0x2000)
#define VIP_GLD_MSR_CONFIG (MSR_VIP + 0x2001)
#define VIP_GLD_MSR_PM (MSR_VIP + 0x2004)
-#define VIP_BIST (MSR_VIP + 0x2005)
+#define VIP_BIST (MSR_VIP + 0x2005)
+#define VIP_GIO_MSR_SEL (MSR_VIP + 0x2010)
/* */
/* AES GLIU1 port 6*/
/* */
#define AES_GLD_MSR_CAP (MSR_AES + 0x2000)
#define AES_GLD_MSR_CONFIG (MSR_AES + 0x2001)
#define AES_GLD_MSR_PM (MSR_AES + 0x2004)
-#define AES_CONTROL (MSR_AES + 0x2006)
+#define AES_CONTROL (MSR_AES + 0x2006)
/* more fun stuff */
#define BM 1 /* Base Mask - map power of 2 size aligned region*/
#define BMO 2 /* BM with an offset*/
#if !defined(__ROMCC__) && !defined(ASSEMBLY)
#if defined(__PRE_RAM__)
-#else
-void cpubug(void);
+void cpuRegInit(void);
+void SystemPreInit(void);
#endif
+void cpubug(void);
#endif
#endif /* CPU_AMD_GX2DEF_H */
select CPU_AMD_GX2
select NORTHBRIDGE_AMD_GX2
select SOUTHBRIDGE_AMD_CS5536
- select ROMCC
select UDELAY_TSC
+ select USE_DCACHE_RAM
+ select USE_PRINTK_IN_CAR
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_256
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
#include "lib/ramtest.c"
#include "northbridge/amd/gx2/pll_reset.c"
#include "cpu/amd/model_gx2/cpureginit.c"
#include "cpu/amd/model_gx2/syspreinit.c"
-static void msr_init(void)
-{
- /* total physical memory */
- __builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02);
-
- /* traditional memory 0kB-512kB, 512kB-1MB */
- __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
- __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
+#include "cpu/amd/model_lx/msrinit.c"
- __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
- __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
-
- /* put code in northbridge[init].c here */
-}
-
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
static const struct mem_controller memctrl [] = {
{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
SystemPreInit();
-
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
cs5536_early_setup();
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
pll_reset();
cpuRegInit();
select CPU_AMD_GX2
select NORTHBRIDGE_AMD_GX2
select SOUTHBRIDGE_AMD_CS5535
- select ROMCC
select UDELAY_TSC
+ select USE_DCACHE_RAM
+ select USE_PRINTK_IN_CAR
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_256
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
#include "lib/ramtest.c"
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/gx2def.h>
+#include "southbridge/amd/cs5535/cs5535.h"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#include "northbridge/amd/gx2/pll_reset.c"
#include "cpu/amd/model_gx2/cpureginit.c"
#include "cpu/amd/model_gx2/syspreinit.c"
-static void msr_init(void)
-{
- __builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02);
-
- __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
- __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
- __builtin_wrmsr(0x10000026, 0x400fffc0, 0x2cfbc040);
- __builtin_wrmsr(0x10000027, 0xfff00000, 0xff);
- __builtin_wrmsr(0x10000028, 0x7bf00100, 0x2000000f);
- __builtin_wrmsr(0x1000002c, 0xff030003, 0x20000000);
-
- __builtin_wrmsr(0x10000080, 0x3, 0x0);
-
- __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
- __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
- __builtin_wrmsr(0x40000023, 0x400fffc0, 0x20000040);
- __builtin_wrmsr(0x40000024, 0xff4ffffc, 0x200000ef);
- __builtin_wrmsr(0x40000029, 0x7bf00100, 0x2000000f);
- __builtin_wrmsr(0x4000002d, 0xff030003, 0x20000000);
-
- __builtin_wrmsr(0x50002001, 0x27, 0x0);
- __builtin_wrmsr(0x4c002001, 0x1, 0x0);
-}
+#include "cpu/amd/model_lx/msrinit.c"
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
static const struct mem_controller memctrl [] = {
{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
cs5535_early_setup();
print_err("done cs5535 early\n");
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
pll_reset();
print_err("done pll_reset\n");
select CPU_AMD_GX2
select NORTHBRIDGE_AMD_GX2
select SOUTHBRIDGE_AMD_CS5536
- select ROMCC
select UDELAY_TSC
+ select USE_DCACHE_RAM
+ select USE_PRINTK_IN_CAR
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_256
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
#include "lib/ramtest.c"
#include "northbridge/amd/gx2/pll_reset.c"
#include "cpu/amd/model_gx2/cpureginit.c"
#include "cpu/amd/model_gx2/syspreinit.c"
-static void msr_init(void)
-{
- __builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02);
-
- __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
- __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
-
- __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
- __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
-}
+#include "cpu/amd/model_lx/msrinit.c"
static void gpio_init(void)
{
outl(m, GPIOL_EVENTS_ENABLE);
}
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
static const struct mem_controller memctrl [] = {
{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
uart_init();
console_init();
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
pll_reset();
cpuRegInit();
select CPU_AMD_GX2
select NORTHBRIDGE_AMD_GX2
select SOUTHBRIDGE_AMD_CS5536
- select ROMCC
select UDELAY_TSC
+ select USE_DCACHE_RAM
+ select USE_PRINTK_IN_CAR
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_256
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
#include "lib/ramtest.c"
#include "northbridge/amd/gx2/pll_reset.c"
#include "cpu/amd/model_gx2/cpureginit.c"
#include "cpu/amd/model_gx2/syspreinit.c"
-static void msr_init(void)
-{
- __builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02);
-
- __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
- __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
-
- __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
- __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
-}
+#include "cpu/amd/model_lx/msrinit.c"
static void gpio_init(void)
{
outl(m, GPIOL_EVENTS_ENABLE);
}
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
static const struct mem_controller memctrl [] = {
{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
uart_init();
console_init();
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
pll_reset();
cpuRegInit();
select CPU_AMD_GX2
select NORTHBRIDGE_AMD_GX2
select SOUTHBRIDGE_AMD_CS5536
- select ROMCC
select UDELAY_TSC
+ select USE_DCACHE_RAM
+ select USE_PRINTK_IN_CAR
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select BOARD_ROMSIZE_KB_256
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
#include "lib/ramtest.c"
#include "northbridge/amd/gx2/pll_reset.c"
#include "cpu/amd/model_gx2/cpureginit.c"
#include "cpu/amd/model_gx2/syspreinit.c"
+#include "cpu/amd/model_lx/msrinit.c"
-static void msr_init(void)
-{
- /* Setup access to cache under 1MB.
- __builtin_wrmsr(CPU_RCONF_DEFAULT, 0x1000a000, 0x24fffc02); /* Rom Properties: Write Serialize, WriteProtect.
- * RomBase: 0xFFFC0
- * SysTop to RomBase Properties: Write Serialize, Cache Disable.
- * SysTop: 0x000A0
- * System Memory Properties: (Write Back) */
-
- __builtin_wrmsr(CPU_RCONF_A0_BF, 0x00000000, 0x00000000); /* 0xA0000-0xBFFFF : (Write Back) */
- __builtin_wrmsr(CPU_RCONF_C0_DF, 0x00000000, 0x00000000); /* 0xC0000-0xDFFFF : (Write Back) */
- __builtin_wrmsr(CPU_RCONF_E0_FF, 0x00000000, 0x00000000); /* 0xE0000-0xFFFFF : (Write Back) */
-
- /* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */
- __builtin_wrmsr(MSR_GLIU0_BASE1, 0x000fff80, 0x20000000); /* 0x00000-0x7FFFF */
- __builtin_wrmsr(MSR_GLIU0_BASE2, 0x080fffe0, 0x20000000); /* 0x80000-0x9FFFF */
- __builtin_wrmsr(MSR_GLIU0_SHADOW, 0xffff0003, 0x2000ffff); /* 0xC0000-0xFFFFF */
- __builtin_wrmsr(MSR_GLIU1_BASE1, 0x000fff80, 0x20000000); /* 0x00000-0x7FFFF */
- __builtin_wrmsr(MSR_GLIU1_BASE2, 0x080fffe0, 0x20000000); /* 0x80000-0x9FFFF */
- __builtin_wrmsr(MSR_GLIU1_SHADOW, 0xffff0003, 0x2000ffff); /* 0xC0000-0xFFFFF */
-
- /* put code in northbridge[init].c here */
-}
-
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
static const struct mem_controller memctrl [] = {
{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
uart_init();
console_init();
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
pll_reset();
cpuRegInit();
#define CALIBRATE_INTERVAL ((20*CLOCK_TICK_RATE)/1000) /* 20ms */
#define CALIBRATE_DIVISOR (20*1000) /* 20ms / 20000 == 1usec */
+#if 0
static unsigned int calibrate_tsc(void)
{
/* Set the Gate high, disable speaker */
print_err("bad_ctc\n");
return 0;
}
+#endif
/* spll_raw_clk = SYSREF * FbDIV,
* GLIU Clock = spll_raw_clk / MDIV
msr.lo = 0x8ea0ad6a;
wrmsr(0x4c00000f, msr);
- /* Fixes from Jordan Crouse of AMD. */
-
- /* make sure there is nothing stale in the cache */
- __asm__("wbinvd\n");
-
- print_debug("RAM DLL lock\n");
/* The RAM dll needs a write to lock on so generate a few dummy writes */
+ /* Note: The descriptor needs to be enabled to point at memory */
volatile unsigned long *ptr;
- for (i=0;i<5;i++) {
+ for (i = 0; i < 5; i++) {
ptr = (void *)i;
*ptr = (unsigned long)i;
}
+ print_info("RAM DLL lock\n");
+
}
uint16_t channel0[DIMM_SOCKETS];
};
+void sdram_initialize(int controllers, const struct mem_controller *ctrl);
+
#endif /* RAMINIT_H */
#include <cpu/x86/msr.h>
#include <cpu/x86/cache.h>
#include "southbridge/amd/cs5535/cs5535.h"
-// This code uses some cs5536 includes because cs5535 includes are empty:
-#include "southbridge/amd/cs5536/cs5536.h"
/* the structs in this file only set msr.lo. But ... that may not always be true */
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Nils Jacobs
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
#ifndef _CS5535_H
#define _CS5535_H
+/* SouthBridge Equates */
+#define CS5535_GLINK_PORT_NUM 0x02 /* port of the SouthBridge */
+#define NB_PCI ((2 << 29) + (4 << 26)) /* NB GLPCI is in the same location on all Geodes. */
+#define MSR_SB ((CS5535_GLINK_PORT_NUM << 23) + NB_PCI) /* address to the SouthBridge */
+#define SB_SHIFT 20 /* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift. */
+
+#define CS5535_DEV_NUM 0x0F /* default PCI device number for CS5535 */
+#define SMBUS_IO_BASE 0x6000
+#define GPIO_IO_BASE 0x6100
+#define MFGPT_IO_BASE 0x6200
+#define ACPI_IO_BASE 0x9C00
+#define PMS_IO_BASE 0x9D00
+
+/* Cs5536 as follows. */
+/* SB_GLIU */
+/* port0 - GLIU */
+/* port1 - GLPCI */
+/* port2 - USB Controller #2 */
+/* port3 - ATA-5 Controller */
+/* port4 - MDD */
+/* port5 - AC97 */
+/* port6 - USB Controller #1 */
+/* port7 - GLCP */
+
+#define MSR_SB_GLIU ((9 << 14) + MSR_SB) /* 51024xxx or 510*xxxx - fake out just like GL0 on CPU. */
+#define MSR_SB_GLPCI (MSR_SB) /* 5100xxxx - don't go to the GLIU */
+#define MSR_SB_USB2 ((2 << SB_SHIFT) + MSR_SB) /* 5120xxxx */
+#define MSR_SB_ATA ((3 << SB_SHIFT) + MSR_SB) /* 5130xxxx */
+#define MSR_SB_MDD ((4 << SB_SHIFT) + MSR_SB) /* 5140xxxx, a.k.a. DIVIL = Diverse Integrated Logic device */
+#define MSR_SB_AC97 ((5 << SB_SHIFT) + MSR_SB) /* 5150xxxx */
+#define MSR_SB_USB1 ((6 << SB_SHIFT) + MSR_SB) /* 5160xxxx */
+#define MSR_SB_GLCP ((7 << SB_SHIFT) + MSR_SB) /* 5170xxxx */
+
+/* GLIU */
+#define GLIU_SB_GLD_MSR_PM (MSR_SB_GLIU + 0x04)
+
+/* USB1 */
+#define USB1_SB_GLD_MSR_CONF (MSR_SB_USB1 + 0x01)
+#define USB1_SB_GLD_MSR_PM (MSR_SB_USB1 + 0x04)
+
+/* USB2 */
+#define USB2_SB_GLD_MSR_CONF (MSR_SB_USB2 + 0x01)
+#define USB2_SB_GLD_MSR_PM (MSR_SB_USB2 + 0x04)
+
+/* ATA */
+#define ATA_SB_GLD_MSR_CONF (MSR_SB_ATA + 0x01)
+#define ATA_SB_GLD_MSR_ERR (MSR_SB_ATA + 0x03)
+#define ATA_SB_GLD_MSR_PM (MSR_SB_ATA + 0x04)
+
+/* AC97 */
+#define AC97_SB_GLD_MSR_CONF (MSR_SB_AC97 + 0x01)
+#define AC97_SB_GLD_MSR_PM (MSR_SB_AC97 + 0x04)
+
+/* GLPCI */
+#define GLPCI_SB_GLD_MSR_PM (MSR_SB_GLPCI + 0x04)
+#define GLPCI_SB_CTRL (MSR_SB_GLPCI + 0x10)
+#define GLPCI_CRTL_PPIDE_SET (1 << 17)
+
+/* GLCP */
+#define GLCP_SB_GLD_MSR_PM (MSR_SB_GLCP + 0x04)
+
+/* MDD */
+#define MDD_SB_GLD_MSR_CONF (MSR_SB_MDD + 0x01)
+#define MDD_SB_GLD_MSR_PM (MSR_SB_MDD + 0x04)
+#define MDD_LBAR_SMB (MSR_SB_MDD + 0x0B)
+#define MDD_LBAR_GPIO (MSR_SB_MDD + 0x0C)
+#define MDD_LBAR_MFGPT (MSR_SB_MDD + 0x0D)
+#define MDD_LBAR_ACPI (MSR_SB_MDD + 0x0E)
+#define MDD_LBAR_PMS (MSR_SB_MDD + 0x0F)
+#define MDD_LBAR_FLSH0 (MSR_SB_MDD + 0x010)
+#define MDD_LBAR_FLSH1 (MSR_SB_MDD + 0x011)
+#define MDD_LBAR_FLSH2 (MSR_SB_MDD + 0x012)
+#define MDD_LBAR_FLSH3 (MSR_SB_MDD + 0x013)
+#define MDD_PIN_OPT (MSR_SB_MDD + 0x015)
+#define MDD_NORF_CNTRL (MSR_SB_MDD + 0x018)
+
+/* GPIO */
+#define GPIOL_2_SET (1 << 2)
+
+/* GPIO LOW Bank Bit Registers */
+#define GPIOL_INPUT_ENABLE (0x20)
+#define GPIOL_IN_AUX1_SELECT (0x34)
+
+/* FLASH device macros */
+#define FLASH_TYPE_NONE 0 /* No flash device installed */
+#define FLASH_TYPE_NAND 1 /* NAND device */
+
+#define FLASH_IF_MEM 1 /* Memory or memory-mapped I/O interface for Flash device */
+
+/* Flash Memory Mask values */
+#define FLASH_MEM_4K 0xFFFFF000
+
+#if !defined(ASSEMBLY) && !defined(__ROMCC__)
+#if defined(__PRE_RAM__)
+void cs5535_disable_internal_uart(void);
+#else
+void chipsetinit(void);
#endif
+#endif
+
+#endif /* _CS5535_H */
*
*/
-#define CS5535_GLINK_PORT_NUM 0x02 /* the geode link port number to the CS5535 */
-#define CS5535_DEV_NUM 0x0F /* default PCI device number for CS5535 */
-
/**
* @brief Setup PCI IDSEL for CS5535
*
}
}
-static int cs5535_setup_iobase(void)
+static void cs5535_setup_iobase(void)
{
msr_t msr;
-
/* setup LBAR for SMBus controller */
- __builtin_wrmsr(0x5140000b, 0x00006000, 0x0000f001);
+ msr.hi = 0x0000f001;
+ msr.lo = SMBUS_IO_BASE;
+ wrmsr(MDD_LBAR_SMB, msr);
+
/* setup LBAR for GPIO */
- __builtin_wrmsr(0x5140000c, 0x00006100, 0x0000f001);
+ msr.hi = 0x0000f001;
+ msr.lo = GPIO_IO_BASE;
+ wrmsr(MDD_LBAR_GPIO, msr);
+
/* setup LBAR for MFGPT */
- __builtin_wrmsr(0x5140000d, 0x00006200, 0x0000f001);
- /* setup LBAR for ACPI */
- __builtin_wrmsr(0x5140000e, 0x00009c00, 0x0000f001);
- /* setup LBAR for PM Support */
- __builtin_wrmsr(0x5140000f, 0x00009d00, 0x0000f001);
-}
+ msr.hi = 0x0000f001;
+ msr.lo = MFGPT_IO_BASE;
+ wrmsr(MDD_LBAR_MFGPT, msr);
-static void cs5535_setup_power_bottun(void)
-{
- /* not implemented yet */
-#if 0
- pwrBtn_setup:
- ;
- ; Power Button Setup
- ;
- ;mov eax, 0C0020000h ; 4 seconds + lock
- mov eax, 040020000h ; 4 seconds no lock
- mov dx, PMLogic_BASE + 40h
- out dx, eax
-
- ; setup GPIO24, it is the external signal for 5535 vsb_work_aux
- ; which controls all voltage rails except Vstandby & Vmem.
- ; We need to enable, OUT_AUX1 and OUTPUT_ENABLE in this order.
- ; If GPIO24 is not enabled then soft-off will not work.
- mov dx, GPIOH_OUT_AUX1_SELECT
- mov eax, GPIOH_24_SET
- out dx, eax
- mov dx, GPIOH_OUTPUT_ENABLE
- out dx, eax
+ /* setup LBAR for ACPI */
+ msr.hi = 0x0000f001;
+ msr.lo = ACPI_IO_BASE;
+ wrmsr(MDD_LBAR_ACPI, msr);
-#endif
+ /* setup LBAR for PM Support */
+ msr.hi = 0x0000f001;
+ msr.lo = PMS_IO_BASE;
+ wrmsr(MDD_LBAR_PMS, msr);
}
static void cs5535_setup_gpio(void)
//outl(val, 0x6100 + 0x34);
}
-static void cs5535_disable_internal_uart(void)
+void cs5535_disable_internal_uart(void)
{
- /* not implemented yet */
-#if 0
- ; The UARTs default to enabled.
- ; Disable and reset them and configure them later. (SIO init)
- mov ecx, MDD_UART1_CONF
- RDMSR
- mov eax, 1h ; reset
- WRMSR
- mov eax, 0h ; disabled
- WRMSR
-
- mov ecx, MDD_UART2_CONF
- RDMSR
- mov eax, 1h ; reset
- WRMSR
- mov eax, 0h ; disabled
- WRMSR
-
-#endif
}
static void cs5535_setup_cis_mode(void)
msr_t msr;
/* setup CPU interface serial to mode C on both sides */
- msr = __builtin_rdmsr(0x51000010);
+ msr = rdmsr(GLPCI_SB_CTRL);
msr.lo &= ~0x18;
msr.lo |= 0x10;
- __builtin_wrmsr(0x51000010, msr.lo, msr.hi);
+ wrmsr(GLPCI_SB_CTRL, msr);
//Only do this if we are building for 5535
- __builtin_wrmsr(0x54002010, 0x00000002, 0x00000000);
+ msr.lo = 0x2;
+ msr.hi = 0x0;
+ wrmsr(VIP_GIO_MSR_SEL, msr);
}
static void dummy(void)
{
}
-static int cs5535_early_setup(void)
+static void cs5535_early_setup(void)
{
msr_t msr;
#define SMBUS_IO_BASE 0x6000
/* initialization for SMBus Controller */
-static int cs5535_enable_smbus(void)
+static void cs5535_enable_smbus(void)
{
unsigned char val;
val |= (0xEF | SMB_ADD_SAEN);
outb(val, SMBUS_IO_BASE + SMB_ADD);
}
-
-static int smbus_read_byte(unsigned device, unsigned address)
-{
- return do_smbus_read_byte(SMBUS_IO_BASE, device, address-1);
-}
-
-#if 0
-static int smbus_recv_byte(unsigned device)
-{
- return do_smbus_recv_byte(SMBUS_IO_BASE, device);
-}
-
-static int smbus_send_byte(unsigned device, unsigned char val)
-{
- return do_smbus_send_byte(SMBUS_IO_BASE, device, val);
-}
-
-
-static int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
-{
- return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
-}
-#endif
#define SMBUS_STATUS_MASK 0xfbff
#define SMBUS_IO_BASE 0x6000
-
-static void smbus_delay(void)
-{
- outb(0x80, 0x80);
-}
-
-/* generate a smbus start condition */
-static int smbus_start_condition(unsigned smbus_io_base)
-{
- unsigned char val;
- unsigned long loops;
- loops = SMBUS_TIMEOUT;
-
- /* issue a START condition */
- val = inb(smbus_io_base + SMB_CTRL1);
- outb(val | SMB_CTRL1_START, smbus_io_base + SMB_CTRL1);
-
- /* check for bus conflict */
- val = inb(smbus_io_base + SMB_STS);
- if ((val & SMB_STS_BER) != 0)
- return SMBUS_ERROR;
-
- /* check for SDA status */
- do {
- smbus_delay();
- val = inw(smbus_io_base + SMB_STS);
- if ((val & SMB_STS_SDAST) != 0) {
- break;
- }
- } while(--loops);
- return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
-}
-
-static int smbus_check_stop_condition(unsigned smbus_io_base)
-{
- unsigned char val;
- unsigned long loops;
- loops = SMBUS_TIMEOUT;
- /* check for SDA status */
- do {
- smbus_delay();
- val = inw(smbus_io_base + SMB_CTRL1);
- if ((val & SMB_CTRL1_STOP) == 0) {
- break;
- }
- } while(--loops);
- return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
-}
-
-static int smbus_stop_condition(unsigned smbus_io_base)
-{
- unsigned char val;
- val = inb(smbus_io_base + SMB_CTRL1);
- outb(SMB_CTRL1_STOP, smbus_io_base + SMB_CTRL1);
-}
-
-static int smbus_send_slave_address(unsigned smbus_io_base, unsigned char device)
-{
- unsigned char val;
- unsigned long loops;
- loops = SMBUS_TIMEOUT;
-
- /* send the slave address */
- outb(device, smbus_io_base + SMB_SDA);
-
- /* check for bus conflict and NACK */
- val = inb(smbus_io_base + SMB_STS);
- if (((val & SMB_STS_BER) != 0) ||
- ((val & SMB_STS_NEGACK) != 0))
- return SMBUS_ERROR;
-
- /* check for SDA status */
- do {
- smbus_delay();
- val = inw(smbus_io_base + SMB_STS);
- if ((val & SMB_STS_SDAST) != 0) {
- break;
- }
- } while(--loops);
- return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
-}
-
-static int smbus_send_command(unsigned smbus_io_base, unsigned char command)
-{
- unsigned char val;
- unsigned long loops;
- loops = SMBUS_TIMEOUT;
-
- /* send the command */
- outb(command, smbus_io_base + SMB_SDA);
-
- /* check for bus conflict and NACK */
- val = inb(smbus_io_base + SMB_STS);
- if (((val & SMB_STS_BER) != 0) ||
- ((val & SMB_STS_NEGACK) != 0))
- return SMBUS_ERROR;
-
- /* check for SDA status */
- do {
- smbus_delay();
- val = inw(smbus_io_base + SMB_STS);
- if ((val & SMB_STS_SDAST) != 0) {
- break;
- }
- } while(--loops);
- return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
-}
-
-static unsigned char do_smbus_read_byte(unsigned smbus_io_base, unsigned char device, unsigned char address)
-{
- unsigned char val, val1;
-
- smbus_check_stop_condition(smbus_io_base);
-
- smbus_start_condition(smbus_io_base);
-
- smbus_send_slave_address(smbus_io_base, device);
-
- smbus_send_command(smbus_io_base, address);
-
- smbus_start_condition(smbus_io_base);
-
- smbus_send_slave_address(smbus_io_base, device | 0x01);
-
- /* send NACK to slave */
- val = inb(smbus_io_base + SMB_CTRL1);
- outb(val | SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
-
- val = inb(smbus_io_base + SMB_SDA);
-
- //smbus_stop_condition(smbus_io_base);
-
- return val;
-}
projects / coreboot.git / commitdiff