This patch cleans up and clarifies Geode source code comments.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/cpu/amd/model_lx/cpureginit.c b/src/cpu/amd/model_lx/cpureginit.c
index e4a29b9b789d6fc9ab9ae2aaa184fe3fc4e8cc1c..2624b54836e6e1b5d8bc042b7eaa796dc2a2a957 100644 (file)
--- a/src/cpu/amd/model_lx/cpureginit.c
+++ b/src/cpu/amd/model_lx/cpureginit.c
@@ -101,11 +101,6 @@ void SetDelayControl(void)
 ;1              16              400MHz          0x82*10055 0x56960004            4
 ;
 ;2              4,4     400MHz          0x82710000 0x56960004            4
-;2              8,8     400MHz          0xC27100A5 0x56960004            4     *** OUT OF PUBLISHED ENVELOPE ***
-;
-;2             16,4     >333            0xB27100A5 0x56960004            4     *** OUT OF PUBLISHED ENVELOPE ***
-;2             16,8     >333            0xB27100A5 0x56960004            4     *** OUT OF PUBLISHED ENVELOPE ***
-;2             16,16    >333            0xB2710000 0x56960004            4     *** OUT OF PUBLISHED ENVELOPE ***
 ;
 ;1              4               <=333MHz        0x83*100FF 0x56960004            3
 ;1              8               <=333MHz        0x83*100AA 0x56960004            3
@@ -114,9 +109,6 @@ void SetDelayControl(void)
 ;2              4,4     <=333MHz        0x837100A5 0x56960004            3
 ;2              8,8     <=333MHz        0x937100A5 0x56960004            3
 ;
-;2             16,4     <=333MHz        0xB37100A5 0x56960004            3     *** OUT OF PUBLISHED ENVELOPE ***
-;2             16,8     <=333MHz        0xB37100A5 0x56960004            3     *** OUT OF PUBLISHED ENVELOPE ***
-;2             16,16    <=333MHz        0xB37100A5 0x56960004            3     *** OUT OF PUBLISHED ENVELOPE ***
 ;=========================================================================
 ;* - Bit 55 (disable SDCLK 1,3,5) should be set if there is a single DIMM in slot 0,
 ;       but it should be clear for all 2 DIMM settings and if a single DIMM is in slot 1.
@@ -130,9 +122,9 @@ void SetDelayControl(void)
 ;              DIMM     Max MBUS
 ;DIMMs devices  Frequency       MCP 0x4C00000F Setting
 ;----- -------  ---------       ----------------------
-;1              4               400MHz          0xF2F100FF 0x56960004            4                     The MC changes improve Salsa.
-;1              8               400MHz          0xF2F100FF 0x56960004            4                     Delay controls no real change,
-;1              4               <=333MHz        0xF2F100FF 0x56960004            3                     just fixing typo in left side.
+;1              4               400MHz          0xF2F100FF 0x56960004            4                     The No VTT changes improve timing.
+;1              8               400MHz          0xF2F100FF 0x56960004            4
+;1              4               <=333MHz        0xF2F100FF 0x56960004            3
 ;1              8               <=333MHz        0xF2F100FF 0x56960004            3
 ;1              16              <=333MHz        0xF2F100FF 0x56960004            3
 */
@@ -233,8 +225,8 @@ void cpuRegInit(void)
        wrmsr(msrnum, msr);
 
        /*
-          ; Castle performance setting.
-          ; Enable Quack for fewer re-RAS on the MC
+        * LX performance setting.
+        * Enable Quack for fewer re-RAS on the MC
         */
        msrnum = GLIU0_ARB;
        msr = rdmsr(msrnum);

diff --git a/src/cpu/amd/model_lx/vsmsetup.c b/src/cpu/amd/model_lx/vsmsetup.c
index 35c1381187a460b7a0bf2ad2e64ea846378d723d..8ad0a3b41da030371bb390c1e8253af38a7005d1 100644 (file)
--- a/src/cpu/amd/model_lx/vsmsetup.c
+++ b/src/cpu/amd/model_lx/vsmsetup.c
@@ -290,8 +290,7 @@ void do_vsmbios(void)
        /* this is the base of rom on the LX at present. At some point, this has to be
         * much better parameterized
         */
-       /* the VSA starts at the base of rom - 64 */
-       //rom = ((unsigned long) 0) - (ROM_SIZE  + 64*1024);
+
        //VSA is cat onto the end after LB builds
        rom = ((unsigned long)0) - (ROM_SIZE + 36 * 1024);
        buf = (unsigned char *)VSA2_BUFFER;

diff --git a/src/include/cpu/amd/geode_post_code.h b/src/include/cpu/amd/geode_post_code.h
index 5a0e57689a1c5d91e4ea303f06482a4459712d73..72ee5e3cf70ffb95e327d47c1825ae6456df9f1e 100644 (file)
--- a/src/include/cpu/amd/geode_post_code.h
+++ b/src/include/cpu/amd/geode_post_code.h
@@ -19,178 +19,178 @@
 /* standard AMD post definitions -- might as well use them. */
 #define POST_Output_Port                               (0x080) /*      port to write post codes to*/
 
-#define POST_preSioInit                                        (0x000) /* geode.asm*/
-#define POST_clockInit                                 (0x001) /* geode.asm*/
-#define POST_CPURegInit                                        (0x002) /* geode.asm*/
-#define POST_UNREAL                                            (0x003) /* geode.asm*/
-#define POST_CPUMemRegInit                             (0x004) /* geode.asm*/
-#define POST_CPUTest                                   (0x005) /* geode.asm*/
-#define POST_memSetup                                  (0x006) /* geode.asm*/
-#define POST_memSetUpStack                             (0x007) /* geode.asm*/
-#define POST_memTest                                   (0x008) /* geode.asm*/
-#define POST_shadowRom                                 (0x009) /* geode.asm*/
-#define POST_memRAMoptimize                            (0x00A) /* geode.asm*/
-#define POST_cacheInit                                 (0x00B) /* geode.asm*/
-#define POST_northBridgeInit                   (0x00C) /* geode.asm*/
-#define POST_chipsetInit                               (0x00D) /* geode.asm*/
-#define POST_sioTest                                   (0x00E) /* geode.asm*/
-#define POST_pcATjunk                                  (0x00F) /* geode.asm*/
-
-
-#define POST_intTable                                  (0x010) /* geode.asm*/
-#define POST_memInfo                                   (0x011) /* geode.asm*/
-#define POST_romCopy                                   (0x012) /* geode.asm*/
-#define POST_PLLCheck                                  (0x013) /* geode.asm*/
-#define POST_keyboardInit                              (0x014) /* geode.asm*/
-#define POST_cpuCacheOff                               (0x015) /* geode.asm*/
-#define POST_BDAInit                                   (0x016) /* geode.asm*/
-#define POST_pciScan                                   (0x017) /* geode.asm*/
-#define POST_optionRomInit                             (0x018) /* geode.asm*/
-#define POST_ResetLimits                               (0x019) /* geode.asm*/
-#define POST_summary_screen                            (0x01A) /* geode.asm*/
-#define POST_Boot                                              (0x01B) /* geode.asm*/
-#define POST_SystemPreInit                             (0x01C) /* geode.asm*/
-#define POST_ClearRebootFlag                   (0x01D) /* geode.asm*/
-#define POST_GLIUInit                                  (0x01E) /* geode.asm*/
-#define POST_BootFailed                                        (0x01F) /* geode.asm*/
-
-
-#define POST_CPU_ID                                            (0x020) /* cpucpuid.asm*/
-#define POST_COUNTERBROKEN                             (0x021) /* pllinit.asm*/
-#define POST_DIFF_DIMMS                                        (0x022) /* pllinit.asm*/
-#define POST_WIGGLE_MEM_LINES                  (0x023) /* pllinit.asm*/
-#define POST_NO_GLIU_DESC                              (0x024) /* pllinit.asm*/
-#define POST_CPU_LCD_CHECK                             (0x025) /* pllinit.asm*/
-#define POST_CPU_LCD_PASS                              (0x026) /* pllinit.asm*/
-#define POST_CPU_LCD_FAIL                              (0x027) /* pllinit.asm*/
-#define POST_CPU_STEPPING                              (0x028) /* cpucpuid.asm*/
-#define POST_CPU_DM_BIST_FAILURE               (0x029) /* gx2reg.asm*/
-#define POST_CPU_FLAGS                                 (0x02A) /* cpucpuid.asm*/
-#define POST_CHIPSET_ID                                        (0x02b) /* chipset.asm*/
-#define POST_CHIPSET_ID_PASS                   (0x02c) /* chipset.asm*/
-#define POST_CHIPSET_ID_FAIL                   (0x02d) /* chipset.asm*/
-#define POST_CPU_ID_GOOD                               (0x02E) /* cpucpuid.asm*/
-#define POST_CPU_ID_FAIL                               (0x02F) /* cpucpuid.asm*/
+#define POST_preSioInit                                        (0x000)
+#define POST_clockInit                                 (0x001)
+#define POST_CPURegInit                                        (0x002)
+#define POST_UNREAL                                            (0x003)
+#define POST_CPUMemRegInit                             (0x004)
+#define POST_CPUTest                                   (0x005)
+#define POST_memSetup                                  (0x006)
+#define POST_memSetUpStack                             (0x007)
+#define POST_memTest                                   (0x008)
+#define POST_shadowRom                                 (0x009)
+#define POST_memRAMoptimize                            (0x00A)
+#define POST_cacheInit                                 (0x00B)
+#define POST_northBridgeInit                   (0x00C)
+#define POST_chipsetInit                               (0x00D)
+#define POST_sioTest                                   (0x00E)
+#define POST_pcATjunk                                  (0x00F)
+
+
+#define POST_intTable                                  (0x010)
+#define POST_memInfo                                   (0x011)
+#define POST_romCopy                                   (0x012)
+#define POST_PLLCheck                                  (0x013)
+#define POST_keyboardInit                              (0x014)
+#define POST_cpuCacheOff                               (0x015)
+#define POST_BDAInit                                   (0x016)
+#define POST_pciScan                                   (0x017)
+#define POST_optionRomInit                             (0x018)
+#define POST_ResetLimits                               (0x019)
+#define POST_summary_screen                            (0x01A)
+#define POST_Boot                                              (0x01B)
+#define POST_SystemPreInit                             (0x01C)
+#define POST_ClearRebootFlag                   (0x01D)
+#define POST_GLIUInit                                  (0x01E)
+#define POST_BootFailed                                        (0x01F)
+
+
+#define POST_CPU_ID                                            (0x020)
+#define POST_COUNTERBROKEN                             (0x021)
+#define POST_DIFF_DIMMS                                        (0x022)
+#define POST_WIGGLE_MEM_LINES                  (0x023)
+#define POST_NO_GLIU_DESC                              (0x024)
+#define POST_CPU_LCD_CHECK                             (0x025)
+#define POST_CPU_LCD_PASS                              (0x026)
+#define POST_CPU_LCD_FAIL                              (0x027)
+#define POST_CPU_STEPPING                              (0x028)
+#define POST_CPU_DM_BIST_FAILURE               (0x029)
+#define POST_CPU_FLAGS                                 (0x02A)
+#define POST_CHIPSET_ID                                        (0x02b)
+#define POST_CHIPSET_ID_PASS                   (0x02c)
+#define POST_CHIPSET_ID_FAIL                   (0x02d)
+#define POST_CPU_ID_GOOD                               (0x02E)
+#define POST_CPU_ID_FAIL                               (0x02F)
 
 
 
 /*     PCI config*/
-#define P80_PCICFG                                     (0x030) /*      pcispace.asm*/
+#define P80_PCICFG                                     (0x030)
 
 
 /*     PCI io*/
-#define P80_PCIIO                                      (0x040) /*      pcispace.asm*/
+#define P80_PCIIO                                      (0x040)
 
 
 /*     PCI memory*/
-#define P80_PCIMEM                                     (0x050) /*      pcispace.asm*/
+#define P80_PCIMEM                                     (0x050)
 
 
 /*     SIO*/
-#define P80_SIO                                                (0x060)         /*      *sio.asm*/
+#define P80_SIO                                                (0x060)
 
 /*     Memory Setp*/
-#define P80_MEM_SETUP                          (0x070) /* docboot meminit*/
-#define POST_MEM_SETUP                         (0x070) /* memsize.asm*/
-#define ERROR_32BIT_DIMMS                      (0x071) /* memsize.asm*/
-#define POST_MEM_SETUP2                                (0x072) /* memsize.asm*/
-#define POST_MEM_SETUP3                                (0x073) /* memsize.asm*/
-#define POST_MEM_SETUP4                                (0x074) /* memsize.asm*/
-#define POST_MEM_SETUP5                                (0x075) /* memsize.asm*/
-#define POST_MEM_ENABLE                                (0x076) /* memsize.asm*/
-#define ERROR_NO_DIMMS                         (0x077) /* memsize.asm*/
-#define ERROR_DIFF_DIMMS                       (0x078) /* memsize.asm*/
-#define ERROR_BAD_LATENCY                      (0x079) /* memsize.asm*/
-#define ERROR_SET_PAGE                         (0x07a) /* memsize.asm*/
-#define ERROR_DENSITY_DIMM                     (0x07b) /* memsize.asm*/
-#define ERROR_UNSUPPORTED_DIMM         (0x07c) /* memsize.asm*/
-#define ERROR_BANK_SET                         (0x07d) /* memsize.asm*/
-#define POST_MEM_SETUP_GOOD                    (0x07E) /* memsize.asm*/
-#define POST_MEM_SETUP_FAIL                    (0x07F) /* memsize.asm*/
-
-
-#define POST_UserPreInit                               (0x080) /* geode.asm*/
-#define POST_UserPostInit                              (0x081) /* geode.asm*/
-#define POST_Equipment_check                   (0x082) /* geode.asm*/
-#define POST_InitNVRAMBX                               (0x083) /* geode.asm*/
-#define POST_NoPIRTable                                        (0x084) /* pci.asm*/
-#define POST_ChipsetFingerPrintPass            (0x085) /*      prechipsetinit*/
-#define POST_ChipsetFingerPrintFail            (0x086) /*      prechipsetinit*/
-#define POST_CPU_IM_TAG_BIST_FAILURE   (0x087) /*      gx2reg.asm*/
-#define POST_CPU_IM_DATA_BIST_FAILURE  (0x088) /*      gx2reg.asm*/
-#define POST_CPU_FPU_BIST_FAILURE              (0x089) /*      gx2reg.asm*/
-#define POST_CPU_BTB_BIST_FAILURE              (0x08a) /*      gx2reg.asm*/
-#define POST_CPU_EX_BIST_FAILURE               (0x08b) /*      gx2reg.asm*/
-#define POST_Chipset_PI_Test_Fail                      (0x08c) /*      prechipsetinit*/
-#define POST_Chipset_SMBus_SDA_Test_Fail       (0x08d) /*      prechipsetinit*/
-#define POST_BIT_CLK_Fail                              (0x08e) /*      Hawk geode.asm override*/
-
-
-#define POST_STACK_SETUP                               (0x090) /* memstack.asm*/
-#define POST_CPU_PF_BIST_FAILURE               (0x091) /*      gx2reg.asm*/
-#define POST_CPU_L2_BIST_FAILURE               (0x092) /*      gx2reg.asm*/
-#define POST_CPU_GLCP_BIST_FAILURE             (0x093) /*      gx2reg.asm*/
-#define POST_CPU_DF_BIST_FAILURE               (0x094) /*      gx2reg.asm*/
-#define POST_CPU_VG_BIST_FAILURE               (0x095) /*      gx2reg.asm*/
-#define POST_CPU_VIP_BIST_FAILURE              (0x096) /*      gx2reg.asm*/
-#define POST_STACK_SETUP_PASS                  (0x09E) /* memstack.asm*/
-#define POST_STACK_SETUP_FAIL                  (0x09F) /* memstack.asm*/
-
-
-#define POST_PLL_INIT                                  (0x0A0) /* pllinit.asm*/
-#define POST_PLL_MANUAL                                        (0x0A1) /* pllinit.asm*/
-#define POST_PLL_STRAP                                 (0x0A2) /* pllinit.asm*/
-#define POST_PLL_RESET_FAIL                            (0x0A3) /* pllinit.asm*/
-#define POST_PLL_PCI_FAIL                              (0x0A4) /* pllinit.asm*/
-#define POST_PLL_MEM_FAIL                              (0x0A5) /* pllinit.asm*/
-#define POST_PLL_CPU_VER_FAIL                  (0x0A6) /* pllinit.asm*/
-
-
-#define POST_MEM_TESTMEM                       (0x0B0) /* memtest.asm*/
-#define POST_MEM_TESTMEM1                      (0x0B1) /* memtest.asm*/
-#define POST_MEM_TESTMEM2                      (0x0B2) /* memtest.asm*/
-#define POST_MEM_TESTMEM3                      (0x0B3) /* memtest.asm*/
-#define POST_MEM_TESTMEM4                      (0x0B4) /* memtest.asm*/
-#define POST_MEM_TESTMEM_PASS          (0x0BE) /* memtest.asm*/
-#define POST_MEM_TESTMEM_FAIL          (0x0BF) /* memtest.asm*/
-
-
-#define POST_SECUROM_SECBOOT_START             (0x0C0) /* secstart.asm*/
-#define POST_SECUROM_BOOTSRCSETUP              (0x0C1) /* secstart.asm*/
-#define POST_SECUROM_REMAP_FAIL                        (0x0C2) /* secstart.asm*/
-#define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3) /* secstart.asm*/
-#define POST_SECUROM_DCACHESETUP               (0x0C4) /* secstart.asm*/
-#define POST_SECUROM_DCACHESETUP_FAIL  (0x0C5) /* secstart.asm*/
-#define POST_SECUROM_ICACHESETUP               (0x0C6) /* secstart.asm*/
-#define POST_SECUROM_DESCRIPTORSETUP   (0x0C7) /* secstart.asm*/
-#define POST_SECUROM_DCACHESETUPBIOS   (0x0C8) /* secstart.asm*/
-#define POST_SECUROM_PLATFORMSETUP             (0x0C9) /* secstart.asm*/
-#define POST_SECUROM_SIGCHECKBIOS              (0x0CA) /* secstart.asm*/
-#define POST_SECUROM_ICACHESETUPBIOS   (0x0CB) /* secstart.asm*/
-#define POST_SECUROM_PASS                              (0x0CC) /* secstart.asm*/
-#define POST_SECUROM_FAIL                              (0x0CD) /* secstart.asm*/
-
-#define POST_RCONFInitError                            (0x0CE) /* cache.asm*/
-#define POST_CacheInitError                            (0x0CF) /* cache.asm*/
-
-
-#define POST_ROM_PREUNCOMPRESS                 (0x0D0) /* rominit.asm*/
-#define POST_ROM_UNCOMPRESS                            (0x0D1) /* rominit.asm*/
-#define POST_ROM_SMM_INIT                              (0x0D2) /* rominit.asm*/
-#define POST_ROM_VID_BIOS                              (0x0D3) /* rominit.asm*/
-#define POST_ROM_LCDINIT                               (0x0D4) /* rominit.asm*/
-#define POST_ROM_SPLASH                                        (0x0D5) /* rominit.asm*/
-#define POST_ROM_HDDINIT                               (0x0D6) /* rominit.asm*/
-#define POST_ROM_SYS_INIT                              (0x0D7) /* rominit.asm*/
-#define POST_ROM_DMM_INIT                              (0x0D8) /* rominit.asm*/
-#define POST_ROM_TVINIT                                        (0x0D9) /* rominit.asm*/
+#define P80_MEM_SETUP                          (0x070)
+#define POST_MEM_SETUP                         (0x070)
+#define ERROR_32BIT_DIMMS                      (0x071)
+#define POST_MEM_SETUP2                                (0x072)
+#define POST_MEM_SETUP3                                (0x073)
+#define POST_MEM_SETUP4                                (0x074)
+#define POST_MEM_SETUP5                                (0x075)
+#define POST_MEM_ENABLE                                (0x076)
+#define ERROR_NO_DIMMS                         (0x077)
+#define ERROR_DIFF_DIMMS                       (0x078)
+#define ERROR_BAD_LATENCY                      (0x079)
+#define ERROR_SET_PAGE                         (0x07a)
+#define ERROR_DENSITY_DIMM                     (0x07b)
+#define ERROR_UNSUPPORTED_DIMM         (0x07c)
+#define ERROR_BANK_SET                         (0x07d)
+#define POST_MEM_SETUP_GOOD                    (0x07E)
+#define POST_MEM_SETUP_FAIL                    (0x07F)
+
+
+#define POST_UserPreInit                               (0x080)
+#define POST_UserPostInit                              (0x081)
+#define POST_Equipment_check                   (0x082)
+#define POST_InitNVRAMBX                               (0x083)
+#define POST_NoPIRTable                                        (0x084)
+#define POST_ChipsetFingerPrintPass            (0x085)
+#define POST_ChipsetFingerPrintFail            (0x086)
+#define POST_CPU_IM_TAG_BIST_FAILURE   (0x087)
+#define POST_CPU_IM_DATA_BIST_FAILURE  (0x088)
+#define POST_CPU_FPU_BIST_FAILURE              (0x089)
+#define POST_CPU_BTB_BIST_FAILURE              (0x08a)
+#define POST_CPU_EX_BIST_FAILURE               (0x08b)
+#define POST_Chipset_PI_Test_Fail                      (0x08c)
+#define POST_Chipset_SMBus_SDA_Test_Fail       (0x08d)
+#define POST_BIT_CLK_Fail                              (0x08e)
+
+
+#define POST_STACK_SETUP                               (0x090)
+#define POST_CPU_PF_BIST_FAILURE               (0x091)
+#define POST_CPU_L2_BIST_FAILURE               (0x092)
+#define POST_CPU_GLCP_BIST_FAILURE             (0x093)
+#define POST_CPU_DF_BIST_FAILURE               (0x094)
+#define POST_CPU_VG_BIST_FAILURE               (0x095)
+#define POST_CPU_VIP_BIST_FAILURE              (0x096)
+#define POST_STACK_SETUP_PASS                  (0x09E)
+#define POST_STACK_SETUP_FAIL                  (0x09F)
+
+
+#define POST_PLL_INIT                                  (0x0A0)
+#define POST_PLL_MANUAL                                        (0x0A1)
+#define POST_PLL_STRAP                                 (0x0A2)
+#define POST_PLL_RESET_FAIL                            (0x0A3)
+#define POST_PLL_PCI_FAIL                              (0x0A4)
+#define POST_PLL_MEM_FAIL                              (0x0A5)
+#define POST_PLL_CPU_VER_FAIL                  (0x0A6)
+
+
+#define POST_MEM_TESTMEM                       (0x0B0)
+#define POST_MEM_TESTMEM1                      (0x0B1)
+#define POST_MEM_TESTMEM2                      (0x0B2)
+#define POST_MEM_TESTMEM3                      (0x0B3)
+#define POST_MEM_TESTMEM4                      (0x0B4)
+#define POST_MEM_TESTMEM_PASS          (0x0BE)
+#define POST_MEM_TESTMEM_FAIL          (0x0BF)
+
+
+#define POST_SECUROM_SECBOOT_START             (0x0C0)
+#define POST_SECUROM_BOOTSRCSETUP              (0x0C1)
+#define POST_SECUROM_REMAP_FAIL                        (0x0C2)
+#define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3)
+#define POST_SECUROM_DCACHESETUP               (0x0C4)
+#define POST_SECUROM_DCACHESETUP_FAIL  (0x0C5)
+#define POST_SECUROM_ICACHESETUP               (0x0C6)
+#define POST_SECUROM_DESCRIPTORSETUP   (0x0C7)
+#define POST_SECUROM_DCACHESETUPBIOS   (0x0C8)
+#define POST_SECUROM_PLATFORMSETUP             (0x0C9)
+#define POST_SECUROM_SIGCHECKBIOS              (0x0CA)
+#define POST_SECUROM_ICACHESETUPBIOS   (0x0CB)
+#define POST_SECUROM_PASS                              (0x0CC)
+#define POST_SECUROM_FAIL                              (0x0CD)
+
+#define POST_RCONFInitError                            (0x0CE)
+#define POST_CacheInitError                            (0x0CF)
+
+
+#define POST_ROM_PREUNCOMPRESS                 (0x0D0)
+#define POST_ROM_UNCOMPRESS                            (0x0D1)
+#define POST_ROM_SMM_INIT                              (0x0D2)
+#define POST_ROM_VID_BIOS                              (0x0D3)
+#define POST_ROM_LCDINIT                               (0x0D4)
+#define POST_ROM_SPLASH                                        (0x0D5)
+#define POST_ROM_HDDINIT                               (0x0D6)
+#define POST_ROM_SYS_INIT                              (0x0D7)
+#define POST_ROM_DMM_INIT                              (0x0D8)
+#define POST_ROM_TVINIT                                        (0x0D9)
 #define POST_ROM_POSTUNCOMPRESS                        (0x0DE)
 
 
-#define P80_CHIPSET_INIT                               (0x0E0) /* chipset.asm*/
-#define POST_PreChipsetInit                            (0x0E1) /* geode.asm*/
-#define POST_LateChipsetInit                   (0x0E2) /* geode.asm*/
-#define POST_NORTHB_INIT                               (0x0E8) /* northb.asm*/
+#define P80_CHIPSET_INIT                               (0x0E0)
+#define POST_PreChipsetInit                            (0x0E1)
+#define POST_LateChipsetInit                   (0x0E2)
+#define POST_NORTHB_INIT                               (0x0E8)
 
 
-#define POST_INTR_SEG_JUMP                             (0x0F0) /* vector.asm*/
+#define POST_INTR_SEG_JUMP                             (0x0F0)

diff --git a/src/include/cpu/amd/vr.h b/src/include/cpu/amd/vr.h
index 286eaa94c5aa314c07ad352cf73c860d444a7cd2..e98ac86409ad237a91d9d278c305014700c61264 100644 (file)
--- a/src/include/cpu/amd/vr.h
+++ b/src/include/cpu/amd/vr.h
@@ -476,8 +476,6 @@
 
 /*
  * Write to a Virtual Register
- * AX = Class/Index
- * CX = data to write
  */
 static inline void vrWrite(uint16_t wClassIndex, uint16_t wData)
 {
@@ -487,7 +485,6 @@ static inline void vrWrite(uint16_t wClassIndex, uint16_t wData)
 
  /*
  * Read from a Virtual Register
- * AX = Class/Index
  * Returns a 16-bit word of data
  */
 static inline uint16_t vrRead(uint16_t wClassIndex)

diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c
index 7f419e739e9ed0a0a7ff7661fe8be79908433735..4ad67006bb8f0e052371b793394cc4fd6f8dce6f 100644 (file)
--- a/src/northbridge/amd/lx/northbridge.c
+++ b/src/northbridge/amd/lx/northbridge.c
@@ -127,6 +127,7 @@ int sizeram(void)
        int sizem = 0;
        unsigned short dimm;
 
+       /* Get the RAM size from the memory controller as calculated and set by auto_size_dimm() */
        msr = rdmsr(MC_CF07_DATA);
        printk_debug("sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo);
 
@@ -134,14 +135,14 @@ int sizeram(void)
        dimm = msr.hi;
        /* installed? */
        if ((dimm & 7) != 7) {
-               sizem = 4 << ((dimm >> 12) & 0x0F);
+               sizem = 4 << ((dimm >> 12) & 0x0F); /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */
        }
 
        /* dimm 1 */
        dimm = msr.hi >> 16;
        /* installed? */
        if ((dimm & 7) != 7) {
-               sizem += 4 << ((dimm >> 12) & 0x0F);
+               sizem += 4 << ((dimm >> 12) & 0x0F); /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */
        }
 
        printk_debug("sizeram: sizem 0x%xMB\n", sizem);

diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index afbec24a3946614f96abd487907a1b79ed84a7aa..653323619b46ea5d45475a73543755e84358802e 100644 (file)
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -131,14 +131,12 @@ static void pmChipsetInit(void)
 
        /*      PM_SED */
        port = (PMS_IO_BASE + 0x014);
-/*     mov             eax, 0x057642   ; 100ms, works*/
-       val = 0x04601;          /*  5ms */
+       val = 0x04601;          /*  5ms, # of 3.57954MHz clock edges */
        outl(val, port);
 
        /*      PM_SIDD */
        port = (PMS_IO_BASE + 0x020);
-/*     mov             eax, 0x0AEC84   ; 200ms, works*/
-       val = 0x08C02;          /*  10ms */
+       val = 0x08C02;          /*  10ms, # of 3.57954MHz clock edges */
        outl(val, port);
 }
 

diff --git a/src/southbridge/amd/cs5536/cs5536_early_setup.c b/src/southbridge/amd/cs5536/cs5536_early_setup.c
index d534bead90785548ad7cad944355422868712fa7..d6ba0894023fddaedbc4eb953c2a5c1af60dbff0 100644 (file)
--- a/src/southbridge/amd/cs5536/cs5536_early_setup.c
+++ b/src/southbridge/amd/cs5536/cs5536_early_setup.c
@@ -97,10 +97,10 @@ static void cs5536_setup_power_button(void)
        /*      Power Button Setup */
        outl(0x40020000, PMS_IO_BASE + 0x40);
 
-       /* setup GPIO24, it is the external signal for 5536 vsb_work_aux
-        * which controls all voltage rails except Vstandby & Vmem.
+       /* setup WORK_AUX/GPIO24, it is the external signal for 5536
+        * vsb_work_aux controls all voltage rails except Vstandby & Vmem.
         * We need to enable, OUT_AUX1 and OUTPUT_ENABLE in this order.
-        * If GPIO24 is not enabled then soft-off will not work. 
+        * If WORK_AUX/GPIO24 is not enabled then soft-off will not work.
         */
        outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUT_AUX1_SELECT);
        outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
@@ -127,7 +127,7 @@ static void cs5536_disable_internal_uart(void)
 {
        msr_t msr;
        /* The UARTs default to enabled.
-        * Disable and reset them and configure them later. (SIO init) 
+        * Disable and reset them and configure them later. (SIO init)
         */
        msr = rdmsr(MDD_UART1_CONF);
        msr.lo = 1;             // reset