*(.eh_frame);
}
- _bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0 || CONFIG_AMD_AGESA, "Do not use global variables in romstage");
+ _bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0 || CONFIG_CPU_AMD_AGESA, "Do not use global variables in romstage");
}
subdirs-$(CONFIG_CPU_AMD_SC520) += sc520
subdirs-$(CONFIG_CPU_AMD_SOCKET_S1G1) += socket_S1G1
-subdirs-$(CONFIG_AMD_AGESA) += agesa
+subdirs-$(CONFIG_CPU_AMD_AGESA) += agesa
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
-config AMD_AGESA
+config CPU_AMD_AGESA
bool
+ default y if CPU_AMD_AGESA_FAMILY10
+ default y if CPU_AMD_AGESA_FAMILY12
+ default y if CPU_AMD_AGESA_FAMILY14
default y if CPU_AMD_AGESA_FAMILY15
default n
-if AMD_AGESA
+if CPU_AMD_AGESA
config XIP_ROM_SIZE
hex
source src/cpu/amd/agesa/family14/Kconfig
source src/cpu/amd/agesa/family15/Kconfig
-endif # AMD_AGESA
+endif # CPU_AMD_AGESA
ramstage-y += reset.c
#SB800 CIMx share AGESA V5 lib code
-ifneq ($(CONFIG_AMD_AGESA),y)
+ifneq ($(CONFIG_CPU_AMD_AGESA),y)
AGESA_ROOT ?= src/vendorcode/amd/agesa/f14
romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
select ENABLE_APIC_EXT_ID
select GFXUMA
-config AMD_AGESA
- bool
- default y
-
config MAINBOARD_DIR
string
default amd/inagua
select BOARD_ROMSIZE_KB_4096
select GFXUMA
-config AMD_AGESA
- bool
- default y
-
config MAINBOARD_DIR
string
default amd/persimmon
select GFXUMA
select UDELAY_LAPIC
-config AMD_AGESA
- bool
- default y
-
config MAINBOARD_DIR
string
default amd/south_station
select ENABLE_APIC_EXT_ID
select GFXUMA
-config AMD_AGESA
- bool
- default y
-
config MAINBOARD_DIR
string
default amd/torpedo
select GFXUMA
select UDELAY_LAPIC
-config AMD_AGESA
- bool
- default y
-
config MAINBOARD_DIR
string
default amd/union_station
select BOARD_ROMSIZE_KB_4096
select GFXUMA
-config AMD_AGESA
- bool
- default y
-
config MAINBOARD_DIR
string
default asrock/e350m1
ramstage-y += reset.c
#SB800 CIMx share AGESA V5 lib code
-ifneq ($(CONFIG_AMD_AGESA),y)
+ifneq ($(CONFIG_CPU_AMD_AGESA),y)
AGESA_ROOT ?= src/vendorcode/amd/agesa/f14
romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
ramstage-y += reset.c
#SB800 CIMx share AGESA V5 lib code
-ifneq ($(CONFIG_AMD_AGESA),y)
+ifneq ($(CONFIG_CPU_AMD_AGESA),y)
AGESA_ROOT ?= src/vendorcode/amd/agesa/f14
romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
config NORTHBRIDGE_AMD_AGESA
bool
- default AMD_AGESA
+ default CPU_AMD_AGESA
if NORTHBRIDGE_AMD_AGESA