Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3586 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
+ * [15: 0] MrsAddress (Address for MRS/EMRS Commands)
+ * this field specifies the dsata driven on the DRAM address pins
+ * 15-0 for MRS and EMRS commands
+ * [18:16] MrsBank (Bank Address for MRS/EMRS Commands)
+ * this files specifies the data driven on the DRAM bank pins for
+ * the MRS and EMRS commands
* [23:19] reverved
* [23:19] reverved
- * [24:24] SendPchgAll (Send Precharge All Command)
- * Setting this bit causes the DRAM controller to send a precharge all command. This bit is cleared by the hardware after the command completes
+ * [24:24] SendPchgAll (Send Precharge All Command)
+ * Setting this bit causes the DRAM controller to send a precharge
+ * all command. This bit is cleared by the hardware after the
+ * command completes
* [25:25] SendAutoRefresh (Send Auto Refresh Command)
* [25:25] SendAutoRefresh (Send Auto Refresh Command)
- * Setting this bit causes the DRAM controller to send an auto refresh command. This bit is cleared by the hardware after the command completes
+ * Setting this bit causes the DRAM controller to send an auto
+ * refresh command. This bit is cleared by the hardware after the
+ * command completes
* [26:26] SendMrsCmd (Send MRS/EMRS Command)
* [26:26] SendMrsCmd (Send MRS/EMRS Command)
- * Setting this bit causes the DRAM controller to send the MRS or EMRS command defined by the MrsAddress and MrsBank fields. This bit is cleared by the hardware adter the commmand completes
+ * Setting this bit causes the DRAM controller to send the MRS or
+ * EMRS command defined by the MrsAddress and MrsBank fields. This
+ * bit is cleared by the hardware adter the commmand completes
- * Setting this bit causes the DRAM controller to de-assert the memory reset pin. This bit cannot be used to assert the memory reset pin
+ * Setting this bit causes the DRAM controller to de-assert the
+ * memory reset pin. This bit cannot be used to assert the memory
+ * reset pin
* [28:28] AssertCke (Assert CKE)
* [28:28] AssertCke (Assert CKE)
- * setting this bit causes the DRAM controller to assert the CKE pins. This bit cannot be used to de-assert the CKE pins
+ * setting this bit causes the DRAM controller to assert the CKE
+ * pins. This bit cannot be used to de-assert the CKE pins
* [30:29] reverved
* [31:31] EnDramInit (Enable DRAM Initialization)
* [30:29] reverved
* [31:31] EnDramInit (Enable DRAM Initialization)
- * Setting this bit puts the DRAM controller in a BIOS controlled DRAM initialization mode. BIOS must clear this bit aster DRAM initialization is complete.
- */
-// PCI_ADDR(0, 0x18, 2, 0x7C), 0x60f80000, 0,
+ * Setting this bit puts the DRAM controller in a BIOS controlled
+ * DRAM initialization mode. BIOS must clear this bit aster DRAM
- * 0 = DRAM address and control signals are driven for one MEMCLK cycle
- * 1 = One additional MEMCLK of setup time is provided on all DRAM address and control signals except CS, CKE, and ODT; i.e., these signals are drivern for two MEMCLK cycles rather than one
- * when set, this bit indicates that the memory clear function is complete. Only clear by reset. BIOS should not write or read the DRAM until this bit is set by hardware
- * When set to 1, indicates that each entry in the page tables dynamically adjusts the idle cycle limit based on page Conflict/Page Miss (PC/PM) traffic
+ * When set to 1, indicates that each entry in the page tables
+ * dynamically adjusts the idle cycle limit based on page
+ * Conflict/Page Miss (PC/PM) traffic
* [ 8: 6] ILD_lmt ( Idle Cycle Limit)
* 000 = 0 cycles
* 001 = 4 cycles
* 010 = 8 cycles
* 011 = 16 cycles
* 100 = 32 cycles
* [ 8: 6] ILD_lmt ( Idle Cycle Limit)
* 000 = 0 cycles
* 001 = 4 cycles
* 010 = 8 cycles
* 011 = 16 cycles
* 100 = 32 cycles
- * 101 = 64 cycles
+ * 101 = 64 cycles
* 110 = 128 cycles
* 110 = 128 cycles
- * 111 = 256 cycles
+ * 111 = 256 cycles
* [ 9: 9] DramEnabled ( DRAM Enabled)
* [ 9: 9] DramEnabled ( DRAM Enabled)
- * When Set, this bit indicates that the DRAM is enabled, this bit is set by hardware after DRAM initialization or on an exit from self refresh. The DRAM controller is intialized after the
- * hardware-controlled initialization process ( initiated by the F2 0x90[DramInit]) completes or when the BIOS-controlled initialization process completes (F2 0x7c(EnDramInit] is
+ * When Set, this bit indicates that the DRAM is enabled, this
+ * bit is set by hardware after DRAM initialization or on an exit
+ * from self refresh. The DRAM controller is intialized after the
+ * hardware-controlled initialization process ( initiated by the
+ * F2 0x90[DramInit]) completes or when the BIOS-controlled
+ * initialization process completes (F2 0x7c(EnDramInit] is
* written from 1 to 0)
* [23:10] Reserved
* written from 1 to 0)
* [23:10] Reserved
- * [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel B, BIOS should set it to reduce the power consumption)
- * Bit F(1207) M2 Package S1g1 Package
- * 0 N/A MA1_CLK1 N/A
- * 1 N/A MA0_CLK1 MA0_CLK1
- * 2 MA3_CLK N/A N/A
- * 3 MA2_CLK N/A N/A
- * 4 MA1_CLK MA1_CLK0 N/A
- * 5 MA0_CLK MA0_CLK0 MA0_CLK0
- * 6 N/A MA1_CLK2 N/A
- * 7 N/A MA0_CLK2 MA0_CLK2
+ * [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel B,
+ * BIOS should set it to reduce the power consumption)
- set_TT(ctrl, param, DRAM_CONFIG_HIGH, DCH_DcqBypassMax_SHIFT, DCH_DcqBypassMax_MASK,DCH_DcqBypassMax_BASE, DCH_DcqBypassMax_MIN, DCH_DcqBypassMax_MAX, param->DcqByPassMax, "DcqBypassMax"); // value need to be in CMOS
+ set_TT(ctrl, param, DRAM_CONFIG_HIGH, DCH_DcqBypassMax_SHIFT, DCH_DcqBypassMax_MASK,DCH_DcqBypassMax_BASE, DCH_DcqBypassMax_MIN, DCH_DcqBypassMax_MAX, param->DcqByPassMax, "DcqBypassMax"); // value need to be in CMOS