Change-Id: I1abaaa2af4de940584039f9b8c348bb57fb611e0
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/125
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Peter Stuge <peter@stuge.se>
{
device_t dev;
struct resource *res;
- uint32_t dword;
+ u32 dword;
dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x1, 0));
if (dev) {
static void sio_setup(void)
{
- uint32_t dword;
- uint8_t byte;
+ u32 dword;
+ u8 byte;
/* Subject decoding */
byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
- static const uint16_t spd_addr[] = {
+ static const u16 spd_addr[] = {
DIMM0, DIMM1, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,