more fixes for via ... plus a little more spew.

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1164 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c
index 6231d1167ed42b0e5cff4c81df9a224d19b6f7c0..687b102bbea75b67bc746cd707995d6d7e26593a 100644 (file)
--- a/src/boot/hardwaremain.c
+++ b/src/boot/hardwaremain.c
@@ -160,6 +160,7 @@ void hardwaremain(int boot_complete)
 
        /* If we have already booted attempt a hard reboot */
        if (boot_complete) {
+               printk_spew("calling hard_reset\n");
                hard_reset();
        }
        CONFIGURE(CONF_PASS_PRE_PCI);

diff --git a/src/mainboard/via/epia/auto.c b/src/mainboard/via/epia/auto.c
index e5ea66cec142770de55e80e806ea803df71899f0..fe999b06083a7b24a98f66719a6d03c43d07fa3c 100644 (file)
--- a/src/mainboard/via/epia/auto.c
+++ b/src/mainboard/via/epia/auto.c
@@ -50,6 +50,30 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "sdram/generic_sdram.c"
  */
 
+static void
+enable_mainboard_devices(void) {
+  device_t dev;
+  /* dev 0 for southbridge */
+  
+  dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
+  
+  if (dev == PCI_DEV_INVALID) {
+    die("Southbridge not found!!!\n");
+  }
+  pci_write_config8(dev, 0x50, 7);
+  pci_write_config8(dev, 0x51, 0xff);
+}
+
+static void
+enable_shadow_ram(void) {
+  device_t dev = 0; /* no need to look up 0:0.0 */
+  unsigned char shadowreg;
+  /* dev 0 for southbridge */
+  shadowreg = pci_read_config8(dev, 0x63);
+  /* 0xf0000-0xfffff */
+  shadowreg |= 0x30;
+  pci_write_config8(dev, 0x63, shadowreg);
+}
 static void main(void)
 {
   unsigned long x;
@@ -57,10 +81,12 @@ static void main(void)
   outb(5, 0x80);
 
        enable_vt8231_serial();
+       enable_mainboard_devices();
        uart_init();
        console_init();
        
        enable_smbus();
+       enable_shadow_ram();
        /*
        memreset_setup();
         this is way more generic than we need.

diff --git a/src/mainboard/via/epia/irq_tables.c b/src/mainboard/via/epia/irq_tables.c
index b59ce9f1e92744fb94f24d533bcc9bbaa67a7528..894c27dec5cd0f814bb36c510e054b8bc2430782 100644 (file)
--- a/src/mainboard/via/epia/irq_tables.c
+++ b/src/mainboard/via/epia/irq_tables.c
@@ -7,19 +7,26 @@
 
 #include <arch/pirq_routing.h>
 
-
 const struct irq_routing_table intel_irq_routing_table = {
        PIRQ_SIGNATURE, /* u32 signature */
        PIRQ_VERSION,   /* u16 version   */
-       32+16*18,        /* there can be total 18 devices on the bus */
-       1,           /* Where the interrupt router lies (bus) */
-       0x23,           /* Where the interrupt router lies (dev) */
-       0,         /* IRQs devoted exclusively to PCI usage */
-       0x0,         /* Vendor */
-       0x0,         /* Device */
-       0,         /* Crap (miniport) */
+       32+16*5,        /* there can be total 5 devices on the bus */
+       0,              /* Where the interrupt router lies (bus) */
+       0x88,           /* Where the interrupt router lies (dev) */
+       0x1c20,         /* IRQs devoted exclusively to PCI usage */
+       0x1106,         /* Vendor */
+       0x8231,         /* Device */
+       0,              /* Crap (miniport) */
        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-       0x35,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+       0x5e,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
        {
+               /* 8231 ethernet */
+               {0,0x90, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x1, 0},
+               /* 8231 internal */
+               {0,0x88, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x2, 0},
+               /* PCI slot */
+               {0,0xa0, {{0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}}, 0, 0},
+               {0,0x50, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x3, 0},
+               {0,0x98, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0},
        }
 };

diff --git a/targets/via/epia/Config.lb b/targets/via/epia/Config.lb
index 3c7524d250f13a305165dd5dd1e61c8dd6a97b4b..2b80ac4242d3cbd0a0447e3a4fe3f075c3ff5e0b 100644 (file)
--- a/targets/via/epia/Config.lb
+++ b/targets/via/epia/Config.lb
@@ -92,7 +92,8 @@ romimage "normal"
        option LINUXBIOS_EXTRA_VERSION=".0Normal"
        mainboard via/epia
 #      payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
-       payload ../../../../tg3--ide_disk.zelf  
+#      payload ../../../../tg3--ide_disk.zelf  
+       payload ../../../../../lnxieepro100.ebi
 end
 
 romimage "fallback" 
@@ -101,7 +102,8 @@ romimage "fallback"
        option LINUXBIOS_EXTRA_VERSION=".0Fallback"
        mainboard via/epia
 #      payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
-       payload ../../../../tg3--ide_disk.zelf  
+#      payload ../../../../tg3--ide_disk.zelf  
+       payload ../../../../../lnxieepro100.ebi
 end
 
 buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"