#define PCI_DEVICE_ID_VIA_K8T890CE_BR 0xb188
#define PCI_DEVICE_ID_VIA_VT6420_SATA 0x3149
#define PCI_DEVICE_ID_VIA_VT8237R_LPC 0x3227
+#define PCI_DEVICE_ID_VIA_CN700_AGP 0x0314
+#define PCI_DEVICE_ID_VIA_CN700_ERR 0x1314
+#define PCI_DEVICE_ID_VIA_CN700_HOST 0x2314
+#define PCI_DEVICE_ID_VIA_CN700_MEMCTRL 0x3208
+#define PCI_DEVICE_ID_VIA_CN700_PM 0x4314
+#define PCI_DEVICE_ID_VIA_CN700_VLINK 0x7314
+#define PCI_DEVICE_ID_VIA_CN700_BRIDGE 0xB198
+#define PCI_DEVICE_ID_VIA_CN700_VGA 0x3344
#define PCI_VENDOR_ID_SIEMENS 0x110A
#define PCI_DEVICE_ID_SIEMENS_DSCC4 0x2102
--- /dev/null
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+config chip.h
+object vgabios.o
+object northbridge.o
+driver agp.o
+driver vga.o
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "chip.h"
+#include "northbridge.h"
+#include "cn700.h"
+
+/* This is the main AGP device, and only one used when configured for AGP 2.0 */
+static void agp_init(device_t dev)
+{
+ u32 reg32;
+
+ /* Some of this may not be necessary,
+ * it should be handled by the OS */
+ printk_debug("Enabling AGP.\n");
+
+ /* Allow R/W access to AGP registers */
+ pci_write_config8(dev, 0x4d, 0x15);
+
+ /* Setup PCI latency timer */
+ pci_write_config8(dev, 0xd, 0x8);
+
+ /* Set to AGP 3.0 Mode, which should theoretically render the rest of
+ * the registers set here pointless */
+ pci_write_config8(dev, 0x84, 0xb);
+
+ /* AGP Request Queue Size */
+ pci_write_config8(dev, 0x4a, 0x1f);
+ /* AGP Hardware Support (default 0xc4)
+ * 7: AGP SBA Enable (1 to Enable)
+ * 6: AGP Enable
+ * 5: Reserved
+ * 4: Fast Write Enable
+ * 3: AGP8X Mode Enable
+ * 2: AGP4X Mode Enable
+ * 1: AGP2X Mode Enable
+ * 0: AGP1X Mode Enable */
+ pci_write_config8(dev, 0x4b, 0xc4);
+
+ /* Enable AGP Backdoor */
+ pci_write_config8(dev, 0xb5, 0x03);
+
+ /* Set aperture to 32MB */
+ /* TODO: Use config option, explain how it works */
+ pci_write_config32(dev, 0x94, 0x00010f38);
+ /* Set GART Table Base Address (31:12) */
+ pci_write_config32(dev, 0x98, (0x1558 << 12));
+ /* Set AGP Aperture Base */
+ pci_write_config32(dev, 0x10, 0xf8000008);
+
+ /* Enable CPU/PMSTR GART Access */
+ reg32 = pci_read_config8(dev, 0xbf);
+ reg32 |= 0x80;
+ pci_write_config8(dev, 0xbf, reg32);
+
+ /* Enable AGP Aperture. */
+ reg32 = pci_read_config32(dev, 0x94);
+ reg32 |= (3 << 7);
+ pci_write_config32(dev, 0x90, reg32);
+
+ /* AGP Control */
+ pci_write_config8(dev, 0xbc, 0x21);
+ pci_write_config8(dev, 0xbd, 0xd2);
+
+ /* AGP Pad, driving strength, and delay control */
+ /* All this should be constant, seeing as the
+ * VGA controller is onboard */
+ pci_write_config8(dev, 0x40, 0xc7);
+ pci_write_config8(dev, 0x41, 0xdb);
+ pci_write_config8(dev, 0x42, 0x10);
+ pci_write_config8(dev, 0x43, 0xdb);
+ pci_write_config8(dev, 0x44, 0x24);
+
+ /* AGPC CKG Control */
+ pci_write_config8(dev, 0xc0, 0x02);
+ pci_write_config8(dev, 0xc1, 0x02);
+}
+
+static const struct device_operations agp_operations = {
+ .read_resources = cn700_noop,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = agp_init,
+ .ops_pci = 0,
+};
+
+static const struct pci_driver agp_driver __pci_driver = {
+ .ops = &agp_operations,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_CN700_AGP,
+};
+
+/* This is the AGP 3.0 "bridge" @Bus 0 Device 1 Func 0. When using AGP 3.0, the
+config in this device takes presidence. We configure both just to be safe. */
+static void agp_bridge_init(device_t dev)
+{
+ printk_debug("Setting up AGP Bridge device\n");
+ pci_write_config16(dev, 0x4, 0x0007);
+
+ /* Secondary Bus Number */
+ pci_write_config8(dev, 0x19, 0x01);
+ /* Subordinate Bus Number */
+ pci_write_config8(dev, 0x1a, 0x01);
+ /* IO Base */
+ pci_write_config8(dev, 0x1c, 0xd0);
+ /* IO Limit */
+ pci_write_config8(dev, 0x1d, 0xd0);
+
+ /* Memory Base */
+ pci_write_config16(dev, 0x20, 0xfb00);
+ /* Memory Limit */
+ pci_write_config16(dev, 0x22, 0xfcf0);
+ /* Prefetchable Memory Base */
+ pci_write_config16(dev, 0x24, 0xf400);
+ /* Prefetchable Memory Limit */
+ pci_write_config16(dev, 0x26, 0xf7f0);
+ /* Enable VGA Compatible Memory/IO Range */
+ pci_write_config8(dev, 0x3e, 0x08);
+
+ /* Second PCI Bus Control (see datasheet) */
+ pci_write_config8(dev, 0x40, 0x83);
+ pci_write_config8(dev, 0x41, 0x43);
+ pci_write_config8(dev, 0x42, 0xe2);
+ pci_write_config8(dev, 0x43, 0x44);
+ pci_write_config8(dev, 0x44, 0x34);
+ pci_write_config8(dev, 0x45, 0x72);
+}
+
+static const struct device_operations agp_bridge_operations = {
+ .read_resources = cn700_noop,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_bus_enable_resources,
+ .init = agp_bridge_init,
+ .scan_bus = pci_scan_bridge,
+ .ops_pci = 0,
+};
+
+static const struct pci_driver agp_bridge_driver __pci_driver = {
+ .ops = &agp_bridge_operations,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_CN700_BRIDGE,
+};
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+struct northbridge_via_cn700_config
+{
+};
+
+extern struct chip_operations northbridge_via_cn700_ops;
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __ROMCC__
+static void cn700_noop(){}
+#endif
+
+/* VGA stuff */
+#define SR_INDEX 0x3c4
+#define SR_DATA 0x3c5
+#define CRTM_INDEX 0x3b4
+#define CRTM_DATA 0x3b5
+#define CRTC_INDEX 0x3d4
+#define CRTC_DATA 0x3d5
+
+/* Memory Controller Registers */
+#define RANK0_END 0x40
+#define RANK1_END 0x41
+#define RANK2_END 0x42
+#define RANK3_END 0x43
+#define RANK0_START 0x48
+#define RANK1_START 0x49
+#define RANK2_START 0x4a
+#define RANK3_START 0x4b
+#define DDR_PAGE_CTL 0x69
+#define DRAM_REFRESH_COUNTER 0x6a
+#define DRAM_MISC_CTL 0x6b
+#define CH_A_DQS_OUTPUT_DELAY 0x70
+#define CH_A_MD_OUTPUT_DELAY 0x71
+
+/* RAM Init Commands */
+#define RAM_COMMAND_NORMAL 0x0
+#define RAM_COMMAND_NOP 0x1
+#define RAM_COMMAND_PRECHARGE 0x2
+#define RAM_COMMAND_MRS 0x3
+#define RAM_COMMAND_CBR 0x4
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <stdlib.h>
+#include <string.h>
+#include <bitops.h>
+#include <cpu/cpu.h>
+#include "chip.h"
+#include "northbridge.h"
+#include "cn700.h"
+
+static void memctrl_init(device_t dev)
+{
+ u16 reg16;
+
+ pci_write_config8(dev, 0x86, 0x2d);
+
+ /* Set up the vga framebuffer size */
+ reg16 = (log2(CONFIG_VIDEO_MB) << 12) | (1 << 15);
+ pci_write_config16(dev, 0xa0, reg16);
+
+ /* Set up VGA timers */
+ pci_write_config8(dev, 0xa2, 0x44);
+
+ pci_write_config16(dev, 0xb0, 0xaa60);
+ pci_write_config8(dev, 0xb8, 0x08);
+}
+
+static const struct device_operations memctrl_operations = {
+ .read_resources = cn700_noop,
+ .init = memctrl_init,
+};
+
+static const struct pci_driver memctrl_driver __pci_driver = {
+ .ops = &memctrl_operations,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_CN700_MEMCTRL,
+};
+
+static void pci_domain_read_resources(device_t dev)
+{
+ struct resource *resource;
+
+ printk_spew("Entering cn700 pci_domain_read_resources.\n");
+
+ /* Initialize the system wide io space constraints */
+ resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
+ resource->limit = 0xffffUL;
+ resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+ IORESOURCE_ASSIGNED;
+
+ /* Initialize the system wide memory resources constraints */
+ resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
+ resource->limit = 0xffffffffULL;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+ IORESOURCE_ASSIGNED;
+
+ printk_spew("Leaving cn700 pci_domain_read_resources.\n");
+}
+
+static void ram_resource(device_t dev, unsigned long index,
+ unsigned long basek, unsigned long sizek)
+{
+ struct resource *resource;
+
+ if (!sizek) {
+ return;
+ }
+ resource = new_resource(dev, index);
+ resource->base = ((resource_t)basek) << 10;
+ resource->size = ((resource_t)sizek) << 10;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
+ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+}
+
+static void tolm_test(void *gp, struct device *dev, struct resource *new)
+{
+ struct resource **best_p = gp;
+ struct resource *best;
+ best = *best_p;
+ if (!best || (best->base > new->base)) {
+ best = new;
+ }
+ *best_p = best;
+}
+
+static u32 find_pci_tolm(struct bus *bus)
+{
+ print_debug("Entering find_pci_tolm\n");
+ struct resource *min;
+ u32 tolm;
+ min = 0;
+ search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
+ tolm = 0xffffffffUL;
+ if (min && tolm > min->base) {
+ tolm = min->base;
+ }
+ print_debug("Leaving find_pci_tolm\n");
+ return tolm;
+}
+
+static void pci_domain_set_resources(device_t dev)
+{
+ static const u8 ramregs[] = {0x40, 0x41, 0x42, 0x43};
+ device_t mc_dev;
+ u32 pci_tolm;
+
+ printk_spew("Entering cn700 pci_domain_set_resources.\n");
+
+ pci_tolm = find_pci_tolm(&dev->link[0]);
+ mc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_CN700_MEMCTRL, 0);
+
+ if (mc_dev) {
+ unsigned long tomk, tolmk;
+ unsigned char rambits;
+ int i, idx;
+
+ for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
+ unsigned char reg;
+ reg = pci_read_config8(mc_dev, ramregs[i]);
+ rambits += reg;
+ }
+
+ tomk = rambits;
+ /* Compute the Top Of Low Memory, in Kb */
+ tolmk = pci_tolm >> 10;
+ if (tolmk >= tomk) {
+ /* The PCI hole does does not overlap the memory. */
+ tolmk = tomk;
+ }
+ /* Report the memory regions */
+ idx = 10;
+ /* TODO: Hole needed? */
+ ram_resource(dev, idx++, 0, 640); /* first 640k */
+ /* Leave a hole for vga */
+ ram_resource(dev, idx++, 768, (tolmk - 768 -
+ (CONFIG_VIDEO_MB * 1024)));
+ }
+ assign_resources(&dev->link[0]);
+}
+
+static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
+{
+ printk_spew("Entering cn700 pci_domain_scan_bus.\n");
+
+ max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
+ return max;
+}
+
+static const struct device_operations pci_domain_ops = {
+ .read_resources = pci_domain_read_resources,
+ .set_resources = pci_domain_set_resources,
+ .enable_resources = enable_childrens_resources,
+ .init = 0,
+ .scan_bus = pci_domain_scan_bus,
+};
+
+static void cpu_bus_init(device_t dev)
+{
+ initialize_cpus(&dev->link[0]);
+}
+
+static void cpu_bus_noop(device_t dev)
+{
+}
+
+static const struct device_operations cpu_bus_ops = {
+ .read_resources = cpu_bus_noop,
+ .set_resources = cpu_bus_noop,
+ .enable_resources = cpu_bus_noop,
+ .init = cpu_bus_init,
+ .scan_bus = 0,
+};
+
+static void enable_dev(struct device *dev)
+{
+ printk_spew("In cn700 enable_dev for device %s.\n", dev_path(dev));
+
+ /* Set the operations if it is a special bus type */
+ if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+ dev->ops = &pci_domain_ops;
+ pci_set_method(dev);
+ }
+ else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
+ dev->ops = &cpu_bus_ops;
+ }
+}
+
+struct chip_operations northbridge_via_cn700_ops = {
+ CHIP_NAME("VIA CN700 Northbridge")
+ .enable_dev = enable_dev,
+};
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef NORTHBRIDGE_VIA_CN700_H
+#define NORTHBRIDGE_VIA_CN700_H
+
+extern unsigned int cn700_scan_root_bus(device_t root, unsigned int max);
+
+#endif /* NORTHBRIDGE_VIA_CN700_H */
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <spd.h>
+#include <sdram_mode.h>
+#include <delay.h>
+#include "cn700.h"
+
+//#define DEBUG_RAM_SETUP 1
+
+#ifdef DEBUG_RAM_SETUP
+#define PRINT_DEBUG_MEM(x) print_debug(x)
+#define PRINT_DEBUG_MEM_HEX8(x) print_debug_hex8(x)
+#define PRINT_DEBUG_MEM_HEX16(x) print_debug_hex16(x)
+#define PRINT_DEBUG_MEM_HEX32(x) print_debug_hex32(x)
+#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
+#else
+#define PRINT_DEBUG_MEM(x)
+#define PRINT_DEBUG_MEM_HEX8(x)
+#define PRINT_DEBUG_MEM_HEX16(x)
+#define PRINT_DEBUG_MEM_HEX32(x)
+#define DUMPNORTH()
+#endif
+
+static void do_ram_command(device_t dev, u8 command, u32 addr_offset)
+{
+ u8 reg;
+
+ /* TODO: Support for multiple DIMMs. */
+
+ reg = pci_read_config8(dev, DRAM_MISC_CTL);
+ reg &= 0xf8; /* Clear bits 2-0. */
+ reg |= command;
+ pci_write_config8(dev, DRAM_MISC_CTL, reg);
+
+ PRINT_DEBUG_MEM(" Sending RAM command 0x");
+ PRINT_DEBUG_MEM_HEX8(reg);
+ PRINT_DEBUG_MEM(" to 0x");
+ PRINT_DEBUG_MEM_HEX32(0 + addr_offset);
+ PRINT_DEBUG_MEM("\r\n");
+
+ read32(0 + addr_offset);
+}
+
+
+/**
+ * Configure the bus between the cpu and the northbridge. This might be able to
+ * be moved to post-ram code in the future. For the most part, these registers
+ * should not be messed around with. These are too complex to explain short of
+ * copying the datasheets into the comments, but most of these values are from
+ * the BIOS Porting Guide, so they should work on any board. If they don't,
+ * try the values from your factory BIOS.
+ *
+ * TODO: Changing the DRAM frequency doesn't work (hard lockup)
+ *
+ * @param dev The northbridge's CPU Host Interface (D0F2)
+ */
+static void c7_cpu_setup(device_t dev)
+{
+ /* Host bus interface registers (D0F2 0x50-0x67) */
+ /* Request phase control */
+ pci_write_config8(dev, 0x50, 0x88);
+ /* CPU Interface Control */
+ pci_write_config8(dev, 0x51, 0x7a);
+ pci_write_config8(dev, 0x52, 0x6f);
+ /* Arbitration */
+ pci_write_config8(dev, 0x53, 0x88);
+ /* Miscellaneous Control */
+ pci_write_config8(dev, 0x54, 0x10);
+ pci_write_config8(dev, 0x55, 0x16);
+ /* Write Policy */
+ pci_write_config8(dev, 0x56, 0x01);
+ /* Miscellaneous Control */
+ /* DRAM Operating Frequency (Bits 7:5)
+ * 000 : 100MHz 001 : 133MHz
+ * 010 : 166MHz 011 : 200MHz
+ * 100 : 266MHz 101 : 333MHz
+ * 110/111 : Reserved */
+ //pci_write_config8(dev, 0x57, 0x60);//set 200MHz dram clock
+ /* CPU Miscellaneous Control */
+ pci_write_config8(dev, 0x59, 0x60);
+ /* Write Policy */
+ pci_write_config8(dev, 0x5d, 0xb2);
+ /* Bandwidth Timer */
+ pci_write_config8(dev, 0x5e, 0x88);
+ /* CPU Miscellaneous Control */
+ pci_write_config8(dev, 0x5f, 0xc7);
+
+ /* Line DRDY# Timing Control */
+ pci_write_config8(dev, 0x60, 0xff);
+ pci_write_config8(dev, 0x61, 0xff);
+ pci_write_config8(dev, 0x62, 0x0f);
+ /* QW DRDY# Timing Control */
+ pci_write_config8(dev, 0x63, 0xff);
+ pci_write_config8(dev, 0x64, 0xff);
+ pci_write_config8(dev, 0x65, 0x0f);
+ /* Read Line Burst DRDY# Timing Control */
+ pci_write_config8(dev, 0x66, 0xff);
+ pci_write_config8(dev, 0x67, 0x70);
+
+ /* Host Bus IO Circuit (See datasheet) */
+ /* Host Address Pullup/down Driving */
+ pci_write_config8(dev, 0x70, 0x33);
+ pci_write_config8(dev, 0x71, 0x00);
+ pci_write_config8(dev, 0x72, 0x33);
+ pci_write_config8(dev, 0x73, 0x00);
+ /* Miscellaneous Control */
+ pci_write_config8(dev, 0x74, 0x00);
+ /* AGTL+ I/O Circuit */
+ pci_write_config8(dev, 0x75, 0x28);
+ /* AGTL+ Compensation Status */
+ pci_write_config8(dev, 0x76, 0x74);
+ /* AGTL+ Auto Compensation Offest */
+ pci_write_config8(dev, 0x77, 0x00);
+ /* Host FSB CKG Control */
+ pci_write_config8(dev, 0x78, 0x0a);
+ /* Address/Address Clock Output Delay Control */
+ pci_write_config8(dev, 0x79, 0xaa);
+ /* Address Strobe Input Delay Control */
+ pci_write_config8(dev, 0x7a, 0x24);
+ /* Address CKG Rising/Falling Time Control */
+ pci_write_config8(dev, 0x7b, 0x00);
+ /* Address CKG Clock Rising/Falling Time Control */
+ pci_write_config8(dev, 0x7c, 0x00);
+ /* Undefined (can't remember why I did this) */
+ pci_write_config8(dev, 0x7d, 0x6d);
+}
+
+/**
+ * Set up various ram and other control registers statically. Some of these may
+ * not be needed, other should be done with spd info, but that's a project for
+ * the future
+ */
+static void sdram_set_registers(const struct mem_controller *ctrl)
+{
+ /* DQ/DQS Strength Control */
+ pci_write_config8(ctrl->d0f3, 0xd0, 0x88);
+ pci_write_config8(ctrl->d0f3, 0xd1, 0x8b);
+ pci_write_config8(ctrl->d0f3, 0xd2, 0x89);
+ /* SMM and APIC Decoding */
+ pci_write_config8(ctrl->d0f3, 0x86, 0x2d);
+
+ /* Driving selection */
+ /* DQ / DQS ODT Driving and Range Select */
+ pci_write_config8(ctrl->d0f3, 0xd5, 0x8a);
+ /* Memory Pads Driving and Range Select */
+ pci_write_config8(ctrl->d0f3, 0xd6, 0xaa);
+ /* DRAM Driving – Group DQS */
+ pci_write_config8(ctrl->d0f3, 0xe0, 0xee);
+ /* DRAM Driving – Group DQ (DQ, MPD, DQM) */
+ pci_write_config8(ctrl->d0f3, 0xe2, 0xac);//ba
+ /* DRAM Driving – Group CS */
+ pci_write_config8(ctrl->d0f3, 0xe4, 0x66);
+ /* DRAM Driving – Group MA */
+ pci_write_config8(ctrl->d0f3, 0xe8, 0x86);
+ /* DRAM Driving – Group MCLK */
+ pci_write_config8(ctrl->d0f3, 0xe6, 0xaa);
+
+ /* ODT (some are set with driving select above) */
+ /* Memory Pad ODT Pullup / Pulldown Control */
+ pci_write_config8(ctrl->d0f3, 0xd4, 0x0a);
+ /* Memory Ranks ODT Lookup Table */
+ pci_write_config8(ctrl->d0f3, 0xd8, 0x00);//was 1
+ /* Compensation Control */
+ pci_write_config8(ctrl->d0f3, 0xd3, 0x89);//enable auto compensation
+
+ /* MCLKO Phase Control */
+ pci_write_config8(ctrl->d0f3, 0x91, 0x02);
+ /* CS/CKE Clock Phase Control */
+ pci_write_config8(ctrl->d0f3, 0x92, 0x06);
+ /* SCMD/MA Clock Phase Control */
+ pci_write_config8(ctrl->d0f3, 0x93, 0x07);
+ /* Channel A DQS Input Capture Range Control */
+ pci_write_config8(ctrl->d0f3, 0x78, 0x83);
+ /* DQS Input Capture Range Control */
+ /* Set in accordance with the BIOS update note */
+ pci_write_config8(ctrl->d0f3, 0x7a, 0x00);
+ /* DQS Input Delay Offset Control */
+ pci_write_config8(ctrl->d0f3, 0x7c, 0x00);
+ /* SDRAM ODT Control */
+ pci_write_config8(ctrl->d0f3, 0xda, 0x80);
+ /* DQ/DQS CKG Output Delay Control - I */
+ pci_write_config8(ctrl->d0f3, 0xdc, 0xff);
+ /* DQ/DQS CKG Output Delay Control - II */
+ pci_write_config8(ctrl->d0f3, 0xdd, 0xff);
+ /* DQS / DQ CKG Duty Cycle Control */
+ pci_write_config8(ctrl->d0f3, 0xec, 0x88);
+ /* MCLK Output Duty Control */
+ pci_write_config8(ctrl->d0f3, 0xee, 0x00);
+ pci_write_config8(ctrl->d0f3, 0xed, 0x10);
+ /* DQS CKG Input Delay Control */
+ pci_write_config8(ctrl->d0f3, 0xef, 0x10);
+
+ pci_write_config8(ctrl->d0f3, 0x77, 0x9d);
+ pci_write_config8(ctrl->d0f3, 0x79, 0x83);
+ pci_write_config16(ctrl->d0f3, 0x88, 0x0020);
+
+ pci_write_config8(ctrl->d0f4, 0xa7, 0x80);
+
+ /* VLink Control */
+ pci_write_config8(ctrl->d0f7, 0xb0, 0x05);
+ pci_write_config8(ctrl->d0f7, 0xb1, 0x01);
+
+ /* Memory base */
+ pci_write_config16(ctrl->d1f0, 0x20, 0xfb00);
+ /* Memory limit */
+ pci_write_config16(ctrl->d1f0, 0x22, 0xfcf0);
+ /* Prefetch memory base */
+ pci_write_config16(ctrl->d1f0, 0x24, 0xf400);
+ /* Prefetch memory limit */
+ pci_write_config16(ctrl->d1f0, 0x26, 0xf7f0);
+ /* PCI to PCI bridge control */
+ pci_write_config16(ctrl->d1f0, 0x3e, 0x0008);
+
+ /* CPU to PCI flow control 1 */
+ pci_write_config8(ctrl->d1f0, 0x40, 0x83);
+ pci_write_config8(ctrl->d1f0, 0x41, 0xc3);//clear reset error, set to 43
+ pci_write_config8(ctrl->d1f0, 0x42, 0xe2);
+ pci_write_config8(ctrl->d1f0, 0x43, 0x44);
+ pci_write_config8(ctrl->d1f0, 0x44, 0x34);
+ pci_write_config8(ctrl->d1f0, 0x45, 0x72);
+
+ /* Disable cross bank/multi page mode */
+ pci_write_config8(ctrl->d0f3, DDR_PAGE_CTL, 0x80);
+ pci_write_config8(ctrl->d0f3, DRAM_REFRESH_COUNTER, 0x00);
+
+ /* Set WR=5 and RFC */
+ pci_write_config8(ctrl->d0f3, 0x61, 0xc7);
+ /* Set CAS=5 */
+ pci_write_config8(ctrl->d0f3, 0x62, 0xaf);
+ pci_write_config8(ctrl->d0f3, 0x63, 0xca);
+ /* Set to DDR2 sdram, BL=8 (0xc8, 0xc0 for bl=4) */
+ pci_write_config8(ctrl->d0f3, 0x6c, 0xc8);
+ /* Allow manual dll reset */
+ pci_write_config8(ctrl->d0f3, 0x6b, 0x10);
+
+ pci_write_config8(ctrl->d0f3, 0x6e, 0x89);
+ pci_write_config8(ctrl->d0f3, 0x67, 0x50);
+ pci_write_config8(ctrl->d0f3, 0x65, 0xd9);
+
+ /* Only enable bank 1, for now */
+ /* TODO: Multiple, dynamically controlled bank enables */
+ pci_write_config8(ctrl->d0f3, 0x54, 0x80);
+ pci_write_config8(ctrl->d0f3, 0x55, 0x00);
+
+ /* Set to 2T, MA Map type 1.
+ * TODO: Needs to become dynamic */
+ pci_write_config16(ctrl->d0f3, 0x50, 0x0020);
+
+ /* BA0-2 Selection. Don't mess with */
+ pci_write_config8(ctrl->d0f3, 0x52, 0x33);
+ pci_write_config8(ctrl->d0f3, 0x53, 0x3f);
+
+ /* Disable bank interleaving. This feature seems useless anyways */
+ pci_write_config32(ctrl->d0f3, 0x58, 0x00000000);
+ pci_write_config8(ctrl->d0f3, 0x88, 0x08);
+
+ /* Some DQS control stuffs */
+ pci_write_config8(ctrl->d0f3, 0x74, 0x04);
+ pci_write_config8(ctrl->d0f3, 0x75, 0x04);
+ pci_write_config8(ctrl->d0f3, 0x76, 0x00);
+}
+
+/**
+ * Set up dram size according to spd data. Eventually, DRAM timings should be
+ * done in a similar manner.
+ *
+ * @param ctrl The northbridge devices and spd addresses.
+ */
+static void sdram_set_spd_registers(const struct mem_controller *ctrl)
+{
+ u8 spd_data, spd_data2;
+
+ /* DRAM Bank Size */
+ spd_data = spd_read_byte(ctrl->channel0[0],
+ SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
+ /* I know this seems weird. Blame JEDEC/Via. */
+ if(spd_data >= 0x10)
+ spd_data = spd_data >> 1;
+ else
+ spd_data = spd_data << 1;
+
+ /* Check for double sided dimm and adjust size accordingly */
+ spd_data2 = spd_read_byte(ctrl->channel0[0], SPD_NUM_BANKS_PER_SDRAM);
+ /* There should be 4 banks on a single sided dimm,
+ * or 8 on a dual sided one */
+ spd_data = spd_data * (spd_data2 / 4);
+ pci_write_config8(ctrl->d0f3, 0x40, spd_data);
+ /* TODO: The rest of the DIMMs */
+}
+
+static void sdram_enable(device_t dev)
+{
+ int i;
+
+ /* 1. Apply NOP. */
+ PRINT_DEBUG_MEM("RAM Enable 1: Apply NOP\r\n");
+ do_ram_command(dev, RAM_COMMAND_NOP, 0);
+ udelay(200);
+
+ /* 2. Precharge all. */
+ PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\r\n");
+ do_ram_command(dev, RAM_COMMAND_PRECHARGE, 0);
+
+ /* 3. Mode register set. */
+ PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n");
+ do_ram_command(dev, RAM_COMMAND_MRS, 0x2000);//enable dll
+ do_ram_command(dev, RAM_COMMAND_MRS, 0x800);//reset dll
+
+ /* 4. Precharge all again. */
+ PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\r\n");
+ do_ram_command(dev, RAM_COMMAND_PRECHARGE, 0);
+
+ /* 5. Perform 8 refresh cycles. Wait tRC each time. */
+ PRINT_DEBUG_MEM("RAM Enable 3: CBR\r\n");
+ do_ram_command(dev, RAM_COMMAND_CBR, 0);
+ /* First read is actually done by do_ram_command */
+ for(i = 0; i < 7; i++) {
+ udelay(100);
+ read32(0);
+ }
+
+ /* 6. Mode register set. */
+ PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n");
+ //safe value for now, BL=8, WR=5, CAS=5
+ /* (E)MRS values are from the BPG. No direct explanation is given, but
+ * they should somehow conform to the JEDEC DDR2 SDRAM Specification
+ * (JESD79-2C). */
+ do_ram_command(dev, RAM_COMMAND_MRS, 0x0022d8);
+
+ /* 7. Mode register set. */
+ PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n");
+ do_ram_command(dev, RAM_COMMAND_MRS, 0x21c20);//default OCD calibration
+ do_ram_command(dev, RAM_COMMAND_MRS, 0x20020);//exit calibration mode
+
+ /* 8. Normal operation */
+ PRINT_DEBUG_MEM("RAM Enable 5: Normal operation\r\n");
+ do_ram_command(dev, RAM_COMMAND_NORMAL, 0);
+
+ /* Enable multipage mode. */
+ pci_write_config8(dev, DDR_PAGE_CTL, 0x83);
+ /* Enable refresh. */
+ pci_write_config8(dev, DRAM_REFRESH_COUNTER, 0x32);
+
+ /* DQS Tuning: testing on a couple different boards has shown this is
+ * static, or close enough that it can be. Which is good, because the
+ * tuning function used too many registers. */
+ pci_write_config8(dev, CH_A_DQS_OUTPUT_DELAY, 0x00);
+ pci_write_config8(dev, CH_A_MD_OUTPUT_DELAY, 0x03);
+
+ /* Enable VGA device with no memory, add memory later. We need this
+ * here to enable the actual device, otherwise it won't show up until
+ * later and LB will have a fit. */
+ pci_write_config16(dev, 0xa0, (1 << 15));
+ pci_write_config16(dev, 0xa4, 0x0010);
+}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey_osgood@verizon.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef RAMINIT_H
+#define RAMINIT_H
+
+#define DIMM_SOCKETS 1 //Only one works, for now.
+
+struct mem_controller {
+ device_t d0f0, d0f2, d0f3, d0f4, d0f7, d1f0;
+ u8 channel0[DIMM_SOCKETS];
+};
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Note: Some of the VGA control registers are located on the memory controller.
+ Registers are set both in raminit.c and northbridge.c */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <stdlib.h>
+#include <string.h>
+#include <bitops.h>
+#include <cpu/cpu.h>
+#include "chip.h"
+#include "northbridge.h"
+#include "cn700.h"
+
+void write_protect_vgabios(void)
+{
+//Don't bother for now
+}
+
+static void vga_init(device_t dev)
+{
+ u8 reg8;
+
+ print_debug("Copying BOCHS Bios to 0xf000\n");
+/* Copy the BOCHs BIOS from 0xFFFFFFFF - ROM_SIZE - BOCHs size (64k) to 0xf0000
+ This is for compatibility with the VGA ROM's BIOS callbacks */
+ memcpy(0xf0000, (0xFFFFFFFF - ROM_SIZE - 0x10000), 0x10000);
+
+ printk_debug("Initializing VGA\n");
+
+ pci_write_config8(dev, 0x3c, 0xb);
+
+ /* Set memory rate to 200MHz */
+ outb(0x3d, CRTM_INDEX);
+ reg8 = inb(CRTM_DATA);
+ reg8 &= 0x0f;
+ reg8 |= (0x1 << 4);
+ outb(0x3d, CRTM_INDEX);
+ outb(reg8, CRTM_DATA);
+
+ /* Set framebuffer size */
+ reg8 = (CONFIG_VIDEO_MB / 4);
+ outb(0x39, SR_INDEX);
+ outb(reg8, SR_DATA);
+
+
+ pci_write_config8(dev, 0x04, 0x07);
+ pci_write_config8(dev, 0x0d, 0x20);
+ pci_write_config32(dev,0x10, 0xf4000008);
+ pci_write_config32(dev,0x14, 0xfb000000);
+ pci_write_config8(dev, 0x3e, 0x02);
+ pci_write_config8(dev, 0x3c, 0x0a);
+
+
+ printk_debug("INSTALL REAL-MODE IDT\n");
+ setup_realmode_idt();
+ printk_debug("DO THE VGA BIOS\n");
+ do_vgabios();
+ /* VGA seems to work without this, but crash & burn with it */
+ //printk_debug("Enable VGA console\n");
+ //vga_enable_console();
+
+ /* It's not clear if these need to be programmed before or after
+ * the VGA bios runs. Try both, clean up later */
+ /* Set memory rate to 200MHz */
+ outb(0x3d, CRTM_INDEX);
+ reg8 = inb(CRTM_DATA);
+ reg8 &= 0x0f;
+ reg8 |= (0x1 << 4);
+ outb(0x3d, CRTM_INDEX);
+ outb(reg8, CRTM_DATA);
+
+ /* Set framebuffer size (again) */
+ reg8 = (CONFIG_VIDEO_MB / 4);
+ outb(0x39, SR_INDEX);
+ outb(reg8, SR_DATA);
+
+ /* Clear the BOCHs Bios out of memory, so it doesn't confuse linux */
+ memset(0xf0000, 0, 0x10000);
+}
+
+static void vga_read_resources(device_t dev)
+{
+ dev->rom_address = 0xfff80000;
+ dev->on_mainboard=1;
+ pci_dev_read_resources(dev);
+}
+
+
+static const struct device_operations vga_operations = {
+ .read_resources = vga_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = vga_init,
+ .ops_pci = 0,
+};
+
+static const struct pci_driver vga_driver __pci_driver = {
+ .ops = &vga_operations,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_CN700_VGA,
+};
--- /dev/null
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#undef __KERNEL__
+#include <arch/io.h>
+//#include <printk.h>
+#include <string.h>
+#include "vgachip.h"
+
+/* vgabios.c. Derived from: */
+
+/*------------------------------------------------------------ -*- C -*-
+ * 2 Kernel Monte a.k.a. Linux loading Linux on x86
+ *
+ * Erik Arjan Hendriks <hendriks@lanl.gov>
+ *
+ * This version is a derivative of the original two kernel monte
+ * which is (C) 2000 Scyld.
+ *
+ * Copyright (C) 2000 Scyld Computing Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Portions related to the alpha architecture are:
+ *
+ * Copyright(C) 2001 University of California. LA-CC Number 01-67.
+ * This software has been authored by an employee or employees of the
+ * University of California, operator of the Los Alamos National
+ * Laboratory under Contract No. W-7405-ENG-36 with the U.S.
+ * Department of Energy. The U.S. Government has rights to use,
+ * reproduce, and distribute this software. If the software is
+ * modified to produce derivative works, such modified software should
+ * be clearly marked, so as not to confuse it with the version
+ * available from LANL.
+ *
+ * This software may be used and distributed according to the terms
+ * of the GNU General Public License, incorporated herein by
+ * reference to http://www.gnu.org/licenses/gpl.html.
+ *
+ * This software is provided by the author(s) "as is" and any express
+ * or implied warranties, including, but not limited to, the implied
+ * warranties of merchantability and fitness for a particular purpose
+ * are disclaimed. In no event shall the author(s) be liable for any
+ * direct, indirect, incidental, special, exemplary, or consequential
+ * damages (including, but not limited to, procurement of substitute
+ * goods or services; loss of use, data, or profits; or business
+ * interruption) however caused and on any theory of liability,
+ * whether in contract, strict liability, or tort (including
+ * negligence or otherwise) arising in any way out of the use of this
+ * software, even if advised of the possibility of such damage.
+ *
+ * $Id: vgabios.c,v 1.5 2004/10/06 17:33:52 rminnich Exp $
+ *--------------------------------------------------------------------*/
+
+/* Modified to be a self sufficient plug in so that it can be used
+ without reliance on other parts of coreboot's core
+ (C) 2005 Nick.Barker9@btinternet.com
+
+ Used initially for epia-m where there are problems getting the bios
+ emulator to successfully run this bios.
+*/
+
+/* Declare a temporary global descriptor table - necessary because the
+ Core part of the bios no longer sets up any 16 bit segments */
+__asm__ (
+ /* pointer to original gdt */
+ "gdtarg: \n"
+ " .word gdt_limit \n"
+ " .long gdt \n"
+
+ /* compute the table limit */
+ "__mygdt_limit = __mygdt_end - __mygdt - 1 \n"
+
+ "__mygdtaddr: \n"
+ " .word __mygdt_limit \n"
+ " .long __mygdt \n"
+
+ "__mygdt: \n"
+ /* selgdt 0, unused */
+ " .word 0x0000, 0x0000 \n"
+ " .byte 0x00, 0x00, 0x00, 0x00 \n"
+
+ /* selgdt 8, unused */
+ " .word 0x0000, 0x0000 \n"
+ " .byte 0x00, 0x00, 0x00, 0x00 \n"
+
+ /* selgdt 0x10, flat code segment */
+ " .word 0xffff, 0x0000 \n"
+ " .byte 0x00, 0x9b, 0xcf, 0x00 \n"
+
+ /* selgdt 0x18, flat data segment */
+ " .word 0xffff, 0x0000 \n"
+ " .byte 0x00, 0x93, 0xcf, 0x00 \n"
+
+ /* selgdt 0x20, unused */
+ " .word 0x0000, 0x0000 \n"
+ " .byte 0x00, 0x00, 0x00, 0x00 \n"
+
+ /* selgdt 0x28 16-bit 64k code at 0x00000000 */
+ " .word 0xffff, 0x0000 \n"
+ " .byte 0, 0x9a, 0, 0 \n"
+
+ /* selgdt 0x30 16-bit 64k data at 0x00000000 */
+ " .word 0xffff, 0x0000 \n"
+ " .byte 0, 0x92, 0, 0 \n"
+
+ "__mygdt_end: \n"
+);
+
+/* Declare a pointer to where our idt is going to be i.e. at mem zero */
+__asm__ ("__myidt: \n"
+ /* 16-bit limit */
+ " .word 1023 \n"
+ /* 24-bit base */
+ " .long 0 \n"
+ " .word 0 \n"
+);
+
+/* The address arguments to this function are PHYSICAL ADDRESSES */
+static void real_mode_switch_call_vga(unsigned long devfn)
+{
+ __asm__ __volatile__ (
+ // paranoia -- does ecx get saved? not sure. This is
+ // the easiest safe thing to do.
+ " pushal \n"
+ /* save the stack */
+ " mov %esp, __stack \n"
+ " jmp 1f \n"
+ "__stack: .long 0 \n"
+ "1:\n"
+ /* get devfn into %ecx */
+ " movl %esp, %ebp \n"
+ " movl 8(%ebp), %ecx \n"
+ /* load 'our' gdt */
+ " lgdt %cs:__mygdtaddr \n"
+
+ /* This configures CS properly for real mode. */
+ " ljmp $0x28, $__rms_16bit\n"
+ "__rms_16bit: \n"
+ " .code16 \n"
+ /* 16 bit code from here on... */
+
+ /* Load the segment registers w/ properly configured segment
+ * descriptors. They will retain these configurations (limits,
+ * writability, etc.) once protected mode is turned off. */
+ " mov $0x30, %ax \n"
+ " mov %ax, %ds \n"
+ " mov %ax, %es \n"
+ " mov %ax, %fs \n"
+ " mov %ax, %gs \n"
+ " mov %ax, %ss \n"
+
+ /* Turn off protection (bit 0 in CR0) */
+ " movl %cr0, %eax \n"
+ " andl $0xFFFFFFFE, %eax \n"
+ " movl %eax, %cr0 \n"
+
+ /* Now really going into real mode */
+ " ljmp $0, $__rms_real\n"
+ "__rms_real: \n"
+
+ /* put the stack at the end of page zero.
+ * that way we can easily share it between real and protected,
+ * since the 16-bit ESP at segment 0 will work for any case.
+ /* Setup a stack */
+ " mov $0x0, %ax \n"
+ " mov %ax, %ss \n"
+ " movl $0x1000, %eax \n"
+ " movl %eax, %esp \n"
+
+ /* Load our 16 it idt */
+ " xor %ax, %ax \n"
+ " mov %ax, %ds \n"
+ " lidt __myidt \n"
+
+ /* Dump zeros in the other segregs */
+ " mov %ax, %es \n"
+ " mov %ax, %fs \n"
+ " mov %ax, %gs \n"
+ " mov $0x40, %ax \n"
+ " mov %ax, %ds \n"
+ " mov %cx, %ax \n"
+
+ /* run VGA BIOS at 0xc000:0003 */
+ " lcall $0xc000, $0x0003\n"
+
+ /* if we got here, just about done.
+ * Need to get back to protected mode */
+ " movl %cr0, %eax \n"
+ " orl $0x0000001, %eax\n" /* PE = 1 */
+ " movl %eax, %cr0 \n"
+
+ /* Now that we are in protected mode jump to a 32 bit code segment. */
+ " data32 ljmp $0x10, $vgarestart\n"
+ "vgarestart:\n"
+ " .code32\n"
+ " movw $0x18, %ax \n"
+ " mov %ax, %ds \n"
+ " mov %ax, %es \n"
+ " mov %ax, %fs \n"
+ " mov %ax, %gs \n"
+ " mov %ax, %ss \n"
+
+ /* restore proper gdt and idt */
+ " lgdt %cs:gdtarg \n"
+ " lidt idtarg \n"
+
+ ".globl vga_exit \n"
+ "vga_exit: \n"
+ " mov __stack, %esp \n"
+ " popal \n"
+ );
+}
+
+__asm__ (".text\n""real_mode_switch_end:\n");
+extern char real_mode_switch_end[];
+
+/* call vga bios int 10 function 0x4f14 to enable main console
+ epia-m does not always autosence the main console so forcing it on is good !! */
+void vga_enable_console()
+{
+ __asm__ __volatile__ (
+ /* paranoia -- does ecx get saved? not sure. This is
+ * the easiest safe thing to do. */
+ " pushal \n"
+ /* save the stack */
+ " mov %esp, __stack \n"
+
+ /* load 'our' gdt */
+ " lgdt %cs:__mygdtaddr \n"
+
+ /* This configures CS properly for real mode. */
+ " ljmp $0x28, $__vga_ec_16bit\n"
+ "__vga_ec_16bit: \n"
+ " .code16 \n"
+ /* 16 bit code from here on... */
+
+ /* Load the segment registers w/ properly configured segment
+ * descriptors. They will retain these configurations (limits,
+ * writability, etc.) once protected mode is turned off. */
+ " mov $0x30, %ax \n"
+ " mov %ax, %ds \n"
+ " mov %ax, %es \n"
+ " mov %ax, %fs \n"
+ " mov %ax, %gs \n"
+ " mov %ax, %ss \n"
+
+ /* Turn off protection (bit 0 in CR0) */
+ " movl %cr0, %eax \n"
+ " andl $0xFFFFFFFE, %eax\n"
+ " movl %eax, %cr0 \n"
+
+ /* Now really going into real mode */
+ " ljmp $0, $__vga_ec_real \n"
+ "__vga_ec_real: \n"
+
+ /* put the stack at the end of page zero.
+ * that way we can easily share it between real and protected,
+ * since the 16-bit ESP at segment 0 will work for any case.
+ /* Setup a stack */
+ " mov $0x0, %ax \n"
+ " mov %ax, %ss \n"
+ " movl $0x1000, %eax \n"
+ " movl %eax, %esp \n"
+
+ /* debugging for RGM */
+ " mov $0x11, %al \n"
+ " outb %al, $0x80 \n"
+
+ /* Load our 16 it idt */
+ " xor %ax, %ax \n"
+ " mov %ax, %ds \n"
+ " lidt __myidt \n"
+
+ /* Dump zeros in the other segregs */
+ " mov %ax, %ds \n"
+ " mov %ax, %es \n"
+ " mov %ax, %fs \n"
+ " mov %ax, %gs \n"
+
+ /* ask bios to enable main console */
+ /* set up for int 10 call - values found from X server
+ * bios call routines */
+ " movw $0x4f14,%ax \n"
+ " movw $0x8003,%bx \n"
+ " movw $1, %cx \n"
+ " movw $0, %dx \n"
+ " movw $0, %di \n"
+ " int $0x10 \n"
+
+ " movb $0x55, %al \n"
+ " outb %al, $0x80 \n"
+
+ /* if we got here, just about done.
+ * Need to get back to protected mode */
+ " movl %cr0, %eax \n"
+ " orl $0x0000001, %eax\n" /* PE = 1 */
+ " movl %eax, %cr0 \n"
+
+ /* Now that we are in protected mode jump to a 32 bit code segment. */
+ " data32 ljmp $0x10, $vga_ec_restart\n"
+ "vga_ec_restart:\n"
+ " .code32\n"
+ " movw $0x18, %ax \n"
+ " mov %ax, %ds \n"
+ " mov %ax, %es \n"
+ " mov %ax, %fs \n"
+ " mov %ax, %gs \n"
+ " mov %ax, %ss \n"
+
+ /* restore proper gdt and idt */
+ " lgdt %cs:gdtarg \n"
+ " lidt idtarg \n"
+ " .globl vga__ec_exit \n"
+ "vga_ec_exit:\n"
+ " mov __stack, %esp \n"
+ " popal\n"
+ );
+}
+
+void do_vgabios(void)
+{
+ device_t dev;
+ unsigned long busdevfn;
+ unsigned int rom = 0;
+ unsigned char *buf;
+ unsigned int size = 64*1024;
+ int i;
+
+ /* clear vga bios data area */
+ for (i = 0x400; i < 0x500; i++) {
+ *(unsigned char *) i = 0;
+ }
+
+ dev = dev_find_class(PCI_CLASS_DISPLAY_VGA<<8 , 0);
+
+ if (!dev) {
+ printk_debug("NO VGA FOUND\n");
+ return;
+ }
+ printk_debug("found VGA: vid=%x, did=%x\n", dev->vendor, dev->device);
+
+ /* declare rom address here - keep any config data out of the way
+ * of core LXB stuff */
+
+ rom = 0xfff80000;
+ pci_write_config32(dev, PCI_ROM_ADDRESS, rom|1);
+ printk_debug("rom base, size: %x\n", rom);
+
+ buf = (unsigned char *) rom;
+ if ((buf[0] == 0x55) && (buf[1] == 0xaa)) {
+ memcpy((void *) 0xc0000, buf, size);
+
+ write_protect_vgabios(); // in northbridge
+
+ // check signature again
+ buf = (unsigned char *) 0xc0000;
+ if (buf[0]==0x55 && buf[1]==0xAA) {
+ busdevfn = (dev->bus->secondary << 8) | dev->path.u.pci.devfn;
+ printk_debug("bus/devfn = %#x\n", busdevfn);
+
+ real_mode_switch_call_vga(busdevfn);
+ } else
+ printk_debug("Failed to copy VGA BIOS to 0xc0000\n");
+ } else
+ printk_debug("BAD SIGNATURE 0x%x 0x%x\n", buf[0], buf[1]);
+
+ pci_write_config32(dev, PCI_ROM_ADDRESS, 0);
+}
+
+
+// we had hoped to avoid this.
+// this is a stub IDT only. It's main purpose is to ignore calls
+// to the BIOS.
+// no longer. Dammit. We have to respond to these.
+struct realidt {
+ unsigned short offset, cs;
+};
+
+// from a handy writeup that andrey found.
+
+// handler.
+// There are some assumptions we can make here.
+// First, the Top Of Stack (TOS) is located on the top of page zero.
+// we can share this stack between real and protected mode.
+// that simplifies a lot of things ...
+// we'll just push all the registers on the stack as longwords,
+// and pop to protected mode.
+// second, since this only ever runs as part of coreboot,
+// we know all the segment register values -- so we don't save any.
+// keep the handler that calls things small. It can do a call to
+// more complex code in coreboot itself. This helps a lot as we don't
+// have to do address fixup in this little stub, and calls are absolute
+// so the handler is relocatable.
+void handler(void)
+{
+ __asm__ __volatile__ (
+ " .code16 \n"
+ "idthandle: \n"
+ " pushal \n"
+ " movb $0, %al \n"
+ " ljmp $0, $callbiosint16\n"
+ "end_idthandle: \n"
+ " .code32 \n"
+ );
+}
+
+void debughandler(void)
+{
+ __asm__ __volatile__ (
+ " .code16 \n"
+ "debughandle: \n"
+ " pushw %cx \n"
+ " movw $250, %cx \n"
+ "dbh1: \n"
+ " loop dbh1 \n"
+ " popw %cx \n"
+ " iret \n"
+ "end_debughandle: \n"
+ ".code32 \n"
+ );
+}
+
+// Calling conventions. The first C function is called with this stuff
+// on the stack. They look like value parameters, but note that if you
+// modify them they will go back to the INTx function modified.
+// the C function will call the biosint function with these as
+// REFERENCE parameters. In this way, we can easily get
+// returns back to the INTx caller (i.e. vgabios)
+void callbiosint(void)
+{
+ __asm__ __volatile__ (
+ " .code16 \n"
+ "callbiosint16: \n"
+ " push %ds \n"
+ " push %es \n"
+ " push %fs \n"
+ " push %gs \n"
+ // clean up the int #. To save space we put it in the lower
+ // byte. But the top 24 bits are junk.
+ " andl $0xff, %eax\n"
+ // this push does two things:
+ // - put the INT # on the stack as a parameter
+ // - provides us with a temp for the %cr0 mods.
+ " pushl %eax \n"
+ " movl %cr0, %eax\n"
+ " orl $0x00000001, %eax\n" /* PE = 1 */
+ " movl %eax, %cr0\n"
+ /* Now that we are in protected mode jump to a 32 bit code segment. */
+ " data32 ljmp $0x10, $biosprotect\n"
+ "biosprotect: \n"
+ " .code32 \n"
+ " movw $0x18, %ax \n"
+ " mov %ax, %ds \n"
+ " mov %ax, %es \n"
+ " mov %ax, %fs \n"
+ " mov %ax, %gs \n"
+ " mov %ax, %ss \n"
+ " lidt idtarg \n"
+ " call biosint \n"
+ // back to real mode ...
+ " ljmp $0x28, $__rms_16bit2\n"
+ "__rms_16bit2: \n"
+ " .code16 \n"
+ /* 16 bit code from here on... */
+ /* Load the segment registers w/ properly configured segment
+ * descriptors. They will retain these configurations (limits,
+ * writability, etc.) once protected mode is turned off. */
+ " mov $0x30, %ax \n"
+ " mov %ax, %ds \n"
+ " mov %ax, %es \n"
+ " mov %ax, %fs \n"
+ " mov %ax, %gs \n"
+ " mov %ax, %ss \n"
+
+ /* Turn off protection (bit 0 in CR0) */
+ " movl %cr0, %eax \n"
+ " andl $0xFFFFFFFE, %eax \n"
+ " movl %eax, %cr0 \n"
+
+ /* Now really going into real mode */
+ " ljmp $0, $__rms_real2 \n"
+ "__rms_real2: \n"
+
+ /* Setup a stack
+ * FixME: where is esp? */
+ " mov $0x0, %ax \n"
+ " mov %ax, %ss \n"
+
+ /* ebugging for RGM */
+ " mov $0x11, %al \n"
+ " outb %al, $0x80 \n"
+
+ /* Load our 16 it idt */
+ " xor %ax, %ax \n"
+ " mov %ax, %ds \n"
+ " lidt __myidt \n"
+
+ /* Dump zeros in the other segregs */
+ " mov %ax, %es \n"
+ " mov %ax, %fs \n"
+ " mov %ax, %gs \n"
+ " mov $0x40, %ax \n"
+ " mov %ax, %ds \n"
+
+ /* pop the INT # that you pushed earlier */
+ " popl %eax \n"
+ " pop %gs \n"
+ " pop %fs \n"
+ " pop %es \n"
+ " pop %ds \n"
+ " popal \n"
+ " iret \n"
+ " .code32 \n"
+ );
+}
+
+enum {
+ PCIBIOS = 0x1a,
+ MEMSIZE = 0x12
+};
+
+int pcibios(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp,
+ unsigned long *pesp, unsigned long *pebx, unsigned long *pedx,
+ unsigned long *pecx, unsigned long *peax, unsigned long *pflags);
+
+int handleint21(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp,
+ unsigned long *pesp, unsigned long *pebx, unsigned long *pedx,
+ unsigned long *pecx, unsigned long *peax, unsigned long *pflags
+ );
+
+extern void vga_exit(void);
+
+int biosint(unsigned long intnumber,
+ unsigned long gsfs, unsigned long dses,
+ unsigned long edi, unsigned long esi,
+ unsigned long ebp, unsigned long esp,
+ unsigned long ebx, unsigned long edx,
+ unsigned long ecx, unsigned long eax,
+ unsigned long cs_ip, unsigned short stackflags)
+{
+ unsigned long ip;
+ unsigned long cs;
+ unsigned long flags;
+ int ret = -1;
+
+ ip = cs_ip & 0xffff;
+ cs = cs_ip >> 16;
+ flags = stackflags;
+
+ printk_debug("biosint: INT# 0x%lx\n", intnumber);
+ printk_debug("biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n",
+ eax, ebx, ecx, edx);
+ printk_debug("biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n",
+ ebp, esp, edi, esi);
+ printk_debug("biosint: ip 0x%x cs 0x%x flags 0x%x\n",
+ ip, cs, flags);
+
+ // cases in a good compiler are just as good as your own tables.
+ switch (intnumber) {
+ case 0 ... 15:
+ // These are not BIOS service, but the CPU-generated exceptions
+ printk_info("biosint: Oops, exception %u\n", intnumber);
+ if (esp < 0x1000) {
+ printk_debug("Stack contents: ");
+ while (esp < 0x1000) {
+ printk_debug("0x%04x ", *(unsigned short *) esp);
+ esp += 2;
+ }
+ printk_debug("\n");
+ }
+ printk_debug("biosint: Bailing out\n");
+ // "longjmp"
+ vga_exit();
+ break;
+
+ case PCIBIOS:
+ ret = pcibios( &edi, &esi, &ebp, &esp,
+ &ebx, &edx, &ecx, &eax, &flags);
+ break;
+ case MEMSIZE:
+ // who cares.
+ eax = 64 * 1024;
+ ret = 0;
+ break;
+ case 0x15:
+ ret=handleint21( &edi, &esi, &ebp, &esp,
+ &ebx, &edx, &ecx, &eax, &flags);
+ break;
+ default:
+ printk_info("BIOSINT: Unsupport int #0x%x\n",
+ intnumber);
+ break;
+ }
+ if (ret)
+ flags |= 1; // carry flags
+ else
+ flags &= ~1;
+ stackflags = flags;
+ return ret;
+}
+
+
+void setup_realmode_idt(void)
+{
+ extern unsigned char idthandle, end_idthandle;
+ extern unsigned char debughandle, end_debughandle;
+
+ int i;
+ struct realidt *idts = (struct realidt *) 0;
+ int codesize = &end_idthandle - &idthandle;
+ unsigned char *intbyte, *codeptr;
+
+ // for each int, we create a customized little handler
+ // that just pushes %ax, puts the int # in %al,
+ // then calls the common interrupt handler.
+ // this necessitated because intel didn't know much about
+ // architecture when they did the 8086 (it shows)
+ // (hmm do they know anymore even now :-)
+ // obviously you can see I don't really care about memory
+ // efficiency. If I did I would probe back through the stack
+ // and get it that way. But that's really disgusting.
+ for (i = 0; i < 256; i++) {
+ idts[i].cs = 0;
+ codeptr = (char*) 4096 + i * codesize;
+ idts[i].offset = (unsigned) codeptr;
+ memcpy(codeptr, &idthandle, codesize);
+ intbyte = codeptr + 3;
+ *intbyte = i;
+ }
+
+ // fixed entry points
+
+ // VGA BIOSes tend to hardcode f000:f065 as the previous handler of
+ // int10.
+ // calling convention here is the same as INTs, we can reuse
+ // the int entry code.
+ codeptr = (char*) 0xff065;
+ memcpy(codeptr, &idthandle, codesize);
+ intbyte = codeptr + 3;
+ *intbyte = 0x42; /* int42 is the relocated int10 */
+
+ /* debug handler - useful to set a programmable delay between instructions if the
+ TF bit is set upon call to real mode */
+ idts[1].cs = 0;
+ idts[1].offset = 16384;
+ memcpy(16384, &debughandle, &end_debughandle - &debughandle);
+
+
+}
+
+
+
+enum {
+ CHECK = 0xb001,
+ FINDDEV = 0xb102,
+ READCONFBYTE = 0xb108,
+ READCONFWORD = 0xb109,
+ READCONFDWORD = 0xb10a,
+ WRITECONFBYTE = 0xb10b,
+ WRITECONFWORD = 0xb10c,
+ WRITECONFDWORD = 0xb10d
+};
+
+// errors go in AH. Just set these up so that word assigns
+// will work. KISS.
+enum {
+ PCIBIOS_NODEV = 0x8600,
+ PCIBIOS_BADREG = 0x8700
+};
+
+int
+pcibios(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp,
+ unsigned long *pesp, unsigned long *pebx, unsigned long *pedx,
+ unsigned long *pecx, unsigned long *peax, unsigned long *pflags)
+{
+ unsigned long edi = *pedi;
+ unsigned long esi = *pesi;
+ unsigned long ebp = *pebp;
+ unsigned long esp = *pesp;
+ unsigned long ebx = *pebx;
+ unsigned long edx = *pedx;
+ unsigned long ecx = *pecx;
+ unsigned long eax = *peax;
+ unsigned long flags = *pflags;
+ unsigned short func = (unsigned short) eax;
+ int retval = 0;
+ unsigned short devid, vendorid, devfn;
+ short devindex; /* Use short to get rid of garbage in upper half of 32-bit register */
+ unsigned char bus;
+ device_t dev;
+
+ switch(func) {
+ case CHECK:
+ *pedx = 0x4350;
+ *pecx = 0x2049;
+ retval = 0;
+ break;
+ case FINDDEV:
+ {
+ devid = *pecx;
+ vendorid = *pedx;
+ devindex = *pesi;
+ dev = 0;
+ while ((dev = dev_find_device(vendorid, devid, dev))) {
+ if (devindex <= 0)
+ break;
+ devindex--;
+ }
+ if (dev) {
+ unsigned short busdevfn;
+ *peax = 0;
+ // busnum is an unsigned char;
+ // devfn is an int, so we mask it off.
+ busdevfn = (dev->bus->secondary << 8)
+ | (dev->path.u.pci.devfn & 0xff);
+ printk_debug("0x%x: return 0x%x\n", func, busdevfn);
+ *pebx = busdevfn;
+ retval = 0;
+ } else {
+ *peax = PCIBIOS_NODEV;
+ retval = -1;
+ }
+ }
+ break;
+ case READCONFDWORD:
+ case READCONFWORD:
+ case READCONFBYTE:
+ case WRITECONFDWORD:
+ case WRITECONFWORD:
+ case WRITECONFBYTE:
+ {
+ unsigned long dword;
+ unsigned short word;
+ unsigned char byte;
+ unsigned char reg;
+
+ devfn = *pebx & 0xff;
+ bus = *pebx >> 8;
+ reg = *pedi;
+ dev = dev_find_slot(bus, devfn);
+ if (! dev) {
+ printk_debug("0x%x: BAD DEVICE bus %d devfn 0x%x\n", func, bus, devfn);
+ // idiots. the pcibios guys assumed you'd never pass a bad bus/devfn!
+ *peax = PCIBIOS_BADREG;
+ retval = -1;
+ }
+ switch(func) {
+ case READCONFBYTE:
+ byte = pci_read_config8(dev, reg);
+ *pecx = byte;
+ break;
+ case READCONFWORD:
+ word = pci_read_config16(dev, reg);
+ *pecx = word;
+ break;
+ case READCONFDWORD:
+ dword = pci_read_config32(dev, reg);
+ *pecx = dword;
+ break;
+ case WRITECONFBYTE:
+ byte = *pecx;
+ pci_write_config8(dev, reg, byte);
+ break;
+ case WRITECONFWORD:
+ word = *pecx;
+ pci_write_config16(dev, reg, word);
+ break;
+ case WRITECONFDWORD:
+ dword = *pecx;
+ pci_write_config32(dev, reg, dword);
+ break;
+ }
+
+ if (retval)
+ retval = PCIBIOS_BADREG;
+ printk_debug("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n",
+ func, bus, devfn, reg, *pecx);
+ *peax = 0;
+ retval = 0;
+ }
+ break;
+ default:
+ printk_err("UNSUPPORTED PCIBIOS FUNCTION 0x%x\n", func);
+ break;
+ }
+
+ return retval;
+}
+
+int handleint21(unsigned long *edi, unsigned long *esi, unsigned long *ebp,
+ unsigned long *esp, unsigned long *ebx, unsigned long *edx,
+ unsigned long *ecx, unsigned long *eax, unsigned long *flags)
+{
+ int res=-1;
+ switch(*eax&0xffff)
+ {
+ case 0x5f19:
+ break;
+ case 0x5f18:
+ *eax=0x5f;
+ *ebx=0x545; // MCLK = 133, 32M frame buffer, 256 M main memory
+ *ecx=0x060;
+ res=0;
+ break;
+ case 0x5f00:
+ *eax = 0x8600;
+ break;
+ case 0x5f01:
+ *eax = 0x5f;
+ *ecx = (*ecx & 0xffffff00 ) | 2; // panel type = 2 = 1024 * 768
+ res = 0;
+ break;
+ case 0x5f02:
+ *eax=0x5f;
+ *ebx= (*ebx & 0xffff0000) | 2;
+ *ecx= (*ecx & 0xffff0000) | 0x401; // PAL + crt only
+ *edx= (*edx & 0xffff0000) | 0; // TV Layout - default
+ res=0;
+ break;
+ case 0x5f0f:
+ *eax=0x860f;
+ break;
+ }
+ return res;
+}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _PC80_VGABIOS
+#define _PC80_VGABIOS
+
+extern struct chip_control pc80_vgabios_control;
+
+struct pc80_vgabios_config {
+ int nothing;
+};
+
+#endif /* _PC80_VGABIOS */
projects / coreboot.git / commitdiff