+ meminfo->is_64MuxMode = 0;
+
+ /* single dimm */
+ if ((meminfo->dimm_mask & ((1 << DIMM_SOCKETS) - 1)) !=
+ ((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
+ if (((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
+ /* mux capable and single dimm in channelB */
+ if (mux_cap) {
+ printk_spew("Enable 64MuxMode & BurstLength32\n");
+ dcm = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
+ dcm |= DCM_Mode64BitMux;
+ pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dcm);
+ dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+ //dcl |= DCL_BurstLength32; /* 32byte mode for channelB only */
+ pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
+ meminfo->is_64MuxMode = 1;
+ } else {
+ meminfo->dimm_mask &= ~((1 << (DIMM_SOCKETS * 2)) - (1 << DIMM_SOCKETS));
+ }
+ }
+ } else { /* unmatched dual dimms ? */
+ /* unmatched dual dimms not supported by meminit code. Use single channelA dimm. */
+ meminfo->dimm_mask &= ~((1 << (DIMM_SOCKETS * 2)) - (1 << DIMM_SOCKETS));
+ printk_spew("Unmatched dual dimms. Use single channelA dimm.\n");
+ }
+ return meminfo->dimm_mask;