$(eval $(call evaluate_subdirs))
-define c_dsl_template
-$(obj)/$(1)%.c: src/$(1)%.dsl $(obj)/build.h
+define objs_dsl_template
+$(obj)/$(1)%.o: src/$(1)%.asl
@printf " IASL $$(subst $$(shell pwd)/,,$$(@))\n"
- iasl -p $$(basename $$@) -tc $$<
- perl -pi -e 's/AmlCode/AmlCode_$$(notdir $$(basename $$@))/g' $$(basename $$@).hex
- mv $$(basename $$@).hex $$@
+ $(CPP) -D__ACPI__ -P $(CPPFLAGS) -include $(obj)/config.h -I$(src) -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$(basename $$@).asl
+ iasl -p $$(basename $$@) -tc $$(basename $$@).asl
+ mv $$(basename $$@).hex $$(basename $$@).c
+ $(CC) -m32 $$(CFLAGS) $$(if $$(subst dsdt,,$$(basename $$(notdir $$@))), -DAmlCode=AmlCode_$$(basename $$(notdir $$@))) -c -o $$@ $$(basename $$@).c
endef
define objs_c_template
usetemplate=$(foreach d,$(sort $(dir $($(1)))),$(eval $(call $(1)_$(2)_template,$(subst $(obj)/,,$(d)))))
usetemplate=$(foreach d,$(sort $(dir $($(1)))),$(eval $(call $(1)_$(2)_template,$(subst $(obj)/,,$(d)))))
-$(eval $(call usetemplate,c,dsl))
+$(eval $(call usetemplate,objs,dsl))
$(eval $(call usetemplate,objs,c))
$(eval $(call usetemplate,objs,S))
$(eval $(call usetemplate,initobjs,c))
ifdef POST_EVALUATION
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.dsl
- iasl -p $(obj)/mainboard/$(MAINBOARDDIR)/dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.dsl
- mv $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
ifdef POST_EVALUATION
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.dsl
- iasl -p $(obj)/mainboard/$(MAINBOARDDIR)/dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.dsl
- mv $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
ifdef POST_EVALUATION
-$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/acpi/dsdt.asl
- iasl -p $(obj)/dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/acpi/dsdt.asl
- mv $(obj)/dsdt.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
0x00010001
)
{
- Include ("debug.asl")
+ #include "debug.asl"
}
*/
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* DefinitionBlock Statement */
-DefinitionBlock (
- "DSDT.AML", /* Output filename */
- "DSDT", /* Signature */
- 0x02, /* DSDT Revision, needs to be 2 for 64bit */
- "AMD ", /* OEMID */
- "DBM690T ", /* TABLE ID */
- 0x00010001 /* OEM Revision */
- )
-{ /* Start of ASL file */
- /* Include ("debug.asl") */ /* Include global debug methods if needed */
-
- /* Data to be patched by the BIOS during POST */
- /* FIXME the patching is not done yet! */
- /* Memory related values */
- Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
- Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
- Name(PBLN, 0x0) /* Length of BIOS area */
-
- Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
- Name(HPBA, 0xFED00000) /* Base address of HPET table */
-
- Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
-
- /* USB overcurrent mapping pins. */
- Name(UOM0, 0)
- Name(UOM1, 2)
- Name(UOM2, 0)
- Name(UOM3, 7)
- Name(UOM4, 2)
- Name(UOM5, 2)
- Name(UOM6, 6)
- Name(UOM7, 2)
- Name(UOM8, 6)
- Name(UOM9, 6)
-
- /* Some global data */
- Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
- Name(OSV, Ones) /* Assume nothing */
- Name(PMOD, One) /* Assume APIC */
-
- /* PIC IRQ mapping registers, C00h-C01h */
- OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
- Field(PRQM, ByteAcc, NoLock, Preserve) {
- PRQI, 0x00000008,
- PRQD, 0x00000008, /* Offset: 1h */
- }
- IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
- PINA, 0x00000008, /* Index 0 */
- PINB, 0x00000008, /* Index 1 */
- PINC, 0x00000008, /* Index 2 */
- PIND, 0x00000008, /* Index 3 */
- AINT, 0x00000008, /* Index 4 */
- SINT, 0x00000008, /* Index 5 */
- , 0x00000008, /* Index 6 */
- AAUD, 0x00000008, /* Index 7 */
- AMOD, 0x00000008, /* Index 8 */
- PINE, 0x00000008, /* Index 9 */
- PINF, 0x00000008, /* Index A */
- PING, 0x00000008, /* Index B */
- PINH, 0x00000008, /* Index C */
- }
-
- /* PCI Error control register */
- OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
- Field(PERC, ByteAcc, NoLock, Preserve) {
- SENS, 0x00000001,
- PENS, 0x00000001,
- SENE, 0x00000001,
- PENE, 0x00000001,
- }
-
- /* Client Management index/data registers */
- OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
- Field(CMT, ByteAcc, NoLock, Preserve) {
- CMTI, 8,
- /* Client Management Data register */
- G64E, 1,
- G64O, 1,
- G32O, 2,
- , 2,
- GPSL, 2,
- }
-
- /* GPM Port register */
- OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
- Field(GPT, ByteAcc, NoLock, Preserve) {
- GPB0,1,
- GPB1,1,
- GPB2,1,
- GPB3,1,
- GPB4,1,
- GPB5,1,
- GPB6,1,
- GPB7,1,
- }
-
- /* Flash ROM program enable register */
- OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
- Field(FRE, ByteAcc, NoLock, Preserve) {
- , 0x00000006,
- FLRE, 0x00000001,
- }
-
- /* PM2 index/data registers */
- OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
- Field(PM2R, ByteAcc, NoLock, Preserve) {
- PM2I, 0x00000008,
- PM2D, 0x00000008,
- }
-
- /* Power Management I/O registers */
- OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
- Field(PIOR, ByteAcc, NoLock, Preserve) {
- PIOI, 0x00000008,
- PIOD, 0x00000008,
- }
- IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
- Offset(0x00), /* MiscControl */
- , 1,
- T1EE, 1,
- T2EE, 1,
- Offset(0x01), /* MiscStatus */
- , 1,
- T1E, 1,
- T2E, 1,
- Offset(0x04), /* SmiWakeUpEventEnable3 */
- , 7,
- SSEN, 1,
- Offset(0x07), /* SmiWakeUpEventStatus3 */
- , 7,
- CSSM, 1,
- Offset(0x10), /* AcpiEnable */
- , 6,
- PWDE, 1,
- Offset(0x1C), /* ProgramIoEnable */
- , 3,
- MKME, 1,
- IO3E, 1,
- IO2E, 1,
- IO1E, 1,
- IO0E, 1,
- Offset(0x1D), /* IOMonitorStatus */
- , 3,
- MKMS, 1,
- IO3S, 1,
- IO2S, 1,
- IO1S, 1,
- IO0S,1,
- Offset(0x20), /* AcpiPmEvtBlk */
- APEB, 16,
- Offset(0x36), /* GEvtLevelConfig */
- , 6,
- ELC6, 1,
- ELC7, 1,
- Offset(0x37), /* GPMLevelConfig0 */
- , 3,
- PLC0, 1,
- PLC1, 1,
- PLC2, 1,
- PLC3, 1,
- PLC8, 1,
- Offset(0x38), /* GPMLevelConfig1 */
- , 1,
- PLC4, 1,
- PLC5, 1,
- , 1,
- PLC6, 1,
- PLC7, 1,
- Offset(0x3B), /* PMEStatus1 */
- GP0S, 1,
- GM4S, 1,
- GM5S, 1,
- APS, 1,
- GM6S, 1,
- GM7S, 1,
- GP2S, 1,
- STSS, 1,
- Offset(0x55), /* SoftPciRst */
- SPRE, 1,
- , 1,
- , 1,
- PNAT, 1,
- PWMK, 1,
- PWNS, 1,
-
- /* Offset(0x61), */ /* Options_1 */
- /* ,7, */
- /* R617,1, */
-
- Offset(0x65), /* UsbPMControl */
- , 4,
- URRE, 1,
- Offset(0x68), /* MiscEnable68 */
- , 3,
- TMTE, 1,
- , 1,
- Offset(0x92), /* GEVENTIN */
- , 7,
- E7IS, 1,
- Offset(0x96), /* GPM98IN */
- G8IS, 1,
- G9IS, 1,
- Offset(0x9A), /* EnhanceControl */
- ,7,
- HPDE, 1,
- Offset(0xA8), /* PIO7654Enable */
- IO4E, 1,
- IO5E, 1,
- IO6E, 1,
- IO7E, 1,
- Offset(0xA9), /* PIO7654Status */
- IO4S, 1,
- IO5S, 1,
- IO6S, 1,
- IO7S, 1,
- }
-
- /* PM1 Event Block
- * First word is PM1_Status, Second word is PM1_Enable
- */
- OperationRegion(P1EB, SystemIO, APEB, 0x04)
- Field(P1EB, ByteAcc, NoLock, Preserve) {
- TMST, 1,
- , 3,
- BMST, 1,
- GBST, 1,
- Offset(0x01),
- PBST, 1,
- , 1,
- RTST, 1,
- , 3,
- PWST, 1,
- SPWS, 1,
- Offset(0x02),
- TMEN, 1,
- , 4,
- GBEN, 1,
- Offset(0x03),
- PBEN, 1,
- , 1,
- RTEN, 1,
- , 3,
- PWDA, 1,
- }
-
- Scope(\_SB) {
-
- /* PCIe Configuration Space for 16 busses */
- OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
- Field(PCFG, ByteAcc, NoLock, Preserve) {
- /* Byte offsets are computed using the following technique:
- * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
- * The 8 comes from 8 functions per device, and 4096 bytes per function config space
- */
- Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */
- STB5, 32,
- Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
- PT0D, 1,
- PT1D, 1,
- PT2D, 1,
- PT3D, 1,
- PT4D, 1,
- PT5D, 1,
- PT6D, 1,
- PT7D, 1,
- PT8D, 1,
- PT9D, 1,
- Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
- SBIE, 1,
- SBME, 1,
- Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
- SBRI, 8,
- Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
- SBB1, 32,
- Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
- ,14,
- P92E, 1, /* Port92 decode enable */
- }
-
- OperationRegion(SB5, SystemMemory, STB5, 0x1000)
- Field(SB5, AnyAcc, NoLock, Preserve)
- {
- /* Port 0 */
- Offset(0x120), /* Port 0 Task file status */
- P0ER, 1,
- , 2,
- P0DQ, 1,
- , 3,
- P0BY, 1,
- Offset(0x128), /* Port 0 Serial ATA status */
- P0DD, 4,
- , 4,
- P0IS, 4,
- Offset(0x12C), /* Port 0 Serial ATA control */
- P0DI, 4,
- Offset(0x130), /* Port 0 Serial ATA error */
- , 16,
- P0PR, 1,
-
- /* Port 1 */
- offset(0x1A0), /* Port 1 Task file status */
- P1ER, 1,
- , 2,
- P1DQ, 1,
- , 3,
- P1BY, 1,
- Offset(0x1A8), /* Port 1 Serial ATA status */
- P1DD, 4,
- , 4,
- P1IS, 4,
- Offset(0x1AC), /* Port 1 Serial ATA control */
- P1DI, 4,
- Offset(0x1B0), /* Port 1 Serial ATA error */
- , 16,
- P1PR, 1,
-
- /* Port 2 */
- Offset(0x220), /* Port 2 Task file status */
- P2ER, 1,
- , 2,
- P2DQ, 1,
- , 3,
- P2BY, 1,
- Offset(0x228), /* Port 2 Serial ATA status */
- P2DD, 4,
- , 4,
- P2IS, 4,
- Offset(0x22C), /* Port 2 Serial ATA control */
- P2DI, 4,
- Offset(0x230), /* Port 2 Serial ATA error */
- , 16,
- P2PR, 1,
-
- /* Port 3 */
- Offset(0x2A0), /* Port 3 Task file status */
- P3ER, 1,
- , 2,
- P3DQ, 1,
- , 3,
- P3BY, 1,
- Offset(0x2A8), /* Port 3 Serial ATA status */
- P3DD, 4,
- , 4,
- P3IS, 4,
- Offset(0x2AC), /* Port 3 Serial ATA control */
- P3DI, 4,
- Offset(0x2B0), /* Port 3 Serial ATA error */
- , 16,
- P3PR, 1,
- }
- }
-
- Include ("routing.asl")
-
- Scope(\_SB) {
-
- Method(CkOT, 0){
-
- if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */
-
- if(CondRefOf(\_OSI,Local1))
- {
- Store(1, OSTP) /* Assume some form of XP */
- if (\_OSI("Windows 2006")) /* Vista */
- {
- Store(2, OSTP)
- }
- } else {
- If(WCMP(\_OS,"Linux")) {
- Store(3, OSTP) /* Linux */
- } Else {
- Store(4, OSTP) /* Gotta be WinCE */
- }
- }
- Return(OSTP)
- }
-
- Method(_PIC, 0x01, NotSerialized)
- {
- If (Arg0)
- {
- \_SB.CIRQ()
- }
- Store(Arg0, PMOD)
- }
-
- Method(CIRQ, 0x00, NotSerialized)
- {
- Store(0, PINA)
- Store(0, PINB)
- Store(0, PINC)
- Store(0, PIND)
- Store(0, PINE)
- Store(0, PINF)
- Store(0, PING)
- Store(0, PINH)
- }
-
- Name(IRQB, ResourceTemplate(){
- IRQ(Level,ActiveLow,Shared){15}
- })
-
- Name(IRQP, ResourceTemplate(){
- IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
- })
-
- Name(PITF, ResourceTemplate(){
- IRQ(Level,ActiveLow,Exclusive){9}
- })
-
- Device(INTA) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 1)
-
- Method(_STA, 0) {
- if (PINA) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTA._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKA\\_DIS\n") */
- Store(0, PINA)
- } /* End Method(_SB.INTA._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKA\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTA._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKA\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINA, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTA._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKA\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINA)
- } /* End Method(_SB.INTA._SRS) */
- } /* End Device(INTA) */
-
- Device(INTB) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 2)
-
- Method(_STA, 0) {
- if (PINB) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTB._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKB\\_DIS\n") */
- Store(0, PINB)
- } /* End Method(_SB.INTB._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKB\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTB._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKB\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINB, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTB._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKB\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINB)
- } /* End Method(_SB.INTB._SRS) */
- } /* End Device(INTB) */
-
- Device(INTC) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 3)
-
- Method(_STA, 0) {
- if (PINC) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTC._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKC\\_DIS\n") */
- Store(0, PINC)
- } /* End Method(_SB.INTC._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKC\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTC._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKC\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINC, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTC._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKC\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINC)
- } /* End Method(_SB.INTC._SRS) */
- } /* End Device(INTC) */
-
- Device(INTD) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 4)
-
- Method(_STA, 0) {
- if (PIND) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTD._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKD\\_DIS\n") */
- Store(0, PIND)
- } /* End Method(_SB.INTD._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKD\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTD._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKD\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PIND, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTD._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKD\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PIND)
- } /* End Method(_SB.INTD._SRS) */
- } /* End Device(INTD) */
-
- Device(INTE) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 5)
-
- Method(_STA, 0) {
- if (PINE) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTE._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKE\\_DIS\n") */
- Store(0, PINE)
- } /* End Method(_SB.INTE._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKE\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTE._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKE\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINE, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTE._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKE\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINE)
- } /* End Method(_SB.INTE._SRS) */
- } /* End Device(INTE) */
-
- Device(INTF) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 6)
-
- Method(_STA, 0) {
- if (PINF) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTF._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKF\\_DIS\n") */
- Store(0, PINF)
- } /* End Method(_SB.INTF._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKF\\_PRS\n") */
- Return(PITF)
- } /* Method(_SB.INTF._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKF\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINF, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTF._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKF\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINF)
- } /* End Method(_SB.INTF._SRS) */
- } /* End Device(INTF) */
-
- Device(INTG) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 7)
-
- Method(_STA, 0) {
- if (PING) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTG._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKG\\_DIS\n") */
- Store(0, PING)
- } /* End Method(_SB.INTG._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKG\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTG._CRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKG\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PING, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTG._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKG\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PING)
- } /* End Method(_SB.INTG._SRS) */
- } /* End Device(INTG) */
-
- Device(INTH) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 8)
-
- Method(_STA, 0) {
- if (PINH) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTH._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKH\\_DIS\n") */
- Store(0, PINH)
- } /* End Method(_SB.INTH._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKH\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTH._CRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKH\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINH, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTH._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKH\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINH)
- } /* End Method(_SB.INTH._SRS) */
- } /* End Device(INTH) */
-
- } /* End Scope(_SB) */
-
-
- /* Supported sleep states: */
- Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
-
- If (LAnd(SSFG, 0x01)) {
- Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
- }
- If (LAnd(SSFG, 0x02)) {
- Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
- }
- If (LAnd(SSFG, 0x04)) {
- Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
- }
- If (LAnd(SSFG, 0x08)) {
- Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
- }
-
- Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
-
- Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
- Name(CSMS, 0) /* Current System State */
-
- /* Wake status package */
- Name(WKST,Package(){Zero, Zero})
-
- /*
- * \_PTS - Prepare to Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2, etc
- *
- * Exit:
- * -none-
- *
- * The _PTS control method is executed at the beginning of the sleep process
- * for S1-S5. The sleeping value is passed to the _PTS control method. This
- * control method may be executed a relatively long time before entering the
- * sleep state and the OS may abort the operation without notification to
- * the ACPI driver. This method cannot modify the configuration or power
- * state of any device in the system.
- */
- Method(\_PTS, 1) {
- /* DBGO("\\_PTS\n") */
- /* DBGO("From S0 to S") */
- /* DBGO(Arg0) */
- /* DBGO("\n") */
-
- /* Don't allow PCIRST# to reset USB */
- if (LEqual(Arg0,3)){
- Store(0,URRE)
- }
-
- /* Clear sleep SMI status flag and enable sleep SMI trap. */
- /*Store(One, CSSM)
- Store(One, SSEN)*/
-
- /* On older chips, clear PciExpWakeDisEn */
- /*if (LLessEqual(\_SB.SBRI, 0x13)) {
- * Store(0,\_SB.PWDE)
- *}
- */
-
- /* Clear wake status structure. */
- Store(0, Index(WKST,0))
- Store(0, Index(WKST,1))
- \_SB.PCI0.SIOS (Arg0)
- } /* End Method(\_PTS) */
-
- /*
- * The following method results in a "not a valid reserved NameSeg"
- * warning so I have commented it out for the duration. It isn't
- * used, so it could be removed.
- *
- *
- * \_GTS OEM Going To Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * -none-
- *
- * Method(\_GTS, 1) {
- * DBGO("\\_GTS\n")
- * DBGO("From S0 to S")
- * DBGO(Arg0)
- * DBGO("\n")
- * }
- */
-
- /*
- * \_BFS OEM Back From Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * -none-
- */
- Method(\_BFS, 1) {
- /* DBGO("\\_BFS\n") */
- /* DBGO("From S") */
- /* DBGO(Arg0) */
- /* DBGO(" to S0\n") */
- }
-
- /*
- * \_WAK System Wake method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * Return package of 2 DWords
- * Dword 1 - Status
- * 0x00000000 wake succeeded
- * 0x00000001 Wake was signaled but failed due to lack of power
- * 0x00000002 Wake was signaled but failed due to thermal condition
- * Dword 2 - Power Supply state
- * if non-zero the effective S-state the power supply entered
- */
- Method(\_WAK, 1) {
- /* DBGO("\\_WAK\n") */
- /* DBGO("From S") */
- /* DBGO(Arg0) */
- /* DBGO(" to S0\n") */
-
- /* Re-enable HPET */
- Store(1,HPDE)
-
- /* Restore PCIRST# so it resets USB */
- if (LEqual(Arg0,3)){
- Store(1,URRE)
- }
-
- /* Arbitrarily clear PciExpWakeStatus */
- Store(PWST, PWST)
-
- /* if(DeRefOf(Index(WKST,0))) {
- * Store(0, Index(WKST,1))
- * } else {
- * Store(Arg0, Index(WKST,1))
- * }
- */
- \_SB.PCI0.SIOW (Arg0)
- Return(WKST)
- } /* End Method(\_WAK) */
-
- Scope(\_GPE) { /* Start Scope GPE */
- /* General event 0 */
- /* Method(_L00) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 1 */
- /* Method(_L01) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 2 */
- /* Method(_L02) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 3 */
- Method(_L03) {
- /* DBGO("\\_GPE\\_L00\n") */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* General event 4 */
- /* Method(_L04) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 5 */
- /* Method(_L05) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 6 - Used for GPM6, moved to USB.asl */
- /* Method(_L06) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 7 - Used for GPM7, moved to USB.asl */
- /* Method(_L07) {
- * DBGO("\\_GPE\\_L07\n")
- * }
- */
-
- /* Legacy PM event */
- Method(_L08) {
- /* DBGO("\\_GPE\\_L08\n") */
- }
-
- /* Temp warning (TWarn) event */
- Method(_L09) {
- /* DBGO("\\_GPE\\_L09\n") */
- Notify (\_TZ.TZ00, 0x80)
- }
-
- /* Reserved */
- /* Method(_L0A) {
- * DBGO("\\_GPE\\_L0A\n")
- * }
- */
-
- /* USB controller PME# */
- Method(_L0B) {
- /* DBGO("\\_GPE\\_L0B\n") */
- Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* AC97 controller PME# */
- /* Method(_L0C) {
- * DBGO("\\_GPE\\_L0C\n")
- * }
- */
-
- /* OtherTherm PME# */
- /* Method(_L0D) {
- * DBGO("\\_GPE\\_L0D\n")
- * }
- */
-
- /* GPM9 SCI event - Moved to USB.asl */
- /* Method(_L0E) {
- * DBGO("\\_GPE\\_L0E\n")
- * }
- */
-
- /* PCIe HotPlug event */
- /* Method(_L0F) {
- * DBGO("\\_GPE\\_L0F\n")
- * }
- */
-
- /* ExtEvent0 SCI event */
- Method(_L10) {
- /* DBGO("\\_GPE\\_L10\n") */
- }
-
-
- /* ExtEvent1 SCI event */
- Method(_L11) {
- /* DBGO("\\_GPE\\_L11\n") */
- }
-
- /* PCIe PME# event */
- /* Method(_L12) {
- * DBGO("\\_GPE\\_L12\n")
- * }
- */
-
- /* GPM0 SCI event - Moved to USB.asl */
- /* Method(_L13) {
- * DBGO("\\_GPE\\_L13\n")
- * }
- */
-
- /* GPM1 SCI event - Moved to USB.asl */
- /* Method(_L14) {
- * DBGO("\\_GPE\\_L14\n")
- * }
- */
-
- /* GPM2 SCI event - Moved to USB.asl */
- /* Method(_L15) {
- * DBGO("\\_GPE\\_L15\n")
- * }
- */
-
- /* GPM3 SCI event - Moved to USB.asl */
- /* Method(_L16) {
- * DBGO("\\_GPE\\_L16\n")
- * }
- */
-
- /* GPM8 SCI event - Moved to USB.asl */
- /* Method(_L17) {
- * DBGO("\\_GPE\\_L17\n")
- * }
- */
-
- /* GPIO0 or GEvent8 event */
- Method(_L18) {
- /* DBGO("\\_GPE\\_L18\n") */
- Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* GPM4 SCI event - Moved to USB.asl */
- /* Method(_L19) {
- * DBGO("\\_GPE\\_L19\n")
- * }
- */
-
- /* GPM5 SCI event - Moved to USB.asl */
- /* Method(_L1A) {
- * DBGO("\\_GPE\\_L1A\n")
- * }
- */
-
- /* Azalia SCI event */
- Method(_L1B) {
- /* DBGO("\\_GPE\\_L1B\n") */
- Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* GPM6 SCI event - Reassigned to _L06 */
- /* Method(_L1C) {
- * DBGO("\\_GPE\\_L1C\n")
- * }
- */
-
- /* GPM7 SCI event - Reassigned to _L07 */
- /* Method(_L1D) {
- * DBGO("\\_GPE\\_L1D\n")
- * }
- */
-
- /* GPIO2 or GPIO66 SCI event */
- /* Method(_L1E) {
- * DBGO("\\_GPE\\_L1E\n")
- * }
- */
-
- /* SATA SCI event - Moved to sata.asl */
- /* Method(_L1F) {
- * DBGO("\\_GPE\\_L1F\n")
- * }
- */
-
- } /* End Scope GPE */
-
- Include ("usb.asl")
-
- /* South Bridge */
- Scope(\_SB) { /* Start \_SB scope */
- Include ("globutil.asl") /* global utility methods expected within the \_SB scope */
-
- /* _SB.PCI0 */
- /* Note: Only need HID on Primary Bus */
- Device(PCI0) {
- External (TOM1)
- External (TOM2)
- Name(_HID, EISAID("PNP0A03"))
- Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
- Method(_BBN, 0) { /* Bus number = 0 */
- Return(0)
- }
- Method(_STA, 0) {
- /* DBGO("\\_SB\\PCI0\\_STA\n") */
- Return(0x0B) /* Status is visible */
- }
-
- Method(_PRT,0) {
- If(PMOD){ Return(APR0) } /* APIC mode */
- Return (PR0) /* PIC Mode */
- } /* end _PRT */
-
- /* Describe the Northbridge devices */
- Device(AMRT) {
- Name(_ADR, 0x00000000)
- } /* end AMRT */
-
- /* The internal GFX bridge */
- Device(AGPB) {
- Name(_ADR, 0x00010000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- Return (APR1)
- }
- } /* end AGPB */
-
- /* The external GFX bridge */
- Device(PBR2) {
- Name(_ADR, 0x00020000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS2) } /* APIC mode */
- Return (PS2) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR2 */
-
- /* Dev3 is also an external GFX bridge, not used in Herring */
-
- Device(PBR4) {
- Name(_ADR, 0x00040000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS4) } /* APIC mode */
- Return (PS4) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR4 */
-
- Device(PBR5) {
- Name(_ADR, 0x00050000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS5) } /* APIC mode */
- Return (PS5) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR5 */
-
- Device(PBR6) {
- Name(_ADR, 0x00060000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS6) } /* APIC mode */
- Return (PS6) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR6 */
-
- /* The onboard EtherNet chip */
- Device(PBR7) {
- Name(_ADR, 0x00070000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS7) } /* APIC mode */
- Return (PS7) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR7 */
-
-
- /* PCI slot 1, 2, 3 */
- Device(PIBR) {
- Name(_ADR, 0x00140004)
- Name(_PRW, Package() {0x18, 4})
-
- Method(_PRT, 0) {
- Return (PCIB)
- }
- }
-
- /* Describe the Southbridge devices */
- Device(STCR) {
- Name(_ADR, 0x00120000)
- Include ("sata.asl")
- } /* end STCR */
-
- Device(UOH1) {
- Name(_ADR, 0x00130000)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH1 */
-
- Device(UOH2) {
- Name(_ADR, 0x00130001)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH2 */
-
- Device(UOH3) {
- Name(_ADR, 0x00130002)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH3 */
-
- Device(UOH4) {
- Name(_ADR, 0x00130003)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH4 */
-
- Device(UOH5) {
- Name(_ADR, 0x00130004)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH5 */
-
- Device(UEH1) {
- Name(_ADR, 0x00130005)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UEH1 */
-
- Device(SBUS) {
- Name(_ADR, 0x00140000)
- } /* end SBUS */
-
- /* Primary (and only) IDE channel */
- Device(IDEC) {
- Name(_ADR, 0x00140001)
- Include ("ide.asl")
- } /* end IDEC */
-
- Device(AZHD) {
- Name(_ADR, 0x00140002)
- OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
- Field(AZPD, AnyAcc, NoLock, Preserve) {
- offset (0x42),
- NSDI, 1,
- NSDO, 1,
- NSEN, 1,
- offset (0x44),
- IPCR, 4,
- offset (0x54),
- PWST, 2,
- , 6,
- PMEB, 1,
- , 6,
- PMST, 1,
- offset (0x62),
- MMCR, 1,
- offset (0x64),
- MMLA, 32,
- offset (0x68),
- MMHA, 32,
- offset (0x6C),
- MMDT, 16,
- }
-
- Method(_INI) {
- If(LEqual(OSTP,3)){ /* If we are running Linux */
- Store(zero, NSEN)
- Store(one, NSDO)
- Store(one, NSDI)
- }
- }
- } /* end AZHD */
-
- Device(LIBR) {
- Name(_ADR, 0x00140003)
- /* Method(_INI) {
- * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
- } */ /* End Method(_SB.SBRDG._INI) */
-
- /* Real Time Clock Device */
- Device(RTC0) {
- Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){8}
- IO(Decode16,0x0070, 0x0070, 0, 2)
- /* IO(Decode16,0x0070, 0x0070, 0, 4) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
-
- Device(TMR) { /* Timer */
- Name(_HID,EISAID("PNP0100")) /* System Timer */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){0}
- IO(Decode16, 0x0040, 0x0040, 0, 4)
- /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
-
- Device(SPKR) { /* Speaker */
- Name(_HID,EISAID("PNP0800")) /* AT style speaker */
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x0061, 0x0061, 0, 1)
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
-
- Device(PIC) {
- Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){2}
- IO(Decode16,0x0020, 0x0020, 0, 2)
- IO(Decode16,0x00A0, 0x00A0, 0, 2)
- /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
- /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
-
- Device(MAD) { /* 8257 DMA */
- Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
- Name(_CRS, ResourceTemplate() {
- DMA(Compatibility,BusMaster,Transfer8){4}
- IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
- IO(Decode16, 0x0081, 0x0081, 0x10, 0x03)
- IO(Decode16, 0x0087, 0x0087, 0x10, 0x01)
- IO(Decode16, 0x0089, 0x0089, 0x10, 0x03)
- IO(Decode16, 0x008F, 0x008F, 0x10, 0x01)
- IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
- }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
- } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
-
- Device(COPR) {
- Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
- IRQNoFlags(){13}
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
-
- Device(HPTM) {
- Name(_HID,EISAID("PNP0103"))
- Name(CRS,ResourceTemplate() {
- Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
- })
- Method(_STA, 0) {
- Return(0x0F) /* sata is visible */
- }
- Method(_CRS, 0) {
- CreateDwordField(CRS, ^HPT._BAS, HPBA)
- Store(HPBA, HPBA)
- Return(CRS)
- }
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
- } /* end LIBR */
-
- Device(HPBR) {
- Name(_ADR, 0x00140004)
- } /* end HostPciBr */
-
- Device(ACAD) {
- Name(_ADR, 0x00140005)
- } /* end Ac97audio */
-
- Device(ACMD) {
- Name(_ADR, 0x00140006)
- } /* end Ac97modem */
-
- /* ITE IT8712F Support */
- OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
- Field (IOID, ByteAcc, NoLock, Preserve)
- {
- SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */
- }
-
- IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
- {
- Offset (0x07),
- LDN, 8, /* Logical Device Number */
- Offset (0x20),
- CID1, 8, /* Chip ID Byte 1, 0x87 */
- CID2, 8, /* Chip ID Byte 2, 0x12 */
- Offset (0x30),
- ACTR, 8, /* Function activate */
- Offset (0xF0),
- APC0, 8, /* APC/PME Event Enable Register */
- APC1, 8, /* APC/PME Status Register */
- APC2, 8, /* APC/PME Control Register 1 */
- APC3, 8, /* Environment Controller Special Configuration Register */
- APC4, 8 /* APC/PME Control Register 2 */
- }
-
- /* Enter the IT8712F MB PnP Mode */
- Method (EPNP)
- {
- Store(0x87, SIOI)
- Store(0x01, SIOI)
- Store(0x55, SIOI)
- Store(0x55, SIOI) /* IT8712F magic number */
- }
- /* Exit the IT8712F MB PnP Mode */
- Method (XPNP)
- {
- Store (0x02, SIOI)
- Store (0x02, SIOD)
- }
-
- /*
- * Keyboard PME is routed to SB600 Gevent3. We can wake
- * up the system by pressing the key.
- */
- Method (SIOS, 1)
- {
- /* We only enable KBD PME for S5. */
- If (LLess (Arg0, 0x05))
- {
- EPNP()
- /* DBGO("IT8712F\n") */
-
- Store (0x4, LDN)
- Store (One, ACTR) /* Enable EC */
- /*
- Store (0x4, LDN)
- Store (0x04, APC4)
- */ /* falling edge. which mode? Not sure. */
-
- Store (0x4, LDN)
- Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
- Store (0x4, LDN)
- Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
-
- XPNP()
- }
- }
- Method (SIOW, 1)
- {
- EPNP()
- Store (0x4, LDN)
- Store (Zero, APC0) /* disable keyboard PME */
- Store (0x4, LDN)
- Store (0xFF, APC1) /* clear keyboard PME status */
- XPNP()
- }
-
- Name(CRES, ResourceTemplate() {
- IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0000, /* range minimum */
- 0x0CF7, /* range maximum */
- 0x0000, /* translation */
- 0x0CF8 /* length */
- )
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0D00, /* range minimum */
- 0xFFFF, /* range maximum */
- 0x0000, /* translation */
- 0xF300 /* length */
- )
-
- Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
- Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
- Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
-
- /* DRAM Memory from 1MB to TopMem */
- Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
-
- /* BIOS space just below 4GB */
- DWORDMemory(
- ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000000, /* Max-Min, RLEN */
- ,,
- PCBM
- )
-
- /* DRAM memory from 4GB to TopMem2 */
- QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0xFFFFFFFF, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000000, /* Max-Min, RLEN */
- ,,
- DMHI
- )
-
- /* BIOS space just below 16EB */
- QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0xFFFFFFFF, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000000, /* Max-Min, RLEN */
- ,,
- PEBM
- )
-
- }) /* End Name(_SB.PCI0.CRES) */
-
- Method(_CRS, 0) {
- /* DBGO("\\_SB\\PCI0\\_CRS\n") */
-
- CreateDWordField(CRES, ^EMM1._BAS, EM1B)
- CreateDWordField(CRES, ^EMM1._LEN, EM1L)
- CreateDWordField(CRES, ^DMLO._BAS, DMLB)
- CreateDWordField(CRES, ^DMLO._LEN, DMLL)
- CreateDWordField(CRES, ^PCBM._MIN, PBMB)
- CreateDWordField(CRES, ^PCBM._LEN, PBML)
-
- CreateQWordField(CRES, ^DMHI._MIN, DMHB)
- CreateQWordField(CRES, ^DMHI._LEN, DMHL)
- CreateQWordField(CRES, ^PEBM._MIN, EBMB)
- CreateQWordField(CRES, ^PEBM._LEN, EBML)
-
- If(LGreater(LOMH, 0xC0000)){
- Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
- Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
- }
-
- /* Set size of memory from 1MB to TopMem */
- Subtract(TOM1, 0x100000, DMLL)
-
- /*
- * If(LNotEqual(TOM2, 0x00000000)){
- * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
- * Subtract(TOM2, 0x100000000, DMHL)
- * }
- */
-
- /* If there is no memory above 4GB, put the BIOS just below 4GB */
- If(LEqual(TOM2, 0x00000000)){
- Store(PBAD,PBMB) /* Reserve the "BIOS" space */
- Store(PBLN,PBML)
- }
- Else { /* Otherwise, put the BIOS just below 16EB */
- ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
- Store(PBLN,EBML)
- }
-
- Return(CRES) /* note to change the Name buffer */
- } /* end of Method(_SB.PCI0._CRS) */
-
- /*
- *
- * FIRST METHOD CALLED UPON BOOT
- *
- * 1. If debugging, print current OS and ACPI interpreter.
- * 2. Get PCI Interrupt routing from ACPI VSM, this
- * value is based on user choice in BIOS setup.
- */
- Method(_INI, 0) {
- /* DBGO("\\_SB\\_INI\n") */
- /* DBGO(" DSDT.ASL code from ") */
- /* DBGO(__DATE__) */
- /* DBGO(" ") */
- /* DBGO(__TIME__) */
- /* DBGO("\n Sleep states supported: ") */
- /* DBGO("\n") */
- /* DBGO(" \\_OS=") */
- /* DBGO(\_OS) */
- /* DBGO("\n \\_REV=") */
- /* DBGO(\_REV) */
- /* DBGO("\n") */
-
- /* Determine the OS we're running on */
- CkOT()
-
- /* On older chips, clear PciExpWakeDisEn */
- /*if (LLessEqual(\SBRI, 0x13)) {
- * Store(0,\PWDE)
- * }
- */
- } /* End Method(_SB._INI) */
- } /* End Device(PCI0) */
-
- Device(PWRB) { /* Start Power button device */
- Name(_HID, EISAID("PNP0C0C"))
- Name(_UID, 0xAA)
- Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
- Name(_STA, 0x0B) /* sata is invisible */
- }
- } /* End \_SB scope */
-
- Scope(\_SI) {
- Method(_SST, 1) {
- /* DBGO("\\_SI\\_SST\n") */
- /* DBGO(" New Indicator state: ") */
- /* DBGO(Arg0) */
- /* DBGO("\n") */
- }
- } /* End Scope SI */
-
- Mutex (SBX0, 0x00)
- OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
- Field (SMB0, ByteAcc, NoLock, Preserve) {
- HSTS, 8, /* SMBUS status */
- SSTS, 8, /* SMBUS slave status */
- HCNT, 8, /* SMBUS control */
- HCMD, 8, /* SMBUS host cmd */
- HADD, 8, /* SMBUS address */
- DAT0, 8, /* SMBUS data0 */
- DAT1, 8, /* SMBUS data1 */
- BLKD, 8, /* SMBUS block data */
- SCNT, 8, /* SMBUS slave control */
- SCMD, 8, /* SMBUS shaow cmd */
- SEVT, 8, /* SMBUS slave event */
- SDAT, 8 /* SMBUS slave data */
- }
-
- Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
- Store (0x1E, HSTS)
- Store (0xFA, Local0)
- While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
- Stall (0x64)
- Decrement (Local0)
- }
-
- Return (Local0)
- }
-
- Method (SWTC, 1, NotSerialized) {
- Store (Arg0, Local0)
- Store (0x07, Local2)
- Store (One, Local1)
- While (LEqual (Local1, One)) {
- Store (And (HSTS, 0x1E), Local3)
- If (LNotEqual (Local3, Zero)) { /* read sucess */
- If (LEqual (Local3, 0x02)) {
- Store (Zero, Local2)
- }
-
- Store (Zero, Local1)
- }
- Else {
- If (LLess (Local0, 0x0A)) { /* read failure */
- Store (0x10, Local2)
- Store (Zero, Local1)
- }
- Else {
- Sleep (0x0A) /* 10 ms, try again */
- Subtract (Local0, 0x0A, Local0)
- }
- }
- }
-
- Return (Local2)
- }
-
- Method (SMBR, 3, NotSerialized) {
- Store (0x07, Local0)
- If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
- Store (WCLR (), Local0) /* clear SMBUS status register before read data */
- If (LEqual (Local0, Zero)) {
- Release (SBX0)
- Return (0x0)
- }
-
- Store (0x1F, HSTS)
- Store (Or (ShiftLeft (Arg1, One), One), HADD)
- Store (Arg2, HCMD)
- If (LEqual (Arg0, 0x07)) {
- Store (0x48, HCNT) /* read byte */
- }
-
- Store (SWTC (0x03E8), Local1) /* 1000 ms */
- If (LEqual (Local1, Zero)) {
- If (LEqual (Arg0, 0x07)) {
- Store (DAT0, Local0)
- }
- }
- Else {
- Store (Local1, Local0)
- }
-
- Release (SBX0)
- }
-
- /* DBGO("the value of SMBusData0 register ") */
- /* DBGO(Arg2) */
- /* DBGO(" is ") */
- /* DBGO(Local0) */
- /* DBGO("\n") */
-
- Return (Local0)
- }
-
- /* THERMAL */
- Scope(\_TZ) {
- Name (KELV, 2732)
- Name (THOT, 800)
- Name (TCRT, 850)
-
- ThermalZone(TZ00) {
- Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
- /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
- Return(Add(0, 2730))
- }
- Method(_AL0,0) { /* Returns package of cooling device to turn on */
- /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
- Return(Package() {\_TZ.TZ00.FAN0})
- }
- Device (FAN0) {
- Name(_HID, EISAID("PNP0C0B"))
- Name(_PR0, Package() {PFN0})
- }
-
- PowerResource(PFN0,0,0) {
- Method(_STA) {
- Store(0xF,Local0)
- Return(Local0)
- }
- Method(_ON) {
- /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
- }
- Method(_OFF) {
- /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
- }
- }
-
- Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
- /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
- Return (Add (THOT, KELV))
- }
- Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
- /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
- Return (Add (TCRT, KELV))
- }
- Method(_TMP,0) { /* return current temp of this zone */
- Store (SMBR (0x07, 0x4C,, 0x00), Local0)
- If (LGreater (Local0, 0x10)) {
- Store (Local0, Local1)
- }
- Else {
- Add (Local0, THOT, Local0)
- Return (Add (400, KELV))
- }
-
- Store (SMBR (0x07, 0x4C, 0x01), Local0)
- /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
- /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
- If (LGreater (Local0, 0x10)) {
- If (LGreater (Local0, Local1)) {
- Store (Local0, Local1)
- }
-
- Multiply (Local1, 10, Local1)
- Return (Add (Local1, KELV))
- }
- Else {
- Add (Local0, THOT, Local0)
- Return (Add (400 , KELV))
- }
- } /* end of _TMP */
- } /* end of TZ00 */
- }
-}
-/* End of ASL file */
/*
Scope(\_SB) {
- Include ("globutil.asl")
+ #include "globutil.asl"
}
*/
Device(PCI0) {
Device(IDEC) {
Name(_ADR, 0x00140001)
- Include ("ide.asl")
+ #include "ide.asl"
}
}
}
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
)
{
- Include ("routing.asl")
+ #include "routing.asl"
}
*/
Device(PCI0) {
Device(SATA) {
Name(_ADR, 0x00120000)
- Include ("sata.asl")
+ #include "sata.asl"
}
}
}
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
)
{
- Include ("usb.asl")
+ #include "usb.asl"
}
*/
Method(UCOC, 0) {
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+ "DSDT.AML", /* Output filename */
+ "DSDT", /* Signature */
+ 0x02, /* DSDT Revision, needs to be 2 for 64bit */
+ "AMD ", /* OEMID */
+ "DBM690T ", /* TABLE ID */
+ 0x00010001 /* OEM Revision */
+ )
+{ /* Start of ASL file */
+ /* #include "acpi/debug.asl" */ /* Include global debug methods if needed */
+
+ /* Data to be patched by the BIOS during POST */
+ /* FIXME the patching is not done yet! */
+ /* Memory related values */
+ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
+ Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+ Name(PBLN, 0x0) /* Length of BIOS area */
+
+ Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
+ Name(HPBA, 0xFED00000) /* Base address of HPET table */
+
+ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+ /* USB overcurrent mapping pins. */
+ Name(UOM0, 0)
+ Name(UOM1, 2)
+ Name(UOM2, 0)
+ Name(UOM3, 7)
+ Name(UOM4, 2)
+ Name(UOM5, 2)
+ Name(UOM6, 6)
+ Name(UOM7, 2)
+ Name(UOM8, 6)
+ Name(UOM9, 6)
+
+ /* Some global data */
+ Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+ Name(OSV, Ones) /* Assume nothing */
+ Name(PMOD, One) /* Assume APIC */
+
+ /* PIC IRQ mapping registers, C00h-C01h */
+ OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
+ Field(PRQM, ByteAcc, NoLock, Preserve) {
+ PRQI, 0x00000008,
+ PRQD, 0x00000008, /* Offset: 1h */
+ }
+ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
+ PINA, 0x00000008, /* Index 0 */
+ PINB, 0x00000008, /* Index 1 */
+ PINC, 0x00000008, /* Index 2 */
+ PIND, 0x00000008, /* Index 3 */
+ AINT, 0x00000008, /* Index 4 */
+ SINT, 0x00000008, /* Index 5 */
+ , 0x00000008, /* Index 6 */
+ AAUD, 0x00000008, /* Index 7 */
+ AMOD, 0x00000008, /* Index 8 */
+ PINE, 0x00000008, /* Index 9 */
+ PINF, 0x00000008, /* Index A */
+ PING, 0x00000008, /* Index B */
+ PINH, 0x00000008, /* Index C */
+ }
+
+ /* PCI Error control register */
+ OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
+ Field(PERC, ByteAcc, NoLock, Preserve) {
+ SENS, 0x00000001,
+ PENS, 0x00000001,
+ SENE, 0x00000001,
+ PENE, 0x00000001,
+ }
+
+ /* Client Management index/data registers */
+ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
+ Field(CMT, ByteAcc, NoLock, Preserve) {
+ CMTI, 8,
+ /* Client Management Data register */
+ G64E, 1,
+ G64O, 1,
+ G32O, 2,
+ , 2,
+ GPSL, 2,
+ }
+
+ /* GPM Port register */
+ OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
+ Field(GPT, ByteAcc, NoLock, Preserve) {
+ GPB0,1,
+ GPB1,1,
+ GPB2,1,
+ GPB3,1,
+ GPB4,1,
+ GPB5,1,
+ GPB6,1,
+ GPB7,1,
+ }
+
+ /* Flash ROM program enable register */
+ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
+ Field(FRE, ByteAcc, NoLock, Preserve) {
+ , 0x00000006,
+ FLRE, 0x00000001,
+ }
+
+ /* PM2 index/data registers */
+ OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
+ Field(PM2R, ByteAcc, NoLock, Preserve) {
+ PM2I, 0x00000008,
+ PM2D, 0x00000008,
+ }
+
+ /* Power Management I/O registers */
+ OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
+ Field(PIOR, ByteAcc, NoLock, Preserve) {
+ PIOI, 0x00000008,
+ PIOD, 0x00000008,
+ }
+ IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
+ Offset(0x00), /* MiscControl */
+ , 1,
+ T1EE, 1,
+ T2EE, 1,
+ Offset(0x01), /* MiscStatus */
+ , 1,
+ T1E, 1,
+ T2E, 1,
+ Offset(0x04), /* SmiWakeUpEventEnable3 */
+ , 7,
+ SSEN, 1,
+ Offset(0x07), /* SmiWakeUpEventStatus3 */
+ , 7,
+ CSSM, 1,
+ Offset(0x10), /* AcpiEnable */
+ , 6,
+ PWDE, 1,
+ Offset(0x1C), /* ProgramIoEnable */
+ , 3,
+ MKME, 1,
+ IO3E, 1,
+ IO2E, 1,
+ IO1E, 1,
+ IO0E, 1,
+ Offset(0x1D), /* IOMonitorStatus */
+ , 3,
+ MKMS, 1,
+ IO3S, 1,
+ IO2S, 1,
+ IO1S, 1,
+ IO0S,1,
+ Offset(0x20), /* AcpiPmEvtBlk */
+ APEB, 16,
+ Offset(0x36), /* GEvtLevelConfig */
+ , 6,
+ ELC6, 1,
+ ELC7, 1,
+ Offset(0x37), /* GPMLevelConfig0 */
+ , 3,
+ PLC0, 1,
+ PLC1, 1,
+ PLC2, 1,
+ PLC3, 1,
+ PLC8, 1,
+ Offset(0x38), /* GPMLevelConfig1 */
+ , 1,
+ PLC4, 1,
+ PLC5, 1,
+ , 1,
+ PLC6, 1,
+ PLC7, 1,
+ Offset(0x3B), /* PMEStatus1 */
+ GP0S, 1,
+ GM4S, 1,
+ GM5S, 1,
+ APS, 1,
+ GM6S, 1,
+ GM7S, 1,
+ GP2S, 1,
+ STSS, 1,
+ Offset(0x55), /* SoftPciRst */
+ SPRE, 1,
+ , 1,
+ , 1,
+ PNAT, 1,
+ PWMK, 1,
+ PWNS, 1,
+
+ /* Offset(0x61), */ /* Options_1 */
+ /* ,7, */
+ /* R617,1, */
+
+ Offset(0x65), /* UsbPMControl */
+ , 4,
+ URRE, 1,
+ Offset(0x68), /* MiscEnable68 */
+ , 3,
+ TMTE, 1,
+ , 1,
+ Offset(0x92), /* GEVENTIN */
+ , 7,
+ E7IS, 1,
+ Offset(0x96), /* GPM98IN */
+ G8IS, 1,
+ G9IS, 1,
+ Offset(0x9A), /* EnhanceControl */
+ ,7,
+ HPDE, 1,
+ Offset(0xA8), /* PIO7654Enable */
+ IO4E, 1,
+ IO5E, 1,
+ IO6E, 1,
+ IO7E, 1,
+ Offset(0xA9), /* PIO7654Status */
+ IO4S, 1,
+ IO5S, 1,
+ IO6S, 1,
+ IO7S, 1,
+ }
+
+ /* PM1 Event Block
+ * First word is PM1_Status, Second word is PM1_Enable
+ */
+ OperationRegion(P1EB, SystemIO, APEB, 0x04)
+ Field(P1EB, ByteAcc, NoLock, Preserve) {
+ TMST, 1,
+ , 3,
+ BMST, 1,
+ GBST, 1,
+ Offset(0x01),
+ PBST, 1,
+ , 1,
+ RTST, 1,
+ , 3,
+ PWST, 1,
+ SPWS, 1,
+ Offset(0x02),
+ TMEN, 1,
+ , 4,
+ GBEN, 1,
+ Offset(0x03),
+ PBEN, 1,
+ , 1,
+ RTEN, 1,
+ , 3,
+ PWDA, 1,
+ }
+
+ Scope(\_SB) {
+
+ /* PCIe Configuration Space for 16 busses */
+ OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
+ Field(PCFG, ByteAcc, NoLock, Preserve) {
+ /* Byte offsets are computed using the following technique:
+ * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
+ * The 8 comes from 8 functions per device, and 4096 bytes per function config space
+ */
+ Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */
+ STB5, 32,
+ Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
+ PT0D, 1,
+ PT1D, 1,
+ PT2D, 1,
+ PT3D, 1,
+ PT4D, 1,
+ PT5D, 1,
+ PT6D, 1,
+ PT7D, 1,
+ PT8D, 1,
+ PT9D, 1,
+ Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
+ SBIE, 1,
+ SBME, 1,
+ Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
+ SBRI, 8,
+ Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
+ SBB1, 32,
+ Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
+ ,14,
+ P92E, 1, /* Port92 decode enable */
+ }
+
+ OperationRegion(SB5, SystemMemory, STB5, 0x1000)
+ Field(SB5, AnyAcc, NoLock, Preserve)
+ {
+ /* Port 0 */
+ Offset(0x120), /* Port 0 Task file status */
+ P0ER, 1,
+ , 2,
+ P0DQ, 1,
+ , 3,
+ P0BY, 1,
+ Offset(0x128), /* Port 0 Serial ATA status */
+ P0DD, 4,
+ , 4,
+ P0IS, 4,
+ Offset(0x12C), /* Port 0 Serial ATA control */
+ P0DI, 4,
+ Offset(0x130), /* Port 0 Serial ATA error */
+ , 16,
+ P0PR, 1,
+
+ /* Port 1 */
+ offset(0x1A0), /* Port 1 Task file status */
+ P1ER, 1,
+ , 2,
+ P1DQ, 1,
+ , 3,
+ P1BY, 1,
+ Offset(0x1A8), /* Port 1 Serial ATA status */
+ P1DD, 4,
+ , 4,
+ P1IS, 4,
+ Offset(0x1AC), /* Port 1 Serial ATA control */
+ P1DI, 4,
+ Offset(0x1B0), /* Port 1 Serial ATA error */
+ , 16,
+ P1PR, 1,
+
+ /* Port 2 */
+ Offset(0x220), /* Port 2 Task file status */
+ P2ER, 1,
+ , 2,
+ P2DQ, 1,
+ , 3,
+ P2BY, 1,
+ Offset(0x228), /* Port 2 Serial ATA status */
+ P2DD, 4,
+ , 4,
+ P2IS, 4,
+ Offset(0x22C), /* Port 2 Serial ATA control */
+ P2DI, 4,
+ Offset(0x230), /* Port 2 Serial ATA error */
+ , 16,
+ P2PR, 1,
+
+ /* Port 3 */
+ Offset(0x2A0), /* Port 3 Task file status */
+ P3ER, 1,
+ , 2,
+ P3DQ, 1,
+ , 3,
+ P3BY, 1,
+ Offset(0x2A8), /* Port 3 Serial ATA status */
+ P3DD, 4,
+ , 4,
+ P3IS, 4,
+ Offset(0x2AC), /* Port 3 Serial ATA control */
+ P3DI, 4,
+ Offset(0x2B0), /* Port 3 Serial ATA error */
+ , 16,
+ P3PR, 1,
+ }
+ }
+
+ #include "acpi/routing.asl"
+
+ Scope(\_SB) {
+
+ Method(CkOT, 0){
+
+ if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */
+
+ if(CondRefOf(\_OSI,Local1))
+ {
+ Store(1, OSTP) /* Assume some form of XP */
+ if (\_OSI("Windows 2006")) /* Vista */
+ {
+ Store(2, OSTP)
+ }
+ } else {
+ If(WCMP(\_OS,"Linux")) {
+ Store(3, OSTP) /* Linux */
+ } Else {
+ Store(4, OSTP) /* Gotta be WinCE */
+ }
+ }
+ Return(OSTP)
+ }
+
+ Method(_PIC, 0x01, NotSerialized)
+ {
+ If (Arg0)
+ {
+ \_SB.CIRQ()
+ }
+ Store(Arg0, PMOD)
+ }
+
+ Method(CIRQ, 0x00, NotSerialized)
+ {
+ Store(0, PINA)
+ Store(0, PINB)
+ Store(0, PINC)
+ Store(0, PIND)
+ Store(0, PINE)
+ Store(0, PINF)
+ Store(0, PING)
+ Store(0, PINH)
+ }
+
+ Name(IRQB, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Shared){15}
+ })
+
+ Name(IRQP, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
+ })
+
+ Name(PITF, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Exclusive){9}
+ })
+
+ Device(INTA) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 1)
+
+ Method(_STA, 0) {
+ if (PINA) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTA._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_DIS\n") */
+ Store(0, PINA)
+ } /* End Method(_SB.INTA._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTA._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINA, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTA._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKA\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINA)
+ } /* End Method(_SB.INTA._SRS) */
+ } /* End Device(INTA) */
+
+ Device(INTB) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 2)
+
+ Method(_STA, 0) {
+ if (PINB) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTB._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_DIS\n") */
+ Store(0, PINB)
+ } /* End Method(_SB.INTB._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTB._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINB, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTB._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKB\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINB)
+ } /* End Method(_SB.INTB._SRS) */
+ } /* End Device(INTB) */
+
+ Device(INTC) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 3)
+
+ Method(_STA, 0) {
+ if (PINC) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTC._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_DIS\n") */
+ Store(0, PINC)
+ } /* End Method(_SB.INTC._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTC._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINC, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTC._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKC\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINC)
+ } /* End Method(_SB.INTC._SRS) */
+ } /* End Device(INTC) */
+
+ Device(INTD) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 4)
+
+ Method(_STA, 0) {
+ if (PIND) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTD._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_DIS\n") */
+ Store(0, PIND)
+ } /* End Method(_SB.INTD._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTD._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIND, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTD._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKD\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIND)
+ } /* End Method(_SB.INTD._SRS) */
+ } /* End Device(INTD) */
+
+ Device(INTE) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 5)
+
+ Method(_STA, 0) {
+ if (PINE) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTE._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_DIS\n") */
+ Store(0, PINE)
+ } /* End Method(_SB.INTE._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTE._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINE, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTE._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKE\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINE)
+ } /* End Method(_SB.INTE._SRS) */
+ } /* End Device(INTE) */
+
+ Device(INTF) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 6)
+
+ Method(_STA, 0) {
+ if (PINF) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTF._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_DIS\n") */
+ Store(0, PINF)
+ } /* End Method(_SB.INTF._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_PRS\n") */
+ Return(PITF)
+ } /* Method(_SB.INTF._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINF, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTF._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKF\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINF)
+ } /* End Method(_SB.INTF._SRS) */
+ } /* End Device(INTF) */
+
+ Device(INTG) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 7)
+
+ Method(_STA, 0) {
+ if (PING) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTG._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKG\\_DIS\n") */
+ Store(0, PING)
+ } /* End Method(_SB.INTG._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKG\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTG._CRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKG\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PING, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTG._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKG\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PING)
+ } /* End Method(_SB.INTG._SRS) */
+ } /* End Device(INTG) */
+
+ Device(INTH) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 8)
+
+ Method(_STA, 0) {
+ if (PINH) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTH._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKH\\_DIS\n") */
+ Store(0, PINH)
+ } /* End Method(_SB.INTH._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKH\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTH._CRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKH\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINH, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTH._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKH\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINH)
+ } /* End Method(_SB.INTH._SRS) */
+ } /* End Device(INTH) */
+
+ } /* End Scope(_SB) */
+
+
+ /* Supported sleep states: */
+ Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
+
+ If (LAnd(SSFG, 0x01)) {
+ Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
+ }
+ If (LAnd(SSFG, 0x02)) {
+ Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
+ }
+ If (LAnd(SSFG, 0x04)) {
+ Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
+ }
+ If (LAnd(SSFG, 0x08)) {
+ Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
+ }
+
+ Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
+
+ Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
+ Name(CSMS, 0) /* Current System State */
+
+ /* Wake status package */
+ Name(WKST,Package(){Zero, Zero})
+
+ /*
+ * \_PTS - Prepare to Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2, etc
+ *
+ * Exit:
+ * -none-
+ *
+ * The _PTS control method is executed at the beginning of the sleep process
+ * for S1-S5. The sleeping value is passed to the _PTS control method. This
+ * control method may be executed a relatively long time before entering the
+ * sleep state and the OS may abort the operation without notification to
+ * the ACPI driver. This method cannot modify the configuration or power
+ * state of any device in the system.
+ */
+ Method(\_PTS, 1) {
+ /* DBGO("\\_PTS\n") */
+ /* DBGO("From S0 to S") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+
+ /* Don't allow PCIRST# to reset USB */
+ if (LEqual(Arg0,3)){
+ Store(0,URRE)
+ }
+
+ /* Clear sleep SMI status flag and enable sleep SMI trap. */
+ /*Store(One, CSSM)
+ Store(One, SSEN)*/
+
+ /* On older chips, clear PciExpWakeDisEn */
+ /*if (LLessEqual(\_SB.SBRI, 0x13)) {
+ * Store(0,\_SB.PWDE)
+ *}
+ */
+
+ /* Clear wake status structure. */
+ Store(0, Index(WKST,0))
+ Store(0, Index(WKST,1))
+ \_SB.PCI0.SIOS (Arg0)
+ } /* End Method(\_PTS) */
+
+ /*
+ * The following method results in a "not a valid reserved NameSeg"
+ * warning so I have commented it out for the duration. It isn't
+ * used, so it could be removed.
+ *
+ *
+ * \_GTS OEM Going To Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * -none-
+ *
+ * Method(\_GTS, 1) {
+ * DBGO("\\_GTS\n")
+ * DBGO("From S0 to S")
+ * DBGO(Arg0)
+ * DBGO("\n")
+ * }
+ */
+
+ /*
+ * \_BFS OEM Back From Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * -none-
+ */
+ Method(\_BFS, 1) {
+ /* DBGO("\\_BFS\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+ }
+
+ /*
+ * \_WAK System Wake method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * Return package of 2 DWords
+ * Dword 1 - Status
+ * 0x00000000 wake succeeded
+ * 0x00000001 Wake was signaled but failed due to lack of power
+ * 0x00000002 Wake was signaled but failed due to thermal condition
+ * Dword 2 - Power Supply state
+ * if non-zero the effective S-state the power supply entered
+ */
+ Method(\_WAK, 1) {
+ /* DBGO("\\_WAK\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+
+ /* Re-enable HPET */
+ Store(1,HPDE)
+
+ /* Restore PCIRST# so it resets USB */
+ if (LEqual(Arg0,3)){
+ Store(1,URRE)
+ }
+
+ /* Arbitrarily clear PciExpWakeStatus */
+ Store(PWST, PWST)
+
+ /* if(DeRefOf(Index(WKST,0))) {
+ * Store(0, Index(WKST,1))
+ * } else {
+ * Store(Arg0, Index(WKST,1))
+ * }
+ */
+ \_SB.PCI0.SIOW (Arg0)
+ Return(WKST)
+ } /* End Method(\_WAK) */
+
+ Scope(\_GPE) { /* Start Scope GPE */
+ /* General event 0 */
+ /* Method(_L00) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 1 */
+ /* Method(_L01) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 2 */
+ /* Method(_L02) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 3 */
+ Method(_L03) {
+ /* DBGO("\\_GPE\\_L00\n") */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* General event 4 */
+ /* Method(_L04) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 5 */
+ /* Method(_L05) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 6 - Used for GPM6, moved to USB.asl */
+ /* Method(_L06) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 7 - Used for GPM7, moved to USB.asl */
+ /* Method(_L07) {
+ * DBGO("\\_GPE\\_L07\n")
+ * }
+ */
+
+ /* Legacy PM event */
+ Method(_L08) {
+ /* DBGO("\\_GPE\\_L08\n") */
+ }
+
+ /* Temp warning (TWarn) event */
+ Method(_L09) {
+ /* DBGO("\\_GPE\\_L09\n") */
+ Notify (\_TZ.TZ00, 0x80)
+ }
+
+ /* Reserved */
+ /* Method(_L0A) {
+ * DBGO("\\_GPE\\_L0A\n")
+ * }
+ */
+
+ /* USB controller PME# */
+ Method(_L0B) {
+ /* DBGO("\\_GPE\\_L0B\n") */
+ Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* AC97 controller PME# */
+ /* Method(_L0C) {
+ * DBGO("\\_GPE\\_L0C\n")
+ * }
+ */
+
+ /* OtherTherm PME# */
+ /* Method(_L0D) {
+ * DBGO("\\_GPE\\_L0D\n")
+ * }
+ */
+
+ /* GPM9 SCI event - Moved to USB.asl */
+ /* Method(_L0E) {
+ * DBGO("\\_GPE\\_L0E\n")
+ * }
+ */
+
+ /* PCIe HotPlug event */
+ /* Method(_L0F) {
+ * DBGO("\\_GPE\\_L0F\n")
+ * }
+ */
+
+ /* ExtEvent0 SCI event */
+ Method(_L10) {
+ /* DBGO("\\_GPE\\_L10\n") */
+ }
+
+
+ /* ExtEvent1 SCI event */
+ Method(_L11) {
+ /* DBGO("\\_GPE\\_L11\n") */
+ }
+
+ /* PCIe PME# event */
+ /* Method(_L12) {
+ * DBGO("\\_GPE\\_L12\n")
+ * }
+ */
+
+ /* GPM0 SCI event - Moved to USB.asl */
+ /* Method(_L13) {
+ * DBGO("\\_GPE\\_L13\n")
+ * }
+ */
+
+ /* GPM1 SCI event - Moved to USB.asl */
+ /* Method(_L14) {
+ * DBGO("\\_GPE\\_L14\n")
+ * }
+ */
+
+ /* GPM2 SCI event - Moved to USB.asl */
+ /* Method(_L15) {
+ * DBGO("\\_GPE\\_L15\n")
+ * }
+ */
+
+ /* GPM3 SCI event - Moved to USB.asl */
+ /* Method(_L16) {
+ * DBGO("\\_GPE\\_L16\n")
+ * }
+ */
+
+ /* GPM8 SCI event - Moved to USB.asl */
+ /* Method(_L17) {
+ * DBGO("\\_GPE\\_L17\n")
+ * }
+ */
+
+ /* GPIO0 or GEvent8 event */
+ Method(_L18) {
+ /* DBGO("\\_GPE\\_L18\n") */
+ Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* GPM4 SCI event - Moved to USB.asl */
+ /* Method(_L19) {
+ * DBGO("\\_GPE\\_L19\n")
+ * }
+ */
+
+ /* GPM5 SCI event - Moved to USB.asl */
+ /* Method(_L1A) {
+ * DBGO("\\_GPE\\_L1A\n")
+ * }
+ */
+
+ /* Azalia SCI event */
+ Method(_L1B) {
+ /* DBGO("\\_GPE\\_L1B\n") */
+ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* GPM6 SCI event - Reassigned to _L06 */
+ /* Method(_L1C) {
+ * DBGO("\\_GPE\\_L1C\n")
+ * }
+ */
+
+ /* GPM7 SCI event - Reassigned to _L07 */
+ /* Method(_L1D) {
+ * DBGO("\\_GPE\\_L1D\n")
+ * }
+ */
+
+ /* GPIO2 or GPIO66 SCI event */
+ /* Method(_L1E) {
+ * DBGO("\\_GPE\\_L1E\n")
+ * }
+ */
+
+ /* SATA SCI event - Moved to sata.asl */
+ /* Method(_L1F) {
+ * DBGO("\\_GPE\\_L1F\n")
+ * }
+ */
+
+ } /* End Scope GPE */
+
+ #include "acpi/usb.asl"
+
+ /* South Bridge */
+ Scope(\_SB) { /* Start \_SB scope */
+ #include "acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
+
+ /* _SB.PCI0 */
+ /* Note: Only need HID on Primary Bus */
+ Device(PCI0) {
+ External (TOM1)
+ External (TOM2)
+ Name(_HID, EISAID("PNP0A03"))
+ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
+ Method(_BBN, 0) { /* Bus number = 0 */
+ Return(0)
+ }
+ Method(_STA, 0) {
+ /* DBGO("\\_SB\\PCI0\\_STA\n") */
+ Return(0x0B) /* Status is visible */
+ }
+
+ Method(_PRT,0) {
+ If(PMOD){ Return(APR0) } /* APIC mode */
+ Return (PR0) /* PIC Mode */
+ } /* end _PRT */
+
+ /* Describe the Northbridge devices */
+ Device(AMRT) {
+ Name(_ADR, 0x00000000)
+ } /* end AMRT */
+
+ /* The internal GFX bridge */
+ Device(AGPB) {
+ Name(_ADR, 0x00010000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ Return (APR1)
+ }
+ } /* end AGPB */
+
+ /* The external GFX bridge */
+ Device(PBR2) {
+ Name(_ADR, 0x00020000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS2) } /* APIC mode */
+ Return (PS2) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR2 */
+
+ /* Dev3 is also an external GFX bridge, not used in Herring */
+
+ Device(PBR4) {
+ Name(_ADR, 0x00040000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS4) } /* APIC mode */
+ Return (PS4) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR4 */
+
+ Device(PBR5) {
+ Name(_ADR, 0x00050000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS5) } /* APIC mode */
+ Return (PS5) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR5 */
+
+ Device(PBR6) {
+ Name(_ADR, 0x00060000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS6) } /* APIC mode */
+ Return (PS6) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR6 */
+
+ /* The onboard EtherNet chip */
+ Device(PBR7) {
+ Name(_ADR, 0x00070000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS7) } /* APIC mode */
+ Return (PS7) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR7 */
+
+
+ /* PCI slot 1, 2, 3 */
+ Device(PIBR) {
+ Name(_ADR, 0x00140004)
+ Name(_PRW, Package() {0x18, 4})
+
+ Method(_PRT, 0) {
+ Return (PCIB)
+ }
+ }
+
+ /* Describe the Southbridge devices */
+ Device(STCR) {
+ Name(_ADR, 0x00120000)
+ #include "acpi/sata.asl"
+ } /* end STCR */
+
+ Device(UOH1) {
+ Name(_ADR, 0x00130000)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH1 */
+
+ Device(UOH2) {
+ Name(_ADR, 0x00130001)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH2 */
+
+ Device(UOH3) {
+ Name(_ADR, 0x00130002)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH3 */
+
+ Device(UOH4) {
+ Name(_ADR, 0x00130003)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH4 */
+
+ Device(UOH5) {
+ Name(_ADR, 0x00130004)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH5 */
+
+ Device(UEH1) {
+ Name(_ADR, 0x00130005)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UEH1 */
+
+ Device(SBUS) {
+ Name(_ADR, 0x00140000)
+ } /* end SBUS */
+
+ /* Primary (and only) IDE channel */
+ Device(IDEC) {
+ Name(_ADR, 0x00140001)
+ #include "acpi/ide.asl"
+ } /* end IDEC */
+
+ Device(AZHD) {
+ Name(_ADR, 0x00140002)
+ OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
+ Field(AZPD, AnyAcc, NoLock, Preserve) {
+ offset (0x42),
+ NSDI, 1,
+ NSDO, 1,
+ NSEN, 1,
+ offset (0x44),
+ IPCR, 4,
+ offset (0x54),
+ PWST, 2,
+ , 6,
+ PMEB, 1,
+ , 6,
+ PMST, 1,
+ offset (0x62),
+ MMCR, 1,
+ offset (0x64),
+ MMLA, 32,
+ offset (0x68),
+ MMHA, 32,
+ offset (0x6C),
+ MMDT, 16,
+ }
+
+ Method(_INI) {
+ If(LEqual(OSTP,3)){ /* If we are running Linux */
+ Store(zero, NSEN)
+ Store(one, NSDO)
+ Store(one, NSDI)
+ }
+ }
+ } /* end AZHD */
+
+ Device(LIBR) {
+ Name(_ADR, 0x00140003)
+ /* Method(_INI) {
+ * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
+ } */ /* End Method(_SB.SBRDG._INI) */
+
+ /* Real Time Clock Device */
+ Device(RTC0) {
+ Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){8}
+ IO(Decode16,0x0070, 0x0070, 0, 2)
+ /* IO(Decode16,0x0070, 0x0070, 0, 4) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
+
+ Device(TMR) { /* Timer */
+ Name(_HID,EISAID("PNP0100")) /* System Timer */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){0}
+ IO(Decode16, 0x0040, 0x0040, 0, 4)
+ /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
+
+ Device(SPKR) { /* Speaker */
+ Name(_HID,EISAID("PNP0800")) /* AT style speaker */
+ Name(_CRS, ResourceTemplate() {
+ IO(Decode16, 0x0061, 0x0061, 0, 1)
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
+
+ Device(PIC) {
+ Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){2}
+ IO(Decode16,0x0020, 0x0020, 0, 2)
+ IO(Decode16,0x00A0, 0x00A0, 0, 2)
+ /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
+ /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
+
+ Device(MAD) { /* 8257 DMA */
+ Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
+ Name(_CRS, ResourceTemplate() {
+ DMA(Compatibility,BusMaster,Transfer8){4}
+ IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
+ IO(Decode16, 0x0081, 0x0081, 0x10, 0x03)
+ IO(Decode16, 0x0087, 0x0087, 0x10, 0x01)
+ IO(Decode16, 0x0089, 0x0089, 0x10, 0x03)
+ IO(Decode16, 0x008F, 0x008F, 0x10, 0x01)
+ IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
+ }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
+ } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
+
+ Device(COPR) {
+ Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
+ Name(_CRS, ResourceTemplate() {
+ IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
+ IRQNoFlags(){13}
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+
+ Device(HPTM) {
+ Name(_HID,EISAID("PNP0103"))
+ Name(CRS,ResourceTemplate() {
+ Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
+ })
+ Method(_STA, 0) {
+ Return(0x0F) /* sata is visible */
+ }
+ Method(_CRS, 0) {
+ CreateDwordField(CRS, ^HPT._BAS, HPBA)
+ Store(HPBA, HPBA)
+ Return(CRS)
+ }
+ } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+ } /* end LIBR */
+
+ Device(HPBR) {
+ Name(_ADR, 0x00140004)
+ } /* end HostPciBr */
+
+ Device(ACAD) {
+ Name(_ADR, 0x00140005)
+ } /* end Ac97audio */
+
+ Device(ACMD) {
+ Name(_ADR, 0x00140006)
+ } /* end Ac97modem */
+
+ /* ITE IT8712F Support */
+ OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
+ Field (IOID, ByteAcc, NoLock, Preserve)
+ {
+ SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */
+ }
+
+ IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x07),
+ LDN, 8, /* Logical Device Number */
+ Offset (0x20),
+ CID1, 8, /* Chip ID Byte 1, 0x87 */
+ CID2, 8, /* Chip ID Byte 2, 0x12 */
+ Offset (0x30),
+ ACTR, 8, /* Function activate */
+ Offset (0xF0),
+ APC0, 8, /* APC/PME Event Enable Register */
+ APC1, 8, /* APC/PME Status Register */
+ APC2, 8, /* APC/PME Control Register 1 */
+ APC3, 8, /* Environment Controller Special Configuration Register */
+ APC4, 8 /* APC/PME Control Register 2 */
+ }
+
+ /* Enter the IT8712F MB PnP Mode */
+ Method (EPNP)
+ {
+ Store(0x87, SIOI)
+ Store(0x01, SIOI)
+ Store(0x55, SIOI)
+ Store(0x55, SIOI) /* IT8712F magic number */
+ }
+ /* Exit the IT8712F MB PnP Mode */
+ Method (XPNP)
+ {
+ Store (0x02, SIOI)
+ Store (0x02, SIOD)
+ }
+
+ /*
+ * Keyboard PME is routed to SB600 Gevent3. We can wake
+ * up the system by pressing the key.
+ */
+ Method (SIOS, 1)
+ {
+ /* We only enable KBD PME for S5. */
+ If (LLess (Arg0, 0x05))
+ {
+ EPNP()
+ /* DBGO("IT8712F\n") */
+
+ Store (0x4, LDN)
+ Store (One, ACTR) /* Enable EC */
+ /*
+ Store (0x4, LDN)
+ Store (0x04, APC4)
+ */ /* falling edge. which mode? Not sure. */
+
+ Store (0x4, LDN)
+ Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
+ Store (0x4, LDN)
+ Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
+
+ XPNP()
+ }
+ }
+ Method (SIOW, 1)
+ {
+ EPNP()
+ Store (0x4, LDN)
+ Store (Zero, APC0) /* disable keyboard PME */
+ Store (0x4, LDN)
+ Store (0xFF, APC1) /* clear keyboard PME status */
+ XPNP()
+ }
+
+ Name(CRES, ResourceTemplate() {
+ IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
+
+ WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, /* address granularity */
+ 0x0000, /* range minimum */
+ 0x0CF7, /* range maximum */
+ 0x0000, /* translation */
+ 0x0CF8 /* length */
+ )
+
+ WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, /* address granularity */
+ 0x0D00, /* range minimum */
+ 0xFFFF, /* range maximum */
+ 0x0000, /* translation */
+ 0xF300 /* length */
+ )
+
+ Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
+ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
+ Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
+ Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
+
+ /* DRAM Memory from 1MB to TopMem */
+ Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
+
+ /* BIOS space just below 4GB */
+ DWORDMemory(
+ ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00, /* Granularity */
+ 0x00000000, /* Min */
+ 0x00000000, /* Max */
+ 0x00000000, /* Translation */
+ 0x00000000, /* Max-Min, RLEN */
+ ,,
+ PCBM
+ )
+
+ /* DRAM memory from 4GB to TopMem2 */
+ QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0xFFFFFFFF, /* Granularity */
+ 0x00000000, /* Min */
+ 0x00000000, /* Max */
+ 0x00000000, /* Translation */
+ 0x00000000, /* Max-Min, RLEN */
+ ,,
+ DMHI
+ )
+
+ /* BIOS space just below 16EB */
+ QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0xFFFFFFFF, /* Granularity */
+ 0x00000000, /* Min */
+ 0x00000000, /* Max */
+ 0x00000000, /* Translation */
+ 0x00000000, /* Max-Min, RLEN */
+ ,,
+ PEBM
+ )
+
+ }) /* End Name(_SB.PCI0.CRES) */
+
+ Method(_CRS, 0) {
+ /* DBGO("\\_SB\\PCI0\\_CRS\n") */
+
+ CreateDWordField(CRES, ^EMM1._BAS, EM1B)
+ CreateDWordField(CRES, ^EMM1._LEN, EM1L)
+ CreateDWordField(CRES, ^DMLO._BAS, DMLB)
+ CreateDWordField(CRES, ^DMLO._LEN, DMLL)
+ CreateDWordField(CRES, ^PCBM._MIN, PBMB)
+ CreateDWordField(CRES, ^PCBM._LEN, PBML)
+
+ CreateQWordField(CRES, ^DMHI._MIN, DMHB)
+ CreateQWordField(CRES, ^DMHI._LEN, DMHL)
+ CreateQWordField(CRES, ^PEBM._MIN, EBMB)
+ CreateQWordField(CRES, ^PEBM._LEN, EBML)
+
+ If(LGreater(LOMH, 0xC0000)){
+ Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
+ Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
+ }
+
+ /* Set size of memory from 1MB to TopMem */
+ Subtract(TOM1, 0x100000, DMLL)
+
+ /*
+ * If(LNotEqual(TOM2, 0x00000000)){
+ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
+ * Subtract(TOM2, 0x100000000, DMHL)
+ * }
+ */
+
+ /* If there is no memory above 4GB, put the BIOS just below 4GB */
+ If(LEqual(TOM2, 0x00000000)){
+ Store(PBAD,PBMB) /* Reserve the "BIOS" space */
+ Store(PBLN,PBML)
+ }
+ Else { /* Otherwise, put the BIOS just below 16EB */
+ ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
+ Store(PBLN,EBML)
+ }
+
+ Return(CRES) /* note to change the Name buffer */
+ } /* end of Method(_SB.PCI0._CRS) */
+
+ /*
+ *
+ * FIRST METHOD CALLED UPON BOOT
+ *
+ * 1. If debugging, print current OS and ACPI interpreter.
+ * 2. Get PCI Interrupt routing from ACPI VSM, this
+ * value is based on user choice in BIOS setup.
+ */
+ Method(_INI, 0) {
+ /* DBGO("\\_SB\\_INI\n") */
+ /* DBGO(" DSDT.ASL code from ") */
+ /* DBGO(__DATE__) */
+ /* DBGO(" ") */
+ /* DBGO(__TIME__) */
+ /* DBGO("\n Sleep states supported: ") */
+ /* DBGO("\n") */
+ /* DBGO(" \\_OS=") */
+ /* DBGO(\_OS) */
+ /* DBGO("\n \\_REV=") */
+ /* DBGO(\_REV) */
+ /* DBGO("\n") */
+
+ /* Determine the OS we're running on */
+ CkOT()
+
+ /* On older chips, clear PciExpWakeDisEn */
+ /*if (LLessEqual(\SBRI, 0x13)) {
+ * Store(0,\PWDE)
+ * }
+ */
+ } /* End Method(_SB._INI) */
+ } /* End Device(PCI0) */
+
+ Device(PWRB) { /* Start Power button device */
+ Name(_HID, EISAID("PNP0C0C"))
+ Name(_UID, 0xAA)
+ Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
+ Name(_STA, 0x0B) /* sata is invisible */
+ }
+ } /* End \_SB scope */
+
+ Scope(\_SI) {
+ Method(_SST, 1) {
+ /* DBGO("\\_SI\\_SST\n") */
+ /* DBGO(" New Indicator state: ") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+ }
+ } /* End Scope SI */
+
+ Mutex (SBX0, 0x00)
+ OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
+ Field (SMB0, ByteAcc, NoLock, Preserve) {
+ HSTS, 8, /* SMBUS status */
+ SSTS, 8, /* SMBUS slave status */
+ HCNT, 8, /* SMBUS control */
+ HCMD, 8, /* SMBUS host cmd */
+ HADD, 8, /* SMBUS address */
+ DAT0, 8, /* SMBUS data0 */
+ DAT1, 8, /* SMBUS data1 */
+ BLKD, 8, /* SMBUS block data */
+ SCNT, 8, /* SMBUS slave control */
+ SCMD, 8, /* SMBUS shaow cmd */
+ SEVT, 8, /* SMBUS slave event */
+ SDAT, 8 /* SMBUS slave data */
+ }
+
+ Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
+ Store (0x1E, HSTS)
+ Store (0xFA, Local0)
+ While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
+ Stall (0x64)
+ Decrement (Local0)
+ }
+
+ Return (Local0)
+ }
+
+ Method (SWTC, 1, NotSerialized) {
+ Store (Arg0, Local0)
+ Store (0x07, Local2)
+ Store (One, Local1)
+ While (LEqual (Local1, One)) {
+ Store (And (HSTS, 0x1E), Local3)
+ If (LNotEqual (Local3, Zero)) { /* read sucess */
+ If (LEqual (Local3, 0x02)) {
+ Store (Zero, Local2)
+ }
+
+ Store (Zero, Local1)
+ }
+ Else {
+ If (LLess (Local0, 0x0A)) { /* read failure */
+ Store (0x10, Local2)
+ Store (Zero, Local1)
+ }
+ Else {
+ Sleep (0x0A) /* 10 ms, try again */
+ Subtract (Local0, 0x0A, Local0)
+ }
+ }
+ }
+
+ Return (Local2)
+ }
+
+ Method (SMBR, 3, NotSerialized) {
+ Store (0x07, Local0)
+ If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
+ Store (WCLR (), Local0) /* clear SMBUS status register before read data */
+ If (LEqual (Local0, Zero)) {
+ Release (SBX0)
+ Return (0x0)
+ }
+
+ Store (0x1F, HSTS)
+ Store (Or (ShiftLeft (Arg1, One), One), HADD)
+ Store (Arg2, HCMD)
+ If (LEqual (Arg0, 0x07)) {
+ Store (0x48, HCNT) /* read byte */
+ }
+
+ Store (SWTC (0x03E8), Local1) /* 1000 ms */
+ If (LEqual (Local1, Zero)) {
+ If (LEqual (Arg0, 0x07)) {
+ Store (DAT0, Local0)
+ }
+ }
+ Else {
+ Store (Local1, Local0)
+ }
+
+ Release (SBX0)
+ }
+
+ /* DBGO("the value of SMBusData0 register ") */
+ /* DBGO(Arg2) */
+ /* DBGO(" is ") */
+ /* DBGO(Local0) */
+ /* DBGO("\n") */
+
+ Return (Local0)
+ }
+
+ /* THERMAL */
+ Scope(\_TZ) {
+ Name (KELV, 2732)
+ Name (THOT, 800)
+ Name (TCRT, 850)
+
+ ThermalZone(TZ00) {
+ Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
+ /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
+ Return(Add(0, 2730))
+ }
+ Method(_AL0,0) { /* Returns package of cooling device to turn on */
+ /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
+ Return(Package() {\_TZ.TZ00.FAN0})
+ }
+ Device (FAN0) {
+ Name(_HID, EISAID("PNP0C0B"))
+ Name(_PR0, Package() {PFN0})
+ }
+
+ PowerResource(PFN0,0,0) {
+ Method(_STA) {
+ Store(0xF,Local0)
+ Return(Local0)
+ }
+ Method(_ON) {
+ /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
+ }
+ Method(_OFF) {
+ /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
+ }
+ }
+
+ Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
+ /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
+ Return (Add (THOT, KELV))
+ }
+ Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
+ /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
+ Return (Add (TCRT, KELV))
+ }
+ Method(_TMP,0) { /* return current temp of this zone */
+ Store (SMBR (0x07, 0x4C,, 0x00), Local0)
+ If (LGreater (Local0, 0x10)) {
+ Store (Local0, Local1)
+ }
+ Else {
+ Add (Local0, THOT, Local0)
+ Return (Add (400, KELV))
+ }
+
+ Store (SMBR (0x07, 0x4C, 0x01), Local0)
+ /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
+ /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
+ If (LGreater (Local0, 0x10)) {
+ If (LGreater (Local0, Local1)) {
+ Store (Local0, Local1)
+ }
+
+ Multiply (Local1, 10, Local1)
+ Return (Add (Local1, KELV))
+ }
+ Else {
+ Add (Local0, THOT, Local0)
+ Return (Add (400 , KELV))
+ }
+ } /* end of _TMP */
+ } /* end of TZ00 */
+ }
+}
+/* End of ASL file */
ifdef POST_EVALUATION
-$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/acpi/dsdt.asl
- iasl -p $(obj)/dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/acpi/dsdt.asl
- mv $(obj)/dsdt.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
0x00010001
)
{
- Include ("debug.asl")
+ #include "debug.asl"
}
*/
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* DefinitionBlock Statement */
-DefinitionBlock (
- "DSDT.AML", /* Output filename */
- "DSDT", /* Signature */
- 0x02, /* DSDT Revision, needs to be 2 for 64bit */
- "AMD ", /* OEMID */
- "PISTACHI", /* TABLE ID */
- 0x00010001 /* OEM Revision */
- )
-{ /* Start of ASL file */
- /* Include ("debug.asl") */ /* Include global debug methods if needed */
-
- /* Data to be patched by the BIOS during POST */
- /* FIXME the patching is not done yet! */
- /* Memory related values */
- Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
- Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
- Name(PBLN, 0x0) /* Length of BIOS area */
-
- Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
- Name(HPBA, 0xFED00000) /* Base address of HPET table */
-
- Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
-
- /* USB overcurrent mapping pins. */
- Name(UOM0, 0)
- Name(UOM1, 2)
- Name(UOM2, 0)
- Name(UOM3, 7)
- Name(UOM4, 2)
- Name(UOM5, 2)
- Name(UOM6, 6)
- Name(UOM7, 2)
- Name(UOM8, 6)
- Name(UOM9, 6)
-
- /* Some global data */
- Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
- Name(OSV, Ones) /* Assume nothing */
- Name(PMOD, One) /* Assume APIC */
-
- /* PIC IRQ mapping registers, C00h-C01h */
- OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
- Field(PRQM, ByteAcc, NoLock, Preserve) {
- PRQI, 0x00000008,
- PRQD, 0x00000008, /* Offset: 1h */
- }
- IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
- PINA, 0x00000008, /* Index 0 */
- PINB, 0x00000008, /* Index 1 */
- PINC, 0x00000008, /* Index 2 */
- PIND, 0x00000008, /* Index 3 */
- AINT, 0x00000008, /* Index 4 */
- SINT, 0x00000008, /* Index 5 */
- , 0x00000008, /* Index 6 */
- AAUD, 0x00000008, /* Index 7 */
- AMOD, 0x00000008, /* Index 8 */
- PINE, 0x00000008, /* Index 9 */
- PINF, 0x00000008, /* Index A */
- PING, 0x00000008, /* Index B */
- PINH, 0x00000008, /* Index C */
- }
-
- /* PCI Error control register */
- OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
- Field(PERC, ByteAcc, NoLock, Preserve) {
- SENS, 0x00000001,
- PENS, 0x00000001,
- SENE, 0x00000001,
- PENE, 0x00000001,
- }
-
- /* Client Management index/data registers */
- OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
- Field(CMT, ByteAcc, NoLock, Preserve) {
- CMTI, 8,
- /* Client Management Data register */
- G64E, 1,
- G64O, 1,
- G32O, 2,
- , 2,
- GPSL, 2,
- }
-
- /* GPM Port register */
- OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
- Field(GPT, ByteAcc, NoLock, Preserve) {
- GPB0,1,
- GPB1,1,
- GPB2,1,
- GPB3,1,
- GPB4,1,
- GPB5,1,
- GPB6,1,
- GPB7,1,
- }
-
- /* Flash ROM program enable register */
- OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
- Field(FRE, ByteAcc, NoLock, Preserve) {
- , 0x00000006,
- FLRE, 0x00000001,
- }
-
- /* PM2 index/data registers */
- OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
- Field(PM2R, ByteAcc, NoLock, Preserve) {
- PM2I, 0x00000008,
- PM2D, 0x00000008,
- }
-
- /* Power Management I/O registers */
- OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
- Field(PIOR, ByteAcc, NoLock, Preserve) {
- PIOI, 0x00000008,
- PIOD, 0x00000008,
- }
- IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
- Offset(0x00), /* MiscControl */
- , 1,
- T1EE, 1,
- T2EE, 1,
- Offset(0x01), /* MiscStatus */
- , 1,
- T1E, 1,
- T2E, 1,
- Offset(0x04), /* SmiWakeUpEventEnable3 */
- , 7,
- SSEN, 1,
- Offset(0x07), /* SmiWakeUpEventStatus3 */
- , 7,
- CSSM, 1,
- Offset(0x10), /* AcpiEnable */
- , 6,
- PWDE, 1,
- Offset(0x1C), /* ProgramIoEnable */
- , 3,
- MKME, 1,
- IO3E, 1,
- IO2E, 1,
- IO1E, 1,
- IO0E, 1,
- Offset(0x1D), /* IOMonitorStatus */
- , 3,
- MKMS, 1,
- IO3S, 1,
- IO2S, 1,
- IO1S, 1,
- IO0S,1,
- Offset(0x20), /* AcpiPmEvtBlk */
- APEB, 16,
- Offset(0x36), /* GEvtLevelConfig */
- , 6,
- ELC6, 1,
- ELC7, 1,
- Offset(0x37), /* GPMLevelConfig0 */
- , 3,
- PLC0, 1,
- PLC1, 1,
- PLC2, 1,
- PLC3, 1,
- PLC8, 1,
- Offset(0x38), /* GPMLevelConfig1 */
- , 1,
- PLC4, 1,
- PLC5, 1,
- , 1,
- PLC6, 1,
- PLC7, 1,
- Offset(0x3B), /* PMEStatus1 */
- GP0S, 1,
- GM4S, 1,
- GM5S, 1,
- APS, 1,
- GM6S, 1,
- GM7S, 1,
- GP2S, 1,
- STSS, 1,
- Offset(0x55), /* SoftPciRst */
- SPRE, 1,
- , 1,
- , 1,
- PNAT, 1,
- PWMK, 1,
- PWNS, 1,
-
- /* Offset(0x61), */ /* Options_1 */
- /* ,7, */
- /* R617,1, */
-
- Offset(0x65), /* UsbPMControl */
- , 4,
- URRE, 1,
- Offset(0x68), /* MiscEnable68 */
- , 3,
- TMTE, 1,
- , 1,
- Offset(0x92), /* GEVENTIN */
- , 7,
- E7IS, 1,
- Offset(0x96), /* GPM98IN */
- G8IS, 1,
- G9IS, 1,
- Offset(0x9A), /* EnhanceControl */
- ,7,
- HPDE, 1,
- Offset(0xA8), /* PIO7654Enable */
- IO4E, 1,
- IO5E, 1,
- IO6E, 1,
- IO7E, 1,
- Offset(0xA9), /* PIO7654Status */
- IO4S, 1,
- IO5S, 1,
- IO6S, 1,
- IO7S, 1,
- }
-
- /* PM1 Event Block
- * First word is PM1_Status, Second word is PM1_Enable
- */
- OperationRegion(P1EB, SystemIO, APEB, 0x04)
- Field(P1EB, ByteAcc, NoLock, Preserve) {
- TMST, 1,
- , 3,
- BMST, 1,
- GBST, 1,
- Offset(0x01),
- PBST, 1,
- , 1,
- RTST, 1,
- , 3,
- PWST, 1,
- SPWS, 1,
- Offset(0x02),
- TMEN, 1,
- , 4,
- GBEN, 1,
- Offset(0x03),
- PBEN, 1,
- , 1,
- RTEN, 1,
- , 3,
- PWDA, 1,
- }
-
- Scope(\_SB) {
-
- /* PCIe Configuration Space for 16 busses */
- OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
- Field(PCFG, ByteAcc, NoLock, Preserve) {
- /* Byte offsets are computed using the following technique:
- * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
- * The 8 comes from 8 functions per device, and 4096 bytes per function config space
- */
- Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */
- STB5, 32,
- Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
- PT0D, 1,
- PT1D, 1,
- PT2D, 1,
- PT3D, 1,
- PT4D, 1,
- PT5D, 1,
- PT6D, 1,
- PT7D, 1,
- PT8D, 1,
- PT9D, 1,
- Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
- SBIE, 1,
- SBME, 1,
- Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
- SBRI, 8,
- Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
- SBB1, 32,
- Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
- ,14,
- P92E, 1, /* Port92 decode enable */
- }
-
- OperationRegion(SB5, SystemMemory, STB5, 0x1000)
- Field(SB5, AnyAcc, NoLock, Preserve)
- {
- /* Port 0 */
- Offset(0x120), /* Port 0 Task file status */
- P0ER, 1,
- , 2,
- P0DQ, 1,
- , 3,
- P0BY, 1,
- Offset(0x128), /* Port 0 Serial ATA status */
- P0DD, 4,
- , 4,
- P0IS, 4,
- Offset(0x12C), /* Port 0 Serial ATA control */
- P0DI, 4,
- Offset(0x130), /* Port 0 Serial ATA error */
- , 16,
- P0PR, 1,
-
- /* Port 1 */
- offset(0x1A0), /* Port 1 Task file status */
- P1ER, 1,
- , 2,
- P1DQ, 1,
- , 3,
- P1BY, 1,
- Offset(0x1A8), /* Port 1 Serial ATA status */
- P1DD, 4,
- , 4,
- P1IS, 4,
- Offset(0x1AC), /* Port 1 Serial ATA control */
- P1DI, 4,
- Offset(0x1B0), /* Port 1 Serial ATA error */
- , 16,
- P1PR, 1,
-
- /* Port 2 */
- Offset(0x220), /* Port 2 Task file status */
- P2ER, 1,
- , 2,
- P2DQ, 1,
- , 3,
- P2BY, 1,
- Offset(0x228), /* Port 2 Serial ATA status */
- P2DD, 4,
- , 4,
- P2IS, 4,
- Offset(0x22C), /* Port 2 Serial ATA control */
- P2DI, 4,
- Offset(0x230), /* Port 2 Serial ATA error */
- , 16,
- P2PR, 1,
-
- /* Port 3 */
- Offset(0x2A0), /* Port 3 Task file status */
- P3ER, 1,
- , 2,
- P3DQ, 1,
- , 3,
- P3BY, 1,
- Offset(0x2A8), /* Port 3 Serial ATA status */
- P3DD, 4,
- , 4,
- P3IS, 4,
- Offset(0x2AC), /* Port 3 Serial ATA control */
- P3DI, 4,
- Offset(0x2B0), /* Port 3 Serial ATA error */
- , 16,
- P3PR, 1,
- }
- }
-
- Include ("routing.asl")
-
- Scope(\_SB) {
-
- Method(CkOT, 0){
-
- if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */
-
- if(CondRefOf(\_OSI,Local1))
- {
- Store(1, OSTP) /* Assume some form of XP */
- if (\_OSI("Windows 2006")) /* Vista */
- {
- Store(2, OSTP)
- }
- } else {
- If(WCMP(\_OS,"Linux")) {
- Store(3, OSTP) /* Linux */
- } Else {
- Store(4, OSTP) /* Gotta be WinCE */
- }
- }
- Return(OSTP)
- }
-
- Method(_PIC, 0x01, NotSerialized)
- {
- If (Arg0)
- {
- \_SB.CIRQ()
- }
- Store(Arg0, PMOD)
- }
-
- Method(CIRQ, 0x00, NotSerialized)
- {
- Store(0, PINA)
- Store(0, PINB)
- Store(0, PINC)
- Store(0, PIND)
- Store(0, PINE)
- Store(0, PINF)
- Store(0, PING)
- Store(0, PINH)
- }
-
- Name(IRQB, ResourceTemplate(){
- IRQ(Level,ActiveLow,Shared){15}
- })
-
- Name(IRQP, ResourceTemplate(){
- IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
- })
-
- Name(PITF, ResourceTemplate(){
- IRQ(Level,ActiveLow,Exclusive){9}
- })
-
- Device(INTA) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 1)
-
- Method(_STA, 0) {
- if (PINA) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTA._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKA\\_DIS\n") */
- Store(0, PINA)
- } /* End Method(_SB.INTA._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKA\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTA._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKA\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINA, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTA._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKA\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINA)
- } /* End Method(_SB.INTA._SRS) */
- } /* End Device(INTA) */
-
- Device(INTB) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 2)
-
- Method(_STA, 0) {
- if (PINB) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTB._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKB\\_DIS\n") */
- Store(0, PINB)
- } /* End Method(_SB.INTB._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKB\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTB._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKB\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINB, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTB._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKB\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINB)
- } /* End Method(_SB.INTB._SRS) */
- } /* End Device(INTB) */
-
- Device(INTC) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 3)
-
- Method(_STA, 0) {
- if (PINC) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTC._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKC\\_DIS\n") */
- Store(0, PINC)
- } /* End Method(_SB.INTC._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKC\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTC._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKC\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINC, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTC._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKC\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINC)
- } /* End Method(_SB.INTC._SRS) */
- } /* End Device(INTC) */
-
- Device(INTD) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 4)
-
- Method(_STA, 0) {
- if (PIND) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTD._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKD\\_DIS\n") */
- Store(0, PIND)
- } /* End Method(_SB.INTD._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKD\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTD._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKD\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PIND, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTD._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKD\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PIND)
- } /* End Method(_SB.INTD._SRS) */
- } /* End Device(INTD) */
-
- Device(INTE) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 5)
-
- Method(_STA, 0) {
- if (PINE) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTE._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKE\\_DIS\n") */
- Store(0, PINE)
- } /* End Method(_SB.INTE._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKE\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTE._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKE\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINE, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTE._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKE\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINE)
- } /* End Method(_SB.INTE._SRS) */
- } /* End Device(INTE) */
-
- Device(INTF) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 6)
-
- Method(_STA, 0) {
- if (PINF) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTF._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKF\\_DIS\n") */
- Store(0, PINF)
- } /* End Method(_SB.INTF._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKF\\_PRS\n") */
- Return(PITF)
- } /* Method(_SB.INTF._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKF\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINF, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTF._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKF\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINF)
- } /* End Method(_SB.INTF._SRS) */
- } /* End Device(INTF) */
-
- Device(INTG) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 7)
-
- Method(_STA, 0) {
- if (PING) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTG._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKG\\_DIS\n") */
- Store(0, PING)
- } /* End Method(_SB.INTG._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKG\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTG._CRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKG\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PING, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTG._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKG\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PING)
- } /* End Method(_SB.INTG._SRS) */
- } /* End Device(INTG) */
-
- Device(INTH) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 8)
-
- Method(_STA, 0) {
- if (PINH) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTH._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKH\\_DIS\n") */
- Store(0, PINH)
- } /* End Method(_SB.INTH._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKH\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTH._CRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKH\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINH, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTH._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKH\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINH)
- } /* End Method(_SB.INTH._SRS) */
- } /* End Device(INTH) */
-
- } /* End Scope(_SB) */
-
-
- /* Supported sleep states: */
- Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
-
- If (LAnd(SSFG, 0x01)) {
- Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
- }
- If (LAnd(SSFG, 0x02)) {
- Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
- }
- If (LAnd(SSFG, 0x04)) {
- Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
- }
- If (LAnd(SSFG, 0x08)) {
- Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
- }
-
- Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
-
- Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
- Name(CSMS, 0) /* Current System State */
-
- /* Wake status package */
- Name(WKST,Package(){Zero, Zero})
-
- /*
- * \_PTS - Prepare to Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2, etc
- *
- * Exit:
- * -none-
- *
- * The _PTS control method is executed at the beginning of the sleep process
- * for S1-S5. The sleeping value is passed to the _PTS control method. This
- * control method may be executed a relatively long time before entering the
- * sleep state and the OS may abort the operation without notification to
- * the ACPI driver. This method cannot modify the configuration or power
- * state of any device in the system.
- */
- Method(\_PTS, 1) {
- /* DBGO("\\_PTS\n") */
- /* DBGO("From S0 to S") */
- /* DBGO(Arg0) */
- /* DBGO("\n") */
-
- /* Don't allow PCIRST# to reset USB */
- if (LEqual(Arg0,3)){
- Store(0,URRE)
- }
-
- /* Clear sleep SMI status flag and enable sleep SMI trap. */
- /*Store(One, CSSM)
- Store(One, SSEN)*/
-
- /* On older chips, clear PciExpWakeDisEn */
- /*if (LLessEqual(\_SB.SBRI, 0x13)) {
- * Store(0,\_SB.PWDE)
- *}
- */
-
- /* Clear wake status structure. */
- Store(0, Index(WKST,0))
- Store(0, Index(WKST,1))
- } /* End Method(\_PTS) */
-
- /*
- * The following method results in a "not a valid reserved NameSeg"
- * warning so I have commented it out for the duration. It isn't
- * used, so it could be removed.
- *
- *
- * \_GTS OEM Going To Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * -none-
- *
- * Method(\_GTS, 1) {
- * DBGO("\\_GTS\n")
- * DBGO("From S0 to S")
- * DBGO(Arg0)
- * DBGO("\n")
- * }
- */
-
- /*
- * \_BFS OEM Back From Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * -none-
- */
- Method(\_BFS, 1) {
- /* DBGO("\\_BFS\n") */
- /* DBGO("From S") */
- /* DBGO(Arg0) */
- /* DBGO(" to S0\n") */
- }
-
- /*
- * \_WAK System Wake method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * Return package of 2 DWords
- * Dword 1 - Status
- * 0x00000000 wake succeeded
- * 0x00000001 Wake was signaled but failed due to lack of power
- * 0x00000002 Wake was signaled but failed due to thermal condition
- * Dword 2 - Power Supply state
- * if non-zero the effective S-state the power supply entered
- */
- Method(\_WAK, 1) {
- /* DBGO("\\_WAK\n") */
- /* DBGO("From S") */
- /* DBGO(Arg0) */
- /* DBGO(" to S0\n") */
-
- /* Re-enable HPET */
- Store(1,HPDE)
-
- /* Restore PCIRST# so it resets USB */
- if (LEqual(Arg0,3)){
- Store(1,URRE)
- }
-
- /* Arbitrarily clear PciExpWakeStatus */
- Store(PWST, PWST)
-
- /* if(DeRefOf(Index(WKST,0))) {
- * Store(0, Index(WKST,1))
- * } else {
- * Store(Arg0, Index(WKST,1))
- * }
- */
-
- Return(WKST)
- } /* End Method(\_WAK) */
-
- Scope(\_GPE) { /* Start Scope GPE */
- /* General event 0 */
- /* Method(_L00) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 1 */
- /* Method(_L01) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 2 */
- /* Method(_L02) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 3 */
- Method(_L03) {
- /* DBGO("\\_GPE\\_L00\n") */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* General event 4 */
- /* Method(_L04) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 5 */
- /* Method(_L05) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 6 - Used for GPM6, moved to USB.asl */
- /* Method(_L06) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 7 - Used for GPM7, moved to USB.asl */
- /* Method(_L07) {
- * DBGO("\\_GPE\\_L07\n")
- * }
- */
-
- /* Legacy PM event */
- Method(_L08) {
- /* DBGO("\\_GPE\\_L08\n") */
- }
-
- /* Temp warning (TWarn) event */
- Method(_L09) {
- /* DBGO("\\_GPE\\_L09\n") */
- Notify (\_TZ.TZ00, 0x80)
- }
-
- /* Reserved */
- /* Method(_L0A) {
- * DBGO("\\_GPE\\_L0A\n")
- * }
- */
-
- /* USB controller PME# */
- Method(_L0B) {
- /* DBGO("\\_GPE\\_L0B\n") */
- Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* AC97 controller PME# */
- /* Method(_L0C) {
- * DBGO("\\_GPE\\_L0C\n")
- * }
- */
-
- /* OtherTherm PME# */
- /* Method(_L0D) {
- * DBGO("\\_GPE\\_L0D\n")
- * }
- */
-
- /* GPM9 SCI event - Moved to USB.asl */
- /* Method(_L0E) {
- * DBGO("\\_GPE\\_L0E\n")
- * }
- */
-
- /* PCIe HotPlug event */
- /* Method(_L0F) {
- * DBGO("\\_GPE\\_L0F\n")
- * }
- */
-
- /* ExtEvent0 SCI event */
- Method(_L10) {
- /* DBGO("\\_GPE\\_L10\n") */
- }
-
-
- /* ExtEvent1 SCI event */
- Method(_L11) {
- /* DBGO("\\_GPE\\_L11\n") */
- }
-
- /* PCIe PME# event */
- /* Method(_L12) {
- * DBGO("\\_GPE\\_L12\n")
- * }
- */
-
- /* GPM0 SCI event - Moved to USB.asl */
- /* Method(_L13) {
- * DBGO("\\_GPE\\_L13\n")
- * }
- */
-
- /* GPM1 SCI event - Moved to USB.asl */
- /* Method(_L14) {
- * DBGO("\\_GPE\\_L14\n")
- * }
- */
-
- /* GPM2 SCI event - Moved to USB.asl */
- /* Method(_L15) {
- * DBGO("\\_GPE\\_L15\n")
- * }
- */
-
- /* GPM3 SCI event - Moved to USB.asl */
- /* Method(_L16) {
- * DBGO("\\_GPE\\_L16\n")
- * }
- */
-
- /* GPM8 SCI event - Moved to USB.asl */
- /* Method(_L17) {
- * DBGO("\\_GPE\\_L17\n")
- * }
- */
-
- /* GPIO0 or GEvent8 event */
- Method(_L18) {
- /* DBGO("\\_GPE\\_L18\n") */
- Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* GPM4 SCI event - Moved to USB.asl */
- /* Method(_L19) {
- * DBGO("\\_GPE\\_L19\n")
- * }
- */
-
- /* GPM5 SCI event */
- Method(_L1A) {
- /* DBGO("\\_GPE\\_L1A\n") */
- Notify (\_SB.SLPB, 0x80)
- }
-
- /* Azalia SCI event */
- Method(_L1B) {
- /* DBGO("\\_GPE\\_L1B\n") */
- Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* GPM6 SCI event - Reassigned to _L06 */
- /* Method(_L1C) {
- * DBGO("\\_GPE\\_L1C\n")
- * }
- */
-
- /* GPM7 SCI event - Reassigned to _L07 */
- /* Method(_L1D) {
- * DBGO("\\_GPE\\_L1D\n")
- * }
- */
-
- /* GPIO2 or GPIO66 SCI event */
- /* Method(_L1E) {
- * DBGO("\\_GPE\\_L1E\n")
- * }
- */
-
- /* SATA SCI event - Moved to sata.asl */
- /* Method(_L1F) {
- * DBGO("\\_GPE\\_L1F\n")
- * }
- */
-
- } /* End Scope GPE */
-
- Include ("usb.asl")
-
- /* South Bridge */
- Scope(\_SB) { /* Start \_SB scope */
- Include ("globutil.asl") /* global utility methods expected within the \_SB scope */
-
- /* _SB.PCI0 */
- /* Note: Only need HID on Primary Bus */
- Device(PCI0) {
- External (TOM1)
- External (TOM2)
- Name(_HID, EISAID("PNP0A03"))
- Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
- Method(_BBN, 0) { /* Bus number = 0 */
- Return(0)
- }
- Method(_STA, 0) {
- /* DBGO("\\_SB\\PCI0\\_STA\n") */
- Return(0x0B) /* Status is visible */
- }
-
- Method(_PRT,0) {
- If(PMOD){ Return(APR0) } /* APIC mode */
- Return (PR0) /* PIC Mode */
- } /* end _PRT */
-
- /* Describe the Northbridge devices */
- Device(AMRT) {
- Name(_ADR, 0x00000000)
- } /* end AMRT */
-
- /* The internal GFX bridge */
- Device(AGPB) {
- Name(_ADR, 0x00010000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- Return (APR1)
- }
- } /* end AGPB */
-
- /* The external GFX bridge */
- Device(PBR2) {
- Name(_ADR, 0x00020000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS2) } /* APIC mode */
- Return (PS2) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR2 */
-
- /* Dev3 is also an external GFX bridge, not used in Herring */
-
- Device(PBR4) {
- Name(_ADR, 0x00040000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS4) } /* APIC mode */
- Return (PS4) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR4 */
-
- Device(PBR5) {
- Name(_ADR, 0x00050000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS5) } /* APIC mode */
- Return (PS5) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR5 */
-
- Device(PBR6) {
- Name(_ADR, 0x00060000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS6) } /* APIC mode */
- Return (PS6) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR6 */
-
- /* The onboard EtherNet chip */
- Device(PBR7) {
- Name(_ADR, 0x00070000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS7) } /* APIC mode */
- Return (PS7) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR7 */
-
-
- /* PCI slot 1, 2, 3 */
- Device(PIBR) {
- Name(_ADR, 0x00140004)
- Name(_PRW, Package() {0x18, 4})
-
- Method(_PRT, 0) {
- Return (PCIB)
- }
- }
-
- /* Describe the Southbridge devices */
- Device(STCR) {
- Name(_ADR, 0x00120000)
- Include ("sata.asl")
- } /* end STCR */
-
- Device(UOH1) {
- Name(_ADR, 0x00130000)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH1 */
-
- Device(UOH2) {
- Name(_ADR, 0x00130001)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH2 */
-
- Device(UOH3) {
- Name(_ADR, 0x00130002)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH3 */
-
- Device(UOH4) {
- Name(_ADR, 0x00130003)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH4 */
-
- Device(UOH5) {
- Name(_ADR, 0x00130004)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH5 */
-
- Device(UEH1) {
- Name(_ADR, 0x00130005)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UEH1 */
-
- Device(SBUS) {
- Name(_ADR, 0x00140000)
- } /* end SBUS */
-
- /* Primary (and only) IDE channel */
- Device(IDEC) {
- Name(_ADR, 0x00140001)
- Include ("ide.asl")
- } /* end IDEC */
-
- Device(AZHD) {
- Name(_ADR, 0x00140002)
- OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
- Field(AZPD, AnyAcc, NoLock, Preserve) {
- offset (0x42),
- NSDI, 1,
- NSDO, 1,
- NSEN, 1,
- offset (0x44),
- IPCR, 4,
- offset (0x54),
- PWST, 2,
- , 6,
- PMEB, 1,
- , 6,
- PMST, 1,
- offset (0x62),
- MMCR, 1,
- offset (0x64),
- MMLA, 32,
- offset (0x68),
- MMHA, 32,
- offset (0x6C),
- MMDT, 16,
- }
-
- Method(_INI) {
- If(LEqual(OSTP,3)){ /* If we are running Linux */
- Store(zero, NSEN)
- Store(one, NSDO)
- Store(one, NSDI)
- }
- }
- } /* end AZHD */
-
- Device(LIBR) {
- Name(_ADR, 0x00140003)
- /* Method(_INI) {
- * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
- } */ /* End Method(_SB.SBRDG._INI) */
-
- /* Real Time Clock Device */
- Device(RTC0) {
- Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){8}
- IO(Decode16,0x0070, 0x0070, 0, 2)
- /* IO(Decode16,0x0070, 0x0070, 0, 4) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
-
- Device(TMR) { /* Timer */
- Name(_HID,EISAID("PNP0100")) /* System Timer */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){0}
- IO(Decode16, 0x0040, 0x0040, 0, 4)
- /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
-
- Device(SPKR) { /* Speaker */
- Name(_HID,EISAID("PNP0800")) /* AT style speaker */
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x0061, 0x0061, 0, 1)
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
-
- Device(PIC) {
- Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){2}
- IO(Decode16,0x0020, 0x0020, 0, 2)
- IO(Decode16,0x00A0, 0x00A0, 0, 2)
- /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
- /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
-
- Device(MAD) { /* 8257 DMA */
- Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
- Name(_CRS, ResourceTemplate() {
- DMA(Compatibility,BusMaster,Transfer8){4}
- IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
- IO(Decode16, 0x0081, 0x0081, 0x10, 0x03)
- IO(Decode16, 0x0087, 0x0087, 0x10, 0x01)
- IO(Decode16, 0x0089, 0x0089, 0x10, 0x03)
- IO(Decode16, 0x008F, 0x008F, 0x10, 0x01)
- IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
- }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
- } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
-
- Device(COPR) {
- Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
- IRQNoFlags(){13}
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
-
- Device(HPTM) {
- Name(_HID,EISAID("PNP0103"))
- Name(CRS,ResourceTemplate() {
- Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
- })
- Method(_STA, 0) {
- Return(0x0F) /* sata is visible */
- }
- Method(_CRS, 0) {
- CreateDwordField(CRS, ^HPT._BAS, HPBA)
- Store(HPBA, HPBA)
- Return(CRS)
- }
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
- } /* end LIBR */
-
- Device(HPBR) {
- Name(_ADR, 0x00140004)
- } /* end HostPciBr */
-
- Device(ACAD) {
- Name(_ADR, 0x00140005)
- } /* end Ac97audio */
-
- Device(ACMD) {
- Name(_ADR, 0x00140006)
- } /* end Ac97modem */
-
- Name(CRES, ResourceTemplate() {
- IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0000, /* range minimum */
- 0x0CF7, /* range maximum */
- 0x0000, /* translation */
- 0x0CF8 /* length */
- )
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0D00, /* range minimum */
- 0xFFFF, /* range maximum */
- 0x0000, /* translation */
- 0xF300 /* length */
- )
-
- Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
- Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
- Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
-
- /* DRAM Memory from 1MB to TopMem */
- Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
-
- /* BIOS space just below 4GB */
- DWORDMemory(
- ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000000, /* Max-Min, RLEN */
- ,,
- PCBM
- )
-
- /* DRAM memory from 4GB to TopMem2 */
- QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0xFFFFFFFF, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000000, /* Max-Min, RLEN */
- ,,
- DMHI
- )
-
- /* BIOS space just below 16EB */
- QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0xFFFFFFFF, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000000, /* Max-Min, RLEN */
- ,,
- PEBM
- )
-
- }) /* End Name(_SB.PCI0.CRES) */
-
- Method(_CRS, 0) {
- /* DBGO("\\_SB\\PCI0\\_CRS\n") */
-
- CreateDWordField(CRES, ^EMM1._BAS, EM1B)
- CreateDWordField(CRES, ^EMM1._LEN, EM1L)
- CreateDWordField(CRES, ^DMLO._BAS, DMLB)
- CreateDWordField(CRES, ^DMLO._LEN, DMLL)
- CreateDWordField(CRES, ^PCBM._MIN, PBMB)
- CreateDWordField(CRES, ^PCBM._LEN, PBML)
-
- CreateQWordField(CRES, ^DMHI._MIN, DMHB)
- CreateQWordField(CRES, ^DMHI._LEN, DMHL)
- CreateQWordField(CRES, ^PEBM._MIN, EBMB)
- CreateQWordField(CRES, ^PEBM._LEN, EBML)
-
- If(LGreater(LOMH, 0xC0000)){
- Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
- Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
- }
-
- /* Set size of memory from 1MB to TopMem */
- Subtract(TOM1, 0x100000, DMLL)
-
- /*
- * If(LNotEqual(TOM2, 0x00000000)){
- * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
- * Subtract(TOM2, 0x100000000, DMHL)
- * }
- */
-
- /* If there is no memory above 4GB, put the BIOS just below 4GB */
- If(LEqual(TOM2, 0x00000000)){
- Store(PBAD,PBMB) /* Reserve the "BIOS" space */
- Store(PBLN,PBML)
- }
- Else { /* Otherwise, put the BIOS just below 16EB */
- ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
- Store(PBLN,EBML)
- }
-
- Return(CRES) /* note to change the Name buffer */
- } /* end of Method(_SB.PCI0._CRS) */
-
- /*
- *
- * FIRST METHOD CALLED UPON BOOT
- *
- * 1. If debugging, print current OS and ACPI interpreter.
- * 2. Get PCI Interrupt routing from ACPI VSM, this
- * value is based on user choice in BIOS setup.
- */
- Method(_INI, 0) {
- /* DBGO("\\_SB\\_INI\n") */
- /* DBGO(" DSDT.ASL code from ") */
- /* DBGO(__DATE__) */
- /* DBGO(" ") */
- /* DBGO(__TIME__) */
- /* DBGO("\n Sleep states supported: ") */
- /* DBGO("\n") */
- /* DBGO(" \\_OS=") */
- /* DBGO(\_OS) */
- /* DBGO("\n \\_REV=") */
- /* DBGO(\_REV) */
- /* DBGO("\n") */
-
- /* Determine the OS we're running on */
- CkOT()
-
- /* On older chips, clear PciExpWakeDisEn */
- /*if (LLessEqual(\SBRI, 0x13)) {
- * Store(0,\PWDE)
- * }
- */
- } /* End Method(_SB._INI) */
- } /* End Device(PCI0) */
-
- Device(PWRB) { /* Start Power button device */
- Name(_HID, EISAID("PNP0C0C"))
- Name(_UID, 0xAA)
- Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
- Name(_STA, 0x0B) /* sata is invisible */
- }
-
- Device (SLPB) {
- Name (_HID, EisaId ("PNP0C0E"))
- Name (_PRW, Package (0x02) {0x0F, 0x04})
- Name (_STA, 0x0B)
- }
- } /* End \_SB scope */
-
- Scope(\_SI) {
- Method(_SST, 1) {
- /* DBGO("\\_SI\\_SST\n") */
- /* DBGO(" New Indicator state: ") */
- /* DBGO(Arg0) */
- /* DBGO("\n") */
- }
- } /* End Scope SI */
-
- OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
- Field (SMB0, ByteAcc, NoLock, Preserve) {
- HSTS, 8, /* SMBUS status */
- SSTS, 8, /* SMBUS slave status */
- HCNT, 8, /* SMBUS control */
- HCMD, 8, /* SMBUS host cmd */
- HADD, 8, /* SMBUS address */
- DAT0, 8, /* SMBUS data0 */
- DAT1, 8, /* SMBUS data1 */
- BLKD, 8, /* SMBUS block data */
- SCNT, 8, /* SMBUS slave control */
- SCMD, 8, /* SMBUS shaow cmd */
- SEVT, 8, /* SMBUS slave event */
- SDAT, 8 /* SMBUS slave data */
- }
-
- Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
- Store (0x1E, HSTS)
- Store (0xFA, Local0)
- While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
- Stall (0x64)
- Decrement (Local0)
- }
-
- Return (Local0)
- }
-
- Method (SWTC, 1, NotSerialized) {
- Store (Arg0, Local0)
- Store (0x07, Local2)
- Store (One, Local1)
- While (LEqual (Local1, One)) {
- Store (And (HSTS, 0x1E), Local3)
- If (LNotEqual (Local3, Zero)) { /* read sucess */
- If (LEqual (Local3, 0x02)) {
- Store (Zero, Local2)
- }
-
- Store (Zero, Local1)
- }
- Else {
- If (LLess (Local0, 0x0A)) { /* read failure */
- Store (0x18, Local2)
- Store (Zero, Local1)
- }
- Else {
- Sleep (0x0A) /* 10 ms, try again */
- Subtract (Local0, 0x0A, Local0)
- }
- }
- }
-
- Return (Local2)
- }
-
- Method (SMBR, 3, NotSerialized) {
- Store (0x07, Local0)
-
- Store (WCLR (), Local0) /* clear SMBUS status register before read data */
-
- Store (0x1F, HSTS)
- Store (Or (ShiftLeft (Arg1, One), One), HADD)
- Store (Arg2, HCMD)
- If (LEqual (Arg0, 0x07)) {
- Store (0x48, HCNT) /* read byte */
- }
-
- Store (SWTC (0x03E8), Local1) /* 1000 ms */
- If (LEqual (Local1, Zero)) {
- If (LEqual (Arg0, 0x07)) {
- Store (DAT0, Local0)
- }
- }
- Else {
- Store (Local1, Local0)
- }
-
- Return (Local0)
- }
-
- /* THERMAL */
- Scope(\_TZ) {
- Name (KELV, 2732)
- Name (THOT, 900)
- Name (TCRT, 950)
-
- ThermalZone(TZ00) {
- Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
- /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
- Return(Add(0, 2730))
- }
- Method(_AL0,0) { /* Returns package of cooling device to turn on */
- /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
- Return(Package() {\_TZ.TZ00.FAN0})
- }
- Device (FAN0) {
- Name(_HID, EISAID("PNP0C0B"))
- Name(_PR0, Package() {PFN0})
- }
-
- PowerResource(PFN0,0,0) {
- Method(_STA) {
- Store(0xF,Local0)
- Return(Local0)
- }
- Method(_ON) {
- /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
- }
- Method(_OFF) {
- /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
- }
- }
-
- Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
- /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
- Return (Add (THOT, KELV))
- }
- Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
- /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
- Return (Add (TCRT, KELV))
- }
- Method(_TMP,0) { /* return current temp of this zone */
- Store (SMBR (0x07, 0x2E,, 0x25), Local0)
- If (LGreater (Local0, 0x20)) {
- Store (Local0, Local1)
- }
- Else {
- Add (Local0, 0x40, Local0)
- Add (Local0, TCRT, Local0)
- Return (Add (550, KELV))
- }
-
- /* Store (SMBR (0x07, 0x2E, 0x26), Local0)
- * If (LGreater (Local0, 0x20)) {
- * If (LGreater (Local0, Local1)) {
- * Store (Local0, Local1)
- * }
- * }
- * Else {
- * Add (Local0, 0x40, Local0)
- * Add (Local0, TCRT, Local0)
- * Return (Add (Local0, KELV))
- * }
- */
-
- Store (SMBR (0x07, 0x2E, 0x27), Local0)
- If (LGreater (Local0, 0x20)) {
- If (LGreater (Local0, Local1)) {
- Store (Local0, Local1)
- }
-
- Subtract (Local1, 0x40, Local1)
- Multiply (Local1, 10, Local1)
- Return (Add (Local1, KELV))
- }
- Else {
- Add (Local0, 0x40, Local0)
- Add (Local0, TCRT, Local0)
- Return (Add (550 , KELV))
- }
- } /* end of _TMP */
- } /* end of TZ00 */
- }
-}
-/* End of ASL file */
/*
Scope(\_SB) {
- Include ("globutil.asl")
+ #include "globutil.asl"
}
*/
Device(PCI0) {
Device(IDEC) {
Name(_ADR, 0x00140001)
- Include ("ide.asl")
+ #include "ide.asl"
}
}
}
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
)
{
- Include ("routing.asl")
+ #include "routing.asl"
}
*/
Device(PCI0) {
Device(SATA) {
Name(_ADR, 0x00120000)
- Include ("sata.asl")
+ #include "sata.asl"
}
}
}
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
)
{
- Include ("usb.asl")
+ #include "usb.asl"
}
*/
Method(UCOC, 0) {
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+ "DSDT.AML", /* Output filename */
+ "DSDT", /* Signature */
+ 0x02, /* DSDT Revision, needs to be 2 for 64bit */
+ "AMD ", /* OEMID */
+ "PISTACHI", /* TABLE ID */
+ 0x00010001 /* OEM Revision */
+ )
+{ /* Start of ASL file */
+ /* #include "acpi/debug.asl" */ /* Include global debug methods if needed */
+
+ /* Data to be patched by the BIOS during POST */
+ /* FIXME the patching is not done yet! */
+ /* Memory related values */
+ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
+ Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+ Name(PBLN, 0x0) /* Length of BIOS area */
+
+ Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
+ Name(HPBA, 0xFED00000) /* Base address of HPET table */
+
+ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+ /* USB overcurrent mapping pins. */
+ Name(UOM0, 0)
+ Name(UOM1, 2)
+ Name(UOM2, 0)
+ Name(UOM3, 7)
+ Name(UOM4, 2)
+ Name(UOM5, 2)
+ Name(UOM6, 6)
+ Name(UOM7, 2)
+ Name(UOM8, 6)
+ Name(UOM9, 6)
+
+ /* Some global data */
+ Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+ Name(OSV, Ones) /* Assume nothing */
+ Name(PMOD, One) /* Assume APIC */
+
+ /* PIC IRQ mapping registers, C00h-C01h */
+ OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
+ Field(PRQM, ByteAcc, NoLock, Preserve) {
+ PRQI, 0x00000008,
+ PRQD, 0x00000008, /* Offset: 1h */
+ }
+ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
+ PINA, 0x00000008, /* Index 0 */
+ PINB, 0x00000008, /* Index 1 */
+ PINC, 0x00000008, /* Index 2 */
+ PIND, 0x00000008, /* Index 3 */
+ AINT, 0x00000008, /* Index 4 */
+ SINT, 0x00000008, /* Index 5 */
+ , 0x00000008, /* Index 6 */
+ AAUD, 0x00000008, /* Index 7 */
+ AMOD, 0x00000008, /* Index 8 */
+ PINE, 0x00000008, /* Index 9 */
+ PINF, 0x00000008, /* Index A */
+ PING, 0x00000008, /* Index B */
+ PINH, 0x00000008, /* Index C */
+ }
+
+ /* PCI Error control register */
+ OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
+ Field(PERC, ByteAcc, NoLock, Preserve) {
+ SENS, 0x00000001,
+ PENS, 0x00000001,
+ SENE, 0x00000001,
+ PENE, 0x00000001,
+ }
+
+ /* Client Management index/data registers */
+ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
+ Field(CMT, ByteAcc, NoLock, Preserve) {
+ CMTI, 8,
+ /* Client Management Data register */
+ G64E, 1,
+ G64O, 1,
+ G32O, 2,
+ , 2,
+ GPSL, 2,
+ }
+
+ /* GPM Port register */
+ OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
+ Field(GPT, ByteAcc, NoLock, Preserve) {
+ GPB0,1,
+ GPB1,1,
+ GPB2,1,
+ GPB3,1,
+ GPB4,1,
+ GPB5,1,
+ GPB6,1,
+ GPB7,1,
+ }
+
+ /* Flash ROM program enable register */
+ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
+ Field(FRE, ByteAcc, NoLock, Preserve) {
+ , 0x00000006,
+ FLRE, 0x00000001,
+ }
+
+ /* PM2 index/data registers */
+ OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
+ Field(PM2R, ByteAcc, NoLock, Preserve) {
+ PM2I, 0x00000008,
+ PM2D, 0x00000008,
+ }
+
+ /* Power Management I/O registers */
+ OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
+ Field(PIOR, ByteAcc, NoLock, Preserve) {
+ PIOI, 0x00000008,
+ PIOD, 0x00000008,
+ }
+ IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
+ Offset(0x00), /* MiscControl */
+ , 1,
+ T1EE, 1,
+ T2EE, 1,
+ Offset(0x01), /* MiscStatus */
+ , 1,
+ T1E, 1,
+ T2E, 1,
+ Offset(0x04), /* SmiWakeUpEventEnable3 */
+ , 7,
+ SSEN, 1,
+ Offset(0x07), /* SmiWakeUpEventStatus3 */
+ , 7,
+ CSSM, 1,
+ Offset(0x10), /* AcpiEnable */
+ , 6,
+ PWDE, 1,
+ Offset(0x1C), /* ProgramIoEnable */
+ , 3,
+ MKME, 1,
+ IO3E, 1,
+ IO2E, 1,
+ IO1E, 1,
+ IO0E, 1,
+ Offset(0x1D), /* IOMonitorStatus */
+ , 3,
+ MKMS, 1,
+ IO3S, 1,
+ IO2S, 1,
+ IO1S, 1,
+ IO0S,1,
+ Offset(0x20), /* AcpiPmEvtBlk */
+ APEB, 16,
+ Offset(0x36), /* GEvtLevelConfig */
+ , 6,
+ ELC6, 1,
+ ELC7, 1,
+ Offset(0x37), /* GPMLevelConfig0 */
+ , 3,
+ PLC0, 1,
+ PLC1, 1,
+ PLC2, 1,
+ PLC3, 1,
+ PLC8, 1,
+ Offset(0x38), /* GPMLevelConfig1 */
+ , 1,
+ PLC4, 1,
+ PLC5, 1,
+ , 1,
+ PLC6, 1,
+ PLC7, 1,
+ Offset(0x3B), /* PMEStatus1 */
+ GP0S, 1,
+ GM4S, 1,
+ GM5S, 1,
+ APS, 1,
+ GM6S, 1,
+ GM7S, 1,
+ GP2S, 1,
+ STSS, 1,
+ Offset(0x55), /* SoftPciRst */
+ SPRE, 1,
+ , 1,
+ , 1,
+ PNAT, 1,
+ PWMK, 1,
+ PWNS, 1,
+
+ /* Offset(0x61), */ /* Options_1 */
+ /* ,7, */
+ /* R617,1, */
+
+ Offset(0x65), /* UsbPMControl */
+ , 4,
+ URRE, 1,
+ Offset(0x68), /* MiscEnable68 */
+ , 3,
+ TMTE, 1,
+ , 1,
+ Offset(0x92), /* GEVENTIN */
+ , 7,
+ E7IS, 1,
+ Offset(0x96), /* GPM98IN */
+ G8IS, 1,
+ G9IS, 1,
+ Offset(0x9A), /* EnhanceControl */
+ ,7,
+ HPDE, 1,
+ Offset(0xA8), /* PIO7654Enable */
+ IO4E, 1,
+ IO5E, 1,
+ IO6E, 1,
+ IO7E, 1,
+ Offset(0xA9), /* PIO7654Status */
+ IO4S, 1,
+ IO5S, 1,
+ IO6S, 1,
+ IO7S, 1,
+ }
+
+ /* PM1 Event Block
+ * First word is PM1_Status, Second word is PM1_Enable
+ */
+ OperationRegion(P1EB, SystemIO, APEB, 0x04)
+ Field(P1EB, ByteAcc, NoLock, Preserve) {
+ TMST, 1,
+ , 3,
+ BMST, 1,
+ GBST, 1,
+ Offset(0x01),
+ PBST, 1,
+ , 1,
+ RTST, 1,
+ , 3,
+ PWST, 1,
+ SPWS, 1,
+ Offset(0x02),
+ TMEN, 1,
+ , 4,
+ GBEN, 1,
+ Offset(0x03),
+ PBEN, 1,
+ , 1,
+ RTEN, 1,
+ , 3,
+ PWDA, 1,
+ }
+
+ Scope(\_SB) {
+
+ /* PCIe Configuration Space for 16 busses */
+ OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
+ Field(PCFG, ByteAcc, NoLock, Preserve) {
+ /* Byte offsets are computed using the following technique:
+ * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
+ * The 8 comes from 8 functions per device, and 4096 bytes per function config space
+ */
+ Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */
+ STB5, 32,
+ Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
+ PT0D, 1,
+ PT1D, 1,
+ PT2D, 1,
+ PT3D, 1,
+ PT4D, 1,
+ PT5D, 1,
+ PT6D, 1,
+ PT7D, 1,
+ PT8D, 1,
+ PT9D, 1,
+ Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
+ SBIE, 1,
+ SBME, 1,
+ Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
+ SBRI, 8,
+ Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
+ SBB1, 32,
+ Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
+ ,14,
+ P92E, 1, /* Port92 decode enable */
+ }
+
+ OperationRegion(SB5, SystemMemory, STB5, 0x1000)
+ Field(SB5, AnyAcc, NoLock, Preserve)
+ {
+ /* Port 0 */
+ Offset(0x120), /* Port 0 Task file status */
+ P0ER, 1,
+ , 2,
+ P0DQ, 1,
+ , 3,
+ P0BY, 1,
+ Offset(0x128), /* Port 0 Serial ATA status */
+ P0DD, 4,
+ , 4,
+ P0IS, 4,
+ Offset(0x12C), /* Port 0 Serial ATA control */
+ P0DI, 4,
+ Offset(0x130), /* Port 0 Serial ATA error */
+ , 16,
+ P0PR, 1,
+
+ /* Port 1 */
+ offset(0x1A0), /* Port 1 Task file status */
+ P1ER, 1,
+ , 2,
+ P1DQ, 1,
+ , 3,
+ P1BY, 1,
+ Offset(0x1A8), /* Port 1 Serial ATA status */
+ P1DD, 4,
+ , 4,
+ P1IS, 4,
+ Offset(0x1AC), /* Port 1 Serial ATA control */
+ P1DI, 4,
+ Offset(0x1B0), /* Port 1 Serial ATA error */
+ , 16,
+ P1PR, 1,
+
+ /* Port 2 */
+ Offset(0x220), /* Port 2 Task file status */
+ P2ER, 1,
+ , 2,
+ P2DQ, 1,
+ , 3,
+ P2BY, 1,
+ Offset(0x228), /* Port 2 Serial ATA status */
+ P2DD, 4,
+ , 4,
+ P2IS, 4,
+ Offset(0x22C), /* Port 2 Serial ATA control */
+ P2DI, 4,
+ Offset(0x230), /* Port 2 Serial ATA error */
+ , 16,
+ P2PR, 1,
+
+ /* Port 3 */
+ Offset(0x2A0), /* Port 3 Task file status */
+ P3ER, 1,
+ , 2,
+ P3DQ, 1,
+ , 3,
+ P3BY, 1,
+ Offset(0x2A8), /* Port 3 Serial ATA status */
+ P3DD, 4,
+ , 4,
+ P3IS, 4,
+ Offset(0x2AC), /* Port 3 Serial ATA control */
+ P3DI, 4,
+ Offset(0x2B0), /* Port 3 Serial ATA error */
+ , 16,
+ P3PR, 1,
+ }
+ }
+
+ #include "acpi/routing.asl"
+
+ Scope(\_SB) {
+
+ Method(CkOT, 0){
+
+ if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */
+
+ if(CondRefOf(\_OSI,Local1))
+ {
+ Store(1, OSTP) /* Assume some form of XP */
+ if (\_OSI("Windows 2006")) /* Vista */
+ {
+ Store(2, OSTP)
+ }
+ } else {
+ If(WCMP(\_OS,"Linux")) {
+ Store(3, OSTP) /* Linux */
+ } Else {
+ Store(4, OSTP) /* Gotta be WinCE */
+ }
+ }
+ Return(OSTP)
+ }
+
+ Method(_PIC, 0x01, NotSerialized)
+ {
+ If (Arg0)
+ {
+ \_SB.CIRQ()
+ }
+ Store(Arg0, PMOD)
+ }
+
+ Method(CIRQ, 0x00, NotSerialized)
+ {
+ Store(0, PINA)
+ Store(0, PINB)
+ Store(0, PINC)
+ Store(0, PIND)
+ Store(0, PINE)
+ Store(0, PINF)
+ Store(0, PING)
+ Store(0, PINH)
+ }
+
+ Name(IRQB, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Shared){15}
+ })
+
+ Name(IRQP, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
+ })
+
+ Name(PITF, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Exclusive){9}
+ })
+
+ Device(INTA) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 1)
+
+ Method(_STA, 0) {
+ if (PINA) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTA._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_DIS\n") */
+ Store(0, PINA)
+ } /* End Method(_SB.INTA._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTA._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINA, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTA._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKA\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINA)
+ } /* End Method(_SB.INTA._SRS) */
+ } /* End Device(INTA) */
+
+ Device(INTB) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 2)
+
+ Method(_STA, 0) {
+ if (PINB) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTB._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_DIS\n") */
+ Store(0, PINB)
+ } /* End Method(_SB.INTB._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTB._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINB, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTB._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKB\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINB)
+ } /* End Method(_SB.INTB._SRS) */
+ } /* End Device(INTB) */
+
+ Device(INTC) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 3)
+
+ Method(_STA, 0) {
+ if (PINC) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTC._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_DIS\n") */
+ Store(0, PINC)
+ } /* End Method(_SB.INTC._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTC._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINC, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTC._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKC\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINC)
+ } /* End Method(_SB.INTC._SRS) */
+ } /* End Device(INTC) */
+
+ Device(INTD) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 4)
+
+ Method(_STA, 0) {
+ if (PIND) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTD._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_DIS\n") */
+ Store(0, PIND)
+ } /* End Method(_SB.INTD._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTD._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIND, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTD._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKD\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIND)
+ } /* End Method(_SB.INTD._SRS) */
+ } /* End Device(INTD) */
+
+ Device(INTE) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 5)
+
+ Method(_STA, 0) {
+ if (PINE) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTE._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_DIS\n") */
+ Store(0, PINE)
+ } /* End Method(_SB.INTE._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTE._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINE, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTE._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKE\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINE)
+ } /* End Method(_SB.INTE._SRS) */
+ } /* End Device(INTE) */
+
+ Device(INTF) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 6)
+
+ Method(_STA, 0) {
+ if (PINF) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTF._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_DIS\n") */
+ Store(0, PINF)
+ } /* End Method(_SB.INTF._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_PRS\n") */
+ Return(PITF)
+ } /* Method(_SB.INTF._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINF, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTF._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKF\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINF)
+ } /* End Method(_SB.INTF._SRS) */
+ } /* End Device(INTF) */
+
+ Device(INTG) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 7)
+
+ Method(_STA, 0) {
+ if (PING) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTG._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKG\\_DIS\n") */
+ Store(0, PING)
+ } /* End Method(_SB.INTG._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKG\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTG._CRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKG\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PING, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTG._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKG\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PING)
+ } /* End Method(_SB.INTG._SRS) */
+ } /* End Device(INTG) */
+
+ Device(INTH) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 8)
+
+ Method(_STA, 0) {
+ if (PINH) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTH._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKH\\_DIS\n") */
+ Store(0, PINH)
+ } /* End Method(_SB.INTH._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKH\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTH._CRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKH\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINH, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTH._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKH\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINH)
+ } /* End Method(_SB.INTH._SRS) */
+ } /* End Device(INTH) */
+
+ } /* End Scope(_SB) */
+
+
+ /* Supported sleep states: */
+ Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
+
+ If (LAnd(SSFG, 0x01)) {
+ Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
+ }
+ If (LAnd(SSFG, 0x02)) {
+ Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
+ }
+ If (LAnd(SSFG, 0x04)) {
+ Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
+ }
+ If (LAnd(SSFG, 0x08)) {
+ Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
+ }
+
+ Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
+
+ Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
+ Name(CSMS, 0) /* Current System State */
+
+ /* Wake status package */
+ Name(WKST,Package(){Zero, Zero})
+
+ /*
+ * \_PTS - Prepare to Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2, etc
+ *
+ * Exit:
+ * -none-
+ *
+ * The _PTS control method is executed at the beginning of the sleep process
+ * for S1-S5. The sleeping value is passed to the _PTS control method. This
+ * control method may be executed a relatively long time before entering the
+ * sleep state and the OS may abort the operation without notification to
+ * the ACPI driver. This method cannot modify the configuration or power
+ * state of any device in the system.
+ */
+ Method(\_PTS, 1) {
+ /* DBGO("\\_PTS\n") */
+ /* DBGO("From S0 to S") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+
+ /* Don't allow PCIRST# to reset USB */
+ if (LEqual(Arg0,3)){
+ Store(0,URRE)
+ }
+
+ /* Clear sleep SMI status flag and enable sleep SMI trap. */
+ /*Store(One, CSSM)
+ Store(One, SSEN)*/
+
+ /* On older chips, clear PciExpWakeDisEn */
+ /*if (LLessEqual(\_SB.SBRI, 0x13)) {
+ * Store(0,\_SB.PWDE)
+ *}
+ */
+
+ /* Clear wake status structure. */
+ Store(0, Index(WKST,0))
+ Store(0, Index(WKST,1))
+ } /* End Method(\_PTS) */
+
+ /*
+ * The following method results in a "not a valid reserved NameSeg"
+ * warning so I have commented it out for the duration. It isn't
+ * used, so it could be removed.
+ *
+ *
+ * \_GTS OEM Going To Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * -none-
+ *
+ * Method(\_GTS, 1) {
+ * DBGO("\\_GTS\n")
+ * DBGO("From S0 to S")
+ * DBGO(Arg0)
+ * DBGO("\n")
+ * }
+ */
+
+ /*
+ * \_BFS OEM Back From Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * -none-
+ */
+ Method(\_BFS, 1) {
+ /* DBGO("\\_BFS\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+ }
+
+ /*
+ * \_WAK System Wake method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * Return package of 2 DWords
+ * Dword 1 - Status
+ * 0x00000000 wake succeeded
+ * 0x00000001 Wake was signaled but failed due to lack of power
+ * 0x00000002 Wake was signaled but failed due to thermal condition
+ * Dword 2 - Power Supply state
+ * if non-zero the effective S-state the power supply entered
+ */
+ Method(\_WAK, 1) {
+ /* DBGO("\\_WAK\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+
+ /* Re-enable HPET */
+ Store(1,HPDE)
+
+ /* Restore PCIRST# so it resets USB */
+ if (LEqual(Arg0,3)){
+ Store(1,URRE)
+ }
+
+ /* Arbitrarily clear PciExpWakeStatus */
+ Store(PWST, PWST)
+
+ /* if(DeRefOf(Index(WKST,0))) {
+ * Store(0, Index(WKST,1))
+ * } else {
+ * Store(Arg0, Index(WKST,1))
+ * }
+ */
+
+ Return(WKST)
+ } /* End Method(\_WAK) */
+
+ Scope(\_GPE) { /* Start Scope GPE */
+ /* General event 0 */
+ /* Method(_L00) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 1 */
+ /* Method(_L01) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 2 */
+ /* Method(_L02) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 3 */
+ Method(_L03) {
+ /* DBGO("\\_GPE\\_L00\n") */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* General event 4 */
+ /* Method(_L04) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 5 */
+ /* Method(_L05) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 6 - Used for GPM6, moved to USB.asl */
+ /* Method(_L06) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 7 - Used for GPM7, moved to USB.asl */
+ /* Method(_L07) {
+ * DBGO("\\_GPE\\_L07\n")
+ * }
+ */
+
+ /* Legacy PM event */
+ Method(_L08) {
+ /* DBGO("\\_GPE\\_L08\n") */
+ }
+
+ /* Temp warning (TWarn) event */
+ Method(_L09) {
+ /* DBGO("\\_GPE\\_L09\n") */
+ Notify (\_TZ.TZ00, 0x80)
+ }
+
+ /* Reserved */
+ /* Method(_L0A) {
+ * DBGO("\\_GPE\\_L0A\n")
+ * }
+ */
+
+ /* USB controller PME# */
+ Method(_L0B) {
+ /* DBGO("\\_GPE\\_L0B\n") */
+ Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* AC97 controller PME# */
+ /* Method(_L0C) {
+ * DBGO("\\_GPE\\_L0C\n")
+ * }
+ */
+
+ /* OtherTherm PME# */
+ /* Method(_L0D) {
+ * DBGO("\\_GPE\\_L0D\n")
+ * }
+ */
+
+ /* GPM9 SCI event - Moved to USB.asl */
+ /* Method(_L0E) {
+ * DBGO("\\_GPE\\_L0E\n")
+ * }
+ */
+
+ /* PCIe HotPlug event */
+ /* Method(_L0F) {
+ * DBGO("\\_GPE\\_L0F\n")
+ * }
+ */
+
+ /* ExtEvent0 SCI event */
+ Method(_L10) {
+ /* DBGO("\\_GPE\\_L10\n") */
+ }
+
+
+ /* ExtEvent1 SCI event */
+ Method(_L11) {
+ /* DBGO("\\_GPE\\_L11\n") */
+ }
+
+ /* PCIe PME# event */
+ /* Method(_L12) {
+ * DBGO("\\_GPE\\_L12\n")
+ * }
+ */
+
+ /* GPM0 SCI event - Moved to USB.asl */
+ /* Method(_L13) {
+ * DBGO("\\_GPE\\_L13\n")
+ * }
+ */
+
+ /* GPM1 SCI event - Moved to USB.asl */
+ /* Method(_L14) {
+ * DBGO("\\_GPE\\_L14\n")
+ * }
+ */
+
+ /* GPM2 SCI event - Moved to USB.asl */
+ /* Method(_L15) {
+ * DBGO("\\_GPE\\_L15\n")
+ * }
+ */
+
+ /* GPM3 SCI event - Moved to USB.asl */
+ /* Method(_L16) {
+ * DBGO("\\_GPE\\_L16\n")
+ * }
+ */
+
+ /* GPM8 SCI event - Moved to USB.asl */
+ /* Method(_L17) {
+ * DBGO("\\_GPE\\_L17\n")
+ * }
+ */
+
+ /* GPIO0 or GEvent8 event */
+ Method(_L18) {
+ /* DBGO("\\_GPE\\_L18\n") */
+ Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* GPM4 SCI event - Moved to USB.asl */
+ /* Method(_L19) {
+ * DBGO("\\_GPE\\_L19\n")
+ * }
+ */
+
+ /* GPM5 SCI event */
+ Method(_L1A) {
+ /* DBGO("\\_GPE\\_L1A\n") */
+ Notify (\_SB.SLPB, 0x80)
+ }
+
+ /* Azalia SCI event */
+ Method(_L1B) {
+ /* DBGO("\\_GPE\\_L1B\n") */
+ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* GPM6 SCI event - Reassigned to _L06 */
+ /* Method(_L1C) {
+ * DBGO("\\_GPE\\_L1C\n")
+ * }
+ */
+
+ /* GPM7 SCI event - Reassigned to _L07 */
+ /* Method(_L1D) {
+ * DBGO("\\_GPE\\_L1D\n")
+ * }
+ */
+
+ /* GPIO2 or GPIO66 SCI event */
+ /* Method(_L1E) {
+ * DBGO("\\_GPE\\_L1E\n")
+ * }
+ */
+
+ /* SATA SCI event - Moved to sata.asl */
+ /* Method(_L1F) {
+ * DBGO("\\_GPE\\_L1F\n")
+ * }
+ */
+
+ } /* End Scope GPE */
+
+ #include "acpi/usb.asl"
+
+ /* South Bridge */
+ Scope(\_SB) { /* Start \_SB scope */
+ #include "acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
+
+ /* _SB.PCI0 */
+ /* Note: Only need HID on Primary Bus */
+ Device(PCI0) {
+ External (TOM1)
+ External (TOM2)
+ Name(_HID, EISAID("PNP0A03"))
+ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
+ Method(_BBN, 0) { /* Bus number = 0 */
+ Return(0)
+ }
+ Method(_STA, 0) {
+ /* DBGO("\\_SB\\PCI0\\_STA\n") */
+ Return(0x0B) /* Status is visible */
+ }
+
+ Method(_PRT,0) {
+ If(PMOD){ Return(APR0) } /* APIC mode */
+ Return (PR0) /* PIC Mode */
+ } /* end _PRT */
+
+ /* Describe the Northbridge devices */
+ Device(AMRT) {
+ Name(_ADR, 0x00000000)
+ } /* end AMRT */
+
+ /* The internal GFX bridge */
+ Device(AGPB) {
+ Name(_ADR, 0x00010000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ Return (APR1)
+ }
+ } /* end AGPB */
+
+ /* The external GFX bridge */
+ Device(PBR2) {
+ Name(_ADR, 0x00020000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS2) } /* APIC mode */
+ Return (PS2) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR2 */
+
+ /* Dev3 is also an external GFX bridge, not used in Herring */
+
+ Device(PBR4) {
+ Name(_ADR, 0x00040000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS4) } /* APIC mode */
+ Return (PS4) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR4 */
+
+ Device(PBR5) {
+ Name(_ADR, 0x00050000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS5) } /* APIC mode */
+ Return (PS5) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR5 */
+
+ Device(PBR6) {
+ Name(_ADR, 0x00060000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS6) } /* APIC mode */
+ Return (PS6) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR6 */
+
+ /* The onboard EtherNet chip */
+ Device(PBR7) {
+ Name(_ADR, 0x00070000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS7) } /* APIC mode */
+ Return (PS7) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR7 */
+
+
+ /* PCI slot 1, 2, 3 */
+ Device(PIBR) {
+ Name(_ADR, 0x00140004)
+ Name(_PRW, Package() {0x18, 4})
+
+ Method(_PRT, 0) {
+ Return (PCIB)
+ }
+ }
+
+ /* Describe the Southbridge devices */
+ Device(STCR) {
+ Name(_ADR, 0x00120000)
+ #include "acpi/sata.asl"
+ } /* end STCR */
+
+ Device(UOH1) {
+ Name(_ADR, 0x00130000)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH1 */
+
+ Device(UOH2) {
+ Name(_ADR, 0x00130001)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH2 */
+
+ Device(UOH3) {
+ Name(_ADR, 0x00130002)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH3 */
+
+ Device(UOH4) {
+ Name(_ADR, 0x00130003)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH4 */
+
+ Device(UOH5) {
+ Name(_ADR, 0x00130004)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH5 */
+
+ Device(UEH1) {
+ Name(_ADR, 0x00130005)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UEH1 */
+
+ Device(SBUS) {
+ Name(_ADR, 0x00140000)
+ } /* end SBUS */
+
+ /* Primary (and only) IDE channel */
+ Device(IDEC) {
+ Name(_ADR, 0x00140001)
+ #include "acpi/ide.asl"
+ } /* end IDEC */
+
+ Device(AZHD) {
+ Name(_ADR, 0x00140002)
+ OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
+ Field(AZPD, AnyAcc, NoLock, Preserve) {
+ offset (0x42),
+ NSDI, 1,
+ NSDO, 1,
+ NSEN, 1,
+ offset (0x44),
+ IPCR, 4,
+ offset (0x54),
+ PWST, 2,
+ , 6,
+ PMEB, 1,
+ , 6,
+ PMST, 1,
+ offset (0x62),
+ MMCR, 1,
+ offset (0x64),
+ MMLA, 32,
+ offset (0x68),
+ MMHA, 32,
+ offset (0x6C),
+ MMDT, 16,
+ }
+
+ Method(_INI) {
+ If(LEqual(OSTP,3)){ /* If we are running Linux */
+ Store(zero, NSEN)
+ Store(one, NSDO)
+ Store(one, NSDI)
+ }
+ }
+ } /* end AZHD */
+
+ Device(LIBR) {
+ Name(_ADR, 0x00140003)
+ /* Method(_INI) {
+ * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
+ } */ /* End Method(_SB.SBRDG._INI) */
+
+ /* Real Time Clock Device */
+ Device(RTC0) {
+ Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){8}
+ IO(Decode16,0x0070, 0x0070, 0, 2)
+ /* IO(Decode16,0x0070, 0x0070, 0, 4) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
+
+ Device(TMR) { /* Timer */
+ Name(_HID,EISAID("PNP0100")) /* System Timer */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){0}
+ IO(Decode16, 0x0040, 0x0040, 0, 4)
+ /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
+
+ Device(SPKR) { /* Speaker */
+ Name(_HID,EISAID("PNP0800")) /* AT style speaker */
+ Name(_CRS, ResourceTemplate() {
+ IO(Decode16, 0x0061, 0x0061, 0, 1)
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
+
+ Device(PIC) {
+ Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){2}
+ IO(Decode16,0x0020, 0x0020, 0, 2)
+ IO(Decode16,0x00A0, 0x00A0, 0, 2)
+ /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
+ /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
+
+ Device(MAD) { /* 8257 DMA */
+ Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
+ Name(_CRS, ResourceTemplate() {
+ DMA(Compatibility,BusMaster,Transfer8){4}
+ IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
+ IO(Decode16, 0x0081, 0x0081, 0x10, 0x03)
+ IO(Decode16, 0x0087, 0x0087, 0x10, 0x01)
+ IO(Decode16, 0x0089, 0x0089, 0x10, 0x03)
+ IO(Decode16, 0x008F, 0x008F, 0x10, 0x01)
+ IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
+ }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
+ } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
+
+ Device(COPR) {
+ Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
+ Name(_CRS, ResourceTemplate() {
+ IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
+ IRQNoFlags(){13}
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+
+ Device(HPTM) {
+ Name(_HID,EISAID("PNP0103"))
+ Name(CRS,ResourceTemplate() {
+ Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
+ })
+ Method(_STA, 0) {
+ Return(0x0F) /* sata is visible */
+ }
+ Method(_CRS, 0) {
+ CreateDwordField(CRS, ^HPT._BAS, HPBA)
+ Store(HPBA, HPBA)
+ Return(CRS)
+ }
+ } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+ } /* end LIBR */
+
+ Device(HPBR) {
+ Name(_ADR, 0x00140004)
+ } /* end HostPciBr */
+
+ Device(ACAD) {
+ Name(_ADR, 0x00140005)
+ } /* end Ac97audio */
+
+ Device(ACMD) {
+ Name(_ADR, 0x00140006)
+ } /* end Ac97modem */
+
+ Name(CRES, ResourceTemplate() {
+ IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
+
+ WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, /* address granularity */
+ 0x0000, /* range minimum */
+ 0x0CF7, /* range maximum */
+ 0x0000, /* translation */
+ 0x0CF8 /* length */
+ )
+
+ WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, /* address granularity */
+ 0x0D00, /* range minimum */
+ 0xFFFF, /* range maximum */
+ 0x0000, /* translation */
+ 0xF300 /* length */
+ )
+
+ Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
+ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
+ Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
+ Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
+
+ /* DRAM Memory from 1MB to TopMem */
+ Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
+
+ /* BIOS space just below 4GB */
+ DWORDMemory(
+ ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00, /* Granularity */
+ 0x00000000, /* Min */
+ 0x00000000, /* Max */
+ 0x00000000, /* Translation */
+ 0x00000000, /* Max-Min, RLEN */
+ ,,
+ PCBM
+ )
+
+ /* DRAM memory from 4GB to TopMem2 */
+ QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0xFFFFFFFF, /* Granularity */
+ 0x00000000, /* Min */
+ 0x00000000, /* Max */
+ 0x00000000, /* Translation */
+ 0x00000000, /* Max-Min, RLEN */
+ ,,
+ DMHI
+ )
+
+ /* BIOS space just below 16EB */
+ QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0xFFFFFFFF, /* Granularity */
+ 0x00000000, /* Min */
+ 0x00000000, /* Max */
+ 0x00000000, /* Translation */
+ 0x00000000, /* Max-Min, RLEN */
+ ,,
+ PEBM
+ )
+
+ }) /* End Name(_SB.PCI0.CRES) */
+
+ Method(_CRS, 0) {
+ /* DBGO("\\_SB\\PCI0\\_CRS\n") */
+
+ CreateDWordField(CRES, ^EMM1._BAS, EM1B)
+ CreateDWordField(CRES, ^EMM1._LEN, EM1L)
+ CreateDWordField(CRES, ^DMLO._BAS, DMLB)
+ CreateDWordField(CRES, ^DMLO._LEN, DMLL)
+ CreateDWordField(CRES, ^PCBM._MIN, PBMB)
+ CreateDWordField(CRES, ^PCBM._LEN, PBML)
+
+ CreateQWordField(CRES, ^DMHI._MIN, DMHB)
+ CreateQWordField(CRES, ^DMHI._LEN, DMHL)
+ CreateQWordField(CRES, ^PEBM._MIN, EBMB)
+ CreateQWordField(CRES, ^PEBM._LEN, EBML)
+
+ If(LGreater(LOMH, 0xC0000)){
+ Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
+ Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
+ }
+
+ /* Set size of memory from 1MB to TopMem */
+ Subtract(TOM1, 0x100000, DMLL)
+
+ /*
+ * If(LNotEqual(TOM2, 0x00000000)){
+ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
+ * Subtract(TOM2, 0x100000000, DMHL)
+ * }
+ */
+
+ /* If there is no memory above 4GB, put the BIOS just below 4GB */
+ If(LEqual(TOM2, 0x00000000)){
+ Store(PBAD,PBMB) /* Reserve the "BIOS" space */
+ Store(PBLN,PBML)
+ }
+ Else { /* Otherwise, put the BIOS just below 16EB */
+ ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
+ Store(PBLN,EBML)
+ }
+
+ Return(CRES) /* note to change the Name buffer */
+ } /* end of Method(_SB.PCI0._CRS) */
+
+ /*
+ *
+ * FIRST METHOD CALLED UPON BOOT
+ *
+ * 1. If debugging, print current OS and ACPI interpreter.
+ * 2. Get PCI Interrupt routing from ACPI VSM, this
+ * value is based on user choice in BIOS setup.
+ */
+ Method(_INI, 0) {
+ /* DBGO("\\_SB\\_INI\n") */
+ /* DBGO(" DSDT.ASL code from ") */
+ /* DBGO(__DATE__) */
+ /* DBGO(" ") */
+ /* DBGO(__TIME__) */
+ /* DBGO("\n Sleep states supported: ") */
+ /* DBGO("\n") */
+ /* DBGO(" \\_OS=") */
+ /* DBGO(\_OS) */
+ /* DBGO("\n \\_REV=") */
+ /* DBGO(\_REV) */
+ /* DBGO("\n") */
+
+ /* Determine the OS we're running on */
+ CkOT()
+
+ /* On older chips, clear PciExpWakeDisEn */
+ /*if (LLessEqual(\SBRI, 0x13)) {
+ * Store(0,\PWDE)
+ * }
+ */
+ } /* End Method(_SB._INI) */
+ } /* End Device(PCI0) */
+
+ Device(PWRB) { /* Start Power button device */
+ Name(_HID, EISAID("PNP0C0C"))
+ Name(_UID, 0xAA)
+ Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
+ Name(_STA, 0x0B) /* sata is invisible */
+ }
+
+ Device (SLPB) {
+ Name (_HID, EisaId ("PNP0C0E"))
+ Name (_PRW, Package (0x02) {0x0F, 0x04})
+ Name (_STA, 0x0B)
+ }
+ } /* End \_SB scope */
+
+ Scope(\_SI) {
+ Method(_SST, 1) {
+ /* DBGO("\\_SI\\_SST\n") */
+ /* DBGO(" New Indicator state: ") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+ }
+ } /* End Scope SI */
+
+ OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
+ Field (SMB0, ByteAcc, NoLock, Preserve) {
+ HSTS, 8, /* SMBUS status */
+ SSTS, 8, /* SMBUS slave status */
+ HCNT, 8, /* SMBUS control */
+ HCMD, 8, /* SMBUS host cmd */
+ HADD, 8, /* SMBUS address */
+ DAT0, 8, /* SMBUS data0 */
+ DAT1, 8, /* SMBUS data1 */
+ BLKD, 8, /* SMBUS block data */
+ SCNT, 8, /* SMBUS slave control */
+ SCMD, 8, /* SMBUS shaow cmd */
+ SEVT, 8, /* SMBUS slave event */
+ SDAT, 8 /* SMBUS slave data */
+ }
+
+ Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
+ Store (0x1E, HSTS)
+ Store (0xFA, Local0)
+ While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
+ Stall (0x64)
+ Decrement (Local0)
+ }
+
+ Return (Local0)
+ }
+
+ Method (SWTC, 1, NotSerialized) {
+ Store (Arg0, Local0)
+ Store (0x07, Local2)
+ Store (One, Local1)
+ While (LEqual (Local1, One)) {
+ Store (And (HSTS, 0x1E), Local3)
+ If (LNotEqual (Local3, Zero)) { /* read sucess */
+ If (LEqual (Local3, 0x02)) {
+ Store (Zero, Local2)
+ }
+
+ Store (Zero, Local1)
+ }
+ Else {
+ If (LLess (Local0, 0x0A)) { /* read failure */
+ Store (0x18, Local2)
+ Store (Zero, Local1)
+ }
+ Else {
+ Sleep (0x0A) /* 10 ms, try again */
+ Subtract (Local0, 0x0A, Local0)
+ }
+ }
+ }
+
+ Return (Local2)
+ }
+
+ Method (SMBR, 3, NotSerialized) {
+ Store (0x07, Local0)
+
+ Store (WCLR (), Local0) /* clear SMBUS status register before read data */
+
+ Store (0x1F, HSTS)
+ Store (Or (ShiftLeft (Arg1, One), One), HADD)
+ Store (Arg2, HCMD)
+ If (LEqual (Arg0, 0x07)) {
+ Store (0x48, HCNT) /* read byte */
+ }
+
+ Store (SWTC (0x03E8), Local1) /* 1000 ms */
+ If (LEqual (Local1, Zero)) {
+ If (LEqual (Arg0, 0x07)) {
+ Store (DAT0, Local0)
+ }
+ }
+ Else {
+ Store (Local1, Local0)
+ }
+
+ Return (Local0)
+ }
+
+ /* THERMAL */
+ Scope(\_TZ) {
+ Name (KELV, 2732)
+ Name (THOT, 900)
+ Name (TCRT, 950)
+
+ ThermalZone(TZ00) {
+ Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
+ /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
+ Return(Add(0, 2730))
+ }
+ Method(_AL0,0) { /* Returns package of cooling device to turn on */
+ /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
+ Return(Package() {\_TZ.TZ00.FAN0})
+ }
+ Device (FAN0) {
+ Name(_HID, EISAID("PNP0C0B"))
+ Name(_PR0, Package() {PFN0})
+ }
+
+ PowerResource(PFN0,0,0) {
+ Method(_STA) {
+ Store(0xF,Local0)
+ Return(Local0)
+ }
+ Method(_ON) {
+ /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
+ }
+ Method(_OFF) {
+ /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
+ }
+ }
+
+ Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
+ /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
+ Return (Add (THOT, KELV))
+ }
+ Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
+ /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
+ Return (Add (TCRT, KELV))
+ }
+ Method(_TMP,0) { /* return current temp of this zone */
+ Store (SMBR (0x07, 0x2E,, 0x25), Local0)
+ If (LGreater (Local0, 0x20)) {
+ Store (Local0, Local1)
+ }
+ Else {
+ Add (Local0, 0x40, Local0)
+ Add (Local0, TCRT, Local0)
+ Return (Add (550, KELV))
+ }
+
+ /* Store (SMBR (0x07, 0x2E, 0x26), Local0)
+ * If (LGreater (Local0, 0x20)) {
+ * If (LGreater (Local0, Local1)) {
+ * Store (Local0, Local1)
+ * }
+ * }
+ * Else {
+ * Add (Local0, 0x40, Local0)
+ * Add (Local0, TCRT, Local0)
+ * Return (Add (Local0, KELV))
+ * }
+ */
+
+ Store (SMBR (0x07, 0x2E, 0x27), Local0)
+ If (LGreater (Local0, 0x20)) {
+ If (LGreater (Local0, Local1)) {
+ Store (Local0, Local1)
+ }
+
+ Subtract (Local1, 0x40, Local1)
+ Multiply (Local1, 10, Local1)
+ Return (Add (Local1, KELV))
+ }
+ Else {
+ Add (Local0, 0x40, Local0)
+ Add (Local0, TCRT, Local0)
+ Return (Add (550 , KELV))
+ }
+ } /* end of _TMP */
+ } /* end of TZ00 */
+ }
+}
+/* End of ASL file */
obj-$(CONFIG_GENERATE_MP_TABLE) += mptable.o
obj-$(CONFIG_GENERATE_PIRQ_TABLE) += irq_tables.o
obj-$(CONFIG_GENERATE_ACPI_TABLES) += dsdt.o
+obj-$(CONFIG_GENERATE_ACPI_TABLES) += ssdt2.o
+obj-$(CONFIG_GENERATE_ACPI_TABLES) += ssdt3.o
+obj-$(CONFIG_GENERATE_ACPI_TABLES) += ssdt4.o
obj-$(CONFIG_GENERATE_ACPI_TABLES) += acpi_tables.o
obj-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.o
-# ./ssdt.o is in northbridge/amd/amdk8/Config.lb
-obj-y += ssdt2.o
-obj-y += ssdt3.o
-obj-y += ssdt4.o
driver-y += ../../../drivers/i2c/i2cmux/i2cmux.o
# This is part of the conversion to init-obj and away from included code.
ifdef POST_EVALUATION
-$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
- iasl -p $(obj)/dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
- mv $(obj)/dsdt.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl
- iasl -p $(obj)/pci2 -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl
- perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' $(obj)/pci2.hex
- mv $(obj)/pci2.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl
- iasl -p $(obj)/pci3 -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl
- perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' $(obj)/pci3.hex
- mv $(obj)/pci3.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl
- iasl -p $(obj)/pci4 -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl
- perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' $(obj)/pci4.hex
- mv $(obj)/pci4.hex $@
-
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+//AMD8111
+ Name (APIC, Package (0x04)
+ {
+ Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present
+ Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11},
+ Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12},
+ Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13}
+ })
+
+ Name (PICM, Package (0x04)
+ {
+ Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00},
+ Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00},
+ Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00},
+ Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00}
+ })
+
+ Name (DNCG, Ones)
+
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LEqual (^DNCG, Ones)) {
+ Store (DADD(\_SB.PCI0.SBDN, 0x0001ffff), Local0)
+ // Update the Device Number according to SBDN
+ Store(Local0, Index (DeRefOf (Index (PICM, 0)), 0))
+ Store(Local0, Index (DeRefOf (Index (PICM, 1)), 0))
+ Store(Local0, Index (DeRefOf (Index (PICM, 2)), 0))
+ Store(Local0, Index (DeRefOf (Index (PICM, 3)), 0))
+
+ Store(Local0, Index (DeRefOf (Index (APIC, 0)), 0))
+ Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0))
+ Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0))
+ Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0))
+
+ Store (0x00, ^DNCG)
+
+ }
+
+ If (LNot (PICF)) {
+ Return (PICM)
+ }
+ Else {
+ Return (APIC)
+ }
+ }
+
+ Device (SBC3)
+ {
+ /* acpi smbus it should be 0x00040003 if 8131 present */
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
+ }
+ OperationRegion (PIRQ, PCI_Config, 0x56, 0x02)
+ Field (PIRQ, ByteAcc, Lock, Preserve)
+ {
+ PIBA, 8,
+ PIDC, 8
+ }
+/*
+ OperationRegion (TS3_, PCI_Config, 0xC4, 0x02)
+ Field (TS3_, DWordAcc, NoLock, Preserve)
+ {
+ PTS3, 16
+ }
+*/
+ }
+
+ Device (HPET)
+ {
+ Name (HPT, 0x00)
+ Name (_HID, EisaId ("PNP0103"))
+ Name (_UID, 0x00)
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400)
+ })
+ Return (BUF0)
+ }
+ }
+
+ #include "amd8111_pic.asl"
+
+ #include "amd8111_isa.asl"
+
+ Device (TP2P)
+ {
+ /* 8111 P2P and it should 0x00030000 when 8131 present*/
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(\_SB.PCI0.SBDN, 0x00000000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x08, 0x03 }) }
+ Else { Return (Package (0x02) { 0x08, 0x01 }) }
+ }
+
+ Device (USB0)
+ {
+ Name (_ADR, 0x00000000)
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) }
+ Else { Return (Package (0x02) { 0x0F, 0x01 }) }
+ }
+ }
+
+ Device (USB1)
+ {
+ Name (_ADR, 0x00000001)
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) }
+ Else { Return (Package (0x02) { 0x0F, 0x01 }) }
+ }
+ }
+
+ Name (APIC, Package (0x0C)
+ {
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, //USB
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 },
+
+ Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, //Slot 4
+ Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 },
+ Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 },
+ Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 },
+
+ Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, //Slot 3
+ Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 },
+ Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 },
+ Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 }
+ })
+
+ Name (PICM, Package (0x0C)
+ {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
+
+ Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //Slot 4
+ Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
+
+ Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, //Slot 3
+ Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }
+ })
+
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
+
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+//AMD8111 isa
+
+ Device (ISA)
+ {
+ /* lpc 0x00040000 */
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(\_SB.PCI0.SBDN, 0x00010000))
+ }
+
+ OperationRegion (PIRY, PCI_Config, 0x51, 0x02) // LPC Decode Registers
+ Field (PIRY, ByteAcc, NoLock, Preserve)
+ {
+ Z000, 2, // Parallel Port Range
+ , 1,
+ ECP, 1, // ECP Enable
+ FDC1, 1, // Floppy Drive Controller 1
+ FDC2, 1, // Floppy Drive Controller 2
+ Offset (0x01),
+ Z001, 3, // Serial Port A Range
+ SAEN, 1, // Serial Post A Enabled
+ Z002, 3, // Serial Port B Range
+ SBEN, 1 // Serial Post B Enabled
+ }
+
+ Device (PIC)
+ {
+ Name (_HID, EisaId ("PNP0000"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0020, 0x0020, 0x01, 0x02)
+ IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02)
+ IRQ (Edge, ActiveHigh, Exclusive) {2}
+ })
+ }
+
+ Device (DMA1)
+ {
+ Name (_HID, EisaId ("PNP0200"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0000, 0x0000, 0x01, 0x10)
+ IO (Decode16, 0x0080, 0x0080, 0x01, 0x10)
+ IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20)
+ DMA (Compatibility, NotBusMaster, Transfer16) {4}
+ })
+ }
+
+ Device (TMR)
+ {
+ Name (_HID, EisaId ("PNP0100"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0040, 0x0040, 0x01, 0x04)
+ IRQ (Edge, ActiveHigh, Exclusive) {0}
+ })
+ }
+
+ Device (RTC)
+ {
+ Name (_HID, EisaId ("PNP0B00"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0070, 0x0070, 0x01, 0x06)
+ IRQ (Edge, ActiveHigh, Exclusive) {8}
+ })
+ }
+
+ Device (SPKR)
+ {
+ Name (_HID, EisaId ("PNP0800"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0061, 0x0061, 0x01, 0x01)
+ })
+ }
+
+ Device (COPR)
+ {
+ Name (_HID, EisaId ("PNP0C04"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x10)
+ IRQ (Edge, ActiveHigh, Exclusive) {13}
+ })
+ }
+
+ Device (SYSR)
+ {
+ Name (_HID, EisaId ("PNP0C02"))
+ Name (_UID, 0x00)
+ Name (SYR1, ResourceTemplate ()
+ {
+ IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02) //wrh092302 - added to report Thor NVRAM
+ IO (Decode16, 0x1100, 0x117F, 0x01, 0x80) //wrh092302 - added to report Thor NVRAM
+ IO (Decode16, 0x1180, 0x11FF, 0x01, 0x80)
+ IO (Decode16, 0x0010, 0x0010, 0x01, 0x10)
+ IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E)
+ IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C)
+ IO (Decode16, 0x0062, 0x0062, 0x01, 0x02)
+ IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B)
+ IO (Decode16, 0x0076, 0x0076, 0x01, 0x0A)
+ IO (Decode16, 0x0090, 0x0090, 0x01, 0x10)
+ IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E)
+ IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10)
+ IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
+ IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
+ })
+ Method (_CRS, 0, NotSerialized)
+ {
+ Return (SYR1)
+ }
+ }
+
+ Device (MEM)
+ {
+ Name (_HID, EisaId ("PNP0C02"))
+ Name (_UID, 0x01)
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF
+ Memory32Fixed (ReadWrite, 0x000C0000, 0x00000000) // video BIOS c0000-c8404
+ Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000) // I/O APIC
+ Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM
+ Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000) // Local APIC
+ Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS
+ Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
+ Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
+ Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS
+ Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS
+ })
+ // Read the Video Memory length
+ CreateDWordField (BUF0, 0x14, CLEN)
+ CreateDWordField (BUF0, 0x10, CBAS)
+
+ ShiftLeft (VGA1, 0x09, Local0)
+ Store (Local0, CLEN)
+
+ Return (BUF0)
+ }
+ }
+
+ Device (PS2M)
+ {
+ Name (_HID, EisaId ("PNP0F13"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IRQNoFlags () {12}
+ })
+ Method (_STA, 0, NotSerialized)
+ {
+ And (FLG0, 0x04, Local0)
+ If (LEqual (Local0, 0x04)) { Return (0x0F) }
+ Else { Return (0x00) }
+ }
+ }
+
+ Device (PS2K)
+ {
+ Name (_HID, EisaId ("PNP0303"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+ IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+ IRQNoFlags () {1}
+ })
+ }
+ #include "superio.asl"
+
+ }
+
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+//AMD8111 pic LNKA B C D
+
+ Device (LNKA)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x01)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local0)
+ If (LEqual (Local0, 0x00)) { Return (0x09) } //Disabled
+ Else { Return (0x0B) } //Enabled
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (BUFA, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {3,5,10,11}
+ })
+ Return (BUFA)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Store (0x01, Local3)
+ And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
+ Store (Local1, Local2)
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local1)
+ }
+
+ ShiftLeft (Local3, Local1, Local3)
+ Not (Local3, Local3)
+ And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUFA, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {}
+ })
+ CreateByteField (BUFA, 0x01, IRA1)
+ CreateByteField (BUFA, 0x02, IRA2)
+ Store (0x00, Local3)
+ Store (0x00, Local4)
+ And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
+ If (LNot (LEqual (Local1, 0x00)))
+ { // Routing enable
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local2)
+ ShiftLeft (One, Local2, Local4)
+ }
+ Else
+ {
+ If (LGreater (Local1, 0x00))
+ {
+ ShiftLeft (One, Local1, Local3)
+ }
+ }
+
+ Store (Local3, IRA1)
+ Store (Local4, IRA2)
+ }
+
+ Return (BUFA)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateByteField (Arg0, 0x01, IRA1)
+ CreateByteField (Arg0, 0x02, IRA2)
+ ShiftLeft (IRA2, 0x08, Local0)
+ Or (Local0, IRA1, Local0)
+ Store (0x00, Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ While (LGreater (Local0, 0x00))
+ {
+ Increment (Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ }
+
+ And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
+ Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
+ }
+ }
+
+ Device (LNKB)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x02)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local0)
+ If (LEqual (Local0, 0x00)) { Return (0x09) }
+ Else { Return (0x0B) }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (BUFB, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {3,5,10,11}
+ })
+ Return (BUFB)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Store (0x01, Local3)
+ And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
+ ShiftRight (Local1, 0x04, Local1)
+ Store (Local1, Local2)
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local1)
+ }
+
+ ShiftLeft (Local3, Local1, Local3)
+ Not (Local3, Local3)
+ And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUFB, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {}
+ })
+ CreateByteField (BUFB, 0x01, IRB1)
+ CreateByteField (BUFB, 0x02, IRB2)
+ Store (0x00, Local3)
+ Store (0x00, Local4)
+ And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
+ ShiftRight (Local1, 0x04, Local1)
+ If (LNot (LEqual (Local1, 0x00)))
+ {
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local2)
+ ShiftLeft (One, Local2, Local4)
+ }
+ Else
+ {
+ If (LGreater (Local1, 0x00))
+ {
+ ShiftLeft (One, Local1, Local3)
+ }
+ }
+
+ Store (Local3, IRB1)
+ Store (Local4, IRB2)
+ }
+
+ Return (BUFB)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateByteField (Arg0, 0x01, IRB1)
+ CreateByteField (Arg0, 0x02, IRB2)
+ ShiftLeft (IRB2, 0x08, Local0)
+ Or (Local0, IRB1, Local0)
+ Store (0x00, Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ While (LGreater (Local0, 0x00))
+ {
+ Increment (Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ }
+
+ And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
+ ShiftLeft (Local1, 0x04, Local1)
+ Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
+ }
+ }
+
+ Device (LNKC)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x03)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local0)
+ If (LEqual (Local0, 0x00)) { Return (0x09) }
+ Else { Return (0x0B) }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (BUFA, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {3,5,10,11}
+ })
+ Return (BUFA)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Store (0x01, Local3)
+ And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
+ Store (Local1, Local2)
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local1)
+ }
+
+ ShiftLeft (Local3, Local1, Local3)
+ Not (Local3, Local3)
+ And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUFA, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {}
+ })
+ CreateByteField (BUFA, 0x01, IRA1)
+ CreateByteField (BUFA, 0x02, IRA2)
+ Store (0x00, Local3)
+ Store (0x00, Local4)
+ And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
+ If (LNot (LEqual (Local1, 0x00)))
+ {
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local2)
+ ShiftLeft (One, Local2, Local4)
+ }
+ Else
+ {
+ If (LGreater (Local1, 0x00))
+ {
+ ShiftLeft (One, Local1, Local3)
+ }
+ }
+
+ Store (Local3, IRA1)
+ Store (Local4, IRA2)
+ }
+
+ Return (BUFA)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateByteField (Arg0, 0x01, IRA1)
+ CreateByteField (Arg0, 0x02, IRA2)
+ ShiftLeft (IRA2, 0x08, Local0)
+ Or (Local0, IRA1, Local0)
+ Store (0x00, Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ While (LGreater (Local0, 0x00))
+ {
+ Increment (Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ }
+
+ And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
+ Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
+ }
+ }
+
+ Device (LNKD)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x04)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local0)
+ If (LEqual (Local0, 0x00)) { Return (0x09) }
+ Else { Return (0x0B) }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (BUFB, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {3,5,10,11}
+ })
+ Return (BUFB)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Store (0x01, Local3)
+ And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
+ ShiftRight (Local1, 0x04, Local1)
+ Store (Local1, Local2)
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local1)
+ }
+
+ ShiftLeft (Local3, Local1, Local3)
+ Not (Local3, Local3)
+ And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUFB, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {}
+ })
+ CreateByteField (BUFB, 0x01, IRB1)
+ CreateByteField (BUFB, 0x02, IRB2)
+ Store (0x00, Local3)
+ Store (0x00, Local4)
+ And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
+ ShiftRight (Local1, 0x04, Local1)
+ If (LNot (LEqual (Local1, 0x00)))
+ {
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local2)
+ ShiftLeft (One, Local2, Local4)
+ }
+ Else
+ {
+ If (LGreater (Local1, 0x00))
+ {
+ ShiftLeft (One, Local1, Local3)
+ }
+ }
+
+ Store (Local3, IRB1)
+ Store (Local4, IRB2)
+ }
+
+ Return (BUFB)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateByteField (Arg0, 0x01, IRB1)
+ CreateByteField (Arg0, 0x02, IRB2)
+ ShiftLeft (IRB2, 0x08, Local0)
+ Or (Local0, IRB1, Local0)
+ Store (0x00, Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ While (LGreater (Local0, 0x00))
+ {
+ Increment (Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ }
+
+ And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
+ ShiftLeft (Local1, 0x04, Local1)
+ Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
+ }
+ }
+
+
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+
+ Device (PG0A)
+ {
+ /* 8132 pcix bridge*/
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 0), 0x00000000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
+ Else { Return (Package (0x02) { 0x29, 0x01 }) }
+ }
+
+ Name (APIC, Package (0x14)
+ {
+ // Slot A - PIRQ BCDA
+ Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 2
+ Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A },
+ Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B },
+ Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 },
+
+ //Cypress Slot A - PIRQ BCDA
+ Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x19 }, //?
+ Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1A },
+ Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x1B },
+ Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x18 },
+
+ //Cypress Slot B - PIRQ CDAB
+ Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1A }, //?
+ Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B },
+ Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x18 },
+ Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x19 },
+
+ //Cypress Slot C - PIRQ DABC
+ Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x1B }, //?
+ Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x18 },
+ Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x19 },
+ Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x1A },
+
+ //Cypress Slot D - PIRQ ABCD
+ Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x18 }, //?
+ Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x19 },
+ Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x1A },
+ Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x1B }
+ })
+ Name (PICM, Package (0x14)
+ {
+ Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 2
+ Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
+
+ Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
+
+ Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
+
+ Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
+
+ Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
+ Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0006FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
+ })
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
+
+ Device (PG0B)
+ {
+ /* 8132 pcix bridge 2 */
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 0), 0x00010000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
+ Else { Return (Package (0x02) { 0x22, 0x01 }) }
+ }
+
+ Name (APIC, Package (0x04)
+ {
+ // Slot A - PIRQ ABCD
+ Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x1F },// Slot 1
+ Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x20 },
+ Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x21 },
+ Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x22 }
+ })
+ Name (PICM, Package (0x04)
+ {
+ Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
+ Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
+ })
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+
+ Device (PG0A)
+ {
+ /* 8132 pcix bridge*/
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 0), 0x00000000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
+ Else { Return (Package (0x02) { 0x29, 0x01 }) }
+ }
+
+ Name (APIC, Package (0x04)
+ {
+ // Slot A - PIRQ BCDA
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B },
+
+ })
+ Name (PICM, Package (0x04)
+ {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
+ })
+
+ Name (DNCG, Ones)
+
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LEqual (^DNCG, Ones)) {
+ Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8
+ Store (0x00, Local1)
+ While (LLess (Local1, 0x04))
+ {
+ // Update the GSI according to HCIN
+ Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
+ Add(Local2, Local0, Local0)
+ Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
+ Increment (Local1)
+ }
+
+ Store (0x00, ^DNCG)
+
+ }
+
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
+
+ Device (PG0B)
+ {
+ /* 8132 pcix bridge 2 */
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 0), 0x00010000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
+ Else { Return (Package (0x02) { 0x22, 0x01 }) }
+ }
+
+ Name (APIC, Package (0x04)
+ {
+ // Slot A - PIRQ ABCD
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 }
+ })
+ Name (PICM, Package (0x04)
+ {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
+ })
+
+ Name (DNCG, Ones)
+
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LEqual (^DNCG, Ones)) {
+ Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8
+ Store (0x00, Local1)
+ While (LLess (Local1, 0x04))
+ {
+ // Update the GSI according to HCIN
+ Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
+ Add(Local2, Local0, Local0)
+ Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
+ Increment (Local1)
+ }
+
+ Store (0x00, ^DNCG)
+
+ }
+
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+
+ Device (PG0A)
+ {
+ /* 8132 pcix bridge*/
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 0), 0x00000000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
+ Else { Return (Package (0x02) { 0x29, 0x01 }) }
+ }
+
+ Name (APIC, Package (0x04)
+ {
+ // Slot A - PIRQ BCDA
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B },
+
+ })
+ Name (PICM, Package (0x04)
+ {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
+ })
+
+ Name (DNCG, Ones)
+
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LEqual (^DNCG, Ones)) {
+ Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14
+ Store (0x00, Local1)
+ While (LLess (Local1, 0x04))
+ {
+ // Update the GSI according to HCIN
+ Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
+ Add(Local2, Local0, Local0)
+ Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
+ Increment (Local1)
+ }
+
+ Store (0x00, ^DNCG)
+
+ }
+
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
+
+ Device (PG0B)
+ {
+ /* 8132 pcix bridge 2 */
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 0), 0x00010000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
+ Else { Return (Package (0x02) { 0x22, 0x01 }) }
+ }
+
+ Name (APIC, Package (0x04)
+ {
+ // Slot A - PIRQ ABCD
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 }
+ })
+ Name (PICM, Package (0x04)
+ {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
+ })
+
+ Name (DNCG, Ones)
+
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LEqual (^DNCG, Ones)) {
+ Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14
+ Store (0x00, Local1)
+ While (LLess (Local1, 0x04))
+ {
+ // Update the GSI according to HCIN
+ Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
+ Add(Local2, Local0, Local0)
+ Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
+ Increment (Local1)
+ }
+
+ Store (0x00, ^DNCG)
+
+ }
+
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
--- /dev/null
+// AMD8151
+ Device (AGPB)
+ {
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 0), 0x00010000))
+ }
+
+ Name (APIC, Package (0x04)
+ {
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 },
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 }
+ })
+ Name (PICM, Package (0x04)
+ {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
+ })
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
+
--- /dev/null
+ #include "amd8111.asl" //real SB at first
+ #include "amd8131.asl"
--- /dev/null
+ #include "amd8132_2.asl"
--- /dev/null
+ #include "amd8151.asl"
--- /dev/null
+ #include "amd8131_2.asl"
--- /dev/null
+// #include "w83627hf.asl"
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440)
+{
+ Scope (_PR)
+ {
+ Processor (CPU0, 0x00, 0x0000C010, 0x06) {}
+ Processor (CPU1, 0x01, 0x00000000, 0x00) {}
+ Processor (CPU2, 0x02, 0x00000000, 0x00) {}
+ Processor (CPU3, 0x03, 0x00000000, 0x00) {}
+
+ }
+
+ Method (FWSO, 0, NotSerialized) { }
+
+ Name (_S0, Package (0x04) { 0x00, 0x00, 0x00, 0x00 })
+ Name (_S1, Package (0x04) { 0x01, 0x01, 0x01, 0x01 })
+ Name (_S3, Package (0x04) { 0x05, 0x05, 0x05, 0x05 })
+ Name (_S5, Package (0x04) { 0x07, 0x07, 0x07, 0x07 })
+
+ Scope (_SB)
+ {
+ Device (PCI0)
+ {
+ /* BUS0 root bus */
+
+ External (BUSN)
+ External (MMIO)
+ External (PCIO)
+ External (SBLK)
+ External (TOM1)
+ External (HCLK)
+ External (SBDN)
+ External (HCDN)
+ External (CBST)
+
+
+ Name (_HID, EisaId ("PNP0A03"))
+ Name (_ADR, 0x00180000)
+ Name (_UID, 0x01)
+
+ Name (HCIN, 0x00) // HC1
+
+ Method (_BBN, 0, NotSerialized)
+ {
+ Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh
+ IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h
+ IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h
+
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Address Space Granularity
+ 0x8100, // Address Range Minimum
+ 0xFFFF, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x7F00,,,
+ , TypeStatic) //8100h-FFFFh
+
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Address Space Granularity
+ 0x000C0000, // Address Range Minimum
+ 0x00000000, // Address Range Maximum
+ 0x00000000, // Address Translation Offset
+ 0x00000000,,,
+ , AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh
+
+ Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF
+
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Address Space Granularity
+ 0x0000, // Address Range Minimum
+ 0x03AF, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x03B0,,,
+ , TypeStatic) //0-CF7h
+
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Address Space Granularity
+ 0x03E0, // Address Range Minimum
+ 0x0CF7, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x0918,,,
+ , TypeStatic) //0-CF7h
+ })
+ \_SB.OSTP ()
+ CreateDWordField (BUF0, 0x3E, VLEN)
+ CreateDWordField (BUF0, 0x36, VMAX)
+ CreateDWordField (BUF0, 0x32, VMIN)
+ ShiftLeft (VGA1, 0x09, Local0)
+ Add (VMIN, Local0, VMAX)
+ Decrement (VMAX)
+ Store (Local0, VLEN)
+ Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
+ Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
+ Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
+ Return (Local3)
+ }
+
+ #include "acpi/pci0_hc.asl"
+
+ }
+ Device (PCI1)
+ {
+ Name (_HID, "PNP0A03")
+ Name (_ADR, 0x00000000)
+ Name (_UID, 0x02)
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (\_SB.PCI0.CBST)
+ }
+ Name (_BBN, 0x00)
+ }
+
+
+ }
+
+ Scope (_GPE)
+ {
+ Method (_L08, 0, NotSerialized)
+ {
+ Notify (\_SB.PCI0, 0x02) //PME# Wakeup
+ }
+
+ Method (_L0F, 0, NotSerialized)
+ {
+ Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup
+ }
+
+ Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B
+ {
+ Notify (\_SB.PCI0.PG0B, 0x02)
+ }
+
+ Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A
+ {
+ Notify (\_SB.PCI0.PG0A, 0x02)
+ }
+ }
+
+ Method (_PTS, 1, NotSerialized)
+ {
+ Or (Arg0, 0xF0, Local0)
+ Store (Local0, DBG1)
+ }
+/*
+ Method (_WAK, 1, NotSerialized)
+ {
+ Or (Arg0, 0xE0, Local0)
+ Store (Local0, DBG1)
+ }
+*/
+ Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode
+ Method (_PIC, 1, NotSerialized) //PIC Flag and Interface Method
+ {
+ Store (Arg0, PICF)
+ }
+
+ OperationRegion (DEBG, SystemIO, 0x80, 0x01)
+ Field (DEBG, ByteAcc, Lock, Preserve)
+ {
+ DBG1, 8
+ }
+
+ OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04)
+ Field (EXTM, WordAcc, Lock, Preserve)
+ {
+ AMEM, 32
+ }
+
+ OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01)
+ Field (VGAM, ByteAcc, Lock, Preserve)
+ {
+ VGA1, 8
+ }
+
+ OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
+ Field (GRAM, ByteAcc, Lock, Preserve)
+ {
+ Offset (0x10),
+ FLG0, 8
+ }
+
+ OperationRegion (GSTS, SystemIO, 0xC028, 0x02)
+ Field (GSTS, ByteAcc, NoLock, Preserve)
+ {
+ , 4,
+ IRQR, 1
+ }
+
+ OperationRegion (Z007, SystemIO, 0x21, 0x01)
+ Field (Z007, ByteAcc, NoLock, Preserve)
+ {
+ Z008, 8
+ }
+
+ OperationRegion (Z009, SystemIO, 0xA1, 0x01)
+ Field (Z009, ByteAcc, NoLock, Preserve)
+ {
+ Z00A, 8
+ }
+
+ #include "northbridge/amd/amdk8/amdk8_util.asl"
+
+}
+
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-//AMD8111
- Name (APIC, Package (0x04)
- {
- Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present
- Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11},
- Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12},
- Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13}
- })
-
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00},
- Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00},
- Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00},
- Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00}
- })
-
- Name (DNCG, Ones)
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LEqual (^DNCG, Ones)) {
- Store (DADD(\_SB.PCI0.SBDN, 0x0001ffff), Local0)
- // Update the Device Number according to SBDN
- Store(Local0, Index (DeRefOf (Index (PICM, 0)), 0))
- Store(Local0, Index (DeRefOf (Index (PICM, 1)), 0))
- Store(Local0, Index (DeRefOf (Index (PICM, 2)), 0))
- Store(Local0, Index (DeRefOf (Index (PICM, 3)), 0))
-
- Store(Local0, Index (DeRefOf (Index (APIC, 0)), 0))
- Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0))
- Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0))
- Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0))
-
- Store (0x00, ^DNCG)
-
- }
-
- If (LNot (PICF)) {
- Return (PICM)
- }
- Else {
- Return (APIC)
- }
- }
-
- Device (SBC3)
- {
- /* acpi smbus it should be 0x00040003 if 8131 present */
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
- }
- OperationRegion (PIRQ, PCI_Config, 0x56, 0x02)
- Field (PIRQ, ByteAcc, Lock, Preserve)
- {
- PIBA, 8,
- PIDC, 8
- }
-/*
- OperationRegion (TS3_, PCI_Config, 0xC4, 0x02)
- Field (TS3_, DWordAcc, NoLock, Preserve)
- {
- PTS3, 16
- }
-*/
- }
-
- Device (HPET)
- {
- Name (HPT, 0x00)
- Name (_HID, EisaId ("PNP0103"))
- Name (_UID, 0x00)
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0F)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400)
- })
- Return (BUF0)
- }
- }
-
- Include ("amd8111_pic.asl")
-
- Include ("amd8111_isa.asl")
-
- Device (TP2P)
- {
- /* 8111 P2P and it should 0x00030000 when 8131 present*/
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(\_SB.PCI0.SBDN, 0x00000000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x08, 0x03 }) }
- Else { Return (Package (0x02) { 0x08, 0x01 }) }
- }
-
- Device (USB0)
- {
- Name (_ADR, 0x00000000)
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) }
- Else { Return (Package (0x02) { 0x0F, 0x01 }) }
- }
- }
-
- Device (USB1)
- {
- Name (_ADR, 0x00000001)
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) }
- Else { Return (Package (0x02) { 0x0F, 0x01 }) }
- }
- }
-
- Name (APIC, Package (0x0C)
- {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, //USB
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 },
-
- Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, //Slot 4
- Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 },
-
- Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, //Slot 3
- Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 },
- Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 },
- Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 }
- })
-
- Name (PICM, Package (0x0C)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
-
- Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //Slot 4
- Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
-
- Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, //Slot 3
- Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }
- })
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
-
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-//AMD8111 isa
-
- Device (ISA)
- {
- /* lpc 0x00040000 */
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(\_SB.PCI0.SBDN, 0x00010000))
- }
-
- OperationRegion (PIRY, PCI_Config, 0x51, 0x02) // LPC Decode Registers
- Field (PIRY, ByteAcc, NoLock, Preserve)
- {
- Z000, 2, // Parallel Port Range
- , 1,
- ECP, 1, // ECP Enable
- FDC1, 1, // Floppy Drive Controller 1
- FDC2, 1, // Floppy Drive Controller 2
- Offset (0x01),
- Z001, 3, // Serial Port A Range
- SAEN, 1, // Serial Post A Enabled
- Z002, 3, // Serial Port B Range
- SBEN, 1 // Serial Post B Enabled
- }
-
- Device (PIC)
- {
- Name (_HID, EisaId ("PNP0000"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0020, 0x0020, 0x01, 0x02)
- IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02)
- IRQ (Edge, ActiveHigh, Exclusive) {2}
- })
- }
-
- Device (DMA1)
- {
- Name (_HID, EisaId ("PNP0200"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0000, 0x0000, 0x01, 0x10)
- IO (Decode16, 0x0080, 0x0080, 0x01, 0x10)
- IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20)
- DMA (Compatibility, NotBusMaster, Transfer16) {4}
- })
- }
-
- Device (TMR)
- {
- Name (_HID, EisaId ("PNP0100"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0040, 0x0040, 0x01, 0x04)
- IRQ (Edge, ActiveHigh, Exclusive) {0}
- })
- }
-
- Device (RTC)
- {
- Name (_HID, EisaId ("PNP0B00"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0070, 0x0070, 0x01, 0x06)
- IRQ (Edge, ActiveHigh, Exclusive) {8}
- })
- }
-
- Device (SPKR)
- {
- Name (_HID, EisaId ("PNP0800"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0061, 0x0061, 0x01, 0x01)
- })
- }
-
- Device (COPR)
- {
- Name (_HID, EisaId ("PNP0C04"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x10)
- IRQ (Edge, ActiveHigh, Exclusive) {13}
- })
- }
-
- Device (SYSR)
- {
- Name (_HID, EisaId ("PNP0C02"))
- Name (_UID, 0x00)
- Name (SYR1, ResourceTemplate ()
- {
- IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02) //wrh092302 - added to report Thor NVRAM
- IO (Decode16, 0x1100, 0x117F, 0x01, 0x80) //wrh092302 - added to report Thor NVRAM
- IO (Decode16, 0x1180, 0x11FF, 0x01, 0x80)
- IO (Decode16, 0x0010, 0x0010, 0x01, 0x10)
- IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E)
- IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C)
- IO (Decode16, 0x0062, 0x0062, 0x01, 0x02)
- IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B)
- IO (Decode16, 0x0076, 0x0076, 0x01, 0x0A)
- IO (Decode16, 0x0090, 0x0090, 0x01, 0x10)
- IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E)
- IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10)
- IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
- IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
- })
- Method (_CRS, 0, NotSerialized)
- {
- Return (SYR1)
- }
- }
-
- Device (MEM)
- {
- Name (_HID, EisaId ("PNP0C02"))
- Name (_UID, 0x01)
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF
- Memory32Fixed (ReadWrite, 0x000C0000, 0x00000000) // video BIOS c0000-c8404
- Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000) // I/O APIC
- Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM
- Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000) // Local APIC
- Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS
- })
- // Read the Video Memory length
- CreateDWordField (BUF0, 0x14, CLEN)
- CreateDWordField (BUF0, 0x10, CBAS)
-
- ShiftLeft (VGA1, 0x09, Local0)
- Store (Local0, CLEN)
-
- Return (BUF0)
- }
- }
-
- Device (PS2M)
- {
- Name (_HID, EisaId ("PNP0F13"))
- Name (_CRS, ResourceTemplate ()
- {
- IRQNoFlags () {12}
- })
- Method (_STA, 0, NotSerialized)
- {
- And (FLG0, 0x04, Local0)
- If (LEqual (Local0, 0x04)) { Return (0x0F) }
- Else { Return (0x00) }
- }
- }
-
- Device (PS2K)
- {
- Name (_HID, EisaId ("PNP0303"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {1}
- })
- }
- Include ("superio.asl")
-
- }
-
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-//AMD8111 pic LNKA B C D
-
- Device (LNKA)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x01)
- Method (_STA, 0, NotSerialized)
- {
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local0)
- If (LEqual (Local0, 0x00)) { Return (0x09) } //Disabled
- Else { Return (0x0B) } //Enabled
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {3,5,10,11}
- })
- Return (BUFA)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Store (0x01, Local3)
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
- Store (Local1, Local2)
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local1)
- }
-
- ShiftLeft (Local3, Local1, Local3)
- Not (Local3, Local3)
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {}
- })
- CreateByteField (BUFA, 0x01, IRA1)
- CreateByteField (BUFA, 0x02, IRA2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
- If (LNot (LEqual (Local1, 0x00)))
- { // Routing enable
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRA1)
- Store (Local4, IRA2)
- }
-
- Return (BUFA)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateByteField (Arg0, 0x01, IRA1)
- CreateByteField (Arg0, 0x02, IRA2)
- ShiftLeft (IRA2, 0x08, Local0)
- Or (Local0, IRA1, Local0)
- Store (0x00, Local1)
- ShiftRight (Local0, 0x01, Local0)
- While (LGreater (Local0, 0x00))
- {
- Increment (Local1)
- ShiftRight (Local0, 0x01, Local0)
- }
-
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
- Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
- }
- }
-
- Device (LNKB)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x02)
- Method (_STA, 0, NotSerialized)
- {
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local0)
- If (LEqual (Local0, 0x00)) { Return (0x09) }
- Else { Return (0x0B) }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFB, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {3,5,10,11}
- })
- Return (BUFB)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Store (0x01, Local3)
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- Store (Local1, Local2)
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local1)
- }
-
- ShiftLeft (Local3, Local1, Local3)
- Not (Local3, Local3)
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFB, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {}
- })
- CreateByteField (BUFB, 0x01, IRB1)
- CreateByteField (BUFB, 0x02, IRB2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- If (LNot (LEqual (Local1, 0x00)))
- {
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRB1)
- Store (Local4, IRB2)
- }
-
- Return (BUFB)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateByteField (Arg0, 0x01, IRB1)
- CreateByteField (Arg0, 0x02, IRB2)
- ShiftLeft (IRB2, 0x08, Local0)
- Or (Local0, IRB1, Local0)
- Store (0x00, Local1)
- ShiftRight (Local0, 0x01, Local0)
- While (LGreater (Local0, 0x00))
- {
- Increment (Local1)
- ShiftRight (Local0, 0x01, Local0)
- }
-
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
- ShiftLeft (Local1, 0x04, Local1)
- Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
- }
- }
-
- Device (LNKC)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x03)
- Method (_STA, 0, NotSerialized)
- {
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local0)
- If (LEqual (Local0, 0x00)) { Return (0x09) }
- Else { Return (0x0B) }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {3,5,10,11}
- })
- Return (BUFA)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Store (0x01, Local3)
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
- Store (Local1, Local2)
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local1)
- }
-
- ShiftLeft (Local3, Local1, Local3)
- Not (Local3, Local3)
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {}
- })
- CreateByteField (BUFA, 0x01, IRA1)
- CreateByteField (BUFA, 0x02, IRA2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
- If (LNot (LEqual (Local1, 0x00)))
- {
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRA1)
- Store (Local4, IRA2)
- }
-
- Return (BUFA)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateByteField (Arg0, 0x01, IRA1)
- CreateByteField (Arg0, 0x02, IRA2)
- ShiftLeft (IRA2, 0x08, Local0)
- Or (Local0, IRA1, Local0)
- Store (0x00, Local1)
- ShiftRight (Local0, 0x01, Local0)
- While (LGreater (Local0, 0x00))
- {
- Increment (Local1)
- ShiftRight (Local0, 0x01, Local0)
- }
-
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
- Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
- }
- }
-
- Device (LNKD)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x04)
- Method (_STA, 0, NotSerialized)
- {
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local0)
- If (LEqual (Local0, 0x00)) { Return (0x09) }
- Else { Return (0x0B) }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFB, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {3,5,10,11}
- })
- Return (BUFB)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Store (0x01, Local3)
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- Store (Local1, Local2)
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local1)
- }
-
- ShiftLeft (Local3, Local1, Local3)
- Not (Local3, Local3)
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFB, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {}
- })
- CreateByteField (BUFB, 0x01, IRB1)
- CreateByteField (BUFB, 0x02, IRB2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- If (LNot (LEqual (Local1, 0x00)))
- {
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRB1)
- Store (Local4, IRB2)
- }
-
- Return (BUFB)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateByteField (Arg0, 0x01, IRB1)
- CreateByteField (Arg0, 0x02, IRB2)
- ShiftLeft (IRB2, 0x08, Local0)
- Or (Local0, IRB1, Local0)
- Store (0x00, Local1)
- ShiftRight (Local0, 0x01, Local0)
- While (LGreater (Local0, 0x00))
- {
- Increment (Local1)
- ShiftRight (Local0, 0x01, Local0)
- }
-
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
- ShiftLeft (Local1, 0x04, Local1)
- Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
- }
- }
-
-
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-
- Device (PG0A)
- {
- /* 8132 pcix bridge*/
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00000000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
- Else { Return (Package (0x02) { 0x29, 0x01 }) }
- }
-
- Name (APIC, Package (0x14)
- {
- // Slot A - PIRQ BCDA
- Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 2
- Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A },
- Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B },
- Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 },
-
- //Cypress Slot A - PIRQ BCDA
- Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x19 }, //?
- Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1A },
- Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x1B },
- Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x18 },
-
- //Cypress Slot B - PIRQ CDAB
- Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1A }, //?
- Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B },
- Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x18 },
- Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x19 },
-
- //Cypress Slot C - PIRQ DABC
- Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x1B }, //?
- Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x18 },
- Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x19 },
- Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x1A },
-
- //Cypress Slot D - PIRQ ABCD
- Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x18 }, //?
- Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x19 },
- Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x1A },
- Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x1B }
- })
- Name (PICM, Package (0x14)
- {
- Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 2
- Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
-
- Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
-
- Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
-
- Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
-
- Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0006FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
- })
- Method (_PRT, 0, NotSerialized)
- {
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
-
- Device (PG0B)
- {
- /* 8132 pcix bridge 2 */
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00010000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
- Else { Return (Package (0x02) { 0x22, 0x01 }) }
- }
-
- Name (APIC, Package (0x04)
- {
- // Slot A - PIRQ ABCD
- Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x1F },// Slot 1
- Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x20 },
- Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x21 },
- Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x22 }
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
- Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
- })
- Method (_PRT, 0, NotSerialized)
- {
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-
- Device (PG0A)
- {
- /* 8132 pcix bridge*/
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00000000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
- Else { Return (Package (0x02) { 0x29, 0x01 }) }
- }
-
- Name (APIC, Package (0x04)
- {
- // Slot A - PIRQ BCDA
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B },
-
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
- })
-
- Name (DNCG, Ones)
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LEqual (^DNCG, Ones)) {
- Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8
- Store (0x00, Local1)
- While (LLess (Local1, 0x04))
- {
- // Update the GSI according to HCIN
- Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
- Add(Local2, Local0, Local0)
- Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
- Increment (Local1)
- }
-
- Store (0x00, ^DNCG)
-
- }
-
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
-
- Device (PG0B)
- {
- /* 8132 pcix bridge 2 */
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00010000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
- Else { Return (Package (0x02) { 0x22, 0x01 }) }
- }
-
- Name (APIC, Package (0x04)
- {
- // Slot A - PIRQ ABCD
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 }
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
- })
-
- Name (DNCG, Ones)
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LEqual (^DNCG, Ones)) {
- Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8
- Store (0x00, Local1)
- While (LLess (Local1, 0x04))
- {
- // Update the GSI according to HCIN
- Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
- Add(Local2, Local0, Local0)
- Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
- Increment (Local1)
- }
-
- Store (0x00, ^DNCG)
-
- }
-
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-
- Device (PG0A)
- {
- /* 8132 pcix bridge*/
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00000000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
- Else { Return (Package (0x02) { 0x29, 0x01 }) }
- }
-
- Name (APIC, Package (0x04)
- {
- // Slot A - PIRQ BCDA
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B },
-
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
- })
-
- Name (DNCG, Ones)
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LEqual (^DNCG, Ones)) {
- Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14
- Store (0x00, Local1)
- While (LLess (Local1, 0x04))
- {
- // Update the GSI according to HCIN
- Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
- Add(Local2, Local0, Local0)
- Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
- Increment (Local1)
- }
-
- Store (0x00, ^DNCG)
-
- }
-
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
-
- Device (PG0B)
- {
- /* 8132 pcix bridge 2 */
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00010000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
- Else { Return (Package (0x02) { 0x22, 0x01 }) }
- }
-
- Name (APIC, Package (0x04)
- {
- // Slot A - PIRQ ABCD
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 }
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
- })
-
- Name (DNCG, Ones)
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LEqual (^DNCG, Ones)) {
- Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14
- Store (0x00, Local1)
- While (LLess (Local1, 0x04))
- {
- // Update the GSI according to HCIN
- Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
- Add(Local2, Local0, Local0)
- Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
- Increment (Local1)
- }
-
- Store (0x00, ^DNCG)
-
- }
-
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
+++ /dev/null
-// AMD8151
- Device (AGPB)
- {
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00010000))
- }
-
- Name (APIC, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 },
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 }
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
- })
- Method (_PRT, 0, NotSerialized)
- {
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
-
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440)
-{
- Scope (_PR)
- {
- Processor (CPU0, 0x00, 0x0000C010, 0x06) {}
- Processor (CPU1, 0x01, 0x00000000, 0x00) {}
- Processor (CPU2, 0x02, 0x00000000, 0x00) {}
- Processor (CPU3, 0x03, 0x00000000, 0x00) {}
-
- }
-
- Method (FWSO, 0, NotSerialized) { }
-
- Name (_S0, Package (0x04) { 0x00, 0x00, 0x00, 0x00 })
- Name (_S1, Package (0x04) { 0x01, 0x01, 0x01, 0x01 })
- Name (_S3, Package (0x04) { 0x05, 0x05, 0x05, 0x05 })
- Name (_S5, Package (0x04) { 0x07, 0x07, 0x07, 0x07 })
-
- Scope (_SB)
- {
- Device (PCI0)
- {
- /* BUS0 root bus */
-
- External (BUSN)
- External (MMIO)
- External (PCIO)
- External (SBLK)
- External (TOM1)
- External (HCLK)
- External (SBDN)
- External (HCDN)
- External (CBST)
-
-
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00180000)
- Name (_UID, 0x01)
-
- Name (HCIN, 0x00) // HC1
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh
- IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h
- IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h
-
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x8100, // Address Range Minimum
- 0xFFFF, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x7F00,,,
- , TypeStatic) //8100h-FFFFh
-
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, // Address Space Granularity
- 0x000C0000, // Address Range Minimum
- 0x00000000, // Address Range Maximum
- 0x00000000, // Address Translation Offset
- 0x00000000,,,
- , AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh
-
- Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF
-
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x03AF, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x03B0,,,
- , TypeStatic) //0-CF7h
-
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x03E0, // Address Range Minimum
- 0x0CF7, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0918,,,
- , TypeStatic) //0-CF7h
- })
- \_SB.OSTP ()
- CreateDWordField (BUF0, 0x3E, VLEN)
- CreateDWordField (BUF0, 0x36, VMAX)
- CreateDWordField (BUF0, 0x32, VMIN)
- ShiftLeft (VGA1, 0x09, Local0)
- Add (VMIN, Local0, VMAX)
- Decrement (VMAX)
- Store (Local0, VLEN)
- Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
- Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
- Return (Local3)
- }
-
- Include ("pci0_hc.asl")
-
- }
- Device (PCI1)
- {
- Name (_HID, "PNP0A03")
- Name (_ADR, 0x00000000)
- Name (_UID, 0x02)
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.PCI0.CBST)
- }
- Name (_BBN, 0x00)
- }
-
-
- }
-
- Scope (_GPE)
- {
- Method (_L08, 0, NotSerialized)
- {
- Notify (\_SB.PCI0, 0x02) //PME# Wakeup
- }
-
- Method (_L0F, 0, NotSerialized)
- {
- Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup
- }
-
- Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B
- {
- Notify (\_SB.PCI0.PG0B, 0x02)
- }
-
- Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A
- {
- Notify (\_SB.PCI0.PG0A, 0x02)
- }
- }
-
- Method (_PTS, 1, NotSerialized)
- {
- Or (Arg0, 0xF0, Local0)
- Store (Local0, DBG1)
- }
-/*
- Method (_WAK, 1, NotSerialized)
- {
- Or (Arg0, 0xE0, Local0)
- Store (Local0, DBG1)
- }
-*/
- Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode
- Method (_PIC, 1, NotSerialized) //PIC Flag and Interface Method
- {
- Store (Arg0, PICF)
- }
-
- OperationRegion (DEBG, SystemIO, 0x80, 0x01)
- Field (DEBG, ByteAcc, Lock, Preserve)
- {
- DBG1, 8
- }
-
- OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04)
- Field (EXTM, WordAcc, Lock, Preserve)
- {
- AMEM, 32
- }
-
- OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01)
- Field (VGAM, ByteAcc, Lock, Preserve)
- {
- VGA1, 8
- }
-
- OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
- Field (GRAM, ByteAcc, Lock, Preserve)
- {
- Offset (0x10),
- FLG0, 8
- }
-
- OperationRegion (GSTS, SystemIO, 0xC028, 0x02)
- Field (GSTS, ByteAcc, NoLock, Preserve)
- {
- , 4,
- IRQR, 1
- }
-
- OperationRegion (Z007, SystemIO, 0x21, 0x01)
- Field (Z007, ByteAcc, NoLock, Preserve)
- {
- Z008, 8
- }
-
- OperationRegion (Z009, SystemIO, 0xA1, 0x01)
- Field (Z009, ByteAcc, NoLock, Preserve)
- {
- Z00A, 8
- }
-
- Include ("../../../../../src/northbridge/amd/amdk8/amdk8_util.asl")
-
-}
-
+++ /dev/null
- Include ("amd8111.asl") //real SB at first
- Include ("amd8131.asl")
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
-{
- Scope (_SB)
- {
- External (DADD, MethodObj)
- External (GHCE, MethodObj)
- External (GHCN, MethodObj)
- External (GHCL, MethodObj)
- External (GHCD, MethodObj)
- External (GNUS, MethodObj)
- External (GIOR, MethodObj)
- External (GMEM, MethodObj)
- External (GWBN, MethodObj)
- External (GBUS, MethodObj)
-
- External (PICF)
-
- External (\_SB.PCI0.LNKA, DeviceObj)
- External (\_SB.PCI0.LNKB, DeviceObj)
- External (\_SB.PCI0.LNKC, DeviceObj)
- External (\_SB.PCI0.LNKD, DeviceObj)
-
- Device (PCIX)
- {
-
- // BUS ? Second HT Chain
- Name (HCIN, 0xcc) // HC2 0x01
-
- Name (_UID, 0xdd) // HC 0x03
-
- Name (_HID, "PNP0A03")
-
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0
- {
- Return (DADD(GHCN(HCIN), 0x00000000))
- }
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.GHCE(HCIN))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () { })
- Store( GHCN(HCIN), Local4)
- Store( GHCL(HCIN), Local5)
-
- Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
- Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
- Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
- Return (Local3)
- }
-
- Include ("pci2_hc.asl")
- }
- }
-
-}
-
+++ /dev/null
- Include ("amd8132_2.asl")
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
-{
- Scope (_SB)
- {
- External (DADD, MethodObj)
- External (GHCE, MethodObj)
- External (GHCN, MethodObj)
- External (GHCL, MethodObj)
- External (GHCD, MethodObj)
- External (GNUS, MethodObj)
- External (GIOR, MethodObj)
- External (GMEM, MethodObj)
- External (GWBN, MethodObj)
- External (GBUS, MethodObj)
-
- External (PICF)
-
- External (\_SB.PCI0.LNKA, DeviceObj)
- External (\_SB.PCI0.LNKB, DeviceObj)
- External (\_SB.PCI0.LNKC, DeviceObj)
- External (\_SB.PCI0.LNKD, DeviceObj)
-
- Device (PCIX)
- {
-
- // BUS ? Second HT Chain
- Name (HCIN, 0xcc) // HC2 0x01
-
- Name (_UID, 0xdd) // HC 0x03
-
- Name (_HID, "PNP0A03")
-
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0
- {
- Return (DADD(GHCN(HCIN), 0x00000000))
- }
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.GHCE(HCIN))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () { })
- Store( GHCN(HCIN), Local4)
- Store( GHCL(HCIN), Local5)
-
- Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
- Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
- Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
- Return (Local3)
- }
-
- Include ("pci3_hc.asl")
- }
- }
-
-}
-
+++ /dev/null
- Include ("amd8151.asl")
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
-{
- Scope (_SB)
- {
- External (DADD, MethodObj)
- External (GHCE, MethodObj)
- External (GHCN, MethodObj)
- External (GHCL, MethodObj)
- External (GHCD, MethodObj)
- External (GNUS, MethodObj)
- External (GIOR, MethodObj)
- External (GMEM, MethodObj)
- External (GWBN, MethodObj)
- External (GBUS, MethodObj)
-
- External (PICF)
-
- External (\_SB.PCI0.LNKA, DeviceObj)
- External (\_SB.PCI0.LNKB, DeviceObj)
- External (\_SB.PCI0.LNKC, DeviceObj)
- External (\_SB.PCI0.LNKD, DeviceObj)
-
- Device (PCIX)
- {
-
- // BUS ? Second HT Chain
- Name (HCIN, 0xcc) // HC2 0x01
-
- Name (_UID, 0xdd) // HC 0x03
-
- Name (_HID, "PNP0A03")
-
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0
- {
- Return (DADD(GHCN(HCIN), 0x00000000))
- }
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.GHCE(HCIN))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () { })
- Store( GHCN(HCIN), Local4)
- Store( GHCL(HCIN), Local5)
-
- Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
- Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
- Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
- Return (Local3)
- }
-
- Include ("pci4_hc.asl")
- }
- }
-
-}
-
+++ /dev/null
- Include ("amd8131_2.asl")
+++ /dev/null
-// Include ("w83627hf.asl")
At this time, For acpi support We got
1. support AMK K8 SRAT --- dynamically (coreboot run-time) (src/northbridge/amd/amdk8/amdk8_acpi.c)
2. support MADT ---- dynamically (coreboot run-time) (src/northbridge/amd/amdk8/amdk8_acpi.c , src/mainboard/amd/serengeti_cheetah/acpi_tables.c)
-3. support DSDT ---- dynamically (Compile time, coreboot run-time, ACPI run-time) (src/mainboard/amd/serengeti_cheetah/{dx/*, get_bus_conf.c}, src/northbridge/amd/amdk8/get_sblk_pci1234.c)
+3. support DSDT ---- dynamically (Compile time, coreboot run-time, ACPI run-time) (src/mainboard/amd/serengeti_cheetah/{acpi/*, get_bus_conf.c}, src/northbridge/amd/amdk8/get_sblk_pci1234.c)
4. Chipset support: amd8111, amd8132
The developers need to change for different MB
-Change dx/dsdt_lb.dsl, according to MB layout
+Change dsdt.asl, according to MB layout
pci1, pci2, pci3, pci4, ...., pci8
if there is HT-IO board, may use pci2.asl.... to create ssdt2.c, and ssdt3,c and ssdt4.c, ....ssdt8.c
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
+{
+ Scope (_SB)
+ {
+ External (DADD, MethodObj)
+ External (GHCE, MethodObj)
+ External (GHCN, MethodObj)
+ External (GHCL, MethodObj)
+ External (GHCD, MethodObj)
+ External (GNUS, MethodObj)
+ External (GIOR, MethodObj)
+ External (GMEM, MethodObj)
+ External (GWBN, MethodObj)
+ External (GBUS, MethodObj)
+
+ External (PICF)
+
+ External (\_SB.PCI0.LNKA, DeviceObj)
+ External (\_SB.PCI0.LNKB, DeviceObj)
+ External (\_SB.PCI0.LNKC, DeviceObj)
+ External (\_SB.PCI0.LNKD, DeviceObj)
+
+ Device (PCIX)
+ {
+
+ // BUS ? Second HT Chain
+ Name (HCIN, 0xcc) // HC2 0x01
+
+ Name (_UID, 0xdd) // HC 0x03
+
+ Name (_HID, "PNP0A03")
+
+ Method (_ADR, 0, NotSerialized) //Fake bus should be 0
+ {
+ Return (DADD(GHCN(HCIN), 0x00000000))
+ }
+
+ Method (_BBN, 0, NotSerialized)
+ {
+ Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (\_SB.GHCE(HCIN))
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate () { })
+ Store( GHCN(HCIN), Local4)
+ Store( GHCL(HCIN), Local5)
+
+ Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
+ Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
+ Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
+ Return (Local3)
+ }
+
+ #include "acpi/pci2_hc.asl"
+ }
+ }
+
+}
+
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
+{
+ Scope (_SB)
+ {
+ External (DADD, MethodObj)
+ External (GHCE, MethodObj)
+ External (GHCN, MethodObj)
+ External (GHCL, MethodObj)
+ External (GHCD, MethodObj)
+ External (GNUS, MethodObj)
+ External (GIOR, MethodObj)
+ External (GMEM, MethodObj)
+ External (GWBN, MethodObj)
+ External (GBUS, MethodObj)
+
+ External (PICF)
+
+ External (\_SB.PCI0.LNKA, DeviceObj)
+ External (\_SB.PCI0.LNKB, DeviceObj)
+ External (\_SB.PCI0.LNKC, DeviceObj)
+ External (\_SB.PCI0.LNKD, DeviceObj)
+
+ Device (PCIX)
+ {
+
+ // BUS ? Second HT Chain
+ Name (HCIN, 0xcc) // HC2 0x01
+
+ Name (_UID, 0xdd) // HC 0x03
+
+ Name (_HID, "PNP0A03")
+
+ Method (_ADR, 0, NotSerialized) //Fake bus should be 0
+ {
+ Return (DADD(GHCN(HCIN), 0x00000000))
+ }
+
+ Method (_BBN, 0, NotSerialized)
+ {
+ Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (\_SB.GHCE(HCIN))
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate () { })
+ Store( GHCN(HCIN), Local4)
+ Store( GHCL(HCIN), Local5)
+
+ Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
+ Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
+ Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
+ Return (Local3)
+ }
+
+ #include "acpi/pci3_hc.asl"
+ }
+ }
+
+}
+
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
+{
+ Scope (_SB)
+ {
+ External (DADD, MethodObj)
+ External (GHCE, MethodObj)
+ External (GHCN, MethodObj)
+ External (GHCL, MethodObj)
+ External (GHCD, MethodObj)
+ External (GNUS, MethodObj)
+ External (GIOR, MethodObj)
+ External (GMEM, MethodObj)
+ External (GWBN, MethodObj)
+ External (GBUS, MethodObj)
+
+ External (PICF)
+
+ External (\_SB.PCI0.LNKA, DeviceObj)
+ External (\_SB.PCI0.LNKB, DeviceObj)
+ External (\_SB.PCI0.LNKC, DeviceObj)
+ External (\_SB.PCI0.LNKD, DeviceObj)
+
+ Device (PCIX)
+ {
+
+ // BUS ? Second HT Chain
+ Name (HCIN, 0xcc) // HC2 0x01
+
+ Name (_UID, 0xdd) // HC 0x03
+
+ Name (_HID, "PNP0A03")
+
+ Method (_ADR, 0, NotSerialized) //Fake bus should be 0
+ {
+ Return (DADD(GHCN(HCIN), 0x00000000))
+ }
+
+ Method (_BBN, 0, NotSerialized)
+ {
+ Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (\_SB.GHCE(HCIN))
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate () { })
+ Store( GHCN(HCIN), Local4)
+ Store( GHCL(HCIN), Local5)
+
+ Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
+ Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
+ Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
+ Return (Local3)
+ }
+
+ #include "acpi/pci4_hc.asl"
+ }
+ }
+
+}
+
ifdef POST_EVALUATION
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
- iasl -p $(obj)/mainboard/$(MAINBOARDDIR)/dsdt -tc $<
- mv $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl
- iasl -p $(obj)/mainboard/$(MAINBOARDDIR)/pci2 -tc $<
- perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' $(obj)/mainboard/$(MAINBOARDDIR)/pci2.hex
- mv $(obj)/mainboard/$(MAINBOARDDIR)/pci2.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl
- iasl -p $(obj)/mainboard/$(MAINBOARDDIR)/pci3 -tc $<
- perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' $(obj)/mainboard/$(MAINBOARDDIR)/pci3.hex
- mv $(obj)/mainboard/$(MAINBOARDDIR)/pci3.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl
- iasl -p $(obj)/mainboard/$(MAINBOARDDIR)/pci4 -tc $<
- perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' $(obj)/mainboard/$(MAINBOARDDIR)/pci4.hex
- mv $(obj)/mainboard/$(MAINBOARDDIR)/pci4.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/ssdt5.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci5.asl
- iasl -p $(obj)/mainboard/$(MAINBOARDDIR)/pci5 -tc $<
- perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' $(obj)/mainboard/$(MAINBOARDDIR)/pci5.hex
- mv $(obj)/mainboard/$(MAINBOARDDIR)/pci5.hex $@
-
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
--- /dev/null
+//
+// This file is part of the coreboot project.
+//
+// Copyright (C) 2007 Advanced Micro Devices, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; version 2 of the License.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+//
+
+//AMD8111
+ Name (APIC, Package (0x04)
+ {
+ Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present
+ Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11},
+ Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12},
+ Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13}
+ })
+
+ Name (PICM, Package (0x04)
+ {
+ Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00},
+ Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00},
+ Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00},
+ Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00}
+ })
+
+ Name (DNCG, Ones)
+
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LEqual (^DNCG, Ones)) {
+ Store (DADD(\_SB.PCI0.SBDN, 0x0001ffff), Local0)
+ // Update the Device Number according to SBDN
+ Store(Local0, Index (DeRefOf (Index (PICM, 0)), 0))
+ Store(Local0, Index (DeRefOf (Index (PICM, 1)), 0))
+ Store(Local0, Index (DeRefOf (Index (PICM, 2)), 0))
+ Store(Local0, Index (DeRefOf (Index (PICM, 3)), 0))
+ Store(Local0, Index (DeRefOf (Index (APIC, 0)), 0))
+ Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0))
+ Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0))
+ Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0))
+ Store (0x00, ^DNCG)
+ }
+ If (LNot (PICF)) {Return (PICM)}
+ Else {Return (APIC)}
+ }
+
+ Device (SBC3)
+ {
+ // acpi smbus it should be 0x00040003 if 8131 present
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
+ }
+ OperationRegion (PIRQ, PCI_Config, 0x56, 0x02)
+ Field (PIRQ, ByteAcc, Lock, Preserve)
+ {
+ PIBA, 8,
+ PIDC, 8
+ }
+//
+// OperationRegion (TS3_, PCI_Config, 0xC4, 0x02)
+// Field (TS3_, DWordAcc, NoLock, Preserve)
+// {
+// PTS3, 16
+// }
+//
+ }
+
+ Device (HPET)
+ {
+ Name (HPT, 0x00)
+ Name (_HID, EisaId ("PNP0103"))
+ Name (_UID, 0x00)
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400)
+ })
+ Return (BUF0)
+ }
+ }
+
+ #include "amd8111_pic.asl"
+
+ #include "amd8111_isa.asl"
+
+ Device (TP2P)
+ {
+ // 8111 P2P and it should 0x00030000 when 8131 present
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(\_SB.PCI0.SBDN, 0x00000000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x08, 0x03 }) }
+ Else { Return (Package (0x02) { 0x08, 0x01 }) }
+ }
+
+ Device (USB0)
+ {
+ Name (_ADR, 0x00000000)
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) }
+ Else { Return (Package (0x02) { 0x0F, 0x01 }) }
+ }
+ }
+
+ Device (USB1)
+ {
+ Name (_ADR, 0x00000001)
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) }
+ Else { Return (Package (0x02) { 0x0F, 0x01 }) }
+ }
+ }
+
+ Name (APIC, Package (0x0C)
+ {
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, //USB
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 },
+
+ Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, //Slot 4
+ Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 },
+ Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 },
+ Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 },
+
+ Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, //Slot 3
+ Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 },
+ Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 },
+ Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 }
+ })
+
+ Name (PICM, Package (0x0C)
+ {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
+
+ Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //Slot 4
+ Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
+
+ Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, //Slot 3
+ Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }
+ })
+
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
+
--- /dev/null
+//
+// This file is part of the coreboot project.
+//
+// Copyright (C) 2007 Advanced Micro Devices, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; version 2 of the License.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+//
+
+//AMD8111 isa
+
+ Device (ISA)
+ {
+ // lpc 0x00040000
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(\_SB.PCI0.SBDN, 0x00010000))
+ }
+
+ OperationRegion (PIRY, PCI_Config, 0x51, 0x02) // LPC Decode Registers
+ Field (PIRY, ByteAcc, NoLock, Preserve)
+ {
+ Z000, 2, // Parallel Port Range
+ , 1,
+ ECP, 1, // ECP Enable
+ FDC1, 1, // Floppy Drive Controller 1
+ FDC2, 1, // Floppy Drive Controller 2
+ Offset (0x01),
+ Z001, 3, // Serial Port A Range
+ SAEN, 1, // Serial Post A Enabled
+ Z002, 3, // Serial Port B Range
+ SBEN, 1 // Serial Post B Enabled
+ }
+
+ Device (PIC)
+ {
+ Name (_HID, EisaId ("PNP0000"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0020, 0x0020, 0x01, 0x02)
+ IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02)
+ IRQ (Edge, ActiveHigh, Exclusive) {2}
+ })
+ }
+
+ Device (DMA1)
+ {
+ Name (_HID, EisaId ("PNP0200"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0000, 0x0000, 0x01, 0x10)
+ IO (Decode16, 0x0080, 0x0080, 0x01, 0x10)
+ IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20)
+ DMA (Compatibility, NotBusMaster, Transfer16) {4}
+ })
+ }
+
+ Device (TMR)
+ {
+ Name (_HID, EisaId ("PNP0100"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0040, 0x0040, 0x01, 0x04)
+ IRQ (Edge, ActiveHigh, Exclusive) {0}
+ })
+ }
+
+ Device (RTC)
+ {
+ Name (_HID, EisaId ("PNP0B00"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0070, 0x0070, 0x01, 0x06)
+ IRQ (Edge, ActiveHigh, Exclusive) {8}
+ })
+ }
+
+ Device (SPKR)
+ {
+ Name (_HID, EisaId ("PNP0800"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0061, 0x0061, 0x01, 0x01)
+ })
+ }
+
+ Device (COPR)
+ {
+ Name (_HID, EisaId ("PNP0C04"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x10)
+ IRQ (Edge, ActiveHigh, Exclusive) {13}
+ })
+ }
+
+ Device (SYSR)
+ {
+ Name (_HID, EisaId ("PNP0C02"))
+ Name (_UID, 0x00)
+ Name (SYR1, ResourceTemplate ()
+ {
+ IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02) //report Thor NVRAM
+ IO (Decode16, 0x1100, 0x117F, 0x01, 0x80) //report Thor NVRAM
+ IO (Decode16, 0x1180, 0x11FF, 0x01, 0x80)
+ IO (Decode16, 0x0010, 0x0010, 0x01, 0x10)
+ IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E)
+ IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C)
+ IO (Decode16, 0x0062, 0x0062, 0x01, 0x02)
+ IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B)
+ IO (Decode16, 0x0076, 0x0076, 0x01, 0x0A)
+ IO (Decode16, 0x0090, 0x0090, 0x01, 0x10)
+ IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E)
+ IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10)
+ IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
+ IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
+ })
+ Method (_CRS, 0, NotSerialized)
+ {
+ Return (SYR1)
+ }
+ }
+
+ Device (MEM)
+ {
+ Name (_HID, EisaId ("PNP0C02"))
+ Name (_UID, 0x01)
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF
+ Memory32Fixed (ReadWrite, 0x000C0000, 0x00000000) // video BIOS c0000-c8404
+ Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000) // I/O APIC
+ Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM
+ Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000) // Local APIC
+ Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS
+ Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
+ Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
+ Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
+ Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
+ })
+ // Read the Video Memory length
+ CreateDWordField (BUF0, 0x14, CLEN)
+ CreateDWordField (BUF0, 0x10, CBAS)
+
+ ShiftLeft (VGA1, 0x09, Local0)
+ Store (Local0, CLEN)
+
+ Return (BUF0)
+ }
+ }
+
+ Device (PS2M)
+ {
+ Name (_HID, EisaId ("PNP0F13"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IRQNoFlags () {12}
+ })
+ Method (_STA, 0, NotSerialized)
+ {
+ And (FLG0, 0x04, Local0)
+ If (LEqual (Local0, 0x04)) { Return (0x0F) }
+ Else { Return (0x00) }
+ }
+ }
+
+ Device (PS2K)
+ {
+ Name (_HID, EisaId ("PNP0303"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+ IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+ IRQNoFlags () {1}
+ })
+ }
+ #include "superio.asl"
+
+ }
+
--- /dev/null
+//
+// This file is part of the coreboot project.
+//
+// Copyright (C) 2007 Advanced Micro Devices, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; version 2 of the License.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+//
+
+//AMD8111 pic LNKA B C D
+
+ Device (LNKA)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x01)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local0)
+ If (LEqual (Local0, 0x00)) { Return (0x09) } //Disabled
+ Else { Return (0x0B) } //Enabled
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (BUFA, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {3,5,10,11}
+ })
+ Return (BUFA)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Store (0x01, Local3)
+ And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
+ Store (Local1, Local2)
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local1)
+ }
+
+ ShiftLeft (Local3, Local1, Local3)
+ Not (Local3, Local3)
+ And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUFA, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {}
+ })
+ CreateByteField (BUFA, 0x01, IRA1)
+ CreateByteField (BUFA, 0x02, IRA2)
+ Store (0x00, Local3)
+ Store (0x00, Local4)
+ And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
+ If (LNot (LEqual (Local1, 0x00)))
+ { // Routing enable
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local2)
+ ShiftLeft (One, Local2, Local4)
+ }
+ Else
+ {
+ If (LGreater (Local1, 0x00))
+ {
+ ShiftLeft (One, Local1, Local3)
+ }
+ }
+
+ Store (Local3, IRA1)
+ Store (Local4, IRA2)
+ }
+
+ Return (BUFA)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateByteField (Arg0, 0x01, IRA1)
+ CreateByteField (Arg0, 0x02, IRA2)
+ ShiftLeft (IRA2, 0x08, Local0)
+ Or (Local0, IRA1, Local0)
+ Store (0x00, Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ While (LGreater (Local0, 0x00))
+ {
+ Increment (Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ }
+
+ And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
+ Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
+ }
+ }
+
+ Device (LNKB)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x02)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local0)
+ If (LEqual (Local0, 0x00)) { Return (0x09) }
+ Else { Return (0x0B) }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (BUFB, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {3,5,10,11}
+ })
+ Return (BUFB)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Store (0x01, Local3)
+ And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
+ ShiftRight (Local1, 0x04, Local1)
+ Store (Local1, Local2)
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local1)
+ }
+
+ ShiftLeft (Local3, Local1, Local3)
+ Not (Local3, Local3)
+ And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUFB, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {}
+ })
+ CreateByteField (BUFB, 0x01, IRB1)
+ CreateByteField (BUFB, 0x02, IRB2)
+ Store (0x00, Local3)
+ Store (0x00, Local4)
+ And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
+ ShiftRight (Local1, 0x04, Local1)
+ If (LNot (LEqual (Local1, 0x00)))
+ {
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local2)
+ ShiftLeft (One, Local2, Local4)
+ }
+ Else
+ {
+ If (LGreater (Local1, 0x00))
+ {
+ ShiftLeft (One, Local1, Local3)
+ }
+ }
+
+ Store (Local3, IRB1)
+ Store (Local4, IRB2)
+ }
+
+ Return (BUFB)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateByteField (Arg0, 0x01, IRB1)
+ CreateByteField (Arg0, 0x02, IRB2)
+ ShiftLeft (IRB2, 0x08, Local0)
+ Or (Local0, IRB1, Local0)
+ Store (0x00, Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ While (LGreater (Local0, 0x00))
+ {
+ Increment (Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ }
+
+ And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
+ ShiftLeft (Local1, 0x04, Local1)
+ Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
+ }
+ }
+
+ Device (LNKC)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x03)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local0)
+ If (LEqual (Local0, 0x00)) { Return (0x09) }
+ Else { Return (0x0B) }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (BUFA, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {3,5,10,11}
+ })
+ Return (BUFA)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Store (0x01, Local3)
+ And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
+ Store (Local1, Local2)
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local1)
+ }
+
+ ShiftLeft (Local3, Local1, Local3)
+ Not (Local3, Local3)
+ And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUFA, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {}
+ })
+ CreateByteField (BUFA, 0x01, IRA1)
+ CreateByteField (BUFA, 0x02, IRA2)
+ Store (0x00, Local3)
+ Store (0x00, Local4)
+ And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
+ If (LNot (LEqual (Local1, 0x00)))
+ {
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local2)
+ ShiftLeft (One, Local2, Local4)
+ }
+ Else
+ {
+ If (LGreater (Local1, 0x00))
+ {
+ ShiftLeft (One, Local1, Local3)
+ }
+ }
+
+ Store (Local3, IRA1)
+ Store (Local4, IRA2)
+ }
+
+ Return (BUFA)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateByteField (Arg0, 0x01, IRA1)
+ CreateByteField (Arg0, 0x02, IRA2)
+ ShiftLeft (IRA2, 0x08, Local0)
+ Or (Local0, IRA1, Local0)
+ Store (0x00, Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ While (LGreater (Local0, 0x00))
+ {
+ Increment (Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ }
+
+ And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
+ Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
+ }
+ }
+
+ Device (LNKD)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x04)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local0)
+ If (LEqual (Local0, 0x00)) { Return (0x09) }
+ Else { Return (0x0B) }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (BUFB, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {3,5,10,11}
+ })
+ Return (BUFB)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Store (0x01, Local3)
+ And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
+ ShiftRight (Local1, 0x04, Local1)
+ Store (Local1, Local2)
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local1)
+ }
+
+ ShiftLeft (Local3, Local1, Local3)
+ Not (Local3, Local3)
+ And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUFB, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {}
+ })
+ CreateByteField (BUFB, 0x01, IRB1)
+ CreateByteField (BUFB, 0x02, IRB2)
+ Store (0x00, Local3)
+ Store (0x00, Local4)
+ And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
+ ShiftRight (Local1, 0x04, Local1)
+ If (LNot (LEqual (Local1, 0x00)))
+ {
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local2)
+ ShiftLeft (One, Local2, Local4)
+ }
+ Else
+ {
+ If (LGreater (Local1, 0x00))
+ {
+ ShiftLeft (One, Local1, Local3)
+ }
+ }
+
+ Store (Local3, IRB1)
+ Store (Local4, IRB2)
+ }
+
+ Return (BUFB)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateByteField (Arg0, 0x01, IRB1)
+ CreateByteField (Arg0, 0x02, IRB2)
+ ShiftLeft (IRB2, 0x08, Local0)
+ Or (Local0, IRB1, Local0)
+ Store (0x00, Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ While (LGreater (Local0, 0x00))
+ {
+ Increment (Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ }
+
+ And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
+ ShiftLeft (Local1, 0x04, Local1)
+ Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
+ }
+ }
+
+
--- /dev/null
+//
+// This file is part of the coreboot project.
+//
+// Copyright (C) 2007 Advanced Micro Devices, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; version 2 of the License.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+//
+ Device (PG0A)
+ {
+ // 8132 pcix bridge
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 0), 0x00000000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
+ Else { Return (Package (0x02) { 0x29, 0x01 }) }
+ }
+
+ Name (APIC, Package (0x04)
+ {
+ // Slot A - PIRQ BCDA
+ Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0018 }, //Slot 2
+ Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x0019 },
+ Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x001A },
+ Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x001B },
+ })
+ Name (PICM, Package (0x04)
+ {
+ Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2
+ Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
+ })
+
+ Name (DNCG, Ones)
+
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LEqual (^DNCG, Ones))
+ {
+ Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8
+ Store (0x00, Local1)
+ While (LLess (Local1, 0x04))
+ {
+ // Update the GSI according to HCIN
+ Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
+ Add(Local2, Local0, Local0)
+ Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
+ Increment (Local1)
+ }
+ Store (0x00, ^DNCG)
+ }
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
+
+ Device (PG0B)
+ {
+ // 8132 pcix bridge 2
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 0), 0x00010000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
+ Else { Return (Package (0x02) { 0x22, 0x01 }) }
+ }
+
+ Name (APIC, Package (0x04)
+ {
+ // Slot A - PIRQ ABCD
+ Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x001F },// Slot 1
+ Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x0020 },
+ Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x0021 },
+ Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x0022 }
+ })
+ Name (PICM, Package (0x04)
+ {
+ Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
+ Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
+ })
+
+ Name (DNCG, Ones)
+
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LEqual (^DNCG, Ones))
+ {
+ Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8
+ Store (0x00, Local1)
+ While (LLess (Local1, 0x04))
+ {
+ // Update the GSI according to HCIN
+ Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
+ Add(Local2, Local0, Local0)
+ Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
+ Increment (Local1)
+ }
+
+ Store (0x00, ^DNCG)
+
+ }
+
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
--- /dev/null
+//
+// This file is part of the coreboot project.
+//
+// Copyright (C) 2007 Advanced Micro Devices, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; version 2 of the License.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+//
+
+ Device (PG0A)
+ {
+ // 8132 pcix bridge
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 0), 0x00000000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
+ Else { Return (Package (0x02) { 0x29, 0x01 }) }
+ }
+
+ Name (APIC, Package (0x14)
+ {
+ // Slot A - PIRQ BCDA
+ Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 2
+ Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A },
+ Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B },
+ Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 },
+
+ //Cypress Slot A - PIRQ BCDA
+ Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x19 }, //?
+ Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1A },
+ Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x1B },
+ Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x18 },
+
+ //Cypress Slot B - PIRQ CDAB
+ Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1A }, //?
+ Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B },
+ Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x18 },
+ Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x19 },
+
+ //Cypress Slot C - PIRQ DABC
+ Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x1B }, //?
+ Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x18 },
+ Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x19 },
+ Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x1A },
+
+ //Cypress Slot D - PIRQ ABCD
+ Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x18 }, //?
+ Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x19 },
+ Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x1A },
+ Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x1B }
+ })
+ Name (PICM, Package (0x14)
+ {
+ Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 2
+ Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
+
+ Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
+
+ Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
+
+ Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
+
+ Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
+ Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0006FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
+ })
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
+
+ Device (PG0B)
+ {
+ // 8132 pcix bridge 2
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 0), 0x00010000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
+ Else { Return (Package (0x02) { 0x22, 0x01 }) }
+ }
+
+ Name (APIC, Package (0x04)
+ {
+ // Slot A - PIRQ ABCD
+ Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x1F },// Slot 1
+ Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x20 },
+ Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x21 },
+ Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x22 }
+ })
+ Name (PICM, Package (0x04)
+ {
+ Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
+ Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
+ })
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
--- /dev/null
+//
+// This file is part of the coreboot project.
+//
+// Copyright (C) 2007 Advanced Micro Devices, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; version 2 of the License.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+//
+
+ Device (PG0A)
+ {
+ // 8132 pcix bridge
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 0), 0x00000000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
+ Else { Return (Package (0x02) { 0x29, 0x01 }) }
+ }
+
+ Name (APIC, Package (0x10)
+ {
+ // Slot 1 - PIRQ ABCD
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 },
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B },
+ // Slot 2 - PIRQ BCDA
+ Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0019 },
+ Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x001A },
+ Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x001B },
+ Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x0018 },
+ // Slot 3 - PIRQ CDAB
+ Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x001A },
+ Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x001B },
+ Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x0018 },
+ Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x0019 },
+ // Slot 4 - PIRQ DABC
+ Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x001B },
+ Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x0018 },
+ Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x0019 },
+ Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x001A },
+
+ })
+ Name (PICM, Package (0x04)
+ {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
+//
+// Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 2
+// Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
+// Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
+// Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
+//
+// Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },//Slot 2
+// Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
+// Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
+// Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
+//
+// Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },//Slot 2
+// Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
+// Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
+// Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
+//
+ })
+
+ Name (DNCG, Ones)
+
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LEqual (^DNCG, Ones)) {
+ Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14
+ Store (0x00, Local1)
+ While (LLess (Local1, 0x10))
+ {
+ // Update the GSI according to HCIN
+ Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
+ Add(Local2, Local0, Local0)
+ Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
+ Increment (Local1)
+ }
+
+ Store (0x00, ^DNCG)
+
+ }
+
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
+
+ Device (PG0B)
+ {
+ // 8132 pcix bridge 2
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 0), 0x00010000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
+ Else { Return (Package (0x02) { 0x22, 0x01 }) }
+ }
+
+ Name (APIC, Package (0x10)
+ {
+ // Slot A - PIRQ ABCD
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 },
+ // Slot A - PIRQ BCDA
+ Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0020 },// Slot 1
+ Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x0021 },
+ Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x0022 },
+ Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x001F },
+ // Slot A - PIRQ CDAB
+ Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x0021 },// Slot 1
+ Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x0022 },
+ Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x001F },
+ Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x0020 },
+ // Slot A - PIRQ DABC
+ Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x0022 },// Slot 1
+ Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x001F },
+ Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x0020 },
+ Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x0021 },
+ })
+ Name (PICM, Package (0x04)
+ {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
+
+// Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 1
+// Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
+// Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
+// Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
+//
+// Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },//Slot 1
+// Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
+// Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
+// Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
+//
+// Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },//Slot 1
+// Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
+// Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
+// Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
+//
+ })
+
+ Name (DNCG, Ones)
+
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LEqual (^DNCG, Ones)) {
+ Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14
+ Store (0x00, Local1)
+ While (LLess (Local1, 0x10))
+ {
+ // Update the GSI according to HCIN
+ Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
+ Add(Local2, Local0, Local0)
+ Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
+ Increment (Local1)
+ }
+
+ Store (0x00, ^DNCG)
+
+ }
+
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
--- /dev/null
+//
+// This file is part of the coreboot project.
+//
+// Copyright (C) 2007 Advanced Micro Devices, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; version 2 of the License.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+//
+
+// AMD8151
+ Device (AGPB)
+ {
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 0), 0x00010000))
+ }
+
+ Name (APIC, Package (0x04)
+ {
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 },
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 }
+ })
+ Name (PICM, Package (0x04)
+ {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
+ })
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
+
--- /dev/null
+//
+// This file is part of the coreboot project.
+//
+// Copyright (C) 2007 Advanced Micro Devices, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; version 2 of the License.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+//
+
+ Device (HTXA)
+ {
+ // HTX
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 0), 0x00000000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
+ Else { Return (Package (0x02) { 0x29, 0x01 }) }
+ }
+
+ }
+
--- /dev/null
+//
+// This file is part of the coreboot project.
+//
+// Copyright (C) 2007 Advanced Micro Devices, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; version 2 of the License.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+//
+ #include "amd8111.asl" //real SB at first
+ #include "amd8132.asl"
--- /dev/null
+//
+// This file is part of the coreboot project.
+//
+// Copyright (C) 2007 Advanced Micro Devices, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; version 2 of the License.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+//
+
+ #include "amd8132_2.asl"
--- /dev/null
+//
+// This file is part of the coreboot project.
+//
+// Copyright (C) 2007 Advanced Micro Devices, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; version 2 of the License.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+//
+
+ #include "amd8151.asl"
--- /dev/null
+//
+// This file is part of the coreboot project.
+//
+// Copyright (C) 2007 Advanced Micro Devices, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; version 2 of the License.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+//
+
+ #include "amd8131_2.asl"
--- /dev/null
+//
+// This file is part of the coreboot project.
+//
+// Copyright (C) 2007 Advanced Micro Devices, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; version 2 of the License.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+//
+
+ #include "htx_no_ioapic.asl"
--- /dev/null
+//
+// This file is part of the coreboot project.
+//
+// Copyright (C) 2007 Advanced Micro Devices, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; version 2 of the License.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+//
+
+// #include "w83627hf.asl"
--- /dev/null
+//
+// This file is part of the coreboot project.
+//
+// Copyright (C) 2007 Advanced Micro Devices, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; version 2 of the License.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+//
+DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
+{
+
+// Scope (_PR)
+// {
+// Processor (CPU0, 0x00, 0x0000C010, 0x06) {}
+// Processor (CPU1, 0x01, 0x00000000, 0x00) {}
+// Processor (CPU2, 0x02, 0x00000000, 0x00) {}
+// Processor (CPU3, 0x03, 0x00000000, 0x00) {}
+// }
+
+ Method (FWSO, 0, NotSerialized) { }
+
+ Name (_S0, Package (0x04) { 0x00, 0x00, 0x00, 0x00 })
+ Name (_S1, Package (0x04) { 0x01, 0x01, 0x01, 0x01 })
+ Name (_S3, Package (0x04) { 0x05, 0x05, 0x05, 0x05 })
+ Name (_S5, Package (0x04) { 0x07, 0x07, 0x07, 0x07 })
+
+ Scope (_SB)
+ {
+ Device (PCI0)
+ {
+ // BUS0 root bus
+ External (BUSN)
+ External (MMIO)
+ External (PCIO)
+ External (SBLK)
+ External (TOM1)
+ External (HCLK)
+ External (SBDN)
+ External (HCDN)
+ External (CBST)
+ External (CBB)
+ External (CBS2)
+ External (CBB2)
+
+ Name (_HID, EisaId ("PNP0A03"))
+ Name (_ADR, 0x00000000)
+ Name (_UID, 0x01)
+
+ Name (HCIN, 0x00) // HC1
+
+ Method (_BBN, 0, NotSerialized)
+ {
+ Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh
+ IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h
+ IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h
+
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Address Space Granularity
+ 0x8100, // Address Range Minimum
+ 0xFFFF, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x7F00,,,
+ , TypeStatic) //8100h-FFFFh
+
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Address Space Granularity
+ 0x000C0000, // Address Range Minimum
+ 0x00000000, // Address Range Maximum
+ 0x00000000, // Address Translation Offset
+ 0x00000000,,,
+ , AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh
+
+ Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF
+
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Address Space Granularity
+ 0x0000, // Address Range Minimum
+ 0x03AF, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x03B0,,,
+ , TypeStatic) //0-CF7h
+
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Address Space Granularity
+ 0x03E0, // Address Range Minimum
+ 0x0CF7, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x0918,,,
+ , TypeStatic) //0-CF7h
+ })
+ \_SB.OSTP ()
+ CreateDWordField (BUF0, 0x3E, VLEN)
+ CreateDWordField (BUF0, 0x36, VMAX)
+ CreateDWordField (BUF0, 0x32, VMIN)
+ ShiftLeft (VGA1, 0x09, Local0)
+ Add (VMIN, Local0, VMAX)
+ Decrement (VMAX)
+ Store (Local0, VLEN)
+ Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
+ Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
+ Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
+ Return (Local3)
+ }
+
+ #include "acpi/pci0_hc.asl"
+
+ }
+ Device (PCI1)
+ {
+ Name (_HID, "PNP0A03")
+ Name (_ADR, 0x00000000)
+ Name (_UID, 0x02)
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (\_SB.PCI0.CBST)
+ }
+ Method (_BBN, 0, NotSerialized)
+ {
+ Return (\_SB.PCI0.CBB) // 0 or 0xff
+ }
+
+ }
+ Device (PCI2)
+ {
+ Name (_HID, "PNP0A03")
+ Name (_ADR, 0x00000000)
+ Name (_UID, 0x02)
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (\_SB.PCI0.CBS2)
+ }
+ Method (_BBN, 0, NotSerialized)
+ {
+ Return (\_SB.PCI0.CBB2)// 0xfe
+ }
+ }
+ }
+
+ Scope (_GPE)
+ {
+ Method (_L08, 0, NotSerialized)
+ {
+ Notify (\_SB.PCI0, 0x02) //PME# Wakeup
+ }
+
+ Method (_L0F, 0, NotSerialized)
+ {
+ Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup
+ }
+
+ Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B
+ {
+ Notify (\_SB.PCI0.PG0B, 0x02)
+ }
+
+ Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A
+ {
+ Notify (\_SB.PCI0.PG0A, 0x02)
+ }
+ }
+
+ Method (_PTS, 1, NotSerialized)
+ {
+ Or (Arg0, 0xF0, Local0)
+ Store (Local0, DBG1)
+ }
+//
+// Method (_WAK, 1, NotSerialized)
+// {
+// Or (Arg0, 0xE0, Local0)
+// Store (Local0, DBG1)
+// }
+
+ Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode
+ Method (_PIC, 1, NotSerialized) //PIC Flag and Interface Method
+ {
+ Store (Arg0, PICF)
+ }
+
+ OperationRegion (DEBG, SystemIO, 0x80, 0x01)
+ Field (DEBG, ByteAcc, Lock, Preserve)
+ {
+ DBG1, 8
+ }
+
+ OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04)
+ Field (EXTM, WordAcc, Lock, Preserve)
+ {
+ AMEM, 32
+ }
+
+ OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01)
+ Field (VGAM, ByteAcc, Lock, Preserve)
+ {
+ VGA1, 8
+ }
+
+ OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
+ Field (GRAM, ByteAcc, Lock, Preserve)
+ {
+ Offset (0x10),
+ FLG0, 8
+ }
+
+ OperationRegion (GSTS, SystemIO, 0xC028, 0x02)
+ Field (GSTS, ByteAcc, NoLock, Preserve)
+ {
+ , 4,
+ IRQR, 1
+ }
+
+ OperationRegion (Z007, SystemIO, 0x21, 0x01)
+ Field (Z007, ByteAcc, NoLock, Preserve)
+ {
+ Z008, 8
+ }
+
+ OperationRegion (Z009, SystemIO, 0xA1, 0x01)
+ Field (Z009, ByteAcc, NoLock, Preserve)
+ {
+ Z00A, 8
+ }
+
+ #include "northbridge/amd/amdfam10/amdfam10_util.asl"
+}
+++ /dev/null
-//
-// This file is part of the coreboot project.
-//
-// Copyright (C) 2007 Advanced Micro Devices, Inc.
-//
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; version 2 of the License.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program; if not, write to the Free Software
-// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-//
-
-//AMD8111
- Name (APIC, Package (0x04)
- {
- Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present
- Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11},
- Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12},
- Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13}
- })
-
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00},
- Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00},
- Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00},
- Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00}
- })
-
- Name (DNCG, Ones)
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LEqual (^DNCG, Ones)) {
- Store (DADD(\_SB.PCI0.SBDN, 0x0001ffff), Local0)
- // Update the Device Number according to SBDN
- Store(Local0, Index (DeRefOf (Index (PICM, 0)), 0))
- Store(Local0, Index (DeRefOf (Index (PICM, 1)), 0))
- Store(Local0, Index (DeRefOf (Index (PICM, 2)), 0))
- Store(Local0, Index (DeRefOf (Index (PICM, 3)), 0))
- Store(Local0, Index (DeRefOf (Index (APIC, 0)), 0))
- Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0))
- Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0))
- Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0))
- Store (0x00, ^DNCG)
- }
- If (LNot (PICF)) {Return (PICM)}
- Else {Return (APIC)}
- }
-
- Device (SBC3)
- {
- // acpi smbus it should be 0x00040003 if 8131 present
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
- }
- OperationRegion (PIRQ, PCI_Config, 0x56, 0x02)
- Field (PIRQ, ByteAcc, Lock, Preserve)
- {
- PIBA, 8,
- PIDC, 8
- }
-//
-// OperationRegion (TS3_, PCI_Config, 0xC4, 0x02)
-// Field (TS3_, DWordAcc, NoLock, Preserve)
-// {
-// PTS3, 16
-// }
-//
- }
-
- Device (HPET)
- {
- Name (HPT, 0x00)
- Name (_HID, EisaId ("PNP0103"))
- Name (_UID, 0x00)
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0F)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400)
- })
- Return (BUF0)
- }
- }
-
- Include ("amd8111_pic.asl")
-
- Include ("amd8111_isa.asl")
-
- Device (TP2P)
- {
- // 8111 P2P and it should 0x00030000 when 8131 present
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(\_SB.PCI0.SBDN, 0x00000000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x08, 0x03 }) }
- Else { Return (Package (0x02) { 0x08, 0x01 }) }
- }
-
- Device (USB0)
- {
- Name (_ADR, 0x00000000)
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) }
- Else { Return (Package (0x02) { 0x0F, 0x01 }) }
- }
- }
-
- Device (USB1)
- {
- Name (_ADR, 0x00000001)
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) }
- Else { Return (Package (0x02) { 0x0F, 0x01 }) }
- }
- }
-
- Name (APIC, Package (0x0C)
- {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, //USB
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 },
-
- Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, //Slot 4
- Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 },
-
- Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, //Slot 3
- Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 },
- Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 },
- Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 }
- })
-
- Name (PICM, Package (0x0C)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
-
- Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //Slot 4
- Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
-
- Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, //Slot 3
- Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }
- })
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
-
+++ /dev/null
-//
-// This file is part of the coreboot project.
-//
-// Copyright (C) 2007 Advanced Micro Devices, Inc.
-//
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; version 2 of the License.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program; if not, write to the Free Software
-// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-//
-
-//AMD8111 isa
-
- Device (ISA)
- {
- // lpc 0x00040000
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(\_SB.PCI0.SBDN, 0x00010000))
- }
-
- OperationRegion (PIRY, PCI_Config, 0x51, 0x02) // LPC Decode Registers
- Field (PIRY, ByteAcc, NoLock, Preserve)
- {
- Z000, 2, // Parallel Port Range
- , 1,
- ECP, 1, // ECP Enable
- FDC1, 1, // Floppy Drive Controller 1
- FDC2, 1, // Floppy Drive Controller 2
- Offset (0x01),
- Z001, 3, // Serial Port A Range
- SAEN, 1, // Serial Post A Enabled
- Z002, 3, // Serial Port B Range
- SBEN, 1 // Serial Post B Enabled
- }
-
- Device (PIC)
- {
- Name (_HID, EisaId ("PNP0000"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0020, 0x0020, 0x01, 0x02)
- IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02)
- IRQ (Edge, ActiveHigh, Exclusive) {2}
- })
- }
-
- Device (DMA1)
- {
- Name (_HID, EisaId ("PNP0200"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0000, 0x0000, 0x01, 0x10)
- IO (Decode16, 0x0080, 0x0080, 0x01, 0x10)
- IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20)
- DMA (Compatibility, NotBusMaster, Transfer16) {4}
- })
- }
-
- Device (TMR)
- {
- Name (_HID, EisaId ("PNP0100"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0040, 0x0040, 0x01, 0x04)
- IRQ (Edge, ActiveHigh, Exclusive) {0}
- })
- }
-
- Device (RTC)
- {
- Name (_HID, EisaId ("PNP0B00"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0070, 0x0070, 0x01, 0x06)
- IRQ (Edge, ActiveHigh, Exclusive) {8}
- })
- }
-
- Device (SPKR)
- {
- Name (_HID, EisaId ("PNP0800"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0061, 0x0061, 0x01, 0x01)
- })
- }
-
- Device (COPR)
- {
- Name (_HID, EisaId ("PNP0C04"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x10)
- IRQ (Edge, ActiveHigh, Exclusive) {13}
- })
- }
-
- Device (SYSR)
- {
- Name (_HID, EisaId ("PNP0C02"))
- Name (_UID, 0x00)
- Name (SYR1, ResourceTemplate ()
- {
- IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02) //report Thor NVRAM
- IO (Decode16, 0x1100, 0x117F, 0x01, 0x80) //report Thor NVRAM
- IO (Decode16, 0x1180, 0x11FF, 0x01, 0x80)
- IO (Decode16, 0x0010, 0x0010, 0x01, 0x10)
- IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E)
- IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C)
- IO (Decode16, 0x0062, 0x0062, 0x01, 0x02)
- IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B)
- IO (Decode16, 0x0076, 0x0076, 0x01, 0x0A)
- IO (Decode16, 0x0090, 0x0090, 0x01, 0x10)
- IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E)
- IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10)
- IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
- IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
- })
- Method (_CRS, 0, NotSerialized)
- {
- Return (SYR1)
- }
- }
-
- Device (MEM)
- {
- Name (_HID, EisaId ("PNP0C02"))
- Name (_UID, 0x01)
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF
- Memory32Fixed (ReadWrite, 0x000C0000, 0x00000000) // video BIOS c0000-c8404
- Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000) // I/O APIC
- Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM
- Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000) // Local APIC
- Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
- })
- // Read the Video Memory length
- CreateDWordField (BUF0, 0x14, CLEN)
- CreateDWordField (BUF0, 0x10, CBAS)
-
- ShiftLeft (VGA1, 0x09, Local0)
- Store (Local0, CLEN)
-
- Return (BUF0)
- }
- }
-
- Device (PS2M)
- {
- Name (_HID, EisaId ("PNP0F13"))
- Name (_CRS, ResourceTemplate ()
- {
- IRQNoFlags () {12}
- })
- Method (_STA, 0, NotSerialized)
- {
- And (FLG0, 0x04, Local0)
- If (LEqual (Local0, 0x04)) { Return (0x0F) }
- Else { Return (0x00) }
- }
- }
-
- Device (PS2K)
- {
- Name (_HID, EisaId ("PNP0303"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {1}
- })
- }
- Include ("superio.asl")
-
- }
-
+++ /dev/null
-//
-// This file is part of the coreboot project.
-//
-// Copyright (C) 2007 Advanced Micro Devices, Inc.
-//
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; version 2 of the License.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program; if not, write to the Free Software
-// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-//
-
-//AMD8111 pic LNKA B C D
-
- Device (LNKA)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x01)
- Method (_STA, 0, NotSerialized)
- {
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local0)
- If (LEqual (Local0, 0x00)) { Return (0x09) } //Disabled
- Else { Return (0x0B) } //Enabled
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {3,5,10,11}
- })
- Return (BUFA)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Store (0x01, Local3)
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
- Store (Local1, Local2)
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local1)
- }
-
- ShiftLeft (Local3, Local1, Local3)
- Not (Local3, Local3)
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {}
- })
- CreateByteField (BUFA, 0x01, IRA1)
- CreateByteField (BUFA, 0x02, IRA2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
- If (LNot (LEqual (Local1, 0x00)))
- { // Routing enable
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRA1)
- Store (Local4, IRA2)
- }
-
- Return (BUFA)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateByteField (Arg0, 0x01, IRA1)
- CreateByteField (Arg0, 0x02, IRA2)
- ShiftLeft (IRA2, 0x08, Local0)
- Or (Local0, IRA1, Local0)
- Store (0x00, Local1)
- ShiftRight (Local0, 0x01, Local0)
- While (LGreater (Local0, 0x00))
- {
- Increment (Local1)
- ShiftRight (Local0, 0x01, Local0)
- }
-
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
- Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
- }
- }
-
- Device (LNKB)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x02)
- Method (_STA, 0, NotSerialized)
- {
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local0)
- If (LEqual (Local0, 0x00)) { Return (0x09) }
- Else { Return (0x0B) }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFB, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {3,5,10,11}
- })
- Return (BUFB)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Store (0x01, Local3)
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- Store (Local1, Local2)
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local1)
- }
-
- ShiftLeft (Local3, Local1, Local3)
- Not (Local3, Local3)
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFB, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {}
- })
- CreateByteField (BUFB, 0x01, IRB1)
- CreateByteField (BUFB, 0x02, IRB2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- If (LNot (LEqual (Local1, 0x00)))
- {
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRB1)
- Store (Local4, IRB2)
- }
-
- Return (BUFB)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateByteField (Arg0, 0x01, IRB1)
- CreateByteField (Arg0, 0x02, IRB2)
- ShiftLeft (IRB2, 0x08, Local0)
- Or (Local0, IRB1, Local0)
- Store (0x00, Local1)
- ShiftRight (Local0, 0x01, Local0)
- While (LGreater (Local0, 0x00))
- {
- Increment (Local1)
- ShiftRight (Local0, 0x01, Local0)
- }
-
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
- ShiftLeft (Local1, 0x04, Local1)
- Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
- }
- }
-
- Device (LNKC)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x03)
- Method (_STA, 0, NotSerialized)
- {
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local0)
- If (LEqual (Local0, 0x00)) { Return (0x09) }
- Else { Return (0x0B) }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {3,5,10,11}
- })
- Return (BUFA)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Store (0x01, Local3)
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
- Store (Local1, Local2)
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local1)
- }
-
- ShiftLeft (Local3, Local1, Local3)
- Not (Local3, Local3)
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {}
- })
- CreateByteField (BUFA, 0x01, IRA1)
- CreateByteField (BUFA, 0x02, IRA2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
- If (LNot (LEqual (Local1, 0x00)))
- {
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRA1)
- Store (Local4, IRA2)
- }
-
- Return (BUFA)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateByteField (Arg0, 0x01, IRA1)
- CreateByteField (Arg0, 0x02, IRA2)
- ShiftLeft (IRA2, 0x08, Local0)
- Or (Local0, IRA1, Local0)
- Store (0x00, Local1)
- ShiftRight (Local0, 0x01, Local0)
- While (LGreater (Local0, 0x00))
- {
- Increment (Local1)
- ShiftRight (Local0, 0x01, Local0)
- }
-
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
- Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
- }
- }
-
- Device (LNKD)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x04)
- Method (_STA, 0, NotSerialized)
- {
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local0)
- If (LEqual (Local0, 0x00)) { Return (0x09) }
- Else { Return (0x0B) }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFB, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {3,5,10,11}
- })
- Return (BUFB)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Store (0x01, Local3)
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- Store (Local1, Local2)
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local1)
- }
-
- ShiftLeft (Local3, Local1, Local3)
- Not (Local3, Local3)
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFB, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {}
- })
- CreateByteField (BUFB, 0x01, IRB1)
- CreateByteField (BUFB, 0x02, IRB2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- If (LNot (LEqual (Local1, 0x00)))
- {
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRB1)
- Store (Local4, IRB2)
- }
-
- Return (BUFB)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateByteField (Arg0, 0x01, IRB1)
- CreateByteField (Arg0, 0x02, IRB2)
- ShiftLeft (IRB2, 0x08, Local0)
- Or (Local0, IRB1, Local0)
- Store (0x00, Local1)
- ShiftRight (Local0, 0x01, Local0)
- While (LGreater (Local0, 0x00))
- {
- Increment (Local1)
- ShiftRight (Local0, 0x01, Local0)
- }
-
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
- ShiftLeft (Local1, 0x04, Local1)
- Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
- }
- }
-
-
+++ /dev/null
-//
-// This file is part of the coreboot project.
-//
-// Copyright (C) 2007 Advanced Micro Devices, Inc.
-//
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; version 2 of the License.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program; if not, write to the Free Software
-// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-//
- Device (PG0A)
- {
- // 8132 pcix bridge
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00000000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
- Else { Return (Package (0x02) { 0x29, 0x01 }) }
- }
-
- Name (APIC, Package (0x04)
- {
- // Slot A - PIRQ BCDA
- Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0018 }, //Slot 2
- Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x0019 },
- Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x001A },
- Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x001B },
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2
- Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
- })
-
- Name (DNCG, Ones)
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LEqual (^DNCG, Ones))
- {
- Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8
- Store (0x00, Local1)
- While (LLess (Local1, 0x04))
- {
- // Update the GSI according to HCIN
- Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
- Add(Local2, Local0, Local0)
- Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
- Increment (Local1)
- }
- Store (0x00, ^DNCG)
- }
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
-
- Device (PG0B)
- {
- // 8132 pcix bridge 2
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00010000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
- Else { Return (Package (0x02) { 0x22, 0x01 }) }
- }
-
- Name (APIC, Package (0x04)
- {
- // Slot A - PIRQ ABCD
- Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x001F },// Slot 1
- Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x0020 },
- Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x0021 },
- Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x0022 }
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
- Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
- })
-
- Name (DNCG, Ones)
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LEqual (^DNCG, Ones))
- {
- Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8
- Store (0x00, Local1)
- While (LLess (Local1, 0x04))
- {
- // Update the GSI according to HCIN
- Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
- Add(Local2, Local0, Local0)
- Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
- Increment (Local1)
- }
-
- Store (0x00, ^DNCG)
-
- }
-
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
+++ /dev/null
-//
-// This file is part of the coreboot project.
-//
-// Copyright (C) 2007 Advanced Micro Devices, Inc.
-//
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; version 2 of the License.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program; if not, write to the Free Software
-// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-//
-
- Device (PG0A)
- {
- // 8132 pcix bridge
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00000000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
- Else { Return (Package (0x02) { 0x29, 0x01 }) }
- }
-
- Name (APIC, Package (0x14)
- {
- // Slot A - PIRQ BCDA
- Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 2
- Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A },
- Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B },
- Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 },
-
- //Cypress Slot A - PIRQ BCDA
- Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x19 }, //?
- Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1A },
- Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x1B },
- Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x18 },
-
- //Cypress Slot B - PIRQ CDAB
- Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1A }, //?
- Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B },
- Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x18 },
- Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x19 },
-
- //Cypress Slot C - PIRQ DABC
- Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x1B }, //?
- Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x18 },
- Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x19 },
- Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x1A },
-
- //Cypress Slot D - PIRQ ABCD
- Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x18 }, //?
- Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x19 },
- Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x1A },
- Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x1B }
- })
- Name (PICM, Package (0x14)
- {
- Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 2
- Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
-
- Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
-
- Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
-
- Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
-
- Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0006FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
- })
- Method (_PRT, 0, NotSerialized)
- {
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
-
- Device (PG0B)
- {
- // 8132 pcix bridge 2
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00010000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
- Else { Return (Package (0x02) { 0x22, 0x01 }) }
- }
-
- Name (APIC, Package (0x04)
- {
- // Slot A - PIRQ ABCD
- Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x1F },// Slot 1
- Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x20 },
- Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x21 },
- Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x22 }
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
- Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
- })
- Method (_PRT, 0, NotSerialized)
- {
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
+++ /dev/null
-//
-// This file is part of the coreboot project.
-//
-// Copyright (C) 2007 Advanced Micro Devices, Inc.
-//
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; version 2 of the License.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program; if not, write to the Free Software
-// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-//
-
- Device (PG0A)
- {
- // 8132 pcix bridge
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00000000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
- Else { Return (Package (0x02) { 0x29, 0x01 }) }
- }
-
- Name (APIC, Package (0x10)
- {
- // Slot 1 - PIRQ ABCD
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 },
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B },
- // Slot 2 - PIRQ BCDA
- Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0019 },
- Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x001A },
- Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x001B },
- Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x0018 },
- // Slot 3 - PIRQ CDAB
- Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x001A },
- Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x001B },
- Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x0018 },
- Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x0019 },
- // Slot 4 - PIRQ DABC
- Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x001B },
- Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x0018 },
- Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x0019 },
- Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x001A },
-
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
-//
-// Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 2
-// Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
-// Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
-// Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
-//
-// Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },//Slot 2
-// Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
-// Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
-// Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
-//
-// Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },//Slot 2
-// Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
-// Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
-// Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
-//
- })
-
- Name (DNCG, Ones)
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LEqual (^DNCG, Ones)) {
- Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14
- Store (0x00, Local1)
- While (LLess (Local1, 0x10))
- {
- // Update the GSI according to HCIN
- Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
- Add(Local2, Local0, Local0)
- Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
- Increment (Local1)
- }
-
- Store (0x00, ^DNCG)
-
- }
-
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
-
- Device (PG0B)
- {
- // 8132 pcix bridge 2
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00010000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
- Else { Return (Package (0x02) { 0x22, 0x01 }) }
- }
-
- Name (APIC, Package (0x10)
- {
- // Slot A - PIRQ ABCD
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 },
- // Slot A - PIRQ BCDA
- Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0020 },// Slot 1
- Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x0021 },
- Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x0022 },
- Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x001F },
- // Slot A - PIRQ CDAB
- Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x0021 },// Slot 1
- Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x0022 },
- Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x001F },
- Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x0020 },
- // Slot A - PIRQ DABC
- Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x0022 },// Slot 1
- Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x001F },
- Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x0020 },
- Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x0021 },
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
-
-// Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 1
-// Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
-// Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
-// Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
-//
-// Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },//Slot 1
-// Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
-// Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
-// Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
-//
-// Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },//Slot 1
-// Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
-// Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
-// Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
-//
- })
-
- Name (DNCG, Ones)
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LEqual (^DNCG, Ones)) {
- Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14
- Store (0x00, Local1)
- While (LLess (Local1, 0x10))
- {
- // Update the GSI according to HCIN
- Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
- Add(Local2, Local0, Local0)
- Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
- Increment (Local1)
- }
-
- Store (0x00, ^DNCG)
-
- }
-
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
+++ /dev/null
-//
-// This file is part of the coreboot project.
-//
-// Copyright (C) 2007 Advanced Micro Devices, Inc.
-//
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; version 2 of the License.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program; if not, write to the Free Software
-// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-//
-
-// AMD8151
- Device (AGPB)
- {
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00010000))
- }
-
- Name (APIC, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 },
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 }
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
- })
- Method (_PRT, 0, NotSerialized)
- {
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
-
+++ /dev/null
-//
-// This file is part of the coreboot project.
-//
-// Copyright (C) 2007 Advanced Micro Devices, Inc.
-//
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; version 2 of the License.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program; if not, write to the Free Software
-// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-//
-DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
-{
-
-// Scope (_PR)
-// {
-// Processor (CPU0, 0x00, 0x0000C010, 0x06) {}
-// Processor (CPU1, 0x01, 0x00000000, 0x00) {}
-// Processor (CPU2, 0x02, 0x00000000, 0x00) {}
-// Processor (CPU3, 0x03, 0x00000000, 0x00) {}
-// }
-
- Method (FWSO, 0, NotSerialized) { }
-
- Name (_S0, Package (0x04) { 0x00, 0x00, 0x00, 0x00 })
- Name (_S1, Package (0x04) { 0x01, 0x01, 0x01, 0x01 })
- Name (_S3, Package (0x04) { 0x05, 0x05, 0x05, 0x05 })
- Name (_S5, Package (0x04) { 0x07, 0x07, 0x07, 0x07 })
-
- Scope (_SB)
- {
- Device (PCI0)
- {
- // BUS0 root bus
- External (BUSN)
- External (MMIO)
- External (PCIO)
- External (SBLK)
- External (TOM1)
- External (HCLK)
- External (SBDN)
- External (HCDN)
- External (CBST)
- External (CBB)
- External (CBS2)
- External (CBB2)
-
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00000000)
- Name (_UID, 0x01)
-
- Name (HCIN, 0x00) // HC1
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh
- IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h
- IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h
-
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x8100, // Address Range Minimum
- 0xFFFF, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x7F00,,,
- , TypeStatic) //8100h-FFFFh
-
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, // Address Space Granularity
- 0x000C0000, // Address Range Minimum
- 0x00000000, // Address Range Maximum
- 0x00000000, // Address Translation Offset
- 0x00000000,,,
- , AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh
-
- Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF
-
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x03AF, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x03B0,,,
- , TypeStatic) //0-CF7h
-
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x03E0, // Address Range Minimum
- 0x0CF7, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0918,,,
- , TypeStatic) //0-CF7h
- })
- \_SB.OSTP ()
- CreateDWordField (BUF0, 0x3E, VLEN)
- CreateDWordField (BUF0, 0x36, VMAX)
- CreateDWordField (BUF0, 0x32, VMIN)
- ShiftLeft (VGA1, 0x09, Local0)
- Add (VMIN, Local0, VMAX)
- Decrement (VMAX)
- Store (Local0, VLEN)
- Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
- Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
- Return (Local3)
- }
-
- Include ("pci0_hc.asl")
-
- }
- Device (PCI1)
- {
- Name (_HID, "PNP0A03")
- Name (_ADR, 0x00000000)
- Name (_UID, 0x02)
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.PCI0.CBST)
- }
- Method (_BBN, 0, NotSerialized)
- {
- Return (\_SB.PCI0.CBB) // 0 or 0xff
- }
-
- }
- Device (PCI2)
- {
- Name (_HID, "PNP0A03")
- Name (_ADR, 0x00000000)
- Name (_UID, 0x02)
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.PCI0.CBS2)
- }
- Method (_BBN, 0, NotSerialized)
- {
- Return (\_SB.PCI0.CBB2)// 0xfe
- }
- }
- }
-
- Scope (_GPE)
- {
- Method (_L08, 0, NotSerialized)
- {
- Notify (\_SB.PCI0, 0x02) //PME# Wakeup
- }
-
- Method (_L0F, 0, NotSerialized)
- {
- Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup
- }
-
- Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B
- {
- Notify (\_SB.PCI0.PG0B, 0x02)
- }
-
- Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A
- {
- Notify (\_SB.PCI0.PG0A, 0x02)
- }
- }
-
- Method (_PTS, 1, NotSerialized)
- {
- Or (Arg0, 0xF0, Local0)
- Store (Local0, DBG1)
- }
-//
-// Method (_WAK, 1, NotSerialized)
-// {
-// Or (Arg0, 0xE0, Local0)
-// Store (Local0, DBG1)
-// }
-
- Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode
- Method (_PIC, 1, NotSerialized) //PIC Flag and Interface Method
- {
- Store (Arg0, PICF)
- }
-
- OperationRegion (DEBG, SystemIO, 0x80, 0x01)
- Field (DEBG, ByteAcc, Lock, Preserve)
- {
- DBG1, 8
- }
-
- OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04)
- Field (EXTM, WordAcc, Lock, Preserve)
- {
- AMEM, 32
- }
-
- OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01)
- Field (VGAM, ByteAcc, Lock, Preserve)
- {
- VGA1, 8
- }
-
- OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
- Field (GRAM, ByteAcc, Lock, Preserve)
- {
- Offset (0x10),
- FLG0, 8
- }
-
- OperationRegion (GSTS, SystemIO, 0xC028, 0x02)
- Field (GSTS, ByteAcc, NoLock, Preserve)
- {
- , 4,
- IRQR, 1
- }
-
- OperationRegion (Z007, SystemIO, 0x21, 0x01)
- Field (Z007, ByteAcc, NoLock, Preserve)
- {
- Z008, 8
- }
-
- OperationRegion (Z009, SystemIO, 0xA1, 0x01)
- Field (Z009, ByteAcc, NoLock, Preserve)
- {
- Z00A, 8
- }
-
- Include ("../../../../../src/northbridge/amd/amdfam10/amdfam10_util.asl")
-}
+++ /dev/null
-//
-// This file is part of the coreboot project.
-//
-// Copyright (C) 2007 Advanced Micro Devices, Inc.
-//
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; version 2 of the License.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program; if not, write to the Free Software
-// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-//
-
- Device (HTXA)
- {
- // HTX
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00000000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
- Else { Return (Package (0x02) { 0x29, 0x01 }) }
- }
-
- }
-
+++ /dev/null
-//
-// This file is part of the coreboot project.
-//
-// Copyright (C) 2007 Advanced Micro Devices, Inc.
-//
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; version 2 of the License.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program; if not, write to the Free Software
-// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-//
- Include ("amd8111.asl") //real SB at first
- Include ("amd8132.asl")
+++ /dev/null
-//
-// This file is part of the coreboot project.
-//
-// Copyright (C) 2007 Advanced Micro Devices, Inc.
-//
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; version 2 of the License.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program; if not, write to the Free Software
-// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-//
-DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
-{
- Scope (_SB)
- {
- External (DADD, MethodObj)
- External (GHCE, MethodObj)
- External (GHCN, MethodObj)
- External (GHCL, MethodObj)
- External (GHCD, MethodObj)
- External (GNUS, MethodObj)
- External (GIOR, MethodObj)
- External (GMEM, MethodObj)
- External (GWBN, MethodObj)
- External (GBUS, MethodObj)
-
- External (PICF)
-
- External (\_SB.PCI0.LNKA, DeviceObj)
- External (\_SB.PCI0.LNKB, DeviceObj)
- External (\_SB.PCI0.LNKC, DeviceObj)
- External (\_SB.PCI0.LNKD, DeviceObj)
-
- Device (PCIX)
- {
-
- // BUS ? Second HT Chain
- Name (HCIN, 0xcc) // HC2 0x01
-
- Name (_UID, 0xdd) // HC 0x03
-
- Name (_HID, "PNP0A03")
-
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0
- {
- Return (DADD(GHCN(HCIN), 0x00000000))
- }
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.GHCE(HCIN))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () { })
- Store( GHCN(HCIN), Local4)
- Store( GHCL(HCIN), Local5)
-
- Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
- Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
- Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
- Return (Local3)
- }
-
- Include ("pci2_hc.asl")
- }
- }
-
-}
-
+++ /dev/null
-//
-// This file is part of the coreboot project.
-//
-// Copyright (C) 2007 Advanced Micro Devices, Inc.
-//
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; version 2 of the License.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program; if not, write to the Free Software
-// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-//
-
- Include ("amd8132_2.asl")
+++ /dev/null
-//
-// This file is part of the coreboot project.
-//
-// Copyright (C) 2007 Advanced Micro Devices, Inc.
-//
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; version 2 of the License.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program; if not, write to the Free Software
-// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-//
-DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
-{
- Scope (_SB)
- {
- External (DADD, MethodObj)
- External (GHCE, MethodObj)
- External (GHCN, MethodObj)
- External (GHCL, MethodObj)
- External (GHCD, MethodObj)
- External (GNUS, MethodObj)
- External (GIOR, MethodObj)
- External (GMEM, MethodObj)
- External (GWBN, MethodObj)
- External (GBUS, MethodObj)
-
- External (PICF)
-
- External (\_SB.PCI0.LNKA, DeviceObj)
- External (\_SB.PCI0.LNKB, DeviceObj)
- External (\_SB.PCI0.LNKC, DeviceObj)
- External (\_SB.PCI0.LNKD, DeviceObj)
-
- Device (PCIX)
- {
-
- // BUS ? Second HT Chain
- Name (HCIN, 0xcc) // HC2 0x01
-
- Name (_UID, 0xdd) // HC 0x03
-
- Name (_HID, "PNP0A03")
-
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0
- {
- Return (DADD(GHCN(HCIN), 0x00000000))
- }
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.GHCE(HCIN))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () { })
- Store( GHCN(HCIN), Local4)
- Store( GHCL(HCIN), Local5)
-
- Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
- Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
- Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
- Return (Local3)
- }
-
- Include ("pci3_hc.asl")
- }
- }
-
-}
-
+++ /dev/null
-//
-// This file is part of the coreboot project.
-//
-// Copyright (C) 2007 Advanced Micro Devices, Inc.
-//
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; version 2 of the License.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program; if not, write to the Free Software
-// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-//
-
- Include ("amd8151.asl")
+++ /dev/null
-//
-// This file is part of the coreboot project.
-//
-// Copyright (C) 2007 Advanced Micro Devices, Inc.
-//
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; version 2 of the License.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program; if not, write to the Free Software
-// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-//
-DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
-{
- Scope (_SB)
- {
- External (DADD, MethodObj)
- External (GHCE, MethodObj)
- External (GHCN, MethodObj)
- External (GHCL, MethodObj)
- External (GHCD, MethodObj)
- External (GNUS, MethodObj)
- External (GIOR, MethodObj)
- External (GMEM, MethodObj)
- External (GWBN, MethodObj)
- External (GBUS, MethodObj)
-
- External (PICF)
-
- External (\_SB.PCI0.LNKA, DeviceObj)
- External (\_SB.PCI0.LNKB, DeviceObj)
- External (\_SB.PCI0.LNKC, DeviceObj)
- External (\_SB.PCI0.LNKD, DeviceObj)
-
- Device (PCIX)
- {
-
- // BUS ? Second HT Chain
- Name (HCIN, 0xcc) // HC2 0x01
-
- Name (_UID, 0xdd) // HC 0x03
-
- Name (_HID, "PNP0A03")
-
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0
- {
- Return (DADD(GHCN(HCIN), 0x00000000))
- }
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.GHCE(HCIN))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () { })
- Store( GHCN(HCIN), Local4)
- Store( GHCL(HCIN), Local5)
-
- Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
- Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
- Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
- Return (Local3)
- }
-
- Include ("pci4_hc.asl")
- }
- }
-
-}
-
+++ /dev/null
-//
-// This file is part of the coreboot project.
-//
-// Copyright (C) 2007 Advanced Micro Devices, Inc.
-//
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; version 2 of the License.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program; if not, write to the Free Software
-// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-//
-
- Include ("amd8131_2.asl")
+++ /dev/null
-//
-// This file is part of the coreboot project.
-//
-// Copyright (C) 2007 Advanced Micro Devices, Inc.
-//
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; version 2 of the License.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program; if not, write to the Free Software
-// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-//
-
-DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
-{
- Scope (_SB)
- {
- External (DADD, MethodObj)
- External (GHCE, MethodObj)
- External (GHCN, MethodObj)
- External (GHCL, MethodObj)
- External (GHCD, MethodObj)
- External (GNUS, MethodObj)
- External (GIOR, MethodObj)
- External (GMEM, MethodObj)
- External (GWBN, MethodObj)
- External (GBUS, MethodObj)
-
- External (PICF)
-
- External (\_SB.PCI0.LNKA, DeviceObj)
- External (\_SB.PCI0.LNKB, DeviceObj)
- External (\_SB.PCI0.LNKC, DeviceObj)
- External (\_SB.PCI0.LNKD, DeviceObj)
-
- Device (PCIX)
- {
-
- // BUS ? Second HT Chain
- Name (HCIN, 0xcc) // HC2 0x01
-
- Name (_UID, 0xdd) // HC 0x03
-
- Name (_HID, "PNP0A03")
-
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0
- {
- Return (DADD(GHCN(HCIN), 0x00000000))
- }
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.GHCE(HCIN))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () { })
- Store( GHCN(HCIN), Local4)
- Store( GHCL(HCIN), Local5)
-
- Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
- Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
- Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
- Return (Local3)
- }
-
- Include ("pci5_hc.asl")
- }
- }
-
-}
-
+++ /dev/null
-//
-// This file is part of the coreboot project.
-//
-// Copyright (C) 2007 Advanced Micro Devices, Inc.
-//
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; version 2 of the License.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program; if not, write to the Free Software
-// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-//
-
- Include ("htx_no_ioapic.asl")
+++ /dev/null
-//
-// This file is part of the coreboot project.
-//
-// Copyright (C) 2007 Advanced Micro Devices, Inc.
-//
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; version 2 of the License.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program; if not, write to the Free Software
-// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-//
-
-// Include ("w83627hf.asl")
--- /dev/null
+//
+// This file is part of the coreboot project.
+//
+// Copyright (C) 2007 Advanced Micro Devices, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; version 2 of the License.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+//
+DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
+{
+ Scope (_SB)
+ {
+ External (DADD, MethodObj)
+ External (GHCE, MethodObj)
+ External (GHCN, MethodObj)
+ External (GHCL, MethodObj)
+ External (GHCD, MethodObj)
+ External (GNUS, MethodObj)
+ External (GIOR, MethodObj)
+ External (GMEM, MethodObj)
+ External (GWBN, MethodObj)
+ External (GBUS, MethodObj)
+
+ External (PICF)
+
+ External (\_SB.PCI0.LNKA, DeviceObj)
+ External (\_SB.PCI0.LNKB, DeviceObj)
+ External (\_SB.PCI0.LNKC, DeviceObj)
+ External (\_SB.PCI0.LNKD, DeviceObj)
+
+ Device (PCIX)
+ {
+
+ // BUS ? Second HT Chain
+ Name (HCIN, 0xcc) // HC2 0x01
+
+ Name (_UID, 0xdd) // HC 0x03
+
+ Name (_HID, "PNP0A03")
+
+ Method (_ADR, 0, NotSerialized) //Fake bus should be 0
+ {
+ Return (DADD(GHCN(HCIN), 0x00000000))
+ }
+
+ Method (_BBN, 0, NotSerialized)
+ {
+ Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (\_SB.GHCE(HCIN))
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate () { })
+ Store( GHCN(HCIN), Local4)
+ Store( GHCL(HCIN), Local5)
+
+ Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
+ Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
+ Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
+ Return (Local3)
+ }
+
+ #include "acpi/pci2_hc.asl"
+ }
+ }
+
+}
+
--- /dev/null
+//
+// This file is part of the coreboot project.
+//
+// Copyright (C) 2007 Advanced Micro Devices, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; version 2 of the License.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+//
+DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
+{
+ Scope (_SB)
+ {
+ External (DADD, MethodObj)
+ External (GHCE, MethodObj)
+ External (GHCN, MethodObj)
+ External (GHCL, MethodObj)
+ External (GHCD, MethodObj)
+ External (GNUS, MethodObj)
+ External (GIOR, MethodObj)
+ External (GMEM, MethodObj)
+ External (GWBN, MethodObj)
+ External (GBUS, MethodObj)
+
+ External (PICF)
+
+ External (\_SB.PCI0.LNKA, DeviceObj)
+ External (\_SB.PCI0.LNKB, DeviceObj)
+ External (\_SB.PCI0.LNKC, DeviceObj)
+ External (\_SB.PCI0.LNKD, DeviceObj)
+
+ Device (PCIX)
+ {
+
+ // BUS ? Second HT Chain
+ Name (HCIN, 0xcc) // HC2 0x01
+
+ Name (_UID, 0xdd) // HC 0x03
+
+ Name (_HID, "PNP0A03")
+
+ Method (_ADR, 0, NotSerialized) //Fake bus should be 0
+ {
+ Return (DADD(GHCN(HCIN), 0x00000000))
+ }
+
+ Method (_BBN, 0, NotSerialized)
+ {
+ Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (\_SB.GHCE(HCIN))
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate () { })
+ Store( GHCN(HCIN), Local4)
+ Store( GHCL(HCIN), Local5)
+
+ Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
+ Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
+ Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
+ Return (Local3)
+ }
+
+ #include "acpi/pci3_hc.asl"
+ }
+ }
+
+}
+
--- /dev/null
+//
+// This file is part of the coreboot project.
+//
+// Copyright (C) 2007 Advanced Micro Devices, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; version 2 of the License.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+//
+DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
+{
+ Scope (_SB)
+ {
+ External (DADD, MethodObj)
+ External (GHCE, MethodObj)
+ External (GHCN, MethodObj)
+ External (GHCL, MethodObj)
+ External (GHCD, MethodObj)
+ External (GNUS, MethodObj)
+ External (GIOR, MethodObj)
+ External (GMEM, MethodObj)
+ External (GWBN, MethodObj)
+ External (GBUS, MethodObj)
+
+ External (PICF)
+
+ External (\_SB.PCI0.LNKA, DeviceObj)
+ External (\_SB.PCI0.LNKB, DeviceObj)
+ External (\_SB.PCI0.LNKC, DeviceObj)
+ External (\_SB.PCI0.LNKD, DeviceObj)
+
+ Device (PCIX)
+ {
+
+ // BUS ? Second HT Chain
+ Name (HCIN, 0xcc) // HC2 0x01
+
+ Name (_UID, 0xdd) // HC 0x03
+
+ Name (_HID, "PNP0A03")
+
+ Method (_ADR, 0, NotSerialized) //Fake bus should be 0
+ {
+ Return (DADD(GHCN(HCIN), 0x00000000))
+ }
+
+ Method (_BBN, 0, NotSerialized)
+ {
+ Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (\_SB.GHCE(HCIN))
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate () { })
+ Store( GHCN(HCIN), Local4)
+ Store( GHCL(HCIN), Local5)
+
+ Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
+ Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
+ Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
+ Return (Local3)
+ }
+
+ #include "acpi/pci4_hc.asl"
+ }
+ }
+
+}
+
--- /dev/null
+//
+// This file is part of the coreboot project.
+//
+// Copyright (C) 2007 Advanced Micro Devices, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; version 2 of the License.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+//
+
+DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
+{
+ Scope (_SB)
+ {
+ External (DADD, MethodObj)
+ External (GHCE, MethodObj)
+ External (GHCN, MethodObj)
+ External (GHCL, MethodObj)
+ External (GHCD, MethodObj)
+ External (GNUS, MethodObj)
+ External (GIOR, MethodObj)
+ External (GMEM, MethodObj)
+ External (GWBN, MethodObj)
+ External (GBUS, MethodObj)
+
+ External (PICF)
+
+ External (\_SB.PCI0.LNKA, DeviceObj)
+ External (\_SB.PCI0.LNKB, DeviceObj)
+ External (\_SB.PCI0.LNKC, DeviceObj)
+ External (\_SB.PCI0.LNKD, DeviceObj)
+
+ Device (PCIX)
+ {
+
+ // BUS ? Second HT Chain
+ Name (HCIN, 0xcc) // HC2 0x01
+
+ Name (_UID, 0xdd) // HC 0x03
+
+ Name (_HID, "PNP0A03")
+
+ Method (_ADR, 0, NotSerialized) //Fake bus should be 0
+ {
+ Return (DADD(GHCN(HCIN), 0x00000000))
+ }
+
+ Method (_BBN, 0, NotSerialized)
+ {
+ Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (\_SB.GHCE(HCIN))
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate () { })
+ Store( GHCN(HCIN), Local4)
+ Store( GHCL(HCIN), Local5)
+
+ Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
+ Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
+ Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
+ Return (Local3)
+ }
+
+ #include "acpi/pci5_hc.asl"
+ }
+ }
+
+}
+
ifdef POST_EVALUATION
-$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
- iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
- mv dsdt.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
-$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl
- iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl
- perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex
- mv pci2.hex ssdt2.c
-
-$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl"
- iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/
- perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex
- mv pci3.hex ssdt3.c
-
-$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl"
- iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl
- perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex
- mv pci4.hex ssdt4.c
-
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
ifdef POST_EVALUATION
-$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
- iasl -p $(obj)/dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
- mv $(obj)/dsdt.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
ifdef POST_EVALUATION
-$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
- iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
- mv dsdt.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
{
- Include ("../../../../src/northbridge/amd/amdk8/amdk8_util.asl")
+ #include "northbridge/amd/amdk8/amdk8_util.asl"
/* For now only define 2 power states:
* - S0 which is fully on
ifdef POST_EVALUATION
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
-$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
- iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
- mv dsdt.hex $@
-
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
ifdef POST_EVALUATION
-$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
- iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
- mv dsdt.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
$(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c -o $@
DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
{
- Include ("../../../../src/northbridge/amd/amdk8/amdk8_util.asl")
+ #include "northbridge/amd/amdk8/amdk8_util.asl"
/* For now only define 2 power states:
* - S0 which is fully on
ifdef POST_EVALUATION
-$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
- $(CPP) -D__ACPI__ -P $(CPPFLAGS) -include $(obj)/config.h -I$(src)/mainboard/$(MAINBOARDDIR) $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl -o $(obj)/dsdt.asl
- iasl -p $(obj)/dsdt -tc $(obj)/dsdt.asl
- mv $(obj)/dsdt.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
ifdef POST_EVALUATION
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.dsl
- iasl -p $(obj)/mainboard/$(MAINBOARDDIR)/dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.dsl
- mv $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+DefinitionBlock ("DSDT", "DSDT", 1, "EAGLE", "COREBOOT", 0x0000001)
+{
+ Scope (\_PR)
+ {
+ Processor (CPU1, 0x01, 0x00000810, 0x06)
+ {
+ OperationRegion (STBL, SystemMemory, 0xFFFF0000, 0xFFFF)
+ Name (NCPU, 0x80)
+ Name (TYPE, 0x80000000)
+ Name (HNDL, 0x80000000)
+ Name (CFGD, 0x80000000)
+ Name (TBLD, 0x80)
+ Method (_PDC, 1, NotSerialized)
+ {
+ }
+ }
+ }
+
+ Scope (\_PR)
+ {
+ Processor (CPU2, 0x02, 0x00000000, 0x00)
+ {
+ OperationRegion (STBL, SystemMemory, 0xFFFF0000, 0xFFFF)
+ Name (NCPU, 0x80)
+ Name (TYPE, 0x80000000)
+ Name (HNDL, 0x80000000)
+ Name (CFGD, 0x80000000)
+ Name (TBLD, 0x80)
+ Method (_PDC, 1, NotSerialized)
+ {
+ }
+ }
+ }
+
+ /* For now only define 2 power states:
+ * - S0 which is fully on
+ * - S5 which is soft off
+ * Any others would involve declaring the wake up methods.
+ */
+ Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
+ Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
+
+ Name (PICM, 0x00)
+ Method (_PIC, 1, NotSerialized)
+ {
+ Store (Arg0, PICM)
+ }
+
+ /* System bus */
+ Scope (\_SB)
+ {
+ /* Routing PCI0 */
+ Name (PR00, Package (0x0E)
+ {
+ Package (0x04){0x0001FFFF,0x00,LNKA,0x00}, /* EDMA INTA# */
+ Package (0x04){0x0002FFFF,0x00,LNKA,0x00}, /* PCIe port A */
+ Package (0x04){0x0002FFFF,0x01,LNKB,0x00},
+ Package (0x04){0x0002FFFF,0x02,LNKC,0x00},
+ Package (0x04){0x0002FFFF,0x03,LNKD,0x00},
+ Package (0x04){0x0003FFFF,0x00,LNKA,0x00}, /* PCIe port A1 */
+ Package (0x04){0x0003FFFF,0x01,LNKB,0x00},
+ Package (0x04){0x0003FFFF,0x02,LNKC,0x00},
+ Package (0x04){0x0003FFFF,0x03,LNKD,0x00},
+ Package (0x04){0x001CFFFF,0x00,LNKE,0x00}, /* PCIe port B */
+ Package (0x04){0x001DFFFF,0x00,LNKH,0x00}, /* UHCI/EHCI INTA# */
+ Package (0x04){0x001DFFFF,0x01,LNKD,0x00}, /* UHCI INTB# */
+ Package (0x04){0x001FFFFF,0x01,LNKD,0x00}, /* SATA/SMBUS INTB# */
+ Package (0x04){0x001FFFFF,0x03,LNKA,0x00} /* CHAP INTD# */
+ })
+ Name (AR00, Package (0x0E)
+ {
+ Package (0x04){0x0001FFFF,0x00,0x00,0x10}, /* EDMA INTA# */
+ Package (0x04){0x0002FFFF,0x00,0x00,0x10}, /* PCIe port A0 */
+ Package (0x04){0x0002FFFF,0x01,0x00,0x11},
+ Package (0x04){0x0002FFFF,0x02,0x00,0x12},
+ Package (0x04){0x0002FFFF,0x03,0x00,0x13},
+ Package (0x04){0x0003FFFF,0x00,0x00,0x10}, /* PCIe port A1 */
+ Package (0x04){0x0003FFFF,0x01,0x00,0x11},
+ Package (0x04){0x0003FFFF,0x02,0x00,0x12},
+ Package (0x04){0x0003FFFF,0x03,0x00,0x13},
+ Package (0x04){0x001CFFFF,0x00,0x00,0x14}, /* PCIe port B */
+ Package (0x04){0x001DFFFF,0x00,0x00,0x17}, /* UHCI/EHCI INTA# */
+ Package (0x04){0x001DFFFF,0x01,0x00,0x13}, /* UHCI INTB# */
+ Package (0x04){0x001FFFFF,0x01,0x00,0x13}, /* SATA/SMBUS INTB# */
+ Package (0x04){0x001FFFFF,0x0D,0x00,0x10} /* CHAP INTD# */
+ })
+ /* Routing PCIe Port A */
+ Name (PR0A, Package (0x04)
+ {
+ Package (0x04){0xFFFF,0x00,LNKA,0x00},
+ Package (0x04){0xFFFF,0x01,LNKB,0x00},
+ Package (0x04){0xFFFF,0x02,LNKC,0x00},
+ Package (0x04){0xFFFF,0x03,LNKD,0x00}
+ })
+ Name (AR0A, Package (0x04)
+ {
+ Package (0x04){0xFFFF,0x00,0x00,0x10},
+ Package (0x04){0xFFFF,0x01,0x00,0x11},
+ Package (0x04){0xFFFF,0x02,0x00,0x12},
+ Package (0x04){0xFFFF,0x03,0x00,0x13}
+ })
+ /* Routing PCIe Port B */
+ Name (PR0B, Package (0x04)
+ {
+ Package (0x04){0xFFFF,0x00,LNKA,0x00},
+ Package (0x04){0xFFFF,0x01,LNKB,0x00},
+ Package (0x04){0xFFFF,0x02,LNKC,0x00},
+ Package (0x04){0xFFFF,0x03,LNKD,0x00}
+ })
+ Name (AR0B, Package (0x04)
+ {
+ Package (0x04){0xFFFF,0x00,0x00,0x10},
+ Package (0x04){0xFFFF,0x01,0x00,0x11},
+ Package (0x04){0xFFFF,0x02,0x00,0x12},
+ Package (0x04){0xFFFF,0x03,0x00,0x13}
+ })
+ /* Routing Bus PCI */
+ Name (PR01, Package (0x04)
+ {
+ Package (0x04){0x0000FFFF,0x00,LNKA,0x00},
+ Package (0x04){0x0000FFFF,0x01,LNKB,0x00},
+ Package (0x04){0x0000FFFF,0x02,LNKC,0x00},
+ Package (0x04){0x0000FFFF,0x03,LNKD,0x00},
+ })
+ Name (AR01, Package (0x04)
+ {
+ Package (0x04){0x0000FFFF,0x00,0x00,0x10},
+ Package (0x04){0x0000FFFF,0x01,0x00,0x11},
+ Package (0x04){0x0000FFFF,0x02,0x00,0x12},
+ Package (0x04){0x0000FFFF,0x03,0x00,0x13},
+ })
+
+ Name (PRSA, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared, )
+ {3,4,5,6,7,10,11,12,14,15}
+ })
+ Alias (PRSA, PRSB)
+ Alias (PRSA, PRSC)
+ Alias (PRSA, PRSD)
+ Alias (PRSA, PRSE)
+ Alias (PRSA, PRSF)
+ Alias (PRSA, PRSG)
+ Alias (PRSA, PRSH)
+
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A08"))
+ Name (_CID, EisaId ("PNP0A03"))
+ Name (_ADR, 0x00)
+ Name (_SEG, 0x00)
+ Name (_UID, 0x00)
+ Name (_BBN, 0x00)
+
+ Name (SUPP, 0) /* PCI _OSC Support Field Value */
+ Name (CTRL, 0) /* PCI _OSC Control Field Value */
+
+ Method (_OSC, 4)
+ {
+ /* Check for proper GUID */
+ If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
+ {
+ /* Create DWORD-adressable field from the Capabilities Buffer */
+ CreateDWordField (Arg3, 0, CDW1)
+ CreateDWordField (Arg3, 4, CDW2)
+ CreateDWordField (Arg3, 8, CDW3)
+
+ /* Save Capabilities DWord 2 & 3 */
+ Store (CDW2, SUPP)
+ Store (CDW3, CTRL)
+
+ /* Don't care of OS capabilites */
+ /* We support nothing (maybe we should add PCIe Capability Structure Control) */
+ And (CTRL, 0x00, CTRL)
+
+ /* Query flag clear ? */
+ If (Not (And (CDW1, 1)))
+ {
+ /* Nothing to do */
+ }
+
+ /* Unknown revision ? */
+ If (LNotEqual (Arg1, One))
+ {
+ Or (CDW1, 0x08, CDW1)
+ }
+
+ /* Capabilities bits masked ? */
+ If (LNotEqual (CDW3, CTRL))
+ {
+ Or (CDW1, 0x10, CDW1)
+ }
+
+ /* Update DWORD3 in the buffer */
+ Store (CTRL, CDW3)
+
+ Return (Arg3)
+ }
+ Else
+ {
+ /* Unrecognized UUID */
+ Or (CDW1, 4, CDW1)
+ Return (Arg3)
+ }
+ } /* End _OSC */
+
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (PICM)
+ {
+ Return (AR00)
+ }
+
+ Return (PR00)
+ }
+
+ /* PCI Express Port A */
+ Device (EPA0)
+ {
+ Name (_ADR, 0x00020000)
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (PICM)
+ {
+ Return (AR0A)
+ }
+
+ Return (PR0A)
+ }
+ }
+
+ /* PCI Express Port A1 */
+ Device (EPA1)
+ {
+ Name (_ADR, 0x00030000)
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (PICM)
+ {
+ Return (AR0A)
+ }
+
+ Return (PR0A)
+ }
+ }
+
+ /* PCI Express Port B0 */
+ Device (EPB0)
+ {
+ Name (_ADR, 0x001C0000)
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (PICM)
+ {
+ Return (AR0B)
+ }
+
+ Return (PR0B)
+ }
+ }
+
+ /* PCI Bridge */
+ Device (P0P1)
+ {
+ Name (_ADR, 0x001E0000)
+
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (PICM)
+ {
+ Return (AR01)
+ }
+
+ Return (PR01)
+ }
+ }
+
+ /* LPC I/F Bridge */
+ Device (ISA) {
+ Name (_ADR, 0x001F0000)
+
+ /* MMCONF */
+ Device (^PCIE)
+ {
+ Name (_HID, EisaId ("PNP0C02"))
+ Name (_UID, 0x11)
+ Name (CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadOnly,
+ 0xE0000000, // Address Base
+ 0x10000000, // Address Length
+ _Y10)
+ })
+ Method (_CRS, 0, NotSerialized)
+ {
+ CreateDWordField (CRS, \_SB.PCI0.PCIE._Y10._BAS, BAS1)
+ CreateDWordField (CRS, \_SB.PCI0.PCIE._Y10._LEN, LEN1)
+ Store (0xE0000000, BAS1)
+ Store (0x10000000, LEN1)
+ Return (CRS)
+ }
+ }
+
+ /* PIC */
+ Device (PIC)
+ {
+ Name (_HID, EisaId ("PNP0000"))
+ Name (_CRS, ResourceTemplate()
+ {
+ IO (Decode16,
+ 0x0020,
+ 0x0020,
+ 0x00,
+ 0x02,
+ )
+ IO (Decode16,
+ 0x00A0,
+ 0x00A0,
+ 0x00,
+ 0x02,
+ )
+ IRQNoFlags ()
+ {2}
+ })
+ }
+
+ /* Real time clock */
+ Device (RTC0)
+ {
+ Name (_HID, EisaId ("PNP0B00"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16,
+ 0x0070,
+ 0x0070,
+ 0x00,
+ 0x02)
+ IRQNoFlags ()
+ {8}
+ })
+ }
+
+ Device (UAR1)
+ {
+ Name (_UID, 0x01)
+ Name (_HID, EisaId ("PNP0501"))
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Return (CMPR)
+ }
+
+ Name (CMPR, ResourceTemplate ()
+ {
+ StartDependentFn (0x00, 0x00)
+ {
+ IO (Decode16,0x03F8,0x03F8,0x01,0x08)
+ IRQNoFlags () {4}
+ DMA (Compatibility, NotBusMaster, Transfer8) {}
+ }
+ StartDependentFnNoPri ()
+ {
+ IO (Decode16,0x03F8,0x03F8,0x01,0x08)
+ IRQNoFlags () {3,4,5,6,7,10,11,12}
+ DMA (Compatibility, NotBusMaster, Transfer8) {}
+ }
+ StartDependentFnNoPri ()
+ {
+ IO (Decode16,0x02F8,0x02F8,0x01,0x08)
+ IRQNoFlags () {3,4,5,6,7,10,11,12}
+ DMA (Compatibility, NotBusMaster, Transfer8) {}
+ }
+ StartDependentFnNoPri ()
+ {
+ IO (Decode16,0x03E8,0x03E8,0x01,0x08)
+ IRQNoFlags () {3,4,5,6,7,10,11,12}
+ DMA (Compatibility, NotBusMaster, Transfer8) {}
+ }
+ StartDependentFnNoPri ()
+ {
+ IO (Decode16,0x02E8,0x02E8,0x01,0x08)
+ IRQNoFlags () {3,4,5,6,7,10,11,12}
+ DMA (Compatibility, NotBusMaster, Transfer8) {}
+ }
+ EndDependentFn ()
+ })
+ }
+
+ /* PS/2 keyboard (seems to be important for WinXP install) */
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+ IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+ IRQNoFlags () {1}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* PS/2 mouse */
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ IRQNoFlags () {12}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* COM ports of SIO */
+ Device(SIO) {
+ OperationRegion (PT4E, SystemIO, 0x4E, 0x02)
+ Field (PT4E, ByteAcc, NoLock, Preserve)
+ {
+ PO4E, 8,
+ PO4F, 8
+ }
+
+ IndexField (PO4E, PO4F, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x07),
+ ILDN, 8,
+ Offset (0x28),
+ SIUI, 8,
+ SIUC, 8,
+ Offset (0x30),
+ IACT, 8,
+ Offset (0x60),
+ IIOH, 8,
+ IIOL, 8,
+ Offset (0x70),
+ IINT, 8
+ }
+
+ Method (IENF, 0, NotSerialized)
+ {
+ Store (0x80, PO4E)
+ Store (0x86, PO4E)
+ }
+
+ Method (IEXF, 0, NotSerialized)
+ {
+ Store (0x68, PO4E)
+ Store (0x08, PO4E)
+ }
+
+ Device (COM1)
+ {
+ Name (_UID, 0x03)
+ Name (_HID, EisaId ("PNP0501"))
+ Method (_STA, 0, NotSerialized)
+ {
+ IENF ()
+ Store (0x04, ILDN)
+ Store (IACT, Local0)
+ IEXF ()
+ If (LEqual (Local0, 0xFF))
+ {
+ Return (0x00)
+ }
+
+ If (LEqual (Local0, One))
+ {
+ Return (0x0F)
+ }
+ Else
+ {
+ Return (0x0D)
+ }
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ IENF ()
+ Store (0x04, ILDN)
+ Store (Zero, IACT)
+ IEXF ()
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BFU1, ResourceTemplate ()
+ {
+ IO (Decode16,
+ 0x03F8, // Range Minimum
+ 0x03F8, // Range Maximum
+ 0x08, // Alignment
+ 0x08, // Length
+ _Y03)
+ IRQNoFlags (_Y04)
+ {5}
+ })
+ CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM1._CRS._Y03._MIN, IMIN)
+ CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM1._CRS._Y03._MAX, IMAX)
+ CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM1._CRS._Y04._INT, IRQ0)
+ IENF ()
+ Store (0x04, ILDN)
+ Store (IIOH, Local0)
+ ShiftLeft (Local0, 0x08, Local1)
+ Store (IIOL, Local0)
+ Add (Local1, Local0, Local0)
+ Store (Local0, IMIN)
+ Store (Local0, IMAX)
+ Store (IINT, Local0)
+ IEXF ()
+ Store (0x01, Local1)
+ ShiftLeft (Local1, Local0, IRQ0)
+ Return (BFU1)
+ }
+
+ Name (_PRS, ResourceTemplate ()
+ {
+ StartDependentFnNoPri ()
+ {
+ IO (Decode16,
+ 0x03F8, // Range Minimum
+ 0x03F8, // Range Maximum
+ 0x08, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {5}
+ }
+ StartDependentFnNoPri ()
+ {
+ IO (Decode16,
+ 0x02F8, // Range Minimum
+ 0x02F8, // Range Maximum
+ 0x08, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {9}
+ }
+ EndDependentFn ()
+ })
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateByteField (Arg0, 0x02, IOLO)
+ CreateByteField (Arg0, 0x03, IOHI)
+ CreateWordField (Arg0, 0x09, IRQ0)
+ IENF ()
+ Store (0x04, ILDN)
+ Store (Zero, IACT)
+ Store (IOLO, IIOL)
+ Store (IOHI, IIOH)
+ FindSetRightBit (IRQ0, Local0)
+ If (LGreater (Local0, 0x00))
+ {
+ Decrement (Local0)
+ }
+
+ Store (Local0, IINT)
+ Store (One, IACT)
+ IEXF ()
+ }
+ } /* COM1 */
+
+ Device (COM2)
+ {
+ Name (_UID, 0x04)
+ Name (_HID, EisaId ("PNP0501"))
+ Method (_STA, 0, NotSerialized)
+ {
+ IENF ()
+ Store (0x05, ILDN)
+ Store (IACT, Local0)
+ IEXF ()
+ If (LEqual (Local0, 0xFF))
+ {
+ Return (0x00)
+ }
+
+ If (LEqual (Local0, One))
+ {
+ Return (0x0F)
+ }
+ Else
+ {
+ Return (0x0D)
+ }
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ IENF ()
+ Store (0x05, ILDN)
+ Store (Zero, IACT)
+ IEXF ()
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BFU1, ResourceTemplate ()
+ {
+ IO (Decode16,
+ 0x03F8, // Range Minimum
+ 0x03F8, // Range Maximum
+ 0x08, // Alignment
+ 0x08, // Length
+ _Y05)
+ IRQNoFlags (_Y06)
+ {9}
+ })
+ CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM2._CRS._Y05._MIN, IMIN)
+ CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM2._CRS._Y05._MAX, IMAX)
+ CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM2._CRS._Y06._INT, IRQ0)
+ IENF ()
+ Store (0x05, ILDN)
+ Store (IIOH, Local0)
+ ShiftLeft (Local0, 0x08, Local1)
+ Store (IIOL, Local0)
+ Add (Local1, Local0, Local0)
+ Store (Local0, IMIN)
+ Store (Local0, IMAX)
+ Store (IINT, Local0)
+ IEXF ()
+ Store (0x01, Local1)
+ ShiftLeft (Local1, Local0, IRQ0)
+ Return (BFU1)
+ }
+
+ Name (_PRS, ResourceTemplate ()
+ {
+ StartDependentFnNoPri ()
+ {
+ IO (Decode16,
+ 0x03F8, // Range Minimum
+ 0x03F8, // Range Maximum
+ 0x08, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {5}
+ }
+ StartDependentFnNoPri ()
+ {
+ IO (Decode16,
+ 0x02F8, // Range Minimum
+ 0x02F8, // Range Maximum
+ 0x08, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {9}
+ }
+ EndDependentFn ()
+ })
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateByteField (Arg0, 0x02, IOLO)
+ CreateByteField (Arg0, 0x03, IOHI)
+ CreateWordField (Arg0, 0x09, IRQ0)
+ IENF ()
+ Store (0x05, ILDN)
+ Store (Zero, IACT)
+ Store (IOLO, IIOL)
+ Store (IOHI, IIOH)
+ FindSetRightBit (IRQ0, Local0)
+ If (LGreater (Local0, 0x00))
+ {
+ Decrement (Local0)
+ }
+
+ Store (Local0, IINT)
+ Store (One, IACT)
+ IEXF ()
+ }
+ } /* COM2 */
+ } /* Device SIO */
+ } /* Device ISA */
+ } /* Device PCI 0*/
+ } /* Scope SB */
+
+ OperationRegion (_SB.PCI0.ISA.PIX0, PCI_Config, 0x60, 0x0C)
+ Field (\_SB.PCI0.ISA.PIX0, ByteAcc, NoLock, Preserve)
+ {
+ PIRA, 8,
+ PIRB, 8,
+ PIRC, 8,
+ PIRD, 8,
+ Offset (0x08),
+ PIRE, 8,
+ PIRF, 8,
+ PIRG, 8,
+ PIRH, 8
+ }
+
+ Scope (_SB)
+ {
+ Name (BUFA, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared, _Y1C)
+ {15}
+ })
+ CreateWordField (BUFA, \_SB._Y1C._INT, IRA0)
+ Device (LNKA)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x01)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (PIRA, 0x80, Local0)
+ If (Local0)
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Return (PRSA)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Or (PIRA, 0x80, PIRA)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ And (PIRA, 0x0F, Local0)
+ ShiftLeft (0x01, Local0, IRA0)
+ Return (BUFA)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateWordField (Arg0, 0x01, IRA)
+ FindSetRightBit (IRA, Local0)
+ Decrement (Local0)
+ Store (Local0, PIRA)
+ }
+ }
+
+ Device (LNKB)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x02)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (PIRB, 0x80, Local0)
+ If (Local0)
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Return (PRSB)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Or (PIRB, 0x80, PIRB)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ And (PIRB, 0x0F, Local0)
+ ShiftLeft (0x01, Local0, IRA0)
+ Return (BUFA)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateWordField (Arg0, 0x01, IRA)
+ FindSetRightBit (IRA, Local0)
+ Decrement (Local0)
+ Store (Local0, PIRB)
+ }
+ }
+
+ Device (LNKC)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x03)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (PIRC, 0x80, Local0)
+ If (Local0)
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Return (PRSC)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Or (PIRC, 0x80, PIRC)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ And (PIRC, 0x0F, Local0)
+ ShiftLeft (0x01, Local0, IRA0)
+ Return (BUFA)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateWordField (Arg0, 0x01, IRA)
+ FindSetRightBit (IRA, Local0)
+ Decrement (Local0)
+ Store (Local0, PIRC)
+ }
+ }
+
+ Device (LNKD)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x04)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (PIRD, 0x80, Local0)
+ If (Local0)
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Return (PRSD)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Or (PIRD, 0x80, PIRD)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ And (PIRD, 0x0F, Local0)
+ ShiftLeft (0x01, Local0, IRA0)
+ Return (BUFA)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateWordField (Arg0, 0x01, IRA)
+ FindSetRightBit (IRA, Local0)
+ Decrement (Local0)
+ Store (Local0, PIRD)
+ }
+ }
+
+ Device (LNKE)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x05)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (PIRE, 0x80, Local0)
+ If (Local0)
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Return (PRSE)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Or (PIRE, 0x80, PIRE)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ And (PIRE, 0x0F, Local0)
+ ShiftLeft (0x01, Local0, IRA0)
+ Return (BUFA)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateWordField (Arg0, 0x01, IRA)
+ FindSetRightBit (IRA, Local0)
+ Decrement (Local0)
+ Store (Local0, PIRE)
+ }
+ }
+
+ Device (LNKF)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x06)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (PIRF, 0x80, Local0)
+ If (Local0)
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Return (PRSF)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Or (PIRF, 0x80, PIRF)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ And (PIRF, 0x0F, Local0)
+ ShiftLeft (0x01, Local0, IRA0)
+ Return (BUFA)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateWordField (Arg0, 0x01, IRA)
+ FindSetRightBit (IRA, Local0)
+ Decrement (Local0)
+ Store (Local0, PIRF)
+ }
+ }
+
+ Device (LNKG)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x07)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (PIRG, 0x80, Local0)
+ If (Local0)
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Return (PRSG)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Or (PIRG, 0x80, PIRG)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ And (PIRG, 0x0F, Local0)
+ ShiftLeft (0x01, Local0, IRA0)
+ Return (BUFA)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateWordField (Arg0, 0x01, IRA)
+ FindSetRightBit (IRA, Local0)
+ Decrement (Local0)
+ Store (Local0, PIRG)
+ }
+ }
+
+ Device (LNKH)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x08)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (PIRH, 0x80, Local0)
+ If (Local0)
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Return (PRSH)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Or (PIRH, 0x80, PIRH)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ And (PIRH, 0x0F, Local0)
+ ShiftLeft (0x01, Local0, IRA0)
+ Return (BUFA)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateWordField (Arg0, 0x01, IRA)
+ FindSetRightBit (IRA, Local0)
+ Decrement (Local0)
+ Store (Local0, PIRH)
+ }
+ }
+ }
+}
+
+
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-DefinitionBlock ("DSDT", "DSDT", 1, "EAGLE", "COREBOOT", 0x0000001)
-{
- Scope (\_PR)
- {
- Processor (CPU1, 0x01, 0x00000810, 0x06)
- {
- OperationRegion (STBL, SystemMemory, 0xFFFF0000, 0xFFFF)
- Name (NCPU, 0x80)
- Name (TYPE, 0x80000000)
- Name (HNDL, 0x80000000)
- Name (CFGD, 0x80000000)
- Name (TBLD, 0x80)
- Method (_PDC, 1, NotSerialized)
- {
- }
- }
- }
-
- Scope (\_PR)
- {
- Processor (CPU2, 0x02, 0x00000000, 0x00)
- {
- OperationRegion (STBL, SystemMemory, 0xFFFF0000, 0xFFFF)
- Name (NCPU, 0x80)
- Name (TYPE, 0x80000000)
- Name (HNDL, 0x80000000)
- Name (CFGD, 0x80000000)
- Name (TBLD, 0x80)
- Method (_PDC, 1, NotSerialized)
- {
- }
- }
- }
-
- /* For now only define 2 power states:
- * - S0 which is fully on
- * - S5 which is soft off
- * Any others would involve declaring the wake up methods.
- */
- Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
- Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
-
- Name (PICM, 0x00)
- Method (_PIC, 1, NotSerialized)
- {
- Store (Arg0, PICM)
- }
-
- /* System bus */
- Scope (\_SB)
- {
- /* Routing PCI0 */
- Name (PR00, Package (0x0E)
- {
- Package (0x04){0x0001FFFF,0x00,LNKA,0x00}, /* EDMA INTA# */
- Package (0x04){0x0002FFFF,0x00,LNKA,0x00}, /* PCIe port A */
- Package (0x04){0x0002FFFF,0x01,LNKB,0x00},
- Package (0x04){0x0002FFFF,0x02,LNKC,0x00},
- Package (0x04){0x0002FFFF,0x03,LNKD,0x00},
- Package (0x04){0x0003FFFF,0x00,LNKA,0x00}, /* PCIe port A1 */
- Package (0x04){0x0003FFFF,0x01,LNKB,0x00},
- Package (0x04){0x0003FFFF,0x02,LNKC,0x00},
- Package (0x04){0x0003FFFF,0x03,LNKD,0x00},
- Package (0x04){0x001CFFFF,0x00,LNKE,0x00}, /* PCIe port B */
- Package (0x04){0x001DFFFF,0x00,LNKH,0x00}, /* UHCI/EHCI INTA# */
- Package (0x04){0x001DFFFF,0x01,LNKD,0x00}, /* UHCI INTB# */
- Package (0x04){0x001FFFFF,0x01,LNKD,0x00}, /* SATA/SMBUS INTB# */
- Package (0x04){0x001FFFFF,0x03,LNKA,0x00} /* CHAP INTD# */
- })
- Name (AR00, Package (0x0E)
- {
- Package (0x04){0x0001FFFF,0x00,0x00,0x10}, /* EDMA INTA# */
- Package (0x04){0x0002FFFF,0x00,0x00,0x10}, /* PCIe port A0 */
- Package (0x04){0x0002FFFF,0x01,0x00,0x11},
- Package (0x04){0x0002FFFF,0x02,0x00,0x12},
- Package (0x04){0x0002FFFF,0x03,0x00,0x13},
- Package (0x04){0x0003FFFF,0x00,0x00,0x10}, /* PCIe port A1 */
- Package (0x04){0x0003FFFF,0x01,0x00,0x11},
- Package (0x04){0x0003FFFF,0x02,0x00,0x12},
- Package (0x04){0x0003FFFF,0x03,0x00,0x13},
- Package (0x04){0x001CFFFF,0x00,0x00,0x14}, /* PCIe port B */
- Package (0x04){0x001DFFFF,0x00,0x00,0x17}, /* UHCI/EHCI INTA# */
- Package (0x04){0x001DFFFF,0x01,0x00,0x13}, /* UHCI INTB# */
- Package (0x04){0x001FFFFF,0x01,0x00,0x13}, /* SATA/SMBUS INTB# */
- Package (0x04){0x001FFFFF,0x0D,0x00,0x10} /* CHAP INTD# */
- })
- /* Routing PCIe Port A */
- Name (PR0A, Package (0x04)
- {
- Package (0x04){0xFFFF,0x00,LNKA,0x00},
- Package (0x04){0xFFFF,0x01,LNKB,0x00},
- Package (0x04){0xFFFF,0x02,LNKC,0x00},
- Package (0x04){0xFFFF,0x03,LNKD,0x00}
- })
- Name (AR0A, Package (0x04)
- {
- Package (0x04){0xFFFF,0x00,0x00,0x10},
- Package (0x04){0xFFFF,0x01,0x00,0x11},
- Package (0x04){0xFFFF,0x02,0x00,0x12},
- Package (0x04){0xFFFF,0x03,0x00,0x13}
- })
- /* Routing PCIe Port B */
- Name (PR0B, Package (0x04)
- {
- Package (0x04){0xFFFF,0x00,LNKA,0x00},
- Package (0x04){0xFFFF,0x01,LNKB,0x00},
- Package (0x04){0xFFFF,0x02,LNKC,0x00},
- Package (0x04){0xFFFF,0x03,LNKD,0x00}
- })
- Name (AR0B, Package (0x04)
- {
- Package (0x04){0xFFFF,0x00,0x00,0x10},
- Package (0x04){0xFFFF,0x01,0x00,0x11},
- Package (0x04){0xFFFF,0x02,0x00,0x12},
- Package (0x04){0xFFFF,0x03,0x00,0x13}
- })
- /* Routing Bus PCI */
- Name (PR01, Package (0x04)
- {
- Package (0x04){0x0000FFFF,0x00,LNKA,0x00},
- Package (0x04){0x0000FFFF,0x01,LNKB,0x00},
- Package (0x04){0x0000FFFF,0x02,LNKC,0x00},
- Package (0x04){0x0000FFFF,0x03,LNKD,0x00},
- })
- Name (AR01, Package (0x04)
- {
- Package (0x04){0x0000FFFF,0x00,0x00,0x10},
- Package (0x04){0x0000FFFF,0x01,0x00,0x11},
- Package (0x04){0x0000FFFF,0x02,0x00,0x12},
- Package (0x04){0x0000FFFF,0x03,0x00,0x13},
- })
-
- Name (PRSA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared, )
- {3,4,5,6,7,10,11,12,14,15}
- })
- Alias (PRSA, PRSB)
- Alias (PRSA, PRSC)
- Alias (PRSA, PRSD)
- Alias (PRSA, PRSE)
- Alias (PRSA, PRSF)
- Alias (PRSA, PRSG)
- Alias (PRSA, PRSH)
-
- Device (PCI0)
- {
- Name (_HID, EisaId ("PNP0A08"))
- Name (_CID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00)
- Name (_SEG, 0x00)
- Name (_UID, 0x00)
- Name (_BBN, 0x00)
-
- Name (SUPP, 0) /* PCI _OSC Support Field Value */
- Name (CTRL, 0) /* PCI _OSC Control Field Value */
-
- Method (_OSC, 4)
- {
- /* Check for proper GUID */
- If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
- {
- /* Create DWORD-adressable field from the Capabilities Buffer */
- CreateDWordField (Arg3, 0, CDW1)
- CreateDWordField (Arg3, 4, CDW2)
- CreateDWordField (Arg3, 8, CDW3)
-
- /* Save Capabilities DWord 2 & 3 */
- Store (CDW2, SUPP)
- Store (CDW3, CTRL)
-
- /* Don't care of OS capabilites */
- /* We support nothing (maybe we should add PCIe Capability Structure Control) */
- And (CTRL, 0x00, CTRL)
-
- /* Query flag clear ? */
- If (Not (And (CDW1, 1)))
- {
- /* Nothing to do */
- }
-
- /* Unknown revision ? */
- If (LNotEqual (Arg1, One))
- {
- Or (CDW1, 0x08, CDW1)
- }
-
- /* Capabilities bits masked ? */
- If (LNotEqual (CDW3, CTRL))
- {
- Or (CDW1, 0x10, CDW1)
- }
-
- /* Update DWORD3 in the buffer */
- Store (CTRL, CDW3)
-
- Return (Arg3)
- }
- Else
- {
- /* Unrecognized UUID */
- Or (CDW1, 4, CDW1)
- Return (Arg3)
- }
- } /* End _OSC */
-
- Method (_PRT, 0, NotSerialized)
- {
- If (PICM)
- {
- Return (AR00)
- }
-
- Return (PR00)
- }
-
- /* PCI Express Port A */
- Device (EPA0)
- {
- Name (_ADR, 0x00020000)
- Method (_PRT, 0, NotSerialized)
- {
- If (PICM)
- {
- Return (AR0A)
- }
-
- Return (PR0A)
- }
- }
-
- /* PCI Express Port A1 */
- Device (EPA1)
- {
- Name (_ADR, 0x00030000)
- Method (_PRT, 0, NotSerialized)
- {
- If (PICM)
- {
- Return (AR0A)
- }
-
- Return (PR0A)
- }
- }
-
- /* PCI Express Port B0 */
- Device (EPB0)
- {
- Name (_ADR, 0x001C0000)
- Method (_PRT, 0, NotSerialized)
- {
- If (PICM)
- {
- Return (AR0B)
- }
-
- Return (PR0B)
- }
- }
-
- /* PCI Bridge */
- Device (P0P1)
- {
- Name (_ADR, 0x001E0000)
-
- Method (_PRT, 0, NotSerialized)
- {
- If (PICM)
- {
- Return (AR01)
- }
-
- Return (PR01)
- }
- }
-
- /* LPC I/F Bridge */
- Device (ISA) {
- Name (_ADR, 0x001F0000)
-
- /* MMCONF */
- Device (^PCIE)
- {
- Name (_HID, EisaId ("PNP0C02"))
- Name (_UID, 0x11)
- Name (CRS, ResourceTemplate ()
- {
- Memory32Fixed (ReadOnly,
- 0xE0000000, // Address Base
- 0x10000000, // Address Length
- _Y10)
- })
- Method (_CRS, 0, NotSerialized)
- {
- CreateDWordField (CRS, \_SB.PCI0.PCIE._Y10._BAS, BAS1)
- CreateDWordField (CRS, \_SB.PCI0.PCIE._Y10._LEN, LEN1)
- Store (0xE0000000, BAS1)
- Store (0x10000000, LEN1)
- Return (CRS)
- }
- }
-
- /* PIC */
- Device (PIC)
- {
- Name (_HID, EisaId ("PNP0000"))
- Name (_CRS, ResourceTemplate()
- {
- IO (Decode16,
- 0x0020,
- 0x0020,
- 0x00,
- 0x02,
- )
- IO (Decode16,
- 0x00A0,
- 0x00A0,
- 0x00,
- 0x02,
- )
- IRQNoFlags ()
- {2}
- })
- }
-
- /* Real time clock */
- Device (RTC0)
- {
- Name (_HID, EisaId ("PNP0B00"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0070,
- 0x0070,
- 0x00,
- 0x02)
- IRQNoFlags ()
- {8}
- })
- }
-
- Device (UAR1)
- {
- Name (_UID, 0x01)
- Name (_HID, EisaId ("PNP0501"))
-
- Method (_PRS, 0, NotSerialized)
- {
- Return (CMPR)
- }
-
- Name (CMPR, ResourceTemplate ()
- {
- StartDependentFn (0x00, 0x00)
- {
- IO (Decode16,0x03F8,0x03F8,0x01,0x08)
- IRQNoFlags () {4}
- DMA (Compatibility, NotBusMaster, Transfer8) {}
- }
- StartDependentFnNoPri ()
- {
- IO (Decode16,0x03F8,0x03F8,0x01,0x08)
- IRQNoFlags () {3,4,5,6,7,10,11,12}
- DMA (Compatibility, NotBusMaster, Transfer8) {}
- }
- StartDependentFnNoPri ()
- {
- IO (Decode16,0x02F8,0x02F8,0x01,0x08)
- IRQNoFlags () {3,4,5,6,7,10,11,12}
- DMA (Compatibility, NotBusMaster, Transfer8) {}
- }
- StartDependentFnNoPri ()
- {
- IO (Decode16,0x03E8,0x03E8,0x01,0x08)
- IRQNoFlags () {3,4,5,6,7,10,11,12}
- DMA (Compatibility, NotBusMaster, Transfer8) {}
- }
- StartDependentFnNoPri ()
- {
- IO (Decode16,0x02E8,0x02E8,0x01,0x08)
- IRQNoFlags () {3,4,5,6,7,10,11,12}
- DMA (Compatibility, NotBusMaster, Transfer8) {}
- }
- EndDependentFn ()
- })
- }
-
- /* PS/2 keyboard (seems to be important for WinXP install) */
- Device (KBD)
- {
- Name (_HID, EisaId ("PNP0303"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {1}
- })
- Return (TMP)
- }
- }
-
- /* PS/2 mouse */
- Device (MOU)
- {
- Name (_HID, EisaId ("PNP0F13"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IRQNoFlags () {12}
- })
- Return (TMP)
- }
- }
-
- /* COM ports of SIO */
- Device(SIO) {
- OperationRegion (PT4E, SystemIO, 0x4E, 0x02)
- Field (PT4E, ByteAcc, NoLock, Preserve)
- {
- PO4E, 8,
- PO4F, 8
- }
-
- IndexField (PO4E, PO4F, ByteAcc, NoLock, Preserve)
- {
- Offset (0x07),
- ILDN, 8,
- Offset (0x28),
- SIUI, 8,
- SIUC, 8,
- Offset (0x30),
- IACT, 8,
- Offset (0x60),
- IIOH, 8,
- IIOL, 8,
- Offset (0x70),
- IINT, 8
- }
-
- Method (IENF, 0, NotSerialized)
- {
- Store (0x80, PO4E)
- Store (0x86, PO4E)
- }
-
- Method (IEXF, 0, NotSerialized)
- {
- Store (0x68, PO4E)
- Store (0x08, PO4E)
- }
-
- Device (COM1)
- {
- Name (_UID, 0x03)
- Name (_HID, EisaId ("PNP0501"))
- Method (_STA, 0, NotSerialized)
- {
- IENF ()
- Store (0x04, ILDN)
- Store (IACT, Local0)
- IEXF ()
- If (LEqual (Local0, 0xFF))
- {
- Return (0x00)
- }
-
- If (LEqual (Local0, One))
- {
- Return (0x0F)
- }
- Else
- {
- Return (0x0D)
- }
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- IENF ()
- Store (0x04, ILDN)
- Store (Zero, IACT)
- IEXF ()
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BFU1, ResourceTemplate ()
- {
- IO (Decode16,
- 0x03F8, // Range Minimum
- 0x03F8, // Range Maximum
- 0x08, // Alignment
- 0x08, // Length
- _Y03)
- IRQNoFlags (_Y04)
- {5}
- })
- CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM1._CRS._Y03._MIN, IMIN)
- CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM1._CRS._Y03._MAX, IMAX)
- CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM1._CRS._Y04._INT, IRQ0)
- IENF ()
- Store (0x04, ILDN)
- Store (IIOH, Local0)
- ShiftLeft (Local0, 0x08, Local1)
- Store (IIOL, Local0)
- Add (Local1, Local0, Local0)
- Store (Local0, IMIN)
- Store (Local0, IMAX)
- Store (IINT, Local0)
- IEXF ()
- Store (0x01, Local1)
- ShiftLeft (Local1, Local0, IRQ0)
- Return (BFU1)
- }
-
- Name (_PRS, ResourceTemplate ()
- {
- StartDependentFnNoPri ()
- {
- IO (Decode16,
- 0x03F8, // Range Minimum
- 0x03F8, // Range Maximum
- 0x08, // Alignment
- 0x08, // Length
- )
- IRQNoFlags ()
- {5}
- }
- StartDependentFnNoPri ()
- {
- IO (Decode16,
- 0x02F8, // Range Minimum
- 0x02F8, // Range Maximum
- 0x08, // Alignment
- 0x08, // Length
- )
- IRQNoFlags ()
- {9}
- }
- EndDependentFn ()
- })
- Method (_SRS, 1, NotSerialized)
- {
- CreateByteField (Arg0, 0x02, IOLO)
- CreateByteField (Arg0, 0x03, IOHI)
- CreateWordField (Arg0, 0x09, IRQ0)
- IENF ()
- Store (0x04, ILDN)
- Store (Zero, IACT)
- Store (IOLO, IIOL)
- Store (IOHI, IIOH)
- FindSetRightBit (IRQ0, Local0)
- If (LGreater (Local0, 0x00))
- {
- Decrement (Local0)
- }
-
- Store (Local0, IINT)
- Store (One, IACT)
- IEXF ()
- }
- } /* COM1 */
-
- Device (COM2)
- {
- Name (_UID, 0x04)
- Name (_HID, EisaId ("PNP0501"))
- Method (_STA, 0, NotSerialized)
- {
- IENF ()
- Store (0x05, ILDN)
- Store (IACT, Local0)
- IEXF ()
- If (LEqual (Local0, 0xFF))
- {
- Return (0x00)
- }
-
- If (LEqual (Local0, One))
- {
- Return (0x0F)
- }
- Else
- {
- Return (0x0D)
- }
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- IENF ()
- Store (0x05, ILDN)
- Store (Zero, IACT)
- IEXF ()
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BFU1, ResourceTemplate ()
- {
- IO (Decode16,
- 0x03F8, // Range Minimum
- 0x03F8, // Range Maximum
- 0x08, // Alignment
- 0x08, // Length
- _Y05)
- IRQNoFlags (_Y06)
- {9}
- })
- CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM2._CRS._Y05._MIN, IMIN)
- CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM2._CRS._Y05._MAX, IMAX)
- CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM2._CRS._Y06._INT, IRQ0)
- IENF ()
- Store (0x05, ILDN)
- Store (IIOH, Local0)
- ShiftLeft (Local0, 0x08, Local1)
- Store (IIOL, Local0)
- Add (Local1, Local0, Local0)
- Store (Local0, IMIN)
- Store (Local0, IMAX)
- Store (IINT, Local0)
- IEXF ()
- Store (0x01, Local1)
- ShiftLeft (Local1, Local0, IRQ0)
- Return (BFU1)
- }
-
- Name (_PRS, ResourceTemplate ()
- {
- StartDependentFnNoPri ()
- {
- IO (Decode16,
- 0x03F8, // Range Minimum
- 0x03F8, // Range Maximum
- 0x08, // Alignment
- 0x08, // Length
- )
- IRQNoFlags ()
- {5}
- }
- StartDependentFnNoPri ()
- {
- IO (Decode16,
- 0x02F8, // Range Minimum
- 0x02F8, // Range Maximum
- 0x08, // Alignment
- 0x08, // Length
- )
- IRQNoFlags ()
- {9}
- }
- EndDependentFn ()
- })
- Method (_SRS, 1, NotSerialized)
- {
- CreateByteField (Arg0, 0x02, IOLO)
- CreateByteField (Arg0, 0x03, IOHI)
- CreateWordField (Arg0, 0x09, IRQ0)
- IENF ()
- Store (0x05, ILDN)
- Store (Zero, IACT)
- Store (IOLO, IIOL)
- Store (IOHI, IIOH)
- FindSetRightBit (IRQ0, Local0)
- If (LGreater (Local0, 0x00))
- {
- Decrement (Local0)
- }
-
- Store (Local0, IINT)
- Store (One, IACT)
- IEXF ()
- }
- } /* COM2 */
- } /* Device SIO */
- } /* Device ISA */
- } /* Device PCI 0*/
- } /* Scope SB */
-
- OperationRegion (_SB.PCI0.ISA.PIX0, PCI_Config, 0x60, 0x0C)
- Field (\_SB.PCI0.ISA.PIX0, ByteAcc, NoLock, Preserve)
- {
- PIRA, 8,
- PIRB, 8,
- PIRC, 8,
- PIRD, 8,
- Offset (0x08),
- PIRE, 8,
- PIRF, 8,
- PIRG, 8,
- PIRH, 8
- }
-
- Scope (_SB)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared, _Y1C)
- {15}
- })
- CreateWordField (BUFA, \_SB._Y1C._INT, IRA0)
- Device (LNKA)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x01)
- Method (_STA, 0, NotSerialized)
- {
- And (PIRA, 0x80, Local0)
- If (Local0)
- {
- Return (0x09)
- }
- Else
- {
- Return (0x0B)
- }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Return (PRSA)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Or (PIRA, 0x80, PIRA)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- And (PIRA, 0x0F, Local0)
- ShiftLeft (0x01, Local0, IRA0)
- Return (BUFA)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateWordField (Arg0, 0x01, IRA)
- FindSetRightBit (IRA, Local0)
- Decrement (Local0)
- Store (Local0, PIRA)
- }
- }
-
- Device (LNKB)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x02)
- Method (_STA, 0, NotSerialized)
- {
- And (PIRB, 0x80, Local0)
- If (Local0)
- {
- Return (0x09)
- }
- Else
- {
- Return (0x0B)
- }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Return (PRSB)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Or (PIRB, 0x80, PIRB)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- And (PIRB, 0x0F, Local0)
- ShiftLeft (0x01, Local0, IRA0)
- Return (BUFA)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateWordField (Arg0, 0x01, IRA)
- FindSetRightBit (IRA, Local0)
- Decrement (Local0)
- Store (Local0, PIRB)
- }
- }
-
- Device (LNKC)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x03)
- Method (_STA, 0, NotSerialized)
- {
- And (PIRC, 0x80, Local0)
- If (Local0)
- {
- Return (0x09)
- }
- Else
- {
- Return (0x0B)
- }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Return (PRSC)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Or (PIRC, 0x80, PIRC)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- And (PIRC, 0x0F, Local0)
- ShiftLeft (0x01, Local0, IRA0)
- Return (BUFA)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateWordField (Arg0, 0x01, IRA)
- FindSetRightBit (IRA, Local0)
- Decrement (Local0)
- Store (Local0, PIRC)
- }
- }
-
- Device (LNKD)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x04)
- Method (_STA, 0, NotSerialized)
- {
- And (PIRD, 0x80, Local0)
- If (Local0)
- {
- Return (0x09)
- }
- Else
- {
- Return (0x0B)
- }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Return (PRSD)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Or (PIRD, 0x80, PIRD)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- And (PIRD, 0x0F, Local0)
- ShiftLeft (0x01, Local0, IRA0)
- Return (BUFA)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateWordField (Arg0, 0x01, IRA)
- FindSetRightBit (IRA, Local0)
- Decrement (Local0)
- Store (Local0, PIRD)
- }
- }
-
- Device (LNKE)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x05)
- Method (_STA, 0, NotSerialized)
- {
- And (PIRE, 0x80, Local0)
- If (Local0)
- {
- Return (0x09)
- }
- Else
- {
- Return (0x0B)
- }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Return (PRSE)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Or (PIRE, 0x80, PIRE)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- And (PIRE, 0x0F, Local0)
- ShiftLeft (0x01, Local0, IRA0)
- Return (BUFA)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateWordField (Arg0, 0x01, IRA)
- FindSetRightBit (IRA, Local0)
- Decrement (Local0)
- Store (Local0, PIRE)
- }
- }
-
- Device (LNKF)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x06)
- Method (_STA, 0, NotSerialized)
- {
- And (PIRF, 0x80, Local0)
- If (Local0)
- {
- Return (0x09)
- }
- Else
- {
- Return (0x0B)
- }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Return (PRSF)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Or (PIRF, 0x80, PIRF)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- And (PIRF, 0x0F, Local0)
- ShiftLeft (0x01, Local0, IRA0)
- Return (BUFA)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateWordField (Arg0, 0x01, IRA)
- FindSetRightBit (IRA, Local0)
- Decrement (Local0)
- Store (Local0, PIRF)
- }
- }
-
- Device (LNKG)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x07)
- Method (_STA, 0, NotSerialized)
- {
- And (PIRG, 0x80, Local0)
- If (Local0)
- {
- Return (0x09)
- }
- Else
- {
- Return (0x0B)
- }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Return (PRSG)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Or (PIRG, 0x80, PIRG)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- And (PIRG, 0x0F, Local0)
- ShiftLeft (0x01, Local0, IRA0)
- Return (BUFA)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateWordField (Arg0, 0x01, IRA)
- FindSetRightBit (IRA, Local0)
- Decrement (Local0)
- Store (Local0, PIRG)
- }
- }
-
- Device (LNKH)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x08)
- Method (_STA, 0, NotSerialized)
- {
- And (PIRH, 0x80, Local0)
- If (Local0)
- {
- Return (0x09)
- }
- Else
- {
- Return (0x0B)
- }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Return (PRSH)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Or (PIRH, 0x80, PIRH)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- And (PIRH, 0x0F, Local0)
- ShiftLeft (0x01, Local0, IRA0)
- Return (BUFA)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateWordField (Arg0, 0x01, IRA)
- FindSetRightBit (IRA, Local0)
- Decrement (Local0)
- Store (Local0, PIRH)
- }
- }
- }
-}
-
-
obj-$(CONFIG_GENERATE_MP_TABLE) += mptable.o
obj-$(CONFIG_GENERATE_PIRQ_TABLE) += irq_tables.o
obj-$(CONFIG_GENERATE_ACPI_TABLES) += dsdt.o
+obj-$(CONFIG_GENERATE_ACPI_TABLES) += ssdt2.o
+obj-$(CONFIG_GENERATE_ACPI_TABLES) += ssdt3.o
+obj-$(CONFIG_GENERATE_ACPI_TABLES) += ssdt4.o
+obj-$(CONFIG_GENERATE_ACPI_TABLES) += ssdt5.o
obj-$(CONFIG_GENERATE_ACPI_TABLES) += acpi_tables.o
obj-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.o
-# ./ssdt.o is in northbridge/amd/amdk8/Config.lb
-obj-y += ssdt2.o
-obj-y += ssdt3.o
-obj-y += ssdt4.o
-obj-y += ssdt5.o
-
# This is part of the conversion to init-obj and away from included code.
initobj-y += crt0.o
ifdef POST_EVALUATION
-$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
- iasl -p $(obj)/dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
- mv $(obj)/dsdt.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl
- iasl -p $(obj)/pci2 -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl
- perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' $(obj)/pci2.hex
- mv $(obj)/pci2.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl
- iasl -p $(obj)/pci3 -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl
- perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' $(obj)/pci3.hex
- mv $(obj)/pci3.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl
- iasl -p $(obj)/pci4 -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl
- perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' $(obj)/pci4.hex
- mv $(obj)/pci4.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/ssdt5.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci5.asl
- iasl -p $(obj)/pci5 -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/pci5.asl
- perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' $(obj)/pci5.hex
- mv $(obj)/pci5.hex $@
-
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+//AMD8111
+ Name (APIC, Package (0x04)
+ {
+ Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present
+ Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11},
+ Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12},
+ Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13}
+ })
+
+ Name (PICM, Package (0x04)
+ {
+ Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00},
+ Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00},
+ Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00},
+ Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00}
+ })
+
+ Name (DNCG, Ones)
+
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LEqual (^DNCG, Ones)) {
+ Store (DADD(\_SB.PCI0.SBDN, 0x0001ffff), Local0)
+ // Update the Device Number according to SBDN
+ Store(Local0, Index (DeRefOf (Index (PICM, 0)), 0))
+ Store(Local0, Index (DeRefOf (Index (PICM, 1)), 0))
+ Store(Local0, Index (DeRefOf (Index (PICM, 2)), 0))
+ Store(Local0, Index (DeRefOf (Index (PICM, 3)), 0))
+
+ Store(Local0, Index (DeRefOf (Index (APIC, 0)), 0))
+ Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0))
+ Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0))
+ Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0))
+
+ Store (0x00, ^DNCG)
+
+ }
+
+ If (LNot (PICF)) {
+ Return (PICM)
+ }
+ Else {
+ Return (APIC)
+ }
+ }
+
+ Device (SBC3)
+ {
+ /* acpi smbus it should be 0x00040003 if 8131 present */
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
+ }
+ OperationRegion (PIRQ, PCI_Config, 0x56, 0x02)
+ Field (PIRQ, ByteAcc, Lock, Preserve)
+ {
+ PIBA, 8,
+ PIDC, 8
+ }
+/*
+ OperationRegion (TS3_, PCI_Config, 0xC4, 0x02)
+ Field (TS3_, DWordAcc, NoLock, Preserve)
+ {
+ PTS3, 16
+ }
+*/
+ }
+
+ Device (HPET)
+ {
+ Name (HPT, 0x00)
+ Name (_HID, EisaId ("PNP0103"))
+ Name (_UID, 0x00)
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400)
+ })
+ Return (BUF0)
+ }
+ }
+
+ #include "amd8111_pic.asl"
+
+ #include "amd8111_isa.asl"
+
+ Device (TP2P)
+ {
+ /* 8111 P2P and it should 0x00030000 when 8131 present*/
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(\_SB.PCI0.SBDN, 0x00000000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x08, 0x03 }) }
+ Else { Return (Package (0x02) { 0x08, 0x01 }) }
+ }
+
+ Device (USB0)
+ {
+ Name (_ADR, 0x00000000)
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) }
+ Else { Return (Package (0x02) { 0x0F, 0x01 }) }
+ }
+ }
+
+ Device (USB1)
+ {
+ Name (_ADR, 0x00000001)
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) }
+ Else { Return (Package (0x02) { 0x0F, 0x01 }) }
+ }
+ }
+
+ Name (APIC, Package (0x0C)
+ {
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, //USB
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 },
+
+ Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, //Slot 6
+ Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 },
+ Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 },
+ Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 },
+
+ Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, //Slot 5
+ Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 },
+ Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 },
+ Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 }
+ })
+
+ Name (PICM, Package (0x0C)
+ {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
+
+ Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //Slot 6
+ Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
+
+ Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, //Slot 5
+ Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }
+ })
+
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
+
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+//AMD8111 isa
+
+ Device (ISA)
+ {
+ /* lpc 0x00040000 */
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(\_SB.PCI0.SBDN, 0x00010000))
+ }
+
+ OperationRegion (PIRY, PCI_Config, 0x51, 0x02) // LPC Decode Registers
+ Field (PIRY, ByteAcc, NoLock, Preserve)
+ {
+ Z000, 2, // Parallel Port Range
+ , 1,
+ ECP, 1, // ECP Enable
+ FDC1, 1, // Floppy Drive Controller 1
+ FDC2, 1, // Floppy Drive Controller 2
+ Offset (0x01),
+ Z001, 3, // Serial Port A Range
+ SAEN, 1, // Serial Post A Enabled
+ Z002, 3, // Serial Port B Range
+ SBEN, 1 // Serial Post B Enabled
+ }
+
+ Device (PIC)
+ {
+ Name (_HID, EisaId ("PNP0000"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0020, 0x0020, 0x01, 0x02)
+ IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02)
+ IRQ (Edge, ActiveHigh, Exclusive) {2}
+ })
+ }
+
+ Device (DMA1)
+ {
+ Name (_HID, EisaId ("PNP0200"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0000, 0x0000, 0x01, 0x10)
+ IO (Decode16, 0x0080, 0x0080, 0x01, 0x10)
+ IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20)
+ DMA (Compatibility, NotBusMaster, Transfer16) {4}
+ })
+ }
+
+ Device (TMR)
+ {
+ Name (_HID, EisaId ("PNP0100"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0040, 0x0040, 0x01, 0x04)
+ IRQ (Edge, ActiveHigh, Exclusive) {0}
+ })
+ }
+
+ Device (RTC)
+ {
+ Name (_HID, EisaId ("PNP0B00"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0070, 0x0070, 0x01, 0x06)
+ IRQ (Edge, ActiveHigh, Exclusive) {8}
+ })
+ }
+
+ Device (SPKR)
+ {
+ Name (_HID, EisaId ("PNP0800"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0061, 0x0061, 0x01, 0x01)
+ })
+ }
+
+ Device (COPR)
+ {
+ Name (_HID, EisaId ("PNP0C04"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x10)
+ IRQ (Edge, ActiveHigh, Exclusive) {13}
+ })
+ }
+
+ Device (SYSR)
+ {
+ Name (_HID, EisaId ("PNP0C02"))
+ Name (_UID, 0x00)
+ Name (SYR1, ResourceTemplate ()
+ {
+ IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02) //wrh092302 - added to report Thor NVRAM
+ IO (Decode16, 0x1100, 0x117F, 0x01, 0x80) //wrh092302 - added to report Thor NVRAM
+ IO (Decode16, 0x1180, 0x11FF, 0x01, 0x80)
+ IO (Decode16, 0x0010, 0x0010, 0x01, 0x10)
+ IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E)
+ IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C)
+ IO (Decode16, 0x0062, 0x0062, 0x01, 0x02)
+ IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B)
+ IO (Decode16, 0x0076, 0x0076, 0x01, 0x0A)
+ IO (Decode16, 0x0090, 0x0090, 0x01, 0x10)
+ IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E)
+ IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10)
+ IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
+ IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
+ })
+ Method (_CRS, 0, NotSerialized)
+ {
+ Return (SYR1)
+ }
+ }
+
+ Device (MEM)
+ {
+ Name (_HID, EisaId ("PNP0C02"))
+ Name (_UID, 0x01)
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF
+ Memory32Fixed (ReadWrite, 0x000C0000, 0x00000000) // video BIOS c0000-c8404
+ Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000) // I/O APIC
+ Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM
+ Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000) // Local APIC
+ Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS
+ Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
+ Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
+ Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS
+ Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS
+ })
+ // Read the Video Memory length
+ CreateDWordField (BUF0, 0x14, CLEN)
+ CreateDWordField (BUF0, 0x10, CBAS)
+
+ ShiftLeft (VGA1, 0x09, Local0)
+ Store (Local0, CLEN)
+
+ Return (BUF0)
+ }
+ }
+
+ Device (PS2M)
+ {
+ Name (_HID, EisaId ("PNP0F13"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IRQNoFlags () {12}
+ })
+ Method (_STA, 0, NotSerialized)
+ {
+ And (FLG0, 0x04, Local0)
+ If (LEqual (Local0, 0x04)) { Return (0x0F) }
+ Else { Return (0x00) }
+ }
+ }
+
+ Device (PS2K)
+ {
+ Name (_HID, EisaId ("PNP0303"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+ IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+ IRQNoFlags () {1}
+ })
+ }
+ #include "superio.asl"
+
+ }
+
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+//AMD8111 pic LNKA B C D
+
+ Device (LNKA)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x01)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local0)
+ If (LEqual (Local0, 0x00)) { Return (0x09) } //Disabled
+ Else { Return (0x0B) } //Enabled
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (BUFA, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {3,5,10,11}
+ })
+ Return (BUFA)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Store (0x01, Local3)
+ And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
+ Store (Local1, Local2)
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local1)
+ }
+
+ ShiftLeft (Local3, Local1, Local3)
+ Not (Local3, Local3)
+ And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUFA, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {}
+ })
+ CreateByteField (BUFA, 0x01, IRA1)
+ CreateByteField (BUFA, 0x02, IRA2)
+ Store (0x00, Local3)
+ Store (0x00, Local4)
+ And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
+ If (LNot (LEqual (Local1, 0x00)))
+ { // Routing enable
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local2)
+ ShiftLeft (One, Local2, Local4)
+ }
+ Else
+ {
+ If (LGreater (Local1, 0x00))
+ {
+ ShiftLeft (One, Local1, Local3)
+ }
+ }
+
+ Store (Local3, IRA1)
+ Store (Local4, IRA2)
+ }
+
+ Return (BUFA)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateByteField (Arg0, 0x01, IRA1)
+ CreateByteField (Arg0, 0x02, IRA2)
+ ShiftLeft (IRA2, 0x08, Local0)
+ Or (Local0, IRA1, Local0)
+ Store (0x00, Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ While (LGreater (Local0, 0x00))
+ {
+ Increment (Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ }
+
+ And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
+ Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
+ }
+ }
+
+ Device (LNKB)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x02)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local0)
+ If (LEqual (Local0, 0x00)) { Return (0x09) }
+ Else { Return (0x0B) }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (BUFB, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {3,5,10,11}
+ })
+ Return (BUFB)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Store (0x01, Local3)
+ And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
+ ShiftRight (Local1, 0x04, Local1)
+ Store (Local1, Local2)
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local1)
+ }
+
+ ShiftLeft (Local3, Local1, Local3)
+ Not (Local3, Local3)
+ And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUFB, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {}
+ })
+ CreateByteField (BUFB, 0x01, IRB1)
+ CreateByteField (BUFB, 0x02, IRB2)
+ Store (0x00, Local3)
+ Store (0x00, Local4)
+ And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
+ ShiftRight (Local1, 0x04, Local1)
+ If (LNot (LEqual (Local1, 0x00)))
+ {
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local2)
+ ShiftLeft (One, Local2, Local4)
+ }
+ Else
+ {
+ If (LGreater (Local1, 0x00))
+ {
+ ShiftLeft (One, Local1, Local3)
+ }
+ }
+
+ Store (Local3, IRB1)
+ Store (Local4, IRB2)
+ }
+
+ Return (BUFB)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateByteField (Arg0, 0x01, IRB1)
+ CreateByteField (Arg0, 0x02, IRB2)
+ ShiftLeft (IRB2, 0x08, Local0)
+ Or (Local0, IRB1, Local0)
+ Store (0x00, Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ While (LGreater (Local0, 0x00))
+ {
+ Increment (Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ }
+
+ And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
+ ShiftLeft (Local1, 0x04, Local1)
+ Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
+ }
+ }
+
+ Device (LNKC)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x03)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local0)
+ If (LEqual (Local0, 0x00)) { Return (0x09) }
+ Else { Return (0x0B) }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (BUFA, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {3,5,10,11}
+ })
+ Return (BUFA)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Store (0x01, Local3)
+ And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
+ Store (Local1, Local2)
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local1)
+ }
+
+ ShiftLeft (Local3, Local1, Local3)
+ Not (Local3, Local3)
+ And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUFA, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {}
+ })
+ CreateByteField (BUFA, 0x01, IRA1)
+ CreateByteField (BUFA, 0x02, IRA2)
+ Store (0x00, Local3)
+ Store (0x00, Local4)
+ And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
+ If (LNot (LEqual (Local1, 0x00)))
+ {
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local2)
+ ShiftLeft (One, Local2, Local4)
+ }
+ Else
+ {
+ If (LGreater (Local1, 0x00))
+ {
+ ShiftLeft (One, Local1, Local3)
+ }
+ }
+
+ Store (Local3, IRA1)
+ Store (Local4, IRA2)
+ }
+
+ Return (BUFA)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateByteField (Arg0, 0x01, IRA1)
+ CreateByteField (Arg0, 0x02, IRA2)
+ ShiftLeft (IRA2, 0x08, Local0)
+ Or (Local0, IRA1, Local0)
+ Store (0x00, Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ While (LGreater (Local0, 0x00))
+ {
+ Increment (Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ }
+
+ And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
+ Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
+ }
+ }
+
+ Device (LNKD)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x04)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local0)
+ If (LEqual (Local0, 0x00)) { Return (0x09) }
+ Else { Return (0x0B) }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (BUFB, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {3,5,10,11}
+ })
+ Return (BUFB)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Store (0x01, Local3)
+ And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
+ ShiftRight (Local1, 0x04, Local1)
+ Store (Local1, Local2)
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local1)
+ }
+
+ ShiftLeft (Local3, Local1, Local3)
+ Not (Local3, Local3)
+ And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUFB, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {}
+ })
+ CreateByteField (BUFB, 0x01, IRB1)
+ CreateByteField (BUFB, 0x02, IRB2)
+ Store (0x00, Local3)
+ Store (0x00, Local4)
+ And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
+ ShiftRight (Local1, 0x04, Local1)
+ If (LNot (LEqual (Local1, 0x00)))
+ {
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local2)
+ ShiftLeft (One, Local2, Local4)
+ }
+ Else
+ {
+ If (LGreater (Local1, 0x00))
+ {
+ ShiftLeft (One, Local1, Local3)
+ }
+ }
+
+ Store (Local3, IRB1)
+ Store (Local4, IRB2)
+ }
+
+ Return (BUFB)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateByteField (Arg0, 0x01, IRB1)
+ CreateByteField (Arg0, 0x02, IRB2)
+ ShiftLeft (IRB2, 0x08, Local0)
+ Or (Local0, IRB1, Local0)
+ Store (0x00, Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ While (LGreater (Local0, 0x00))
+ {
+ Increment (Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ }
+
+ And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
+ ShiftLeft (Local1, 0x04, Local1)
+ Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
+ }
+ }
+
+
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+
+ Device (PG0A)
+ {
+ /* 8132 pcix bridge*/
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 0), 0x00000000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
+ Else { Return (Package (0x02) { 0x29, 0x01 }) }
+ }
+
+ Name (APIC, Package (0x14)
+ {
+ // Slot 3 - PIRQ BCDA ---- verified
+ Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 3
+ Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A },
+ Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B },
+ Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 },
+
+ //Slot 4 - PIRQ CDAB ---- verified
+ Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1A }, //?
+ Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
+ Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x18 },
+ Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x19 },
+
+ //Onboard NIC 1 - PIRQ DABC
+ Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1B }, //?
+ Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x18 },
+ Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x19 },
+ Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x1A },
+
+ // NIC 2 - PIRQ ABCD -- verified
+ Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x18 }, //?
+ Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x19 },
+ Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1A },
+ Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1B },
+
+ //SERIAL ATA - PIRQ BCDA
+ Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x19 }, //?
+ Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x1A },
+ Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x1B },
+ Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x18 }
+ })
+ Name (PICM, Package (0x14)
+ {
+ Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 3
+ Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
+
+ Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
+ Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
+
+ Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
+
+ Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
+
+ Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }
+ })
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
+
+ Device (PG0B)
+ {
+ /* 8132 pcix bridge 2 */
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 0), 0x00010000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
+ Else { Return (Package (0x02) { 0x22, 0x01 }) }
+ }
+
+ Name (APIC, Package (0x04)
+ {
+ // Slot A - PIRQ CDAB -- verfied
+ Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1E },// Slot 2
+ Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1F },
+ Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1C },
+ Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1D }
+ })
+ Name (PICM, Package (0x04)
+ {
+ Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },//Slot 2
+ Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
+ Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 }
+ })
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+
+ Device (PG0A)
+ {
+ /* 8132 pcix bridge*/
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 0), 0x00000000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
+ Else { Return (Package (0x02) { 0x29, 0x01 }) }
+ }
+
+ Name (APIC, Package (0x04)
+ {
+ // Slot A - PIRQ BCDA
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B },
+
+ })
+ Name (PICM, Package (0x04)
+ {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
+ })
+
+ Name (DNCG, Ones)
+
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LEqual (^DNCG, Ones)) {
+ Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8
+ Store (0x00, Local1)
+ While (LLess (Local1, 0x04))
+ {
+ // Update the GSI according to HCIN
+ Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
+ Add(Local2, Local0, Local0)
+ Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
+ Increment (Local1)
+ }
+
+ Store (0x00, ^DNCG)
+
+ }
+
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
+
+ Device (PG0B)
+ {
+ /* 8132 pcix bridge 2 */
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 0), 0x00010000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
+ Else { Return (Package (0x02) { 0x22, 0x01 }) }
+ }
+
+ Name (APIC, Package (0x04)
+ {
+ // Slot A - PIRQ ABCD
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 }
+ })
+ Name (PICM, Package (0x04)
+ {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
+ })
+
+ Name (DNCG, Ones)
+
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LEqual (^DNCG, Ones)) {
+ Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8
+ Store (0x00, Local1)
+ While (LLess (Local1, 0x04))
+ {
+ // Update the GSI according to HCIN
+ Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
+ Add(Local2, Local0, Local0)
+ Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
+ Increment (Local1)
+ }
+
+ Store (0x00, ^DNCG)
+
+ }
+
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+
+ Device (PG0A)
+ {
+ /* 8132 pcix bridge*/
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 0), 0x00000000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
+ Else { Return (Package (0x02) { 0x29, 0x01 }) }
+ }
+
+ Name (APIC, Package (0x04)
+ {
+ // Slot A - PIRQ BCDA
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B },
+
+ })
+ Name (PICM, Package (0x04)
+ {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
+ })
+
+ Name (DNCG, Ones)
+
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LEqual (^DNCG, Ones)) {
+ Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14
+ Store (0x00, Local1)
+ While (LLess (Local1, 0x04))
+ {
+ // Update the GSI according to HCIN
+ Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
+ Add(Local2, Local0, Local0)
+ Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
+ Increment (Local1)
+ }
+
+ Store (0x00, ^DNCG)
+
+ }
+
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
+
+ Device (PG0B)
+ {
+ /* 8132 pcix bridge 2 */
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 0), 0x00010000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
+ Else { Return (Package (0x02) { 0x22, 0x01 }) }
+ }
+
+ Name (APIC, Package (0x04)
+ {
+ // Slot A - PIRQ ABCD
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 }
+ })
+ Name (PICM, Package (0x04)
+ {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
+ })
+
+ Name (DNCG, Ones)
+
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LEqual (^DNCG, Ones)) {
+ Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14
+ Store (0x00, Local1)
+ While (LLess (Local1, 0x04))
+ {
+ // Update the GSI according to HCIN
+ Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
+ Add(Local2, Local0, Local0)
+ Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
+ Increment (Local1)
+ }
+
+ Store (0x00, ^DNCG)
+
+ }
+
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
--- /dev/null
+// AMD8151
+ Device (AGPB)
+ {
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 0), 0x00010000))
+ }
+
+ Name (APIC, Package (0x04)
+ {
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 },
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 }
+ })
+ Name (PICM, Package (0x04)
+ {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
+ })
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
+
--- /dev/null
+/*
+ * Copyright 2006 AMD
+ */
+
+ Device (HTXA)
+ {
+ /* HTX */
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 0), 0x00000000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
+ Else { Return (Package (0x02) { 0x29, 0x01 }) }
+ }
+
+ }
+
--- /dev/null
+ #include "amd8111.asl" //real SB at first
+ #include "amd8131.asl"
--- /dev/null
+ #include "amd8132_2.asl"
--- /dev/null
+ #include "amd8151.asl"
--- /dev/null
+ #include "amd8131_2.asl"
--- /dev/null
+ #include "htx_no_ioapic.asl"
--- /dev/null
+// #include "w83627hf.asl"
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440)
+{
+ Scope (_PR)
+ {
+ Processor (CPU0, 0x00, 0x0000C010, 0x06) {}
+ Processor (CPU1, 0x01, 0x00000000, 0x00) {}
+ Processor (CPU2, 0x02, 0x00000000, 0x00) {}
+ Processor (CPU3, 0x03, 0x00000000, 0x00) {}
+
+ }
+
+ Method (FWSO, 0, NotSerialized) { }
+
+ Name (_S0, Package (0x04) { 0x00, 0x00, 0x00, 0x00 })
+ Name (_S1, Package (0x04) { 0x01, 0x01, 0x01, 0x01 })
+ Name (_S3, Package (0x04) { 0x05, 0x05, 0x05, 0x05 })
+ Name (_S5, Package (0x04) { 0x07, 0x07, 0x07, 0x07 })
+
+ Scope (_SB)
+ {
+ Device (PCI0)
+ {
+ /* BUS0 root bus */
+
+ External (BUSN)
+ External (MMIO)
+ External (PCIO)
+ External (SBLK)
+ External (TOM1)
+ External (HCLK)
+ External (SBDN)
+ External (HCDN)
+ External (CBST)
+
+
+ Name (_HID, EisaId ("PNP0A03"))
+ Name (_ADR, 0x00180000)
+ Name (_UID, 0x01)
+
+ Name (HCIN, 0x00) // HC1
+
+ Method (_BBN, 0, NotSerialized)
+ {
+ Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh
+ IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h
+ IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h
+
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Address Space Granularity
+ 0x8100, // Address Range Minimum
+ 0xFFFF, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x7F00,,,
+ , TypeStatic) //8100h-FFFFh
+
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Address Space Granularity
+ 0x000C0000, // Address Range Minimum
+ 0x00000000, // Address Range Maximum
+ 0x00000000, // Address Translation Offset
+ 0x00000000,,,
+ , AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh
+
+ Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF
+
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Address Space Granularity
+ 0x0000, // Address Range Minimum
+ 0x03AF, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x03B0,,,
+ , TypeStatic) //0-CF7h
+
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Address Space Granularity
+ 0x03E0, // Address Range Minimum
+ 0x0CF7, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x0918,,,
+ , TypeStatic) //0-CF7h
+ })
+ \_SB.OSTP ()
+ CreateDWordField (BUF0, 0x3E, VLEN)
+ CreateDWordField (BUF0, 0x36, VMAX)
+ CreateDWordField (BUF0, 0x32, VMIN)
+ ShiftLeft (VGA1, 0x09, Local0)
+ Add (VMIN, Local0, VMAX)
+ Decrement (VMAX)
+ Store (Local0, VLEN)
+ Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
+ Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
+ Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
+ Return (Local3)
+ }
+
+ #include "acpi/pci0_hc.asl"
+
+ }
+ Device (PCI1)
+ {
+ Name (_HID, "PNP0A03")
+ Name (_ADR, 0x00000000)
+ Name (_UID, 0x02)
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (\_SB.PCI0.CBST)
+ }
+ Name (_BBN, 0x00)
+ }
+
+
+ }
+
+ Scope (_GPE)
+ {
+ Method (_L08, 0, NotSerialized)
+ {
+ Notify (\_SB.PCI0, 0x02) //PME# Wakeup
+ }
+
+ Method (_L0F, 0, NotSerialized)
+ {
+ Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup
+ }
+
+ Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B
+ {
+ Notify (\_SB.PCI0.PG0B, 0x02)
+ }
+
+ Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A
+ {
+ Notify (\_SB.PCI0.PG0A, 0x02)
+ }
+ }
+
+ Method (_PTS, 1, NotSerialized)
+ {
+ Or (Arg0, 0xF0, Local0)
+ Store (Local0, DBG1)
+ }
+/*
+ Method (_WAK, 1, NotSerialized)
+ {
+ Or (Arg0, 0xE0, Local0)
+ Store (Local0, DBG1)
+ }
+*/
+ Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode
+ Method (_PIC, 1, NotSerialized) //PIC Flag and Interface Method
+ {
+ Store (Arg0, PICF)
+ }
+
+ OperationRegion (DEBG, SystemIO, 0x80, 0x01)
+ Field (DEBG, ByteAcc, Lock, Preserve)
+ {
+ DBG1, 8
+ }
+
+ OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04)
+ Field (EXTM, WordAcc, Lock, Preserve)
+ {
+ AMEM, 32
+ }
+
+ OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01)
+ Field (VGAM, ByteAcc, Lock, Preserve)
+ {
+ VGA1, 8
+ }
+
+ OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
+ Field (GRAM, ByteAcc, Lock, Preserve)
+ {
+ Offset (0x10),
+ FLG0, 8
+ }
+
+ OperationRegion (GSTS, SystemIO, 0xC028, 0x02)
+ Field (GSTS, ByteAcc, NoLock, Preserve)
+ {
+ , 4,
+ IRQR, 1
+ }
+
+ OperationRegion (Z007, SystemIO, 0x21, 0x01)
+ Field (Z007, ByteAcc, NoLock, Preserve)
+ {
+ Z008, 8
+ }
+
+ OperationRegion (Z009, SystemIO, 0xA1, 0x01)
+ Field (Z009, ByteAcc, NoLock, Preserve)
+ {
+ Z00A, 8
+ }
+
+ #include "northbridge/amd/amdk8/amdk8_util.asl"
+
+}
+
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-//AMD8111
- Name (APIC, Package (0x04)
- {
- Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present
- Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11},
- Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12},
- Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13}
- })
-
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00},
- Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00},
- Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00},
- Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00}
- })
-
- Name (DNCG, Ones)
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LEqual (^DNCG, Ones)) {
- Store (DADD(\_SB.PCI0.SBDN, 0x0001ffff), Local0)
- // Update the Device Number according to SBDN
- Store(Local0, Index (DeRefOf (Index (PICM, 0)), 0))
- Store(Local0, Index (DeRefOf (Index (PICM, 1)), 0))
- Store(Local0, Index (DeRefOf (Index (PICM, 2)), 0))
- Store(Local0, Index (DeRefOf (Index (PICM, 3)), 0))
-
- Store(Local0, Index (DeRefOf (Index (APIC, 0)), 0))
- Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0))
- Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0))
- Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0))
-
- Store (0x00, ^DNCG)
-
- }
-
- If (LNot (PICF)) {
- Return (PICM)
- }
- Else {
- Return (APIC)
- }
- }
-
- Device (SBC3)
- {
- /* acpi smbus it should be 0x00040003 if 8131 present */
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
- }
- OperationRegion (PIRQ, PCI_Config, 0x56, 0x02)
- Field (PIRQ, ByteAcc, Lock, Preserve)
- {
- PIBA, 8,
- PIDC, 8
- }
-/*
- OperationRegion (TS3_, PCI_Config, 0xC4, 0x02)
- Field (TS3_, DWordAcc, NoLock, Preserve)
- {
- PTS3, 16
- }
-*/
- }
-
- Device (HPET)
- {
- Name (HPT, 0x00)
- Name (_HID, EisaId ("PNP0103"))
- Name (_UID, 0x00)
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0F)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400)
- })
- Return (BUF0)
- }
- }
-
- Include ("amd8111_pic.asl")
-
- Include ("amd8111_isa.asl")
-
- Device (TP2P)
- {
- /* 8111 P2P and it should 0x00030000 when 8131 present*/
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(\_SB.PCI0.SBDN, 0x00000000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x08, 0x03 }) }
- Else { Return (Package (0x02) { 0x08, 0x01 }) }
- }
-
- Device (USB0)
- {
- Name (_ADR, 0x00000000)
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) }
- Else { Return (Package (0x02) { 0x0F, 0x01 }) }
- }
- }
-
- Device (USB1)
- {
- Name (_ADR, 0x00000001)
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) }
- Else { Return (Package (0x02) { 0x0F, 0x01 }) }
- }
- }
-
- Name (APIC, Package (0x0C)
- {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, //USB
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 },
-
- Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, //Slot 6
- Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 },
-
- Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, //Slot 5
- Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 },
- Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 },
- Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 }
- })
-
- Name (PICM, Package (0x0C)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
-
- Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //Slot 6
- Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
-
- Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, //Slot 5
- Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }
- })
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
-
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-//AMD8111 isa
-
- Device (ISA)
- {
- /* lpc 0x00040000 */
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(\_SB.PCI0.SBDN, 0x00010000))
- }
-
- OperationRegion (PIRY, PCI_Config, 0x51, 0x02) // LPC Decode Registers
- Field (PIRY, ByteAcc, NoLock, Preserve)
- {
- Z000, 2, // Parallel Port Range
- , 1,
- ECP, 1, // ECP Enable
- FDC1, 1, // Floppy Drive Controller 1
- FDC2, 1, // Floppy Drive Controller 2
- Offset (0x01),
- Z001, 3, // Serial Port A Range
- SAEN, 1, // Serial Post A Enabled
- Z002, 3, // Serial Port B Range
- SBEN, 1 // Serial Post B Enabled
- }
-
- Device (PIC)
- {
- Name (_HID, EisaId ("PNP0000"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0020, 0x0020, 0x01, 0x02)
- IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02)
- IRQ (Edge, ActiveHigh, Exclusive) {2}
- })
- }
-
- Device (DMA1)
- {
- Name (_HID, EisaId ("PNP0200"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0000, 0x0000, 0x01, 0x10)
- IO (Decode16, 0x0080, 0x0080, 0x01, 0x10)
- IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20)
- DMA (Compatibility, NotBusMaster, Transfer16) {4}
- })
- }
-
- Device (TMR)
- {
- Name (_HID, EisaId ("PNP0100"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0040, 0x0040, 0x01, 0x04)
- IRQ (Edge, ActiveHigh, Exclusive) {0}
- })
- }
-
- Device (RTC)
- {
- Name (_HID, EisaId ("PNP0B00"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0070, 0x0070, 0x01, 0x06)
- IRQ (Edge, ActiveHigh, Exclusive) {8}
- })
- }
-
- Device (SPKR)
- {
- Name (_HID, EisaId ("PNP0800"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0061, 0x0061, 0x01, 0x01)
- })
- }
-
- Device (COPR)
- {
- Name (_HID, EisaId ("PNP0C04"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x10)
- IRQ (Edge, ActiveHigh, Exclusive) {13}
- })
- }
-
- Device (SYSR)
- {
- Name (_HID, EisaId ("PNP0C02"))
- Name (_UID, 0x00)
- Name (SYR1, ResourceTemplate ()
- {
- IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02) //wrh092302 - added to report Thor NVRAM
- IO (Decode16, 0x1100, 0x117F, 0x01, 0x80) //wrh092302 - added to report Thor NVRAM
- IO (Decode16, 0x1180, 0x11FF, 0x01, 0x80)
- IO (Decode16, 0x0010, 0x0010, 0x01, 0x10)
- IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E)
- IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C)
- IO (Decode16, 0x0062, 0x0062, 0x01, 0x02)
- IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B)
- IO (Decode16, 0x0076, 0x0076, 0x01, 0x0A)
- IO (Decode16, 0x0090, 0x0090, 0x01, 0x10)
- IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E)
- IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10)
- IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
- IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
- })
- Method (_CRS, 0, NotSerialized)
- {
- Return (SYR1)
- }
- }
-
- Device (MEM)
- {
- Name (_HID, EisaId ("PNP0C02"))
- Name (_UID, 0x01)
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF
- Memory32Fixed (ReadWrite, 0x000C0000, 0x00000000) // video BIOS c0000-c8404
- Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000) // I/O APIC
- Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM
- Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000) // Local APIC
- Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS
- })
- // Read the Video Memory length
- CreateDWordField (BUF0, 0x14, CLEN)
- CreateDWordField (BUF0, 0x10, CBAS)
-
- ShiftLeft (VGA1, 0x09, Local0)
- Store (Local0, CLEN)
-
- Return (BUF0)
- }
- }
-
- Device (PS2M)
- {
- Name (_HID, EisaId ("PNP0F13"))
- Name (_CRS, ResourceTemplate ()
- {
- IRQNoFlags () {12}
- })
- Method (_STA, 0, NotSerialized)
- {
- And (FLG0, 0x04, Local0)
- If (LEqual (Local0, 0x04)) { Return (0x0F) }
- Else { Return (0x00) }
- }
- }
-
- Device (PS2K)
- {
- Name (_HID, EisaId ("PNP0303"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {1}
- })
- }
- Include ("superio.asl")
-
- }
-
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-//AMD8111 pic LNKA B C D
-
- Device (LNKA)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x01)
- Method (_STA, 0, NotSerialized)
- {
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local0)
- If (LEqual (Local0, 0x00)) { Return (0x09) } //Disabled
- Else { Return (0x0B) } //Enabled
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {3,5,10,11}
- })
- Return (BUFA)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Store (0x01, Local3)
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
- Store (Local1, Local2)
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local1)
- }
-
- ShiftLeft (Local3, Local1, Local3)
- Not (Local3, Local3)
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {}
- })
- CreateByteField (BUFA, 0x01, IRA1)
- CreateByteField (BUFA, 0x02, IRA2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
- If (LNot (LEqual (Local1, 0x00)))
- { // Routing enable
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRA1)
- Store (Local4, IRA2)
- }
-
- Return (BUFA)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateByteField (Arg0, 0x01, IRA1)
- CreateByteField (Arg0, 0x02, IRA2)
- ShiftLeft (IRA2, 0x08, Local0)
- Or (Local0, IRA1, Local0)
- Store (0x00, Local1)
- ShiftRight (Local0, 0x01, Local0)
- While (LGreater (Local0, 0x00))
- {
- Increment (Local1)
- ShiftRight (Local0, 0x01, Local0)
- }
-
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
- Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
- }
- }
-
- Device (LNKB)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x02)
- Method (_STA, 0, NotSerialized)
- {
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local0)
- If (LEqual (Local0, 0x00)) { Return (0x09) }
- Else { Return (0x0B) }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFB, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {3,5,10,11}
- })
- Return (BUFB)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Store (0x01, Local3)
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- Store (Local1, Local2)
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local1)
- }
-
- ShiftLeft (Local3, Local1, Local3)
- Not (Local3, Local3)
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFB, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {}
- })
- CreateByteField (BUFB, 0x01, IRB1)
- CreateByteField (BUFB, 0x02, IRB2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- If (LNot (LEqual (Local1, 0x00)))
- {
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRB1)
- Store (Local4, IRB2)
- }
-
- Return (BUFB)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateByteField (Arg0, 0x01, IRB1)
- CreateByteField (Arg0, 0x02, IRB2)
- ShiftLeft (IRB2, 0x08, Local0)
- Or (Local0, IRB1, Local0)
- Store (0x00, Local1)
- ShiftRight (Local0, 0x01, Local0)
- While (LGreater (Local0, 0x00))
- {
- Increment (Local1)
- ShiftRight (Local0, 0x01, Local0)
- }
-
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
- ShiftLeft (Local1, 0x04, Local1)
- Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
- }
- }
-
- Device (LNKC)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x03)
- Method (_STA, 0, NotSerialized)
- {
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local0)
- If (LEqual (Local0, 0x00)) { Return (0x09) }
- Else { Return (0x0B) }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {3,5,10,11}
- })
- Return (BUFA)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Store (0x01, Local3)
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
- Store (Local1, Local2)
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local1)
- }
-
- ShiftLeft (Local3, Local1, Local3)
- Not (Local3, Local3)
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {}
- })
- CreateByteField (BUFA, 0x01, IRA1)
- CreateByteField (BUFA, 0x02, IRA2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
- If (LNot (LEqual (Local1, 0x00)))
- {
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRA1)
- Store (Local4, IRA2)
- }
-
- Return (BUFA)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateByteField (Arg0, 0x01, IRA1)
- CreateByteField (Arg0, 0x02, IRA2)
- ShiftLeft (IRA2, 0x08, Local0)
- Or (Local0, IRA1, Local0)
- Store (0x00, Local1)
- ShiftRight (Local0, 0x01, Local0)
- While (LGreater (Local0, 0x00))
- {
- Increment (Local1)
- ShiftRight (Local0, 0x01, Local0)
- }
-
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
- Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
- }
- }
-
- Device (LNKD)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x04)
- Method (_STA, 0, NotSerialized)
- {
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local0)
- If (LEqual (Local0, 0x00)) { Return (0x09) }
- Else { Return (0x0B) }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFB, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {3,5,10,11}
- })
- Return (BUFB)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Store (0x01, Local3)
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- Store (Local1, Local2)
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local1)
- }
-
- ShiftLeft (Local3, Local1, Local3)
- Not (Local3, Local3)
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFB, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {}
- })
- CreateByteField (BUFB, 0x01, IRB1)
- CreateByteField (BUFB, 0x02, IRB2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- If (LNot (LEqual (Local1, 0x00)))
- {
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRB1)
- Store (Local4, IRB2)
- }
-
- Return (BUFB)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateByteField (Arg0, 0x01, IRB1)
- CreateByteField (Arg0, 0x02, IRB2)
- ShiftLeft (IRB2, 0x08, Local0)
- Or (Local0, IRB1, Local0)
- Store (0x00, Local1)
- ShiftRight (Local0, 0x01, Local0)
- While (LGreater (Local0, 0x00))
- {
- Increment (Local1)
- ShiftRight (Local0, 0x01, Local0)
- }
-
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
- ShiftLeft (Local1, 0x04, Local1)
- Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
- }
- }
-
-
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-
- Device (PG0A)
- {
- /* 8132 pcix bridge*/
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00000000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
- Else { Return (Package (0x02) { 0x29, 0x01 }) }
- }
-
- Name (APIC, Package (0x14)
- {
- // Slot 3 - PIRQ BCDA ---- verified
- Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 3
- Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A },
- Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B },
- Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 },
-
- //Slot 4 - PIRQ CDAB ---- verified
- Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1A }, //?
- Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
- Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x18 },
- Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x19 },
-
- //Onboard NIC 1 - PIRQ DABC
- Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1B }, //?
- Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x18 },
- Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x19 },
- Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x1A },
-
- // NIC 2 - PIRQ ABCD -- verified
- Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x18 }, //?
- Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x19 },
- Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1A },
- Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1B },
-
- //SERIAL ATA - PIRQ BCDA
- Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x19 }, //?
- Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x1A },
- Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x1B },
- Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x18 }
- })
- Name (PICM, Package (0x14)
- {
- Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 3
- Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
-
- Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
-
- Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
-
- Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
-
- Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }
- })
- Method (_PRT, 0, NotSerialized)
- {
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
-
- Device (PG0B)
- {
- /* 8132 pcix bridge 2 */
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00010000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
- Else { Return (Package (0x02) { 0x22, 0x01 }) }
- }
-
- Name (APIC, Package (0x04)
- {
- // Slot A - PIRQ CDAB -- verfied
- Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1E },// Slot 2
- Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1F },
- Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1C },
- Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1D }
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },//Slot 2
- Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 }
- })
- Method (_PRT, 0, NotSerialized)
- {
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-
- Device (PG0A)
- {
- /* 8132 pcix bridge*/
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00000000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
- Else { Return (Package (0x02) { 0x29, 0x01 }) }
- }
-
- Name (APIC, Package (0x04)
- {
- // Slot A - PIRQ BCDA
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B },
-
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
- })
-
- Name (DNCG, Ones)
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LEqual (^DNCG, Ones)) {
- Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8
- Store (0x00, Local1)
- While (LLess (Local1, 0x04))
- {
- // Update the GSI according to HCIN
- Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
- Add(Local2, Local0, Local0)
- Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
- Increment (Local1)
- }
-
- Store (0x00, ^DNCG)
-
- }
-
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
-
- Device (PG0B)
- {
- /* 8132 pcix bridge 2 */
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00010000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
- Else { Return (Package (0x02) { 0x22, 0x01 }) }
- }
-
- Name (APIC, Package (0x04)
- {
- // Slot A - PIRQ ABCD
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 }
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
- })
-
- Name (DNCG, Ones)
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LEqual (^DNCG, Ones)) {
- Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8
- Store (0x00, Local1)
- While (LLess (Local1, 0x04))
- {
- // Update the GSI according to HCIN
- Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
- Add(Local2, Local0, Local0)
- Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
- Increment (Local1)
- }
-
- Store (0x00, ^DNCG)
-
- }
-
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-
- Device (PG0A)
- {
- /* 8132 pcix bridge*/
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00000000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
- Else { Return (Package (0x02) { 0x29, 0x01 }) }
- }
-
- Name (APIC, Package (0x04)
- {
- // Slot A - PIRQ BCDA
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B },
-
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
- })
-
- Name (DNCG, Ones)
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LEqual (^DNCG, Ones)) {
- Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14
- Store (0x00, Local1)
- While (LLess (Local1, 0x04))
- {
- // Update the GSI according to HCIN
- Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
- Add(Local2, Local0, Local0)
- Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
- Increment (Local1)
- }
-
- Store (0x00, ^DNCG)
-
- }
-
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
-
- Device (PG0B)
- {
- /* 8132 pcix bridge 2 */
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00010000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
- Else { Return (Package (0x02) { 0x22, 0x01 }) }
- }
-
- Name (APIC, Package (0x04)
- {
- // Slot A - PIRQ ABCD
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 }
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
- })
-
- Name (DNCG, Ones)
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LEqual (^DNCG, Ones)) {
- Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14
- Store (0x00, Local1)
- While (LLess (Local1, 0x04))
- {
- // Update the GSI according to HCIN
- Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
- Add(Local2, Local0, Local0)
- Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
- Increment (Local1)
- }
-
- Store (0x00, ^DNCG)
-
- }
-
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
+++ /dev/null
-// AMD8151
- Device (AGPB)
- {
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00010000))
- }
-
- Name (APIC, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 },
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 }
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
- })
- Method (_PRT, 0, NotSerialized)
- {
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
-
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440)
-{
- Scope (_PR)
- {
- Processor (CPU0, 0x00, 0x0000C010, 0x06) {}
- Processor (CPU1, 0x01, 0x00000000, 0x00) {}
- Processor (CPU2, 0x02, 0x00000000, 0x00) {}
- Processor (CPU3, 0x03, 0x00000000, 0x00) {}
-
- }
-
- Method (FWSO, 0, NotSerialized) { }
-
- Name (_S0, Package (0x04) { 0x00, 0x00, 0x00, 0x00 })
- Name (_S1, Package (0x04) { 0x01, 0x01, 0x01, 0x01 })
- Name (_S3, Package (0x04) { 0x05, 0x05, 0x05, 0x05 })
- Name (_S5, Package (0x04) { 0x07, 0x07, 0x07, 0x07 })
-
- Scope (_SB)
- {
- Device (PCI0)
- {
- /* BUS0 root bus */
-
- External (BUSN)
- External (MMIO)
- External (PCIO)
- External (SBLK)
- External (TOM1)
- External (HCLK)
- External (SBDN)
- External (HCDN)
- External (CBST)
-
-
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00180000)
- Name (_UID, 0x01)
-
- Name (HCIN, 0x00) // HC1
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh
- IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h
- IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h
-
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x8100, // Address Range Minimum
- 0xFFFF, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x7F00,,,
- , TypeStatic) //8100h-FFFFh
-
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, // Address Space Granularity
- 0x000C0000, // Address Range Minimum
- 0x00000000, // Address Range Maximum
- 0x00000000, // Address Translation Offset
- 0x00000000,,,
- , AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh
-
- Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF
-
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x03AF, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x03B0,,,
- , TypeStatic) //0-CF7h
-
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x03E0, // Address Range Minimum
- 0x0CF7, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0918,,,
- , TypeStatic) //0-CF7h
- })
- \_SB.OSTP ()
- CreateDWordField (BUF0, 0x3E, VLEN)
- CreateDWordField (BUF0, 0x36, VMAX)
- CreateDWordField (BUF0, 0x32, VMIN)
- ShiftLeft (VGA1, 0x09, Local0)
- Add (VMIN, Local0, VMAX)
- Decrement (VMAX)
- Store (Local0, VLEN)
- Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
- Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
- Return (Local3)
- }
-
- Include ("pci0_hc.asl")
-
- }
- Device (PCI1)
- {
- Name (_HID, "PNP0A03")
- Name (_ADR, 0x00000000)
- Name (_UID, 0x02)
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.PCI0.CBST)
- }
- Name (_BBN, 0x00)
- }
-
-
- }
-
- Scope (_GPE)
- {
- Method (_L08, 0, NotSerialized)
- {
- Notify (\_SB.PCI0, 0x02) //PME# Wakeup
- }
-
- Method (_L0F, 0, NotSerialized)
- {
- Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup
- }
-
- Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B
- {
- Notify (\_SB.PCI0.PG0B, 0x02)
- }
-
- Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A
- {
- Notify (\_SB.PCI0.PG0A, 0x02)
- }
- }
-
- Method (_PTS, 1, NotSerialized)
- {
- Or (Arg0, 0xF0, Local0)
- Store (Local0, DBG1)
- }
-/*
- Method (_WAK, 1, NotSerialized)
- {
- Or (Arg0, 0xE0, Local0)
- Store (Local0, DBG1)
- }
-*/
- Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode
- Method (_PIC, 1, NotSerialized) //PIC Flag and Interface Method
- {
- Store (Arg0, PICF)
- }
-
- OperationRegion (DEBG, SystemIO, 0x80, 0x01)
- Field (DEBG, ByteAcc, Lock, Preserve)
- {
- DBG1, 8
- }
-
- OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04)
- Field (EXTM, WordAcc, Lock, Preserve)
- {
- AMEM, 32
- }
-
- OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01)
- Field (VGAM, ByteAcc, Lock, Preserve)
- {
- VGA1, 8
- }
-
- OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
- Field (GRAM, ByteAcc, Lock, Preserve)
- {
- Offset (0x10),
- FLG0, 8
- }
-
- OperationRegion (GSTS, SystemIO, 0xC028, 0x02)
- Field (GSTS, ByteAcc, NoLock, Preserve)
- {
- , 4,
- IRQR, 1
- }
-
- OperationRegion (Z007, SystemIO, 0x21, 0x01)
- Field (Z007, ByteAcc, NoLock, Preserve)
- {
- Z008, 8
- }
-
- OperationRegion (Z009, SystemIO, 0xA1, 0x01)
- Field (Z009, ByteAcc, NoLock, Preserve)
- {
- Z00A, 8
- }
-
- Include ("../../../../../src/northbridge/amd/amdk8/amdk8_util.asl")
-
-}
-
+++ /dev/null
-/*
- * Copyright 2006 AMD
- */
-
- Device (HTXA)
- {
- /* HTX */
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00000000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
- Else { Return (Package (0x02) { 0x29, 0x01 }) }
- }
-
- }
-
+++ /dev/null
- Include ("amd8111.asl") //real SB at first
- Include ("amd8131.asl")
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
-{
- Scope (_SB)
- {
- External (DADD, MethodObj)
- External (GHCE, MethodObj)
- External (GHCN, MethodObj)
- External (GHCL, MethodObj)
- External (GHCD, MethodObj)
- External (GNUS, MethodObj)
- External (GIOR, MethodObj)
- External (GMEM, MethodObj)
- External (GWBN, MethodObj)
- External (GBUS, MethodObj)
-
- External (PICF)
-
- External (\_SB.PCI0.LNKA, DeviceObj)
- External (\_SB.PCI0.LNKB, DeviceObj)
- External (\_SB.PCI0.LNKC, DeviceObj)
- External (\_SB.PCI0.LNKD, DeviceObj)
-
- Device (PCIX)
- {
-
- // BUS ? Second HT Chain
- Name (HCIN, 0xcc) // HC2 0x01
-
- Name (_UID, 0xdd) // HC 0x03
-
- Name (_HID, "PNP0A03")
-
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0
- {
- Return (DADD(GHCN(HCIN), 0x00000000))
- }
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.GHCE(HCIN))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () { })
- Store( GHCN(HCIN), Local4)
- Store( GHCL(HCIN), Local5)
-
- Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
- Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
- Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
- Return (Local3)
- }
-
- Include ("pci2_hc.asl")
- }
- }
-
-}
-
+++ /dev/null
- Include ("amd8132_2.asl")
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
-{
- Scope (_SB)
- {
- External (DADD, MethodObj)
- External (GHCE, MethodObj)
- External (GHCN, MethodObj)
- External (GHCL, MethodObj)
- External (GHCD, MethodObj)
- External (GNUS, MethodObj)
- External (GIOR, MethodObj)
- External (GMEM, MethodObj)
- External (GWBN, MethodObj)
- External (GBUS, MethodObj)
-
- External (PICF)
-
- External (\_SB.PCI0.LNKA, DeviceObj)
- External (\_SB.PCI0.LNKB, DeviceObj)
- External (\_SB.PCI0.LNKC, DeviceObj)
- External (\_SB.PCI0.LNKD, DeviceObj)
-
- Device (PCIX)
- {
-
- // BUS ? Second HT Chain
- Name (HCIN, 0xcc) // HC2 0x01
-
- Name (_UID, 0xdd) // HC 0x03
-
- Name (_HID, "PNP0A03")
-
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0
- {
- Return (DADD(GHCN(HCIN), 0x00000000))
- }
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.GHCE(HCIN))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () { })
- Store( GHCN(HCIN), Local4)
- Store( GHCL(HCIN), Local5)
-
- Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
- Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
- Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
- Return (Local3)
- }
-
- Include ("pci3_hc.asl")
- }
- }
-
-}
-
+++ /dev/null
- Include ("amd8151.asl")
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
-{
- Scope (_SB)
- {
- External (DADD, MethodObj)
- External (GHCE, MethodObj)
- External (GHCN, MethodObj)
- External (GHCL, MethodObj)
- External (GHCD, MethodObj)
- External (GNUS, MethodObj)
- External (GIOR, MethodObj)
- External (GMEM, MethodObj)
- External (GWBN, MethodObj)
- External (GBUS, MethodObj)
-
- External (PICF)
-
- External (\_SB.PCI0.LNKA, DeviceObj)
- External (\_SB.PCI0.LNKB, DeviceObj)
- External (\_SB.PCI0.LNKC, DeviceObj)
- External (\_SB.PCI0.LNKD, DeviceObj)
-
- Device (PCIX)
- {
-
- // BUS ? Second HT Chain
- Name (HCIN, 0xcc) // HC2 0x01
-
- Name (_UID, 0xdd) // HC 0x03
-
- Name (_HID, "PNP0A03")
-
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0
- {
- Return (DADD(GHCN(HCIN), 0x00000000))
- }
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.GHCE(HCIN))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () { })
- Store( GHCN(HCIN), Local4)
- Store( GHCL(HCIN), Local5)
-
- Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
- Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
- Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
- Return (Local3)
- }
-
- Include ("pci4_hc.asl")
- }
- }
-
-}
-
+++ /dev/null
- Include ("amd8131_2.asl")
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
-{
- Scope (_SB)
- {
- External (DADD, MethodObj)
- External (GHCE, MethodObj)
- External (GHCN, MethodObj)
- External (GHCL, MethodObj)
- External (GHCD, MethodObj)
- External (GNUS, MethodObj)
- External (GIOR, MethodObj)
- External (GMEM, MethodObj)
- External (GWBN, MethodObj)
- External (GBUS, MethodObj)
-
- External (PICF)
-
- External (\_SB.PCI0.LNKA, DeviceObj)
- External (\_SB.PCI0.LNKB, DeviceObj)
- External (\_SB.PCI0.LNKC, DeviceObj)
- External (\_SB.PCI0.LNKD, DeviceObj)
-
- Device (PCIX)
- {
-
- // BUS ? Second HT Chain
- Name (HCIN, 0xcc) // HC2 0x01
-
- Name (_UID, 0xdd) // HC 0x03
-
- Name (_HID, "PNP0A03")
-
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0
- {
- Return (DADD(GHCN(HCIN), 0x00000000))
- }
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.GHCE(HCIN))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () { })
- Store( GHCN(HCIN), Local4)
- Store( GHCL(HCIN), Local5)
-
- Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
- Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
- Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
- Return (Local3)
- }
-
- Include ("pci5_hc.asl")
- }
- }
-
-}
-
+++ /dev/null
- Include ("htx_no_ioapic.asl")
+++ /dev/null
-// Include ("w83627hf.asl")
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
+{
+ Scope (_SB)
+ {
+ External (DADD, MethodObj)
+ External (GHCE, MethodObj)
+ External (GHCN, MethodObj)
+ External (GHCL, MethodObj)
+ External (GHCD, MethodObj)
+ External (GNUS, MethodObj)
+ External (GIOR, MethodObj)
+ External (GMEM, MethodObj)
+ External (GWBN, MethodObj)
+ External (GBUS, MethodObj)
+
+ External (PICF)
+
+ External (\_SB.PCI0.LNKA, DeviceObj)
+ External (\_SB.PCI0.LNKB, DeviceObj)
+ External (\_SB.PCI0.LNKC, DeviceObj)
+ External (\_SB.PCI0.LNKD, DeviceObj)
+
+ Device (PCIX)
+ {
+
+ // BUS ? Second HT Chain
+ Name (HCIN, 0xcc) // HC2 0x01
+
+ Name (_UID, 0xdd) // HC 0x03
+
+ Name (_HID, "PNP0A03")
+
+ Method (_ADR, 0, NotSerialized) //Fake bus should be 0
+ {
+ Return (DADD(GHCN(HCIN), 0x00000000))
+ }
+
+ Method (_BBN, 0, NotSerialized)
+ {
+ Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (\_SB.GHCE(HCIN))
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate () { })
+ Store( GHCN(HCIN), Local4)
+ Store( GHCL(HCIN), Local5)
+
+ Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
+ Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
+ Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
+ Return (Local3)
+ }
+
+ #include "acpi/pci2_hc.asl"
+ }
+ }
+
+}
+
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
+{
+ Scope (_SB)
+ {
+ External (DADD, MethodObj)
+ External (GHCE, MethodObj)
+ External (GHCN, MethodObj)
+ External (GHCL, MethodObj)
+ External (GHCD, MethodObj)
+ External (GNUS, MethodObj)
+ External (GIOR, MethodObj)
+ External (GMEM, MethodObj)
+ External (GWBN, MethodObj)
+ External (GBUS, MethodObj)
+
+ External (PICF)
+
+ External (\_SB.PCI0.LNKA, DeviceObj)
+ External (\_SB.PCI0.LNKB, DeviceObj)
+ External (\_SB.PCI0.LNKC, DeviceObj)
+ External (\_SB.PCI0.LNKD, DeviceObj)
+
+ Device (PCIX)
+ {
+
+ // BUS ? Second HT Chain
+ Name (HCIN, 0xcc) // HC2 0x01
+
+ Name (_UID, 0xdd) // HC 0x03
+
+ Name (_HID, "PNP0A03")
+
+ Method (_ADR, 0, NotSerialized) //Fake bus should be 0
+ {
+ Return (DADD(GHCN(HCIN), 0x00000000))
+ }
+
+ Method (_BBN, 0, NotSerialized)
+ {
+ Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (\_SB.GHCE(HCIN))
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate () { })
+ Store( GHCN(HCIN), Local4)
+ Store( GHCL(HCIN), Local5)
+
+ Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
+ Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
+ Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
+ Return (Local3)
+ }
+
+ #include "acpi/pci3_hc.asl"
+ }
+ }
+
+}
+
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
+{
+ Scope (_SB)
+ {
+ External (DADD, MethodObj)
+ External (GHCE, MethodObj)
+ External (GHCN, MethodObj)
+ External (GHCL, MethodObj)
+ External (GHCD, MethodObj)
+ External (GNUS, MethodObj)
+ External (GIOR, MethodObj)
+ External (GMEM, MethodObj)
+ External (GWBN, MethodObj)
+ External (GBUS, MethodObj)
+
+ External (PICF)
+
+ External (\_SB.PCI0.LNKA, DeviceObj)
+ External (\_SB.PCI0.LNKB, DeviceObj)
+ External (\_SB.PCI0.LNKC, DeviceObj)
+ External (\_SB.PCI0.LNKD, DeviceObj)
+
+ Device (PCIX)
+ {
+
+ // BUS ? Second HT Chain
+ Name (HCIN, 0xcc) // HC2 0x01
+
+ Name (_UID, 0xdd) // HC 0x03
+
+ Name (_HID, "PNP0A03")
+
+ Method (_ADR, 0, NotSerialized) //Fake bus should be 0
+ {
+ Return (DADD(GHCN(HCIN), 0x00000000))
+ }
+
+ Method (_BBN, 0, NotSerialized)
+ {
+ Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (\_SB.GHCE(HCIN))
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate () { })
+ Store( GHCN(HCIN), Local4)
+ Store( GHCL(HCIN), Local5)
+
+ Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
+ Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
+ Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
+ Return (Local3)
+ }
+
+ #include "acpi/pci4_hc.asl"
+ }
+ }
+
+}
+
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
+{
+ Scope (_SB)
+ {
+ External (DADD, MethodObj)
+ External (GHCE, MethodObj)
+ External (GHCN, MethodObj)
+ External (GHCL, MethodObj)
+ External (GHCD, MethodObj)
+ External (GNUS, MethodObj)
+ External (GIOR, MethodObj)
+ External (GMEM, MethodObj)
+ External (GWBN, MethodObj)
+ External (GBUS, MethodObj)
+
+ External (PICF)
+
+ External (\_SB.PCI0.LNKA, DeviceObj)
+ External (\_SB.PCI0.LNKB, DeviceObj)
+ External (\_SB.PCI0.LNKC, DeviceObj)
+ External (\_SB.PCI0.LNKD, DeviceObj)
+
+ Device (PCIX)
+ {
+
+ // BUS ? Second HT Chain
+ Name (HCIN, 0xcc) // HC2 0x01
+
+ Name (_UID, 0xdd) // HC 0x03
+
+ Name (_HID, "PNP0A03")
+
+ Method (_ADR, 0, NotSerialized) //Fake bus should be 0
+ {
+ Return (DADD(GHCN(HCIN), 0x00000000))
+ }
+
+ Method (_BBN, 0, NotSerialized)
+ {
+ Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (\_SB.GHCE(HCIN))
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate () { })
+ Store( GHCN(HCIN), Local4)
+ Store( GHCL(HCIN), Local5)
+
+ Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
+ Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
+ Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
+ Return (Local3)
+ }
+
+ #include "acpi/pci5_hc.asl"
+ }
+ }
+
+}
+
ifdef POST_EVALUATION
-$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
- $(CPP) -D__ACPI__ -P $(CPPFLAGS) -include $(obj)/config.h -I$(src)/mainboard/$(MAINBOARDDIR) $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl -o $(obj)/dsdt.asl
- iasl -p $(obj)/dsdt -tc $(obj)/dsdt.asl
- mv $(obj)/dsdt.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
ifdef POST_EVALUATION
-$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/acpi/dsdt.asl
- iasl -p $(obj)/dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/acpi/dsdt.asl
- mv $(obj)/dsdt.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
0x00010001
)
{
- Include ("debug.asl")
+ #include "debug.asl"
}
*/
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* DefinitionBlock Statement */
-DefinitionBlock (
- "dsdt.aml", /* Output filename */
- "DSDT", /* Signature */
- 0x02, /* DSDT Revision, needs to be 2 for 64bit */
- "COREv2", /* OEMID */
- "COREBOOT", /* TABLE ID */
- 0x00010001 /* OEM Revision */
- )
-{ /* Start of ASL file */
- /* Include ("debug.asl") */ /* Include global debug methods if needed */
-
- /* Data to be patched by the BIOS during POST */
- /* FIXME the patching is not done yet! */
- /* Memory related values */
- Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
- Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
- Name(PBLN, 0x0) /* Length of BIOS area */
-
- Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
- Name(HPBA, 0xFED00000) /* Base address of HPET table */
-
- Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
-
- /* USB overcurrent mapping pins. */
- Name(UOM0, 0)
- Name(UOM1, 2)
- Name(UOM2, 0)
- Name(UOM3, 7)
- Name(UOM4, 2)
- Name(UOM5, 2)
- Name(UOM6, 6)
- Name(UOM7, 2)
- Name(UOM8, 6)
- Name(UOM9, 6)
-
- /* Some global data */
- Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
- Name(OSV, Ones) /* Assume nothing */
- Name(PMOD, One) /* Assume APIC */
-
- /* PIC IRQ mapping registers, C00h-C01h */
- OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
- Field(PRQM, ByteAcc, NoLock, Preserve) {
- PRQI, 0x00000008,
- PRQD, 0x00000008, /* Offset: 1h */
- }
- IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
- PINA, 0x00000008, /* Index 0 */
- PINB, 0x00000008, /* Index 1 */
- PINC, 0x00000008, /* Index 2 */
- PIND, 0x00000008, /* Index 3 */
- AINT, 0x00000008, /* Index 4 */
- SINT, 0x00000008, /* Index 5 */
- , 0x00000008, /* Index 6 */
- AAUD, 0x00000008, /* Index 7 */
- AMOD, 0x00000008, /* Index 8 */
- PINE, 0x00000008, /* Index 9 */
- PINF, 0x00000008, /* Index A */
- PING, 0x00000008, /* Index B */
- PINH, 0x00000008, /* Index C */
- }
-
- /* PCI Error control register */
- OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
- Field(PERC, ByteAcc, NoLock, Preserve) {
- SENS, 0x00000001,
- PENS, 0x00000001,
- SENE, 0x00000001,
- PENE, 0x00000001,
- }
-
- /* Client Management index/data registers */
- OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
- Field(CMT, ByteAcc, NoLock, Preserve) {
- CMTI, 8,
- /* Client Management Data register */
- G64E, 1,
- G64O, 1,
- G32O, 2,
- , 2,
- GPSL, 2,
- }
-
- /* GPM Port register */
- OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
- Field(GPT, ByteAcc, NoLock, Preserve) {
- GPB0,1,
- GPB1,1,
- GPB2,1,
- GPB3,1,
- GPB4,1,
- GPB5,1,
- GPB6,1,
- GPB7,1,
- }
-
- /* Flash ROM program enable register */
- OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
- Field(FRE, ByteAcc, NoLock, Preserve) {
- , 0x00000006,
- FLRE, 0x00000001,
- }
-
- /* PM2 index/data registers */
- OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
- Field(PM2R, ByteAcc, NoLock, Preserve) {
- PM2I, 0x00000008,
- PM2D, 0x00000008,
- }
-
- /* Power Management I/O registers */
- OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
- Field(PIOR, ByteAcc, NoLock, Preserve) {
- PIOI, 0x00000008,
- PIOD, 0x00000008,
- }
- IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
- Offset(0x00), /* MiscControl */
- , 1,
- T1EE, 1,
- T2EE, 1,
- Offset(0x01), /* MiscStatus */
- , 1,
- T1E, 1,
- T2E, 1,
- Offset(0x04), /* SmiWakeUpEventEnable3 */
- , 7,
- SSEN, 1,
- Offset(0x07), /* SmiWakeUpEventStatus3 */
- , 7,
- CSSM, 1,
- Offset(0x10), /* AcpiEnable */
- , 6,
- PWDE, 1,
- Offset(0x1C), /* ProgramIoEnable */
- , 3,
- MKME, 1,
- IO3E, 1,
- IO2E, 1,
- IO1E, 1,
- IO0E, 1,
- Offset(0x1D), /* IOMonitorStatus */
- , 3,
- MKMS, 1,
- IO3S, 1,
- IO2S, 1,
- IO1S, 1,
- IO0S,1,
- Offset(0x20), /* AcpiPmEvtBlk */
- APEB, 16,
- Offset(0x36), /* GEvtLevelConfig */
- , 6,
- ELC6, 1,
- ELC7, 1,
- Offset(0x37), /* GPMLevelConfig0 */
- , 3,
- PLC0, 1,
- PLC1, 1,
- PLC2, 1,
- PLC3, 1,
- PLC8, 1,
- Offset(0x38), /* GPMLevelConfig1 */
- , 1,
- PLC4, 1,
- PLC5, 1,
- , 1,
- PLC6, 1,
- PLC7, 1,
- Offset(0x3B), /* PMEStatus1 */
- GP0S, 1,
- GM4S, 1,
- GM5S, 1,
- APS, 1,
- GM6S, 1,
- GM7S, 1,
- GP2S, 1,
- STSS, 1,
- Offset(0x55), /* SoftPciRst */
- SPRE, 1,
- , 1,
- , 1,
- PNAT, 1,
- PWMK, 1,
- PWNS, 1,
-
- /* Offset(0x61), */ /* Options_1 */
- /* ,7, */
- /* R617,1, */
-
- Offset(0x65), /* UsbPMControl */
- , 4,
- URRE, 1,
- Offset(0x68), /* MiscEnable68 */
- , 3,
- TMTE, 1,
- , 1,
- Offset(0x92), /* GEVENTIN */
- , 7,
- E7IS, 1,
- Offset(0x96), /* GPM98IN */
- G8IS, 1,
- G9IS, 1,
- Offset(0x9A), /* EnhanceControl */
- ,7,
- HPDE, 1,
- Offset(0xA8), /* PIO7654Enable */
- IO4E, 1,
- IO5E, 1,
- IO6E, 1,
- IO7E, 1,
- Offset(0xA9), /* PIO7654Status */
- IO4S, 1,
- IO5S, 1,
- IO6S, 1,
- IO7S, 1,
- }
-
- /* PM1 Event Block
- * First word is PM1_Status, Second word is PM1_Enable
- */
- OperationRegion(P1EB, SystemIO, APEB, 0x04)
- Field(P1EB, ByteAcc, NoLock, Preserve) {
- TMST, 1,
- , 3,
- BMST, 1,
- GBST, 1,
- Offset(0x01),
- PBST, 1,
- , 1,
- RTST, 1,
- , 3,
- PWST, 1,
- SPWS, 1,
- Offset(0x02),
- TMEN, 1,
- , 4,
- GBEN, 1,
- Offset(0x03),
- PBEN, 1,
- , 1,
- RTEN, 1,
- , 3,
- PWDA, 1,
- }
-
- Scope(\_SB) {
-
- /* PCIe Configuration Space for 16 busses */
- OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
- Field(PCFG, ByteAcc, NoLock, Preserve) {
- /* Byte offsets are computed using the following technique:
- * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
- * The 8 comes from 8 functions per device, and 4096 bytes per function config space
- */
- Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */
- STB5, 32,
- Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
- PT0D, 1,
- PT1D, 1,
- PT2D, 1,
- PT3D, 1,
- PT4D, 1,
- PT5D, 1,
- PT6D, 1,
- PT7D, 1,
- PT8D, 1,
- PT9D, 1,
- Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
- SBIE, 1,
- SBME, 1,
- Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
- SBRI, 8,
- Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
- SBB1, 32,
- Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
- ,14,
- P92E, 1, /* Port92 decode enable */
- }
-
- OperationRegion(SB5, SystemMemory, STB5, 0x1000)
- Field(SB5, AnyAcc, NoLock, Preserve)
- {
- /* Port 0 */
- Offset(0x120), /* Port 0 Task file status */
- P0ER, 1,
- , 2,
- P0DQ, 1,
- , 3,
- P0BY, 1,
- Offset(0x128), /* Port 0 Serial ATA status */
- P0DD, 4,
- , 4,
- P0IS, 4,
- Offset(0x12C), /* Port 0 Serial ATA control */
- P0DI, 4,
- Offset(0x130), /* Port 0 Serial ATA error */
- , 16,
- P0PR, 1,
-
- /* Port 1 */
- offset(0x1A0), /* Port 1 Task file status */
- P1ER, 1,
- , 2,
- P1DQ, 1,
- , 3,
- P1BY, 1,
- Offset(0x1A8), /* Port 1 Serial ATA status */
- P1DD, 4,
- , 4,
- P1IS, 4,
- Offset(0x1AC), /* Port 1 Serial ATA control */
- P1DI, 4,
- Offset(0x1B0), /* Port 1 Serial ATA error */
- , 16,
- P1PR, 1,
-
- /* Port 2 */
- Offset(0x220), /* Port 2 Task file status */
- P2ER, 1,
- , 2,
- P2DQ, 1,
- , 3,
- P2BY, 1,
- Offset(0x228), /* Port 2 Serial ATA status */
- P2DD, 4,
- , 4,
- P2IS, 4,
- Offset(0x22C), /* Port 2 Serial ATA control */
- P2DI, 4,
- Offset(0x230), /* Port 2 Serial ATA error */
- , 16,
- P2PR, 1,
-
- /* Port 3 */
- Offset(0x2A0), /* Port 3 Task file status */
- P3ER, 1,
- , 2,
- P3DQ, 1,
- , 3,
- P3BY, 1,
- Offset(0x2A8), /* Port 3 Serial ATA status */
- P3DD, 4,
- , 4,
- P3IS, 4,
- Offset(0x2AC), /* Port 3 Serial ATA control */
- P3DI, 4,
- Offset(0x2B0), /* Port 3 Serial ATA error */
- , 16,
- P3PR, 1,
- }
- }
-
- Include ("routing.asl")
-
- Scope(\_SB) {
-
- Method(CkOT, 0){
-
- if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */
-
- if(CondRefOf(\_OSI,Local1))
- {
- Store(1, OSTP) /* Assume some form of XP */
- if (\_OSI("Windows 2006")) /* Vista */
- {
- Store(2, OSTP)
- }
- } else {
- If(WCMP(\_OS,"Linux")) {
- Store(3, OSTP) /* Linux */
- } Else {
- Store(4, OSTP) /* Gotta be WinCE */
- }
- }
- Return(OSTP)
- }
-
- Method(_PIC, 0x01, NotSerialized)
- {
- If (Arg0)
- {
- \_SB.CIRQ()
- }
- Store(Arg0, PMOD)
- }
-
- Method(CIRQ, 0x00, NotSerialized)
- {
- Store(0, PINA)
- Store(0, PINB)
- Store(0, PINC)
- Store(0, PIND)
- Store(0, PINE)
- Store(0, PINF)
- Store(0, PING)
- Store(0, PINH)
- }
-
- Name(IRQB, ResourceTemplate(){
- IRQ(Level,ActiveLow,Shared){15}
- })
-
- Name(IRQP, ResourceTemplate(){
- IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
- })
-
- Name(PITF, ResourceTemplate(){
- IRQ(Level,ActiveLow,Exclusive){9}
- })
-
- Device(INTA) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 1)
-
- Method(_STA, 0) {
- if (PINA) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTA._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKA\\_DIS\n") */
- Store(0, PINA)
- } /* End Method(_SB.INTA._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKA\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTA._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKA\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINA, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTA._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKA\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINA)
- } /* End Method(_SB.INTA._SRS) */
- } /* End Device(INTA) */
-
- Device(INTB) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 2)
-
- Method(_STA, 0) {
- if (PINB) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTB._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKB\\_DIS\n") */
- Store(0, PINB)
- } /* End Method(_SB.INTB._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKB\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTB._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKB\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINB, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTB._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKB\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINB)
- } /* End Method(_SB.INTB._SRS) */
- } /* End Device(INTB) */
-
- Device(INTC) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 3)
-
- Method(_STA, 0) {
- if (PINC) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTC._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKC\\_DIS\n") */
- Store(0, PINC)
- } /* End Method(_SB.INTC._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKC\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTC._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKC\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINC, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTC._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKC\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINC)
- } /* End Method(_SB.INTC._SRS) */
- } /* End Device(INTC) */
-
- Device(INTD) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 4)
-
- Method(_STA, 0) {
- if (PIND) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTD._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKD\\_DIS\n") */
- Store(0, PIND)
- } /* End Method(_SB.INTD._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKD\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTD._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKD\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PIND, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTD._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKD\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PIND)
- } /* End Method(_SB.INTD._SRS) */
- } /* End Device(INTD) */
-
- Device(INTE) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 5)
-
- Method(_STA, 0) {
- if (PINE) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTE._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKE\\_DIS\n") */
- Store(0, PINE)
- } /* End Method(_SB.INTE._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKE\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTE._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKE\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINE, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTE._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKE\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINE)
- } /* End Method(_SB.INTE._SRS) */
- } /* End Device(INTE) */
-
- Device(INTF) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 6)
-
- Method(_STA, 0) {
- if (PINF) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTF._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKF\\_DIS\n") */
- Store(0, PINF)
- } /* End Method(_SB.INTF._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKF\\_PRS\n") */
- Return(PITF)
- } /* Method(_SB.INTF._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKF\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINF, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTF._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKF\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINF)
- } /* End Method(_SB.INTF._SRS) */
- } /* End Device(INTF) */
-
- Device(INTG) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 7)
-
- Method(_STA, 0) {
- if (PING) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTG._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKG\\_DIS\n") */
- Store(0, PING)
- } /* End Method(_SB.INTG._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKG\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTG._CRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKG\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PING, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTG._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKG\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PING)
- } /* End Method(_SB.INTG._SRS) */
- } /* End Device(INTG) */
-
- Device(INTH) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 8)
-
- Method(_STA, 0) {
- if (PINH) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTH._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKH\\_DIS\n") */
- Store(0, PINH)
- } /* End Method(_SB.INTH._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKH\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTH._CRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKH\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINH, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTH._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKH\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINH)
- } /* End Method(_SB.INTH._SRS) */
- } /* End Device(INTH) */
-
- } /* End Scope(_SB) */
-
-
- /* Supported sleep states: */
- Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
-
- If (LAnd(SSFG, 0x01)) {
- Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
- }
- If (LAnd(SSFG, 0x02)) {
- Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
- }
- If (LAnd(SSFG, 0x04)) {
- Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
- }
- If (LAnd(SSFG, 0x08)) {
- Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
- }
-
- Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
-
- Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
- Name(CSMS, 0) /* Current System State */
-
- /* Wake status package */
- Name(WKST,Package(){Zero, Zero})
-
- /*
- * \_PTS - Prepare to Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2, etc
- *
- * Exit:
- * -none-
- *
- * The _PTS control method is executed at the beginning of the sleep process
- * for S1-S5. The sleeping value is passed to the _PTS control method. This
- * control method may be executed a relatively long time before entering the
- * sleep state and the OS may abort the operation without notification to
- * the ACPI driver. This method cannot modify the configuration or power
- * state of any device in the system.
- */
- Method(\_PTS, 1) {
- /* DBGO("\\_PTS\n") */
- /* DBGO("From S0 to S") */
- /* DBGO(Arg0) */
- /* DBGO("\n") */
-
- /* Don't allow PCIRST# to reset USB */
- if (LEqual(Arg0,3)){
- Store(0,URRE)
- }
-
- /* Clear sleep SMI status flag and enable sleep SMI trap. */
- /*Store(One, CSSM)
- Store(One, SSEN)*/
-
- /* On older chips, clear PciExpWakeDisEn */
- /*if (LLessEqual(\_SB.SBRI, 0x13)) {
- * Store(0,\_SB.PWDE)
- *}
- */
-
- /* Clear wake status structure. */
- Store(0, Index(WKST,0))
- Store(0, Index(WKST,1))
- \_SB.PCI0.SIOS (Arg0)
- } /* End Method(\_PTS) */
-
- /*
- * The following method results in a "not a valid reserved NameSeg"
- * warning so I have commented it out for the duration. It isn't
- * used, so it could be removed.
- *
- *
- * \_GTS OEM Going To Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * -none-
- *
- * Method(\_GTS, 1) {
- * DBGO("\\_GTS\n")
- * DBGO("From S0 to S")
- * DBGO(Arg0)
- * DBGO("\n")
- * }
- */
-
- /*
- * \_BFS OEM Back From Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * -none-
- */
- Method(\_BFS, 1) {
- /* DBGO("\\_BFS\n") */
- /* DBGO("From S") */
- /* DBGO(Arg0) */
- /* DBGO(" to S0\n") */
- }
-
- /*
- * \_WAK System Wake method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * Return package of 2 DWords
- * Dword 1 - Status
- * 0x00000000 wake succeeded
- * 0x00000001 Wake was signaled but failed due to lack of power
- * 0x00000002 Wake was signaled but failed due to thermal condition
- * Dword 2 - Power Supply state
- * if non-zero the effective S-state the power supply entered
- */
- Method(\_WAK, 1) {
- /* DBGO("\\_WAK\n") */
- /* DBGO("From S") */
- /* DBGO(Arg0) */
- /* DBGO(" to S0\n") */
-
- /* Re-enable HPET */
- Store(1,HPDE)
-
- /* Restore PCIRST# so it resets USB */
- if (LEqual(Arg0,3)){
- Store(1,URRE)
- }
-
- /* Arbitrarily clear PciExpWakeStatus */
- Store(PWST, PWST)
-
- /* if(DeRefOf(Index(WKST,0))) {
- * Store(0, Index(WKST,1))
- * } else {
- * Store(Arg0, Index(WKST,1))
- * }
- */
- \_SB.PCI0.SIOW (Arg0)
- Return(WKST)
- } /* End Method(\_WAK) */
-
- Scope(\_GPE) { /* Start Scope GPE */
- /* General event 0 */
- /* Method(_L00) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 1 */
- /* Method(_L01) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 2 */
- /* Method(_L02) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 3 */
- Method(_L03) {
- /* DBGO("\\_GPE\\_L00\n") */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* General event 4 */
- /* Method(_L04) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 5 */
- /* Method(_L05) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 6 - Used for GPM6, moved to USB.asl */
- /* Method(_L06) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 7 - Used for GPM7, moved to USB.asl */
- /* Method(_L07) {
- * DBGO("\\_GPE\\_L07\n")
- * }
- */
-
- /* Legacy PM event */
- Method(_L08) {
- /* DBGO("\\_GPE\\_L08\n") */
- }
-
- /* Temp warning (TWarn) event */
- Method(_L09) {
- /* DBGO("\\_GPE\\_L09\n") */
- Notify (\_TZ.TZ00, 0x80)
- }
-
- /* Reserved */
- /* Method(_L0A) {
- * DBGO("\\_GPE\\_L0A\n")
- * }
- */
-
- /* USB controller PME# */
- Method(_L0B) {
- /* DBGO("\\_GPE\\_L0B\n") */
- Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* AC97 controller PME# */
- /* Method(_L0C) {
- * DBGO("\\_GPE\\_L0C\n")
- * }
- */
-
- /* OtherTherm PME# */
- /* Method(_L0D) {
- * DBGO("\\_GPE\\_L0D\n")
- * }
- */
-
- /* GPM9 SCI event - Moved to USB.asl */
- /* Method(_L0E) {
- * DBGO("\\_GPE\\_L0E\n")
- * }
- */
-
- /* PCIe HotPlug event */
- /* Method(_L0F) {
- * DBGO("\\_GPE\\_L0F\n")
- * }
- */
-
- /* ExtEvent0 SCI event */
- Method(_L10) {
- /* DBGO("\\_GPE\\_L10\n") */
- }
-
-
- /* ExtEvent1 SCI event */
- Method(_L11) {
- /* DBGO("\\_GPE\\_L11\n") */
- }
-
- /* PCIe PME# event */
- /* Method(_L12) {
- * DBGO("\\_GPE\\_L12\n")
- * }
- */
-
- /* GPM0 SCI event - Moved to USB.asl */
- /* Method(_L13) {
- * DBGO("\\_GPE\\_L13\n")
- * }
- */
-
- /* GPM1 SCI event - Moved to USB.asl */
- /* Method(_L14) {
- * DBGO("\\_GPE\\_L14\n")
- * }
- */
-
- /* GPM2 SCI event - Moved to USB.asl */
- /* Method(_L15) {
- * DBGO("\\_GPE\\_L15\n")
- * }
- */
-
- /* GPM3 SCI event - Moved to USB.asl */
- /* Method(_L16) {
- * DBGO("\\_GPE\\_L16\n")
- * }
- */
-
- /* GPM8 SCI event - Moved to USB.asl */
- /* Method(_L17) {
- * DBGO("\\_GPE\\_L17\n")
- * }
- */
-
- /* GPIO0 or GEvent8 event */
- Method(_L18) {
- /* DBGO("\\_GPE\\_L18\n") */
- Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* GPM4 SCI event - Moved to USB.asl */
- /* Method(_L19) {
- * DBGO("\\_GPE\\_L19\n")
- * }
- */
-
- /* GPM5 SCI event - Moved to USB.asl */
- /* Method(_L1A) {
- * DBGO("\\_GPE\\_L1A\n")
- * }
- */
-
- /* Azalia SCI event */
- Method(_L1B) {
- /* DBGO("\\_GPE\\_L1B\n") */
- Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* GPM6 SCI event - Reassigned to _L06 */
- /* Method(_L1C) {
- * DBGO("\\_GPE\\_L1C\n")
- * }
- */
-
- /* GPM7 SCI event - Reassigned to _L07 */
- /* Method(_L1D) {
- * DBGO("\\_GPE\\_L1D\n")
- * }
- */
-
- /* GPIO2 or GPIO66 SCI event */
- /* Method(_L1E) {
- * DBGO("\\_GPE\\_L1E\n")
- * }
- */
-
- /* SATA SCI event - Moved to sata.asl */
- /* Method(_L1F) {
- * DBGO("\\_GPE\\_L1F\n")
- * }
- */
-
- } /* End Scope GPE */
-
- Include ("usb.asl")
-
- /* South Bridge */
- Scope(\_SB) { /* Start \_SB scope */
- Include ("globutil.asl") /* global utility methods expected within the \_SB scope */
-
- /* _SB.PCI0 */
- /* Note: Only need HID on Primary Bus */
- Device(PCI0) {
- External (TOM1)
- External (TOM2)
- Name(_HID, EISAID("PNP0A03"))
- Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
- Method(_BBN, 0) { /* Bus number = 0 */
- Return(0)
- }
- Method(_STA, 0) {
- /* DBGO("\\_SB\\PCI0\\_STA\n") */
- Return(0x0B) /* Status is visible */
- }
-
- Method(_PRT,0) {
- If(PMOD){ Return(APR0) } /* APIC mode */
- Return (PR0) /* PIC Mode */
- } /* end _PRT */
-
- /* Describe the Northbridge devices */
- Device(AMRT) {
- Name(_ADR, 0x00000000)
- } /* end AMRT */
-
- /* The internal GFX bridge */
- Device(AGPB) {
- Name(_ADR, 0x00010000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- Return (APR1)
- }
- } /* end AGPB */
-
- /* The external GFX bridge */
- Device(PBR2) {
- Name(_ADR, 0x00020000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS2) } /* APIC mode */
- Return (PS2) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR2 */
-
- /* Dev3 is also an external GFX bridge, not used in Herring */
-
- Device(PBR4) {
- Name(_ADR, 0x00040000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS4) } /* APIC mode */
- Return (PS4) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR4 */
-
- Device(PBR5) {
- Name(_ADR, 0x00050000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS5) } /* APIC mode */
- Return (PS5) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR5 */
-
- Device(PBR6) {
- Name(_ADR, 0x00060000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS6) } /* APIC mode */
- Return (PS6) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR6 */
-
- /* The onboard EtherNet chip */
- Device(PBR7) {
- Name(_ADR, 0x00070000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS7) } /* APIC mode */
- Return (PS7) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR7 */
-
-
- /* PCI slot 1, 2, 3 */
- Device(PIBR) {
- Name(_ADR, 0x00140004)
- Name(_PRW, Package() {0x18, 4})
-
- Method(_PRT, 0) {
- Return (PCIB)
- }
- }
-
- /* Describe the Southbridge devices */
- Device(STCR) {
- Name(_ADR, 0x00120000)
- Include ("sata.asl")
- } /* end STCR */
-
- Device(UOH1) {
- Name(_ADR, 0x00130000)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH1 */
-
- Device(UOH2) {
- Name(_ADR, 0x00130001)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH2 */
-
- Device(UOH3) {
- Name(_ADR, 0x00130002)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH3 */
-
- Device(UOH4) {
- Name(_ADR, 0x00130003)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH4 */
-
- Device(UOH5) {
- Name(_ADR, 0x00130004)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH5 */
-
- Device(UEH1) {
- Name(_ADR, 0x00130005)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UEH1 */
-
- Device(SBUS) {
- Name(_ADR, 0x00140000)
- } /* end SBUS */
-
- /* Primary (and only) IDE channel */
- Device(IDEC) {
- Name(_ADR, 0x00140001)
- Include ("ide.asl")
- } /* end IDEC */
-
- Device(AZHD) {
- Name(_ADR, 0x00140002)
- OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
- Field(AZPD, AnyAcc, NoLock, Preserve) {
- offset (0x42),
- NSDI, 1,
- NSDO, 1,
- NSEN, 1,
- offset (0x44),
- IPCR, 4,
- offset (0x54),
- PWST, 2,
- , 6,
- PMEB, 1,
- , 6,
- PMST, 1,
- offset (0x62),
- MMCR, 1,
- offset (0x64),
- MMLA, 32,
- offset (0x68),
- MMHA, 32,
- offset (0x6C),
- MMDT, 16,
- }
-
- Method(_INI) {
- If(LEqual(OSTP,3)){ /* If we are running Linux */
- Store(zero, NSEN)
- Store(one, NSDO)
- Store(one, NSDI)
- }
- }
- } /* end AZHD */
-
- Device(LIBR) {
- Name(_ADR, 0x00140003)
- /* Method(_INI) {
- * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
- } */ /* End Method(_SB.SBRDG._INI) */
-
- /* Real Time Clock Device */
- Device(RTC0) {
- Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){8}
- IO(Decode16,0x0070, 0x0070, 0, 2)
- /* IO(Decode16,0x0070, 0x0070, 0, 4) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
-
- Device(TMR) { /* Timer */
- Name(_HID,EISAID("PNP0100")) /* System Timer */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){0}
- IO(Decode16, 0x0040, 0x0040, 0, 4)
- /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
-
- Device(SPKR) { /* Speaker */
- Name(_HID,EISAID("PNP0800")) /* AT style speaker */
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x0061, 0x0061, 0, 1)
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
-
- Device(PIC) {
- Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){2}
- IO(Decode16,0x0020, 0x0020, 0, 2)
- IO(Decode16,0x00A0, 0x00A0, 0, 2)
- /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
- /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
-
- Device(MAD) { /* 8257 DMA */
- Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
- Name(_CRS, ResourceTemplate() {
- DMA(Compatibility,BusMaster,Transfer8){4}
- IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
- IO(Decode16, 0x0081, 0x0081, 0x10, 0x03)
- IO(Decode16, 0x0087, 0x0087, 0x10, 0x01)
- IO(Decode16, 0x0089, 0x0089, 0x10, 0x03)
- IO(Decode16, 0x008F, 0x008F, 0x10, 0x01)
- IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
- }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
- } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
-
- Device(COPR) {
- Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
- IRQNoFlags(){13}
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
-
- Device(HPTM) {
- Name(_HID,EISAID("PNP0103"))
- Name(CRS,ResourceTemplate() {
- Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
- })
- Method(_STA, 0) {
- Return(0x0F) /* sata is visible */
- }
- Method(_CRS, 0) {
- CreateDwordField(CRS, ^HPT._BAS, HPBA)
- Store(HPBA, HPBA)
- Return(CRS)
- }
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
- } /* end LIBR */
-
- Device(HPBR) {
- Name(_ADR, 0x00140004)
- } /* end HostPciBr */
-
- Device(ACAD) {
- Name(_ADR, 0x00140005)
- } /* end Ac97audio */
-
- Device(ACMD) {
- Name(_ADR, 0x00140006)
- } /* end Ac97modem */
-
- /* ITE IT8712F Support */
- OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
- Field (IOID, ByteAcc, NoLock, Preserve)
- {
- SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */
- }
-
- IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
- {
- Offset (0x07),
- LDN, 8, /* Logical Device Number */
- Offset (0x20),
- CID1, 8, /* Chip ID Byte 1, 0x87 */
- CID2, 8, /* Chip ID Byte 2, 0x12 */
- Offset (0x30),
- ACTR, 8, /* Function activate */
- Offset (0xF0),
- APC0, 8, /* APC/PME Event Enable Register */
- APC1, 8, /* APC/PME Status Register */
- APC2, 8, /* APC/PME Control Register 1 */
- APC3, 8, /* Environment Controller Special Configuration Register */
- APC4, 8 /* APC/PME Control Register 2 */
- }
-
- /* Enter the IT8712F MB PnP Mode */
- Method (EPNP)
- {
- Store(0x87, SIOI)
- Store(0x01, SIOI)
- Store(0x55, SIOI)
- Store(0x55, SIOI) /* IT8712F magic number */
- }
- /* Exit the IT8712F MB PnP Mode */
- Method (XPNP)
- {
- Store (0x02, SIOI)
- Store (0x02, SIOD)
- }
-
- /*
- * Keyboard PME is routed to SB600 Gevent3. We can wake
- * up the system by pressing the key.
- */
- Method (SIOS, 1)
- {
- /* We only enable KBD PME for S5. */
- If (LLess (Arg0, 0x05))
- {
- EPNP()
- /* DBGO("IT8712F\n") */
-
- Store (0x4, LDN)
- Store (One, ACTR) /* Enable EC */
- /*
- Store (0x4, LDN)
- Store (0x04, APC4)
- */ /* falling edge. which mode? Not sure. */
-
- Store (0x4, LDN)
- Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
- Store (0x4, LDN)
- Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
-
- XPNP()
- }
- }
- Method (SIOW, 1)
- {
- EPNP()
- Store (0x4, LDN)
- Store (Zero, APC0) /* disable keyboard PME */
- Store (0x4, LDN)
- Store (0xFF, APC1) /* clear keyboard PME status */
- XPNP()
- }
-
- Name(CRES, ResourceTemplate() {
- IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0000, /* range minimum */
- 0x0CF7, /* range maximum */
- 0x0000, /* translation */
- 0x0CF8 /* length */
- )
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0D00, /* range minimum */
- 0xFFFF, /* range maximum */
- 0x0000, /* translation */
- 0xF300 /* length */
- )
-
- Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
- Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
- Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
-
- /* DRAM Memory from 1MB to TopMem */
- Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
-
- /* BIOS space just below 4GB */
- DWORDMemory(
- ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000000, /* Max-Min, RLEN */
- ,,
- PCBM
- )
-
- /* DRAM memory from 4GB to TopMem2 */
- QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0xFFFFFFFF, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000000, /* Max-Min, RLEN */
- ,,
- DMHI
- )
-
- /* BIOS space just below 16EB */
- QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0xFFFFFFFF, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000000, /* Max-Min, RLEN */
- ,,
- PEBM
- )
-
- }) /* End Name(_SB.PCI0.CRES) */
-
- Method(_CRS, 0) {
- /* DBGO("\\_SB\\PCI0\\_CRS\n") */
-
- CreateDWordField(CRES, ^EMM1._BAS, EM1B)
- CreateDWordField(CRES, ^EMM1._LEN, EM1L)
- CreateDWordField(CRES, ^DMLO._BAS, DMLB)
- CreateDWordField(CRES, ^DMLO._LEN, DMLL)
- CreateDWordField(CRES, ^PCBM._MIN, PBMB)
- CreateDWordField(CRES, ^PCBM._LEN, PBML)
-
- CreateQWordField(CRES, ^DMHI._MIN, DMHB)
- CreateQWordField(CRES, ^DMHI._LEN, DMHL)
- CreateQWordField(CRES, ^PEBM._MIN, EBMB)
- CreateQWordField(CRES, ^PEBM._LEN, EBML)
-
- If(LGreater(LOMH, 0xC0000)){
- Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
- Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
- }
-
- /* Set size of memory from 1MB to TopMem */
- Subtract(TOM1, 0x100000, DMLL)
-
- /*
- * If(LNotEqual(TOM2, 0x00000000)){
- * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
- * Subtract(TOM2, 0x100000000, DMHL)
- * }
- */
-
- /* If there is no memory above 4GB, put the BIOS just below 4GB */
- If(LEqual(TOM2, 0x00000000)){
- Store(PBAD,PBMB) /* Reserve the "BIOS" space */
- Store(PBLN,PBML)
- }
- Else { /* Otherwise, put the BIOS just below 16EB */
- ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
- Store(PBLN,EBML)
- }
-
- Return(CRES) /* note to change the Name buffer */
- } /* end of Method(_SB.PCI0._CRS) */
-
- /*
- *
- * FIRST METHOD CALLED UPON BOOT
- *
- * 1. If debugging, print current OS and ACPI interpreter.
- * 2. Get PCI Interrupt routing from ACPI VSM, this
- * value is based on user choice in BIOS setup.
- */
- Method(_INI, 0) {
- /* DBGO("\\_SB\\_INI\n") */
- /* DBGO(" DSDT.ASL code from ") */
- /* DBGO(__DATE__) */
- /* DBGO(" ") */
- /* DBGO(__TIME__) */
- /* DBGO("\n Sleep states supported: ") */
- /* DBGO("\n") */
- /* DBGO(" \\_OS=") */
- /* DBGO(\_OS) */
- /* DBGO("\n \\_REV=") */
- /* DBGO(\_REV) */
- /* DBGO("\n") */
-
- /* Determine the OS we're running on */
- CkOT()
-
- /* On older chips, clear PciExpWakeDisEn */
- /*if (LLessEqual(\SBRI, 0x13)) {
- * Store(0,\PWDE)
- * }
- */
- } /* End Method(_SB._INI) */
- } /* End Device(PCI0) */
-
- Device(PWRB) { /* Start Power button device */
- Name(_HID, EISAID("PNP0C0C"))
- Name(_UID, 0xAA)
- Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
- Name(_STA, 0x0B) /* sata is invisible */
- }
- } /* End \_SB scope */
-
- Scope(\_SI) {
- Method(_SST, 1) {
- /* DBGO("\\_SI\\_SST\n") */
- /* DBGO(" New Indicator state: ") */
- /* DBGO(Arg0) */
- /* DBGO("\n") */
- }
- } /* End Scope SI */
-
- Mutex (SBX0, 0x00)
- OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
- Field (SMB0, ByteAcc, NoLock, Preserve) {
- HSTS, 8, /* SMBUS status */
- SSTS, 8, /* SMBUS slave status */
- HCNT, 8, /* SMBUS control */
- HCMD, 8, /* SMBUS host cmd */
- HADD, 8, /* SMBUS address */
- DAT0, 8, /* SMBUS data0 */
- DAT1, 8, /* SMBUS data1 */
- BLKD, 8, /* SMBUS block data */
- SCNT, 8, /* SMBUS slave control */
- SCMD, 8, /* SMBUS shaow cmd */
- SEVT, 8, /* SMBUS slave event */
- SDAT, 8 /* SMBUS slave data */
- }
-
- Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
- Store (0x1E, HSTS)
- Store (0xFA, Local0)
- While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
- Stall (0x64)
- Decrement (Local0)
- }
-
- Return (Local0)
- }
-
- Method (SWTC, 1, NotSerialized) {
- Store (Arg0, Local0)
- Store (0x07, Local2)
- Store (One, Local1)
- While (LEqual (Local1, One)) {
- Store (And (HSTS, 0x1E), Local3)
- If (LNotEqual (Local3, Zero)) { /* read sucess */
- If (LEqual (Local3, 0x02)) {
- Store (Zero, Local2)
- }
-
- Store (Zero, Local1)
- }
- Else {
- If (LLess (Local0, 0x0A)) { /* read failure */
- Store (0x10, Local2)
- Store (Zero, Local1)
- }
- Else {
- Sleep (0x0A) /* 10 ms, try again */
- Subtract (Local0, 0x0A, Local0)
- }
- }
- }
-
- Return (Local2)
- }
-
- Method (SMBR, 3, NotSerialized) {
- Store (0x07, Local0)
- If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
- Store (WCLR (), Local0) /* clear SMBUS status register before read data */
- If (LEqual (Local0, Zero)) {
- Release (SBX0)
- Return (0x0)
- }
-
- Store (0x1F, HSTS)
- Store (Or (ShiftLeft (Arg1, One), One), HADD)
- Store (Arg2, HCMD)
- If (LEqual (Arg0, 0x07)) {
- Store (0x48, HCNT) /* read byte */
- }
-
- Store (SWTC (0x03E8), Local1) /* 1000 ms */
- If (LEqual (Local1, Zero)) {
- If (LEqual (Arg0, 0x07)) {
- Store (DAT0, Local0)
- }
- }
- Else {
- Store (Local1, Local0)
- }
-
- Release (SBX0)
- }
-
- /* DBGO("the value of SMBusData0 register ") */
- /* DBGO(Arg2) */
- /* DBGO(" is ") */
- /* DBGO(Local0) */
- /* DBGO("\n") */
-
- Return (Local0)
- }
-
- /* THERMAL */
- Scope(\_TZ) {
- Name (KELV, 2732)
- Name (THOT, 800)
- Name (TCRT, 850)
-
- ThermalZone(TZ00) {
- Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
- /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
- Return(Add(0, 2730))
- }
- Method(_AL0,0) { /* Returns package of cooling device to turn on */
- /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
- Return(Package() {\_TZ.TZ00.FAN0})
- }
- Device (FAN0) {
- Name(_HID, EISAID("PNP0C0B"))
- Name(_PR0, Package() {PFN0})
- }
-
- PowerResource(PFN0,0,0) {
- Method(_STA) {
- Store(0xF,Local0)
- Return(Local0)
- }
- Method(_ON) {
- /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
- }
- Method(_OFF) {
- /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
- }
- }
-
- Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
- /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
- Return (Add (THOT, KELV))
- }
- Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
- /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
- Return (Add (TCRT, KELV))
- }
- Method(_TMP,0) { /* return current temp of this zone */
- Store (SMBR (0x07, 0x4C,, 0x00), Local0)
- If (LGreater (Local0, 0x10)) {
- Store (Local0, Local1)
- }
- Else {
- Add (Local0, THOT, Local0)
- Return (Add (400, KELV))
- }
-
- Store (SMBR (0x07, 0x4C, 0x01), Local0)
- /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
- /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
- If (LGreater (Local0, 0x10)) {
- If (LGreater (Local0, Local1)) {
- Store (Local0, Local1)
- }
-
- Multiply (Local1, 10, Local1)
- Return (Add (Local1, KELV))
- }
- Else {
- Add (Local0, THOT, Local0)
- Return (Add (400 , KELV))
- }
- } /* end of _TMP */
- } /* end of TZ00 */
- }
-}
-/* End of ASL file */
/*
Scope(\_SB) {
- Include ("globutil.asl")
+ #include "globutil.asl"
}
*/
Device(PCI0) {
Device(IDEC) {
Name(_ADR, 0x00140001)
- Include ("ide.asl")
+ #include "ide.asl"
}
}
}
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
)
{
- Include ("routing.asl")
+ #include "routing.asl"
}
*/
Device(PCI0) {
Device(SATA) {
Name(_ADR, 0x00120000)
- Include ("sata.asl")
+ #include "sata.asl"
}
}
}
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
)
{
- Include ("usb.asl")
+ #include "usb.asl"
}
*/
Method(UCOC, 0) {
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+ "dsdt.aml", /* Output filename */
+ "DSDT", /* Signature */
+ 0x02, /* DSDT Revision, needs to be 2 for 64bit */
+ "COREv2", /* OEMID */
+ "COREBOOT", /* TABLE ID */
+ 0x00010001 /* OEM Revision */
+ )
+{ /* Start of ASL file */
+ /* #include "acpi/debug.asl" */ /* Include global debug methods if needed */
+
+ /* Data to be patched by the BIOS during POST */
+ /* FIXME the patching is not done yet! */
+ /* Memory related values */
+ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
+ Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+ Name(PBLN, 0x0) /* Length of BIOS area */
+
+ Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
+ Name(HPBA, 0xFED00000) /* Base address of HPET table */
+
+ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+ /* USB overcurrent mapping pins. */
+ Name(UOM0, 0)
+ Name(UOM1, 2)
+ Name(UOM2, 0)
+ Name(UOM3, 7)
+ Name(UOM4, 2)
+ Name(UOM5, 2)
+ Name(UOM6, 6)
+ Name(UOM7, 2)
+ Name(UOM8, 6)
+ Name(UOM9, 6)
+
+ /* Some global data */
+ Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+ Name(OSV, Ones) /* Assume nothing */
+ Name(PMOD, One) /* Assume APIC */
+
+ /* PIC IRQ mapping registers, C00h-C01h */
+ OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
+ Field(PRQM, ByteAcc, NoLock, Preserve) {
+ PRQI, 0x00000008,
+ PRQD, 0x00000008, /* Offset: 1h */
+ }
+ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
+ PINA, 0x00000008, /* Index 0 */
+ PINB, 0x00000008, /* Index 1 */
+ PINC, 0x00000008, /* Index 2 */
+ PIND, 0x00000008, /* Index 3 */
+ AINT, 0x00000008, /* Index 4 */
+ SINT, 0x00000008, /* Index 5 */
+ , 0x00000008, /* Index 6 */
+ AAUD, 0x00000008, /* Index 7 */
+ AMOD, 0x00000008, /* Index 8 */
+ PINE, 0x00000008, /* Index 9 */
+ PINF, 0x00000008, /* Index A */
+ PING, 0x00000008, /* Index B */
+ PINH, 0x00000008, /* Index C */
+ }
+
+ /* PCI Error control register */
+ OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
+ Field(PERC, ByteAcc, NoLock, Preserve) {
+ SENS, 0x00000001,
+ PENS, 0x00000001,
+ SENE, 0x00000001,
+ PENE, 0x00000001,
+ }
+
+ /* Client Management index/data registers */
+ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
+ Field(CMT, ByteAcc, NoLock, Preserve) {
+ CMTI, 8,
+ /* Client Management Data register */
+ G64E, 1,
+ G64O, 1,
+ G32O, 2,
+ , 2,
+ GPSL, 2,
+ }
+
+ /* GPM Port register */
+ OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
+ Field(GPT, ByteAcc, NoLock, Preserve) {
+ GPB0,1,
+ GPB1,1,
+ GPB2,1,
+ GPB3,1,
+ GPB4,1,
+ GPB5,1,
+ GPB6,1,
+ GPB7,1,
+ }
+
+ /* Flash ROM program enable register */
+ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
+ Field(FRE, ByteAcc, NoLock, Preserve) {
+ , 0x00000006,
+ FLRE, 0x00000001,
+ }
+
+ /* PM2 index/data registers */
+ OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
+ Field(PM2R, ByteAcc, NoLock, Preserve) {
+ PM2I, 0x00000008,
+ PM2D, 0x00000008,
+ }
+
+ /* Power Management I/O registers */
+ OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
+ Field(PIOR, ByteAcc, NoLock, Preserve) {
+ PIOI, 0x00000008,
+ PIOD, 0x00000008,
+ }
+ IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
+ Offset(0x00), /* MiscControl */
+ , 1,
+ T1EE, 1,
+ T2EE, 1,
+ Offset(0x01), /* MiscStatus */
+ , 1,
+ T1E, 1,
+ T2E, 1,
+ Offset(0x04), /* SmiWakeUpEventEnable3 */
+ , 7,
+ SSEN, 1,
+ Offset(0x07), /* SmiWakeUpEventStatus3 */
+ , 7,
+ CSSM, 1,
+ Offset(0x10), /* AcpiEnable */
+ , 6,
+ PWDE, 1,
+ Offset(0x1C), /* ProgramIoEnable */
+ , 3,
+ MKME, 1,
+ IO3E, 1,
+ IO2E, 1,
+ IO1E, 1,
+ IO0E, 1,
+ Offset(0x1D), /* IOMonitorStatus */
+ , 3,
+ MKMS, 1,
+ IO3S, 1,
+ IO2S, 1,
+ IO1S, 1,
+ IO0S,1,
+ Offset(0x20), /* AcpiPmEvtBlk */
+ APEB, 16,
+ Offset(0x36), /* GEvtLevelConfig */
+ , 6,
+ ELC6, 1,
+ ELC7, 1,
+ Offset(0x37), /* GPMLevelConfig0 */
+ , 3,
+ PLC0, 1,
+ PLC1, 1,
+ PLC2, 1,
+ PLC3, 1,
+ PLC8, 1,
+ Offset(0x38), /* GPMLevelConfig1 */
+ , 1,
+ PLC4, 1,
+ PLC5, 1,
+ , 1,
+ PLC6, 1,
+ PLC7, 1,
+ Offset(0x3B), /* PMEStatus1 */
+ GP0S, 1,
+ GM4S, 1,
+ GM5S, 1,
+ APS, 1,
+ GM6S, 1,
+ GM7S, 1,
+ GP2S, 1,
+ STSS, 1,
+ Offset(0x55), /* SoftPciRst */
+ SPRE, 1,
+ , 1,
+ , 1,
+ PNAT, 1,
+ PWMK, 1,
+ PWNS, 1,
+
+ /* Offset(0x61), */ /* Options_1 */
+ /* ,7, */
+ /* R617,1, */
+
+ Offset(0x65), /* UsbPMControl */
+ , 4,
+ URRE, 1,
+ Offset(0x68), /* MiscEnable68 */
+ , 3,
+ TMTE, 1,
+ , 1,
+ Offset(0x92), /* GEVENTIN */
+ , 7,
+ E7IS, 1,
+ Offset(0x96), /* GPM98IN */
+ G8IS, 1,
+ G9IS, 1,
+ Offset(0x9A), /* EnhanceControl */
+ ,7,
+ HPDE, 1,
+ Offset(0xA8), /* PIO7654Enable */
+ IO4E, 1,
+ IO5E, 1,
+ IO6E, 1,
+ IO7E, 1,
+ Offset(0xA9), /* PIO7654Status */
+ IO4S, 1,
+ IO5S, 1,
+ IO6S, 1,
+ IO7S, 1,
+ }
+
+ /* PM1 Event Block
+ * First word is PM1_Status, Second word is PM1_Enable
+ */
+ OperationRegion(P1EB, SystemIO, APEB, 0x04)
+ Field(P1EB, ByteAcc, NoLock, Preserve) {
+ TMST, 1,
+ , 3,
+ BMST, 1,
+ GBST, 1,
+ Offset(0x01),
+ PBST, 1,
+ , 1,
+ RTST, 1,
+ , 3,
+ PWST, 1,
+ SPWS, 1,
+ Offset(0x02),
+ TMEN, 1,
+ , 4,
+ GBEN, 1,
+ Offset(0x03),
+ PBEN, 1,
+ , 1,
+ RTEN, 1,
+ , 3,
+ PWDA, 1,
+ }
+
+ Scope(\_SB) {
+
+ /* PCIe Configuration Space for 16 busses */
+ OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
+ Field(PCFG, ByteAcc, NoLock, Preserve) {
+ /* Byte offsets are computed using the following technique:
+ * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
+ * The 8 comes from 8 functions per device, and 4096 bytes per function config space
+ */
+ Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */
+ STB5, 32,
+ Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
+ PT0D, 1,
+ PT1D, 1,
+ PT2D, 1,
+ PT3D, 1,
+ PT4D, 1,
+ PT5D, 1,
+ PT6D, 1,
+ PT7D, 1,
+ PT8D, 1,
+ PT9D, 1,
+ Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
+ SBIE, 1,
+ SBME, 1,
+ Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
+ SBRI, 8,
+ Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
+ SBB1, 32,
+ Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
+ ,14,
+ P92E, 1, /* Port92 decode enable */
+ }
+
+ OperationRegion(SB5, SystemMemory, STB5, 0x1000)
+ Field(SB5, AnyAcc, NoLock, Preserve)
+ {
+ /* Port 0 */
+ Offset(0x120), /* Port 0 Task file status */
+ P0ER, 1,
+ , 2,
+ P0DQ, 1,
+ , 3,
+ P0BY, 1,
+ Offset(0x128), /* Port 0 Serial ATA status */
+ P0DD, 4,
+ , 4,
+ P0IS, 4,
+ Offset(0x12C), /* Port 0 Serial ATA control */
+ P0DI, 4,
+ Offset(0x130), /* Port 0 Serial ATA error */
+ , 16,
+ P0PR, 1,
+
+ /* Port 1 */
+ offset(0x1A0), /* Port 1 Task file status */
+ P1ER, 1,
+ , 2,
+ P1DQ, 1,
+ , 3,
+ P1BY, 1,
+ Offset(0x1A8), /* Port 1 Serial ATA status */
+ P1DD, 4,
+ , 4,
+ P1IS, 4,
+ Offset(0x1AC), /* Port 1 Serial ATA control */
+ P1DI, 4,
+ Offset(0x1B0), /* Port 1 Serial ATA error */
+ , 16,
+ P1PR, 1,
+
+ /* Port 2 */
+ Offset(0x220), /* Port 2 Task file status */
+ P2ER, 1,
+ , 2,
+ P2DQ, 1,
+ , 3,
+ P2BY, 1,
+ Offset(0x228), /* Port 2 Serial ATA status */
+ P2DD, 4,
+ , 4,
+ P2IS, 4,
+ Offset(0x22C), /* Port 2 Serial ATA control */
+ P2DI, 4,
+ Offset(0x230), /* Port 2 Serial ATA error */
+ , 16,
+ P2PR, 1,
+
+ /* Port 3 */
+ Offset(0x2A0), /* Port 3 Task file status */
+ P3ER, 1,
+ , 2,
+ P3DQ, 1,
+ , 3,
+ P3BY, 1,
+ Offset(0x2A8), /* Port 3 Serial ATA status */
+ P3DD, 4,
+ , 4,
+ P3IS, 4,
+ Offset(0x2AC), /* Port 3 Serial ATA control */
+ P3DI, 4,
+ Offset(0x2B0), /* Port 3 Serial ATA error */
+ , 16,
+ P3PR, 1,
+ }
+ }
+
+ #include "acpi/routing.asl"
+
+ Scope(\_SB) {
+
+ Method(CkOT, 0){
+
+ if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */
+
+ if(CondRefOf(\_OSI,Local1))
+ {
+ Store(1, OSTP) /* Assume some form of XP */
+ if (\_OSI("Windows 2006")) /* Vista */
+ {
+ Store(2, OSTP)
+ }
+ } else {
+ If(WCMP(\_OS,"Linux")) {
+ Store(3, OSTP) /* Linux */
+ } Else {
+ Store(4, OSTP) /* Gotta be WinCE */
+ }
+ }
+ Return(OSTP)
+ }
+
+ Method(_PIC, 0x01, NotSerialized)
+ {
+ If (Arg0)
+ {
+ \_SB.CIRQ()
+ }
+ Store(Arg0, PMOD)
+ }
+
+ Method(CIRQ, 0x00, NotSerialized)
+ {
+ Store(0, PINA)
+ Store(0, PINB)
+ Store(0, PINC)
+ Store(0, PIND)
+ Store(0, PINE)
+ Store(0, PINF)
+ Store(0, PING)
+ Store(0, PINH)
+ }
+
+ Name(IRQB, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Shared){15}
+ })
+
+ Name(IRQP, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
+ })
+
+ Name(PITF, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Exclusive){9}
+ })
+
+ Device(INTA) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 1)
+
+ Method(_STA, 0) {
+ if (PINA) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTA._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_DIS\n") */
+ Store(0, PINA)
+ } /* End Method(_SB.INTA._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTA._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINA, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTA._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKA\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINA)
+ } /* End Method(_SB.INTA._SRS) */
+ } /* End Device(INTA) */
+
+ Device(INTB) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 2)
+
+ Method(_STA, 0) {
+ if (PINB) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTB._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_DIS\n") */
+ Store(0, PINB)
+ } /* End Method(_SB.INTB._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTB._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINB, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTB._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKB\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINB)
+ } /* End Method(_SB.INTB._SRS) */
+ } /* End Device(INTB) */
+
+ Device(INTC) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 3)
+
+ Method(_STA, 0) {
+ if (PINC) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTC._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_DIS\n") */
+ Store(0, PINC)
+ } /* End Method(_SB.INTC._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTC._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINC, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTC._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKC\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINC)
+ } /* End Method(_SB.INTC._SRS) */
+ } /* End Device(INTC) */
+
+ Device(INTD) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 4)
+
+ Method(_STA, 0) {
+ if (PIND) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTD._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_DIS\n") */
+ Store(0, PIND)
+ } /* End Method(_SB.INTD._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTD._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIND, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTD._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKD\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIND)
+ } /* End Method(_SB.INTD._SRS) */
+ } /* End Device(INTD) */
+
+ Device(INTE) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 5)
+
+ Method(_STA, 0) {
+ if (PINE) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTE._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_DIS\n") */
+ Store(0, PINE)
+ } /* End Method(_SB.INTE._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTE._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINE, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTE._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKE\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINE)
+ } /* End Method(_SB.INTE._SRS) */
+ } /* End Device(INTE) */
+
+ Device(INTF) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 6)
+
+ Method(_STA, 0) {
+ if (PINF) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTF._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_DIS\n") */
+ Store(0, PINF)
+ } /* End Method(_SB.INTF._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_PRS\n") */
+ Return(PITF)
+ } /* Method(_SB.INTF._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINF, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTF._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKF\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINF)
+ } /* End Method(_SB.INTF._SRS) */
+ } /* End Device(INTF) */
+
+ Device(INTG) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 7)
+
+ Method(_STA, 0) {
+ if (PING) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTG._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKG\\_DIS\n") */
+ Store(0, PING)
+ } /* End Method(_SB.INTG._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKG\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTG._CRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKG\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PING, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTG._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKG\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PING)
+ } /* End Method(_SB.INTG._SRS) */
+ } /* End Device(INTG) */
+
+ Device(INTH) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 8)
+
+ Method(_STA, 0) {
+ if (PINH) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTH._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKH\\_DIS\n") */
+ Store(0, PINH)
+ } /* End Method(_SB.INTH._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKH\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTH._CRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKH\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINH, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTH._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKH\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINH)
+ } /* End Method(_SB.INTH._SRS) */
+ } /* End Device(INTH) */
+
+ } /* End Scope(_SB) */
+
+
+ /* Supported sleep states: */
+ Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
+
+ If (LAnd(SSFG, 0x01)) {
+ Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
+ }
+ If (LAnd(SSFG, 0x02)) {
+ Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
+ }
+ If (LAnd(SSFG, 0x04)) {
+ Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
+ }
+ If (LAnd(SSFG, 0x08)) {
+ Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
+ }
+
+ Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
+
+ Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
+ Name(CSMS, 0) /* Current System State */
+
+ /* Wake status package */
+ Name(WKST,Package(){Zero, Zero})
+
+ /*
+ * \_PTS - Prepare to Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2, etc
+ *
+ * Exit:
+ * -none-
+ *
+ * The _PTS control method is executed at the beginning of the sleep process
+ * for S1-S5. The sleeping value is passed to the _PTS control method. This
+ * control method may be executed a relatively long time before entering the
+ * sleep state and the OS may abort the operation without notification to
+ * the ACPI driver. This method cannot modify the configuration or power
+ * state of any device in the system.
+ */
+ Method(\_PTS, 1) {
+ /* DBGO("\\_PTS\n") */
+ /* DBGO("From S0 to S") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+
+ /* Don't allow PCIRST# to reset USB */
+ if (LEqual(Arg0,3)){
+ Store(0,URRE)
+ }
+
+ /* Clear sleep SMI status flag and enable sleep SMI trap. */
+ /*Store(One, CSSM)
+ Store(One, SSEN)*/
+
+ /* On older chips, clear PciExpWakeDisEn */
+ /*if (LLessEqual(\_SB.SBRI, 0x13)) {
+ * Store(0,\_SB.PWDE)
+ *}
+ */
+
+ /* Clear wake status structure. */
+ Store(0, Index(WKST,0))
+ Store(0, Index(WKST,1))
+ \_SB.PCI0.SIOS (Arg0)
+ } /* End Method(\_PTS) */
+
+ /*
+ * The following method results in a "not a valid reserved NameSeg"
+ * warning so I have commented it out for the duration. It isn't
+ * used, so it could be removed.
+ *
+ *
+ * \_GTS OEM Going To Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * -none-
+ *
+ * Method(\_GTS, 1) {
+ * DBGO("\\_GTS\n")
+ * DBGO("From S0 to S")
+ * DBGO(Arg0)
+ * DBGO("\n")
+ * }
+ */
+
+ /*
+ * \_BFS OEM Back From Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * -none-
+ */
+ Method(\_BFS, 1) {
+ /* DBGO("\\_BFS\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+ }
+
+ /*
+ * \_WAK System Wake method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * Return package of 2 DWords
+ * Dword 1 - Status
+ * 0x00000000 wake succeeded
+ * 0x00000001 Wake was signaled but failed due to lack of power
+ * 0x00000002 Wake was signaled but failed due to thermal condition
+ * Dword 2 - Power Supply state
+ * if non-zero the effective S-state the power supply entered
+ */
+ Method(\_WAK, 1) {
+ /* DBGO("\\_WAK\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+
+ /* Re-enable HPET */
+ Store(1,HPDE)
+
+ /* Restore PCIRST# so it resets USB */
+ if (LEqual(Arg0,3)){
+ Store(1,URRE)
+ }
+
+ /* Arbitrarily clear PciExpWakeStatus */
+ Store(PWST, PWST)
+
+ /* if(DeRefOf(Index(WKST,0))) {
+ * Store(0, Index(WKST,1))
+ * } else {
+ * Store(Arg0, Index(WKST,1))
+ * }
+ */
+ \_SB.PCI0.SIOW (Arg0)
+ Return(WKST)
+ } /* End Method(\_WAK) */
+
+ Scope(\_GPE) { /* Start Scope GPE */
+ /* General event 0 */
+ /* Method(_L00) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 1 */
+ /* Method(_L01) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 2 */
+ /* Method(_L02) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 3 */
+ Method(_L03) {
+ /* DBGO("\\_GPE\\_L00\n") */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* General event 4 */
+ /* Method(_L04) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 5 */
+ /* Method(_L05) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 6 - Used for GPM6, moved to USB.asl */
+ /* Method(_L06) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 7 - Used for GPM7, moved to USB.asl */
+ /* Method(_L07) {
+ * DBGO("\\_GPE\\_L07\n")
+ * }
+ */
+
+ /* Legacy PM event */
+ Method(_L08) {
+ /* DBGO("\\_GPE\\_L08\n") */
+ }
+
+ /* Temp warning (TWarn) event */
+ Method(_L09) {
+ /* DBGO("\\_GPE\\_L09\n") */
+ Notify (\_TZ.TZ00, 0x80)
+ }
+
+ /* Reserved */
+ /* Method(_L0A) {
+ * DBGO("\\_GPE\\_L0A\n")
+ * }
+ */
+
+ /* USB controller PME# */
+ Method(_L0B) {
+ /* DBGO("\\_GPE\\_L0B\n") */
+ Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* AC97 controller PME# */
+ /* Method(_L0C) {
+ * DBGO("\\_GPE\\_L0C\n")
+ * }
+ */
+
+ /* OtherTherm PME# */
+ /* Method(_L0D) {
+ * DBGO("\\_GPE\\_L0D\n")
+ * }
+ */
+
+ /* GPM9 SCI event - Moved to USB.asl */
+ /* Method(_L0E) {
+ * DBGO("\\_GPE\\_L0E\n")
+ * }
+ */
+
+ /* PCIe HotPlug event */
+ /* Method(_L0F) {
+ * DBGO("\\_GPE\\_L0F\n")
+ * }
+ */
+
+ /* ExtEvent0 SCI event */
+ Method(_L10) {
+ /* DBGO("\\_GPE\\_L10\n") */
+ }
+
+
+ /* ExtEvent1 SCI event */
+ Method(_L11) {
+ /* DBGO("\\_GPE\\_L11\n") */
+ }
+
+ /* PCIe PME# event */
+ /* Method(_L12) {
+ * DBGO("\\_GPE\\_L12\n")
+ * }
+ */
+
+ /* GPM0 SCI event - Moved to USB.asl */
+ /* Method(_L13) {
+ * DBGO("\\_GPE\\_L13\n")
+ * }
+ */
+
+ /* GPM1 SCI event - Moved to USB.asl */
+ /* Method(_L14) {
+ * DBGO("\\_GPE\\_L14\n")
+ * }
+ */
+
+ /* GPM2 SCI event - Moved to USB.asl */
+ /* Method(_L15) {
+ * DBGO("\\_GPE\\_L15\n")
+ * }
+ */
+
+ /* GPM3 SCI event - Moved to USB.asl */
+ /* Method(_L16) {
+ * DBGO("\\_GPE\\_L16\n")
+ * }
+ */
+
+ /* GPM8 SCI event - Moved to USB.asl */
+ /* Method(_L17) {
+ * DBGO("\\_GPE\\_L17\n")
+ * }
+ */
+
+ /* GPIO0 or GEvent8 event */
+ Method(_L18) {
+ /* DBGO("\\_GPE\\_L18\n") */
+ Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* GPM4 SCI event - Moved to USB.asl */
+ /* Method(_L19) {
+ * DBGO("\\_GPE\\_L19\n")
+ * }
+ */
+
+ /* GPM5 SCI event - Moved to USB.asl */
+ /* Method(_L1A) {
+ * DBGO("\\_GPE\\_L1A\n")
+ * }
+ */
+
+ /* Azalia SCI event */
+ Method(_L1B) {
+ /* DBGO("\\_GPE\\_L1B\n") */
+ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* GPM6 SCI event - Reassigned to _L06 */
+ /* Method(_L1C) {
+ * DBGO("\\_GPE\\_L1C\n")
+ * }
+ */
+
+ /* GPM7 SCI event - Reassigned to _L07 */
+ /* Method(_L1D) {
+ * DBGO("\\_GPE\\_L1D\n")
+ * }
+ */
+
+ /* GPIO2 or GPIO66 SCI event */
+ /* Method(_L1E) {
+ * DBGO("\\_GPE\\_L1E\n")
+ * }
+ */
+
+ /* SATA SCI event - Moved to sata.asl */
+ /* Method(_L1F) {
+ * DBGO("\\_GPE\\_L1F\n")
+ * }
+ */
+
+ } /* End Scope GPE */
+
+ #include "acpi/usb.asl"
+
+ /* South Bridge */
+ Scope(\_SB) { /* Start \_SB scope */
+ #include "acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
+
+ /* _SB.PCI0 */
+ /* Note: Only need HID on Primary Bus */
+ Device(PCI0) {
+ External (TOM1)
+ External (TOM2)
+ Name(_HID, EISAID("PNP0A03"))
+ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
+ Method(_BBN, 0) { /* Bus number = 0 */
+ Return(0)
+ }
+ Method(_STA, 0) {
+ /* DBGO("\\_SB\\PCI0\\_STA\n") */
+ Return(0x0B) /* Status is visible */
+ }
+
+ Method(_PRT,0) {
+ If(PMOD){ Return(APR0) } /* APIC mode */
+ Return (PR0) /* PIC Mode */
+ } /* end _PRT */
+
+ /* Describe the Northbridge devices */
+ Device(AMRT) {
+ Name(_ADR, 0x00000000)
+ } /* end AMRT */
+
+ /* The internal GFX bridge */
+ Device(AGPB) {
+ Name(_ADR, 0x00010000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ Return (APR1)
+ }
+ } /* end AGPB */
+
+ /* The external GFX bridge */
+ Device(PBR2) {
+ Name(_ADR, 0x00020000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS2) } /* APIC mode */
+ Return (PS2) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR2 */
+
+ /* Dev3 is also an external GFX bridge, not used in Herring */
+
+ Device(PBR4) {
+ Name(_ADR, 0x00040000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS4) } /* APIC mode */
+ Return (PS4) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR4 */
+
+ Device(PBR5) {
+ Name(_ADR, 0x00050000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS5) } /* APIC mode */
+ Return (PS5) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR5 */
+
+ Device(PBR6) {
+ Name(_ADR, 0x00060000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS6) } /* APIC mode */
+ Return (PS6) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR6 */
+
+ /* The onboard EtherNet chip */
+ Device(PBR7) {
+ Name(_ADR, 0x00070000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS7) } /* APIC mode */
+ Return (PS7) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR7 */
+
+
+ /* PCI slot 1, 2, 3 */
+ Device(PIBR) {
+ Name(_ADR, 0x00140004)
+ Name(_PRW, Package() {0x18, 4})
+
+ Method(_PRT, 0) {
+ Return (PCIB)
+ }
+ }
+
+ /* Describe the Southbridge devices */
+ Device(STCR) {
+ Name(_ADR, 0x00120000)
+ #include "acpi/sata.asl"
+ } /* end STCR */
+
+ Device(UOH1) {
+ Name(_ADR, 0x00130000)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH1 */
+
+ Device(UOH2) {
+ Name(_ADR, 0x00130001)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH2 */
+
+ Device(UOH3) {
+ Name(_ADR, 0x00130002)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH3 */
+
+ Device(UOH4) {
+ Name(_ADR, 0x00130003)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH4 */
+
+ Device(UOH5) {
+ Name(_ADR, 0x00130004)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH5 */
+
+ Device(UEH1) {
+ Name(_ADR, 0x00130005)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UEH1 */
+
+ Device(SBUS) {
+ Name(_ADR, 0x00140000)
+ } /* end SBUS */
+
+ /* Primary (and only) IDE channel */
+ Device(IDEC) {
+ Name(_ADR, 0x00140001)
+ #include "acpi/ide.asl"
+ } /* end IDEC */
+
+ Device(AZHD) {
+ Name(_ADR, 0x00140002)
+ OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
+ Field(AZPD, AnyAcc, NoLock, Preserve) {
+ offset (0x42),
+ NSDI, 1,
+ NSDO, 1,
+ NSEN, 1,
+ offset (0x44),
+ IPCR, 4,
+ offset (0x54),
+ PWST, 2,
+ , 6,
+ PMEB, 1,
+ , 6,
+ PMST, 1,
+ offset (0x62),
+ MMCR, 1,
+ offset (0x64),
+ MMLA, 32,
+ offset (0x68),
+ MMHA, 32,
+ offset (0x6C),
+ MMDT, 16,
+ }
+
+ Method(_INI) {
+ If(LEqual(OSTP,3)){ /* If we are running Linux */
+ Store(zero, NSEN)
+ Store(one, NSDO)
+ Store(one, NSDI)
+ }
+ }
+ } /* end AZHD */
+
+ Device(LIBR) {
+ Name(_ADR, 0x00140003)
+ /* Method(_INI) {
+ * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
+ } */ /* End Method(_SB.SBRDG._INI) */
+
+ /* Real Time Clock Device */
+ Device(RTC0) {
+ Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){8}
+ IO(Decode16,0x0070, 0x0070, 0, 2)
+ /* IO(Decode16,0x0070, 0x0070, 0, 4) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
+
+ Device(TMR) { /* Timer */
+ Name(_HID,EISAID("PNP0100")) /* System Timer */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){0}
+ IO(Decode16, 0x0040, 0x0040, 0, 4)
+ /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
+
+ Device(SPKR) { /* Speaker */
+ Name(_HID,EISAID("PNP0800")) /* AT style speaker */
+ Name(_CRS, ResourceTemplate() {
+ IO(Decode16, 0x0061, 0x0061, 0, 1)
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
+
+ Device(PIC) {
+ Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){2}
+ IO(Decode16,0x0020, 0x0020, 0, 2)
+ IO(Decode16,0x00A0, 0x00A0, 0, 2)
+ /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
+ /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
+
+ Device(MAD) { /* 8257 DMA */
+ Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
+ Name(_CRS, ResourceTemplate() {
+ DMA(Compatibility,BusMaster,Transfer8){4}
+ IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
+ IO(Decode16, 0x0081, 0x0081, 0x10, 0x03)
+ IO(Decode16, 0x0087, 0x0087, 0x10, 0x01)
+ IO(Decode16, 0x0089, 0x0089, 0x10, 0x03)
+ IO(Decode16, 0x008F, 0x008F, 0x10, 0x01)
+ IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
+ }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
+ } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
+
+ Device(COPR) {
+ Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
+ Name(_CRS, ResourceTemplate() {
+ IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
+ IRQNoFlags(){13}
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+
+ Device(HPTM) {
+ Name(_HID,EISAID("PNP0103"))
+ Name(CRS,ResourceTemplate() {
+ Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
+ })
+ Method(_STA, 0) {
+ Return(0x0F) /* sata is visible */
+ }
+ Method(_CRS, 0) {
+ CreateDwordField(CRS, ^HPT._BAS, HPBA)
+ Store(HPBA, HPBA)
+ Return(CRS)
+ }
+ } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+ } /* end LIBR */
+
+ Device(HPBR) {
+ Name(_ADR, 0x00140004)
+ } /* end HostPciBr */
+
+ Device(ACAD) {
+ Name(_ADR, 0x00140005)
+ } /* end Ac97audio */
+
+ Device(ACMD) {
+ Name(_ADR, 0x00140006)
+ } /* end Ac97modem */
+
+ /* ITE IT8712F Support */
+ OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
+ Field (IOID, ByteAcc, NoLock, Preserve)
+ {
+ SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */
+ }
+
+ IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x07),
+ LDN, 8, /* Logical Device Number */
+ Offset (0x20),
+ CID1, 8, /* Chip ID Byte 1, 0x87 */
+ CID2, 8, /* Chip ID Byte 2, 0x12 */
+ Offset (0x30),
+ ACTR, 8, /* Function activate */
+ Offset (0xF0),
+ APC0, 8, /* APC/PME Event Enable Register */
+ APC1, 8, /* APC/PME Status Register */
+ APC2, 8, /* APC/PME Control Register 1 */
+ APC3, 8, /* Environment Controller Special Configuration Register */
+ APC4, 8 /* APC/PME Control Register 2 */
+ }
+
+ /* Enter the IT8712F MB PnP Mode */
+ Method (EPNP)
+ {
+ Store(0x87, SIOI)
+ Store(0x01, SIOI)
+ Store(0x55, SIOI)
+ Store(0x55, SIOI) /* IT8712F magic number */
+ }
+ /* Exit the IT8712F MB PnP Mode */
+ Method (XPNP)
+ {
+ Store (0x02, SIOI)
+ Store (0x02, SIOD)
+ }
+
+ /*
+ * Keyboard PME is routed to SB600 Gevent3. We can wake
+ * up the system by pressing the key.
+ */
+ Method (SIOS, 1)
+ {
+ /* We only enable KBD PME for S5. */
+ If (LLess (Arg0, 0x05))
+ {
+ EPNP()
+ /* DBGO("IT8712F\n") */
+
+ Store (0x4, LDN)
+ Store (One, ACTR) /* Enable EC */
+ /*
+ Store (0x4, LDN)
+ Store (0x04, APC4)
+ */ /* falling edge. which mode? Not sure. */
+
+ Store (0x4, LDN)
+ Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
+ Store (0x4, LDN)
+ Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
+
+ XPNP()
+ }
+ }
+ Method (SIOW, 1)
+ {
+ EPNP()
+ Store (0x4, LDN)
+ Store (Zero, APC0) /* disable keyboard PME */
+ Store (0x4, LDN)
+ Store (0xFF, APC1) /* clear keyboard PME status */
+ XPNP()
+ }
+
+ Name(CRES, ResourceTemplate() {
+ IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
+
+ WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, /* address granularity */
+ 0x0000, /* range minimum */
+ 0x0CF7, /* range maximum */
+ 0x0000, /* translation */
+ 0x0CF8 /* length */
+ )
+
+ WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, /* address granularity */
+ 0x0D00, /* range minimum */
+ 0xFFFF, /* range maximum */
+ 0x0000, /* translation */
+ 0xF300 /* length */
+ )
+
+ Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
+ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
+ Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
+ Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
+
+ /* DRAM Memory from 1MB to TopMem */
+ Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
+
+ /* BIOS space just below 4GB */
+ DWORDMemory(
+ ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00, /* Granularity */
+ 0x00000000, /* Min */
+ 0x00000000, /* Max */
+ 0x00000000, /* Translation */
+ 0x00000000, /* Max-Min, RLEN */
+ ,,
+ PCBM
+ )
+
+ /* DRAM memory from 4GB to TopMem2 */
+ QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0xFFFFFFFF, /* Granularity */
+ 0x00000000, /* Min */
+ 0x00000000, /* Max */
+ 0x00000000, /* Translation */
+ 0x00000000, /* Max-Min, RLEN */
+ ,,
+ DMHI
+ )
+
+ /* BIOS space just below 16EB */
+ QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0xFFFFFFFF, /* Granularity */
+ 0x00000000, /* Min */
+ 0x00000000, /* Max */
+ 0x00000000, /* Translation */
+ 0x00000000, /* Max-Min, RLEN */
+ ,,
+ PEBM
+ )
+
+ }) /* End Name(_SB.PCI0.CRES) */
+
+ Method(_CRS, 0) {
+ /* DBGO("\\_SB\\PCI0\\_CRS\n") */
+
+ CreateDWordField(CRES, ^EMM1._BAS, EM1B)
+ CreateDWordField(CRES, ^EMM1._LEN, EM1L)
+ CreateDWordField(CRES, ^DMLO._BAS, DMLB)
+ CreateDWordField(CRES, ^DMLO._LEN, DMLL)
+ CreateDWordField(CRES, ^PCBM._MIN, PBMB)
+ CreateDWordField(CRES, ^PCBM._LEN, PBML)
+
+ CreateQWordField(CRES, ^DMHI._MIN, DMHB)
+ CreateQWordField(CRES, ^DMHI._LEN, DMHL)
+ CreateQWordField(CRES, ^PEBM._MIN, EBMB)
+ CreateQWordField(CRES, ^PEBM._LEN, EBML)
+
+ If(LGreater(LOMH, 0xC0000)){
+ Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
+ Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
+ }
+
+ /* Set size of memory from 1MB to TopMem */
+ Subtract(TOM1, 0x100000, DMLL)
+
+ /*
+ * If(LNotEqual(TOM2, 0x00000000)){
+ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
+ * Subtract(TOM2, 0x100000000, DMHL)
+ * }
+ */
+
+ /* If there is no memory above 4GB, put the BIOS just below 4GB */
+ If(LEqual(TOM2, 0x00000000)){
+ Store(PBAD,PBMB) /* Reserve the "BIOS" space */
+ Store(PBLN,PBML)
+ }
+ Else { /* Otherwise, put the BIOS just below 16EB */
+ ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
+ Store(PBLN,EBML)
+ }
+
+ Return(CRES) /* note to change the Name buffer */
+ } /* end of Method(_SB.PCI0._CRS) */
+
+ /*
+ *
+ * FIRST METHOD CALLED UPON BOOT
+ *
+ * 1. If debugging, print current OS and ACPI interpreter.
+ * 2. Get PCI Interrupt routing from ACPI VSM, this
+ * value is based on user choice in BIOS setup.
+ */
+ Method(_INI, 0) {
+ /* DBGO("\\_SB\\_INI\n") */
+ /* DBGO(" DSDT.ASL code from ") */
+ /* DBGO(__DATE__) */
+ /* DBGO(" ") */
+ /* DBGO(__TIME__) */
+ /* DBGO("\n Sleep states supported: ") */
+ /* DBGO("\n") */
+ /* DBGO(" \\_OS=") */
+ /* DBGO(\_OS) */
+ /* DBGO("\n \\_REV=") */
+ /* DBGO(\_REV) */
+ /* DBGO("\n") */
+
+ /* Determine the OS we're running on */
+ CkOT()
+
+ /* On older chips, clear PciExpWakeDisEn */
+ /*if (LLessEqual(\SBRI, 0x13)) {
+ * Store(0,\PWDE)
+ * }
+ */
+ } /* End Method(_SB._INI) */
+ } /* End Device(PCI0) */
+
+ Device(PWRB) { /* Start Power button device */
+ Name(_HID, EISAID("PNP0C0C"))
+ Name(_UID, 0xAA)
+ Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
+ Name(_STA, 0x0B) /* sata is invisible */
+ }
+ } /* End \_SB scope */
+
+ Scope(\_SI) {
+ Method(_SST, 1) {
+ /* DBGO("\\_SI\\_SST\n") */
+ /* DBGO(" New Indicator state: ") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+ }
+ } /* End Scope SI */
+
+ Mutex (SBX0, 0x00)
+ OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
+ Field (SMB0, ByteAcc, NoLock, Preserve) {
+ HSTS, 8, /* SMBUS status */
+ SSTS, 8, /* SMBUS slave status */
+ HCNT, 8, /* SMBUS control */
+ HCMD, 8, /* SMBUS host cmd */
+ HADD, 8, /* SMBUS address */
+ DAT0, 8, /* SMBUS data0 */
+ DAT1, 8, /* SMBUS data1 */
+ BLKD, 8, /* SMBUS block data */
+ SCNT, 8, /* SMBUS slave control */
+ SCMD, 8, /* SMBUS shaow cmd */
+ SEVT, 8, /* SMBUS slave event */
+ SDAT, 8 /* SMBUS slave data */
+ }
+
+ Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
+ Store (0x1E, HSTS)
+ Store (0xFA, Local0)
+ While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
+ Stall (0x64)
+ Decrement (Local0)
+ }
+
+ Return (Local0)
+ }
+
+ Method (SWTC, 1, NotSerialized) {
+ Store (Arg0, Local0)
+ Store (0x07, Local2)
+ Store (One, Local1)
+ While (LEqual (Local1, One)) {
+ Store (And (HSTS, 0x1E), Local3)
+ If (LNotEqual (Local3, Zero)) { /* read sucess */
+ If (LEqual (Local3, 0x02)) {
+ Store (Zero, Local2)
+ }
+
+ Store (Zero, Local1)
+ }
+ Else {
+ If (LLess (Local0, 0x0A)) { /* read failure */
+ Store (0x10, Local2)
+ Store (Zero, Local1)
+ }
+ Else {
+ Sleep (0x0A) /* 10 ms, try again */
+ Subtract (Local0, 0x0A, Local0)
+ }
+ }
+ }
+
+ Return (Local2)
+ }
+
+ Method (SMBR, 3, NotSerialized) {
+ Store (0x07, Local0)
+ If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
+ Store (WCLR (), Local0) /* clear SMBUS status register before read data */
+ If (LEqual (Local0, Zero)) {
+ Release (SBX0)
+ Return (0x0)
+ }
+
+ Store (0x1F, HSTS)
+ Store (Or (ShiftLeft (Arg1, One), One), HADD)
+ Store (Arg2, HCMD)
+ If (LEqual (Arg0, 0x07)) {
+ Store (0x48, HCNT) /* read byte */
+ }
+
+ Store (SWTC (0x03E8), Local1) /* 1000 ms */
+ If (LEqual (Local1, Zero)) {
+ If (LEqual (Arg0, 0x07)) {
+ Store (DAT0, Local0)
+ }
+ }
+ Else {
+ Store (Local1, Local0)
+ }
+
+ Release (SBX0)
+ }
+
+ /* DBGO("the value of SMBusData0 register ") */
+ /* DBGO(Arg2) */
+ /* DBGO(" is ") */
+ /* DBGO(Local0) */
+ /* DBGO("\n") */
+
+ Return (Local0)
+ }
+
+ /* THERMAL */
+ Scope(\_TZ) {
+ Name (KELV, 2732)
+ Name (THOT, 800)
+ Name (TCRT, 850)
+
+ ThermalZone(TZ00) {
+ Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
+ /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
+ Return(Add(0, 2730))
+ }
+ Method(_AL0,0) { /* Returns package of cooling device to turn on */
+ /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
+ Return(Package() {\_TZ.TZ00.FAN0})
+ }
+ Device (FAN0) {
+ Name(_HID, EISAID("PNP0C0B"))
+ Name(_PR0, Package() {PFN0})
+ }
+
+ PowerResource(PFN0,0,0) {
+ Method(_STA) {
+ Store(0xF,Local0)
+ Return(Local0)
+ }
+ Method(_ON) {
+ /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
+ }
+ Method(_OFF) {
+ /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
+ }
+ }
+
+ Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
+ /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
+ Return (Add (THOT, KELV))
+ }
+ Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
+ /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
+ Return (Add (TCRT, KELV))
+ }
+ Method(_TMP,0) { /* return current temp of this zone */
+ Store (SMBR (0x07, 0x4C,, 0x00), Local0)
+ If (LGreater (Local0, 0x10)) {
+ Store (Local0, Local1)
+ }
+ Else {
+ Add (Local0, THOT, Local0)
+ Return (Add (400, KELV))
+ }
+
+ Store (SMBR (0x07, 0x4C, 0x01), Local0)
+ /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
+ /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
+ If (LGreater (Local0, 0x10)) {
+ If (LGreater (Local0, Local1)) {
+ Store (Local0, Local1)
+ }
+
+ Multiply (Local1, 10, Local1)
+ Return (Add (Local1, KELV))
+ }
+ Else {
+ Add (Local0, THOT, Local0)
+ Return (Add (400 , KELV))
+ }
+ } /* end of _TMP */
+ } /* end of TZ00 */
+ }
+}
+/* End of ASL file */
ifdef POST_EVALUATION
-$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
- iasl -p $(obj)/dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
- mv $(obj)/dsdt.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
$(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c -o $@
ifdef POST_EVALUATION
-$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
- iasl -p $(obj)/dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
- mv $(obj)/dsdt.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
$(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c -o $@
ifdef POST_EVALUATION
-$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
- $(CPP) -D__ACPI__ -P $(CPPFLAGS) -include $(obj)/config.h -I$(src)/mainboard/$(MAINBOARDDIR) $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl -o $(obj)/dsdt.asl
- iasl -p $(obj)/dsdt -tc $(obj)/dsdt.asl
- mv $(obj)/dsdt.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
ifdef POST_EVALUATION
-$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
- iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
- mv dsdt.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
-$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl
- iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl
- perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex
- mv pci2.hex ssdt2.c
-
-$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl"
- iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/
- perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex
- mv pci3.hex ssdt3.c
-
-$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl"
- iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl
- perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex
- mv pci4.hex ssdt4.c
-
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
ifdef POST_EVALUATION
-$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
- iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
- mv dsdt.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
-$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl
- iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl
- perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex
- mv pci2.hex ssdt2.c
-
-$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl"
- iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/
- perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex
- mv pci3.hex ssdt3.c
-
-$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl"
- iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl
- perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex
- mv pci4.hex ssdt4.c
-
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
ifdef POST_EVALUATION
-$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
- iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
- mv dsdt.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
-$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl
- iasl -p $(obj)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl
- perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' $(obj)/pci2.hex
- mv $(obj)/pci2.hex $(obj)/ssdt2.c
-
-$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl"
- iasl -p $(obj)/pci3 -tc $(CONFIG_MAINBOARD)/
- perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' $(obj)/pci3.hex
- mv $(obj)/pci3.hex $(obj)/ssdt3.c
-
-$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl"
- iasl -p $(obj)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl
- perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' $(obj)/pci4.hex
- mv $(obj)/pci4.hex $(obj)/ssdt4.c
-
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
ifdef POST_EVALUATION
-$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
- iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
- mv dsdt.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
-$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl
- iasl -p $(obj)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl
- perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' $(obj)/pci2.hex
- mv $(obj)/pci2.hex $(obj)/ssdt2.c
-
-$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl"
- iasl -p $(obj)/pci3 -tc $(CONFIG_MAINBOARD)/
- perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' $(obj)/pci3.hex
- mv $(obj)/pci3.hex $(obj)/ssdt3.c
-
-$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl"
- iasl -p $(obj)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl
- perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' $(obj)/pci4.hex
- mv $(obj)/pci4.hex $(obj)/ssdt4.c
-
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
ifdef POST_EVALUATION
-$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/acpi/dsdt.asl
- iasl -p $(obj)/dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/acpi/dsdt.asl
- mv $(obj)/dsdt.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
0x00010001
)
{
- Include ("debug.asl")
+ #include "debug.asl"
}
*/
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* DefinitionBlock Statement */
-DefinitionBlock (
- "DSDT.AML", /* Output filename */
- "DSDT", /* Signature */
- 0x02, /* DSDT Revision, needs to be 2 for 64bit */
- "TECHNEXION", /* OEMID */
- "TIM-5690", /* TABLE ID */
- 0x00010001 /* OEM Revision */
- )
-{ /* Start of ASL file */
- /* Include ("debug.asl") */ /* Include global debug methods if needed */
-
- /* Data to be patched by the BIOS during POST */
- /* FIXME the patching is not done yet! */
- /* Memory related values */
- Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
- Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
- Name(PBLN, 0x0) /* Length of BIOS area */
-
- Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
- Name(HPBA, 0xFED00000) /* Base address of HPET table */
-
- Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
-
- /* USB overcurrent mapping pins. */
- Name(UOM0, 0)
- Name(UOM1, 2)
- Name(UOM2, 0)
- Name(UOM3, 7)
- Name(UOM4, 2)
- Name(UOM5, 2)
- Name(UOM6, 6)
- Name(UOM7, 2)
- Name(UOM8, 6)
- Name(UOM9, 6)
-
- /* Some global data */
- Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
- Name(OSV, Ones) /* Assume nothing */
- Name(PMOD, One) /* Assume APIC */
-
- /* PIC IRQ mapping registers, C00h-C01h */
- OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
- Field(PRQM, ByteAcc, NoLock, Preserve) {
- PRQI, 0x00000008,
- PRQD, 0x00000008, /* Offset: 1h */
- }
- IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
- PINA, 0x00000008, /* Index 0 */
- PINB, 0x00000008, /* Index 1 */
- PINC, 0x00000008, /* Index 2 */
- PIND, 0x00000008, /* Index 3 */
- AINT, 0x00000008, /* Index 4 */
- SINT, 0x00000008, /* Index 5 */
- , 0x00000008, /* Index 6 */
- AAUD, 0x00000008, /* Index 7 */
- AMOD, 0x00000008, /* Index 8 */
- PINE, 0x00000008, /* Index 9 */
- PINF, 0x00000008, /* Index A */
- PING, 0x00000008, /* Index B */
- PINH, 0x00000008, /* Index C */
- }
-
- /* PCI Error control register */
- OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
- Field(PERC, ByteAcc, NoLock, Preserve) {
- SENS, 0x00000001,
- PENS, 0x00000001,
- SENE, 0x00000001,
- PENE, 0x00000001,
- }
-
- /* Client Management index/data registers */
- OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
- Field(CMT, ByteAcc, NoLock, Preserve) {
- CMTI, 8,
- /* Client Management Data register */
- G64E, 1,
- G64O, 1,
- G32O, 2,
- , 2,
- GPSL, 2,
- }
-
- /* GPM Port register */
- OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
- Field(GPT, ByteAcc, NoLock, Preserve) {
- GPB0,1,
- GPB1,1,
- GPB2,1,
- GPB3,1,
- GPB4,1,
- GPB5,1,
- GPB6,1,
- GPB7,1,
- }
-
- /* Flash ROM program enable register */
- OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
- Field(FRE, ByteAcc, NoLock, Preserve) {
- , 0x00000006,
- FLRE, 0x00000001,
- }
-
- /* PM2 index/data registers */
- OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
- Field(PM2R, ByteAcc, NoLock, Preserve) {
- PM2I, 0x00000008,
- PM2D, 0x00000008,
- }
-
- /* Power Management I/O registers */
- OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
- Field(PIOR, ByteAcc, NoLock, Preserve) {
- PIOI, 0x00000008,
- PIOD, 0x00000008,
- }
- IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
- Offset(0x00), /* MiscControl */
- , 1,
- T1EE, 1,
- T2EE, 1,
- Offset(0x01), /* MiscStatus */
- , 1,
- T1E, 1,
- T2E, 1,
- Offset(0x04), /* SmiWakeUpEventEnable3 */
- , 7,
- SSEN, 1,
- Offset(0x07), /* SmiWakeUpEventStatus3 */
- , 7,
- CSSM, 1,
- Offset(0x10), /* AcpiEnable */
- , 6,
- PWDE, 1,
- Offset(0x1C), /* ProgramIoEnable */
- , 3,
- MKME, 1,
- IO3E, 1,
- IO2E, 1,
- IO1E, 1,
- IO0E, 1,
- Offset(0x1D), /* IOMonitorStatus */
- , 3,
- MKMS, 1,
- IO3S, 1,
- IO2S, 1,
- IO1S, 1,
- IO0S,1,
- Offset(0x20), /* AcpiPmEvtBlk */
- APEB, 16,
- Offset(0x36), /* GEvtLevelConfig */
- , 6,
- ELC6, 1,
- ELC7, 1,
- Offset(0x37), /* GPMLevelConfig0 */
- , 3,
- PLC0, 1,
- PLC1, 1,
- PLC2, 1,
- PLC3, 1,
- PLC8, 1,
- Offset(0x38), /* GPMLevelConfig1 */
- , 1,
- PLC4, 1,
- PLC5, 1,
- , 1,
- PLC6, 1,
- PLC7, 1,
- Offset(0x3B), /* PMEStatus1 */
- GP0S, 1,
- GM4S, 1,
- GM5S, 1,
- APS, 1,
- GM6S, 1,
- GM7S, 1,
- GP2S, 1,
- STSS, 1,
- Offset(0x55), /* SoftPciRst */
- SPRE, 1,
- , 1,
- , 1,
- PNAT, 1,
- PWMK, 1,
- PWNS, 1,
-
- /* Offset(0x61), */ /* Options_1 */
- /* ,7, */
- /* R617,1, */
-
- Offset(0x65), /* UsbPMControl */
- , 4,
- URRE, 1,
- Offset(0x68), /* MiscEnable68 */
- , 3,
- TMTE, 1,
- , 1,
- Offset(0x92), /* GEVENTIN */
- , 7,
- E7IS, 1,
- Offset(0x96), /* GPM98IN */
- G8IS, 1,
- G9IS, 1,
- Offset(0x9A), /* EnhanceControl */
- ,7,
- HPDE, 1,
- Offset(0xA8), /* PIO7654Enable */
- IO4E, 1,
- IO5E, 1,
- IO6E, 1,
- IO7E, 1,
- Offset(0xA9), /* PIO7654Status */
- IO4S, 1,
- IO5S, 1,
- IO6S, 1,
- IO7S, 1,
- }
-
- /* PM1 Event Block
- * First word is PM1_Status, Second word is PM1_Enable
- */
- OperationRegion(P1EB, SystemIO, APEB, 0x04)
- Field(P1EB, ByteAcc, NoLock, Preserve) {
- TMST, 1,
- , 3,
- BMST, 1,
- GBST, 1,
- Offset(0x01),
- PBST, 1,
- , 1,
- RTST, 1,
- , 3,
- PWST, 1,
- SPWS, 1,
- Offset(0x02),
- TMEN, 1,
- , 4,
- GBEN, 1,
- Offset(0x03),
- PBEN, 1,
- , 1,
- RTEN, 1,
- , 3,
- PWDA, 1,
- }
-
- Scope(\_SB) {
-
- /* PCIe Configuration Space for 16 busses */
- OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
- Field(PCFG, ByteAcc, NoLock, Preserve) {
- /* Byte offsets are computed using the following technique:
- * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
- * The 8 comes from 8 functions per device, and 4096 bytes per function config space
- */
- Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */
- STB5, 32,
- Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
- PT0D, 1,
- PT1D, 1,
- PT2D, 1,
- PT3D, 1,
- PT4D, 1,
- PT5D, 1,
- PT6D, 1,
- PT7D, 1,
- PT8D, 1,
- PT9D, 1,
- Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
- SBIE, 1,
- SBME, 1,
- Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
- SBRI, 8,
- Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
- SBB1, 32,
- Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
- ,14,
- P92E, 1, /* Port92 decode enable */
- }
-
- OperationRegion(SB5, SystemMemory, STB5, 0x1000)
- Field(SB5, AnyAcc, NoLock, Preserve)
- {
- /* Port 0 */
- Offset(0x120), /* Port 0 Task file status */
- P0ER, 1,
- , 2,
- P0DQ, 1,
- , 3,
- P0BY, 1,
- Offset(0x128), /* Port 0 Serial ATA status */
- P0DD, 4,
- , 4,
- P0IS, 4,
- Offset(0x12C), /* Port 0 Serial ATA control */
- P0DI, 4,
- Offset(0x130), /* Port 0 Serial ATA error */
- , 16,
- P0PR, 1,
-
- /* Port 1 */
- offset(0x1A0), /* Port 1 Task file status */
- P1ER, 1,
- , 2,
- P1DQ, 1,
- , 3,
- P1BY, 1,
- Offset(0x1A8), /* Port 1 Serial ATA status */
- P1DD, 4,
- , 4,
- P1IS, 4,
- Offset(0x1AC), /* Port 1 Serial ATA control */
- P1DI, 4,
- Offset(0x1B0), /* Port 1 Serial ATA error */
- , 16,
- P1PR, 1,
-
- /* Port 2 */
- Offset(0x220), /* Port 2 Task file status */
- P2ER, 1,
- , 2,
- P2DQ, 1,
- , 3,
- P2BY, 1,
- Offset(0x228), /* Port 2 Serial ATA status */
- P2DD, 4,
- , 4,
- P2IS, 4,
- Offset(0x22C), /* Port 2 Serial ATA control */
- P2DI, 4,
- Offset(0x230), /* Port 2 Serial ATA error */
- , 16,
- P2PR, 1,
-
- /* Port 3 */
- Offset(0x2A0), /* Port 3 Task file status */
- P3ER, 1,
- , 2,
- P3DQ, 1,
- , 3,
- P3BY, 1,
- Offset(0x2A8), /* Port 3 Serial ATA status */
- P3DD, 4,
- , 4,
- P3IS, 4,
- Offset(0x2AC), /* Port 3 Serial ATA control */
- P3DI, 4,
- Offset(0x2B0), /* Port 3 Serial ATA error */
- , 16,
- P3PR, 1,
- }
- }
-
- Include ("routing.asl")
-
- Scope(\_SB) {
-
- Method(CkOT, 0){
-
- if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */
-
- if(CondRefOf(\_OSI,Local1))
- {
- Store(1, OSTP) /* Assume some form of XP */
- if (\_OSI("Windows 2006")) /* Vista */
- {
- Store(2, OSTP)
- }
- } else {
- If(WCMP(\_OS,"Linux")) {
- Store(3, OSTP) /* Linux */
- } Else {
- Store(4, OSTP) /* Gotta be WinCE */
- }
- }
- Return(OSTP)
- }
-
- Method(_PIC, 0x01, NotSerialized)
- {
- If (Arg0)
- {
- \_SB.CIRQ()
- }
- Store(Arg0, PMOD)
- }
-
- Method(CIRQ, 0x00, NotSerialized)
- {
- Store(0, PINA)
- Store(0, PINB)
- Store(0, PINC)
- Store(0, PIND)
- Store(0, PINE)
- Store(0, PINF)
- Store(0, PING)
- Store(0, PINH)
- }
-
- Name(IRQB, ResourceTemplate(){
- IRQ(Level,ActiveLow,Shared){15}
- })
-
- Name(IRQP, ResourceTemplate(){
- IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
- })
-
- Name(PITF, ResourceTemplate(){
- IRQ(Level,ActiveLow,Exclusive){9}
- })
-
- Device(INTA) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 1)
-
- Method(_STA, 0) {
- if (PINA) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTA._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKA\\_DIS\n") */
- Store(0, PINA)
- } /* End Method(_SB.INTA._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKA\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTA._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKA\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINA, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTA._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKA\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINA)
- } /* End Method(_SB.INTA._SRS) */
- } /* End Device(INTA) */
-
- Device(INTB) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 2)
-
- Method(_STA, 0) {
- if (PINB) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTB._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKB\\_DIS\n") */
- Store(0, PINB)
- } /* End Method(_SB.INTB._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKB\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTB._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKB\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINB, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTB._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKB\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINB)
- } /* End Method(_SB.INTB._SRS) */
- } /* End Device(INTB) */
-
- Device(INTC) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 3)
-
- Method(_STA, 0) {
- if (PINC) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTC._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKC\\_DIS\n") */
- Store(0, PINC)
- } /* End Method(_SB.INTC._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKC\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTC._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKC\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINC, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTC._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKC\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINC)
- } /* End Method(_SB.INTC._SRS) */
- } /* End Device(INTC) */
-
- Device(INTD) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 4)
-
- Method(_STA, 0) {
- if (PIND) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTD._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKD\\_DIS\n") */
- Store(0, PIND)
- } /* End Method(_SB.INTD._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKD\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTD._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKD\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PIND, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTD._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKD\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PIND)
- } /* End Method(_SB.INTD._SRS) */
- } /* End Device(INTD) */
-
- Device(INTE) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 5)
-
- Method(_STA, 0) {
- if (PINE) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTE._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKE\\_DIS\n") */
- Store(0, PINE)
- } /* End Method(_SB.INTE._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKE\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTE._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKE\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINE, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTE._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKE\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINE)
- } /* End Method(_SB.INTE._SRS) */
- } /* End Device(INTE) */
-
- Device(INTF) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 6)
-
- Method(_STA, 0) {
- if (PINF) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTF._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKF\\_DIS\n") */
- Store(0, PINF)
- } /* End Method(_SB.INTF._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKF\\_PRS\n") */
- Return(PITF)
- } /* Method(_SB.INTF._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKF\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINF, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTF._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKF\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINF)
- } /* End Method(_SB.INTF._SRS) */
- } /* End Device(INTF) */
-
- Device(INTG) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 7)
-
- Method(_STA, 0) {
- if (PING) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTG._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKG\\_DIS\n") */
- Store(0, PING)
- } /* End Method(_SB.INTG._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKG\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTG._CRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKG\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PING, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTG._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKG\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PING)
- } /* End Method(_SB.INTG._SRS) */
- } /* End Device(INTG) */
-
- Device(INTH) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 8)
-
- Method(_STA, 0) {
- if (PINH) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTH._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKH\\_DIS\n") */
- Store(0, PINH)
- } /* End Method(_SB.INTH._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKH\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTH._CRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKH\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINH, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTH._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKH\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINH)
- } /* End Method(_SB.INTH._SRS) */
- } /* End Device(INTH) */
-
- } /* End Scope(_SB) */
-
-
- /* Supported sleep states: */
- Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
-
- If (LAnd(SSFG, 0x01)) {
- Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
- }
- If (LAnd(SSFG, 0x02)) {
- Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
- }
- If (LAnd(SSFG, 0x04)) {
- Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
- }
- If (LAnd(SSFG, 0x08)) {
- Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
- }
-
- Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
-
- Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
- Name(CSMS, 0) /* Current System State */
-
- /* Wake status package */
- Name(WKST,Package(){Zero, Zero})
-
- /*
- * \_PTS - Prepare to Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2, etc
- *
- * Exit:
- * -none-
- *
- * The _PTS control method is executed at the beginning of the sleep process
- * for S1-S5. The sleeping value is passed to the _PTS control method. This
- * control method may be executed a relatively long time before entering the
- * sleep state and the OS may abort the operation without notification to
- * the ACPI driver. This method cannot modify the configuration or power
- * state of any device in the system.
- */
- Method(\_PTS, 1) {
- /* DBGO("\\_PTS\n") */
- /* DBGO("From S0 to S") */
- /* DBGO(Arg0) */
- /* DBGO("\n") */
-
- /* Don't allow PCIRST# to reset USB */
- if (LEqual(Arg0,3)){
- Store(0,URRE)
- }
-
- /* Clear sleep SMI status flag and enable sleep SMI trap. */
- /*Store(One, CSSM)
- Store(One, SSEN)*/
-
- /* On older chips, clear PciExpWakeDisEn */
- /*if (LLessEqual(\_SB.SBRI, 0x13)) {
- * Store(0,\_SB.PWDE)
- *}
- */
-
- /* Clear wake status structure. */
- Store(0, Index(WKST,0))
- Store(0, Index(WKST,1))
- \_SB.PCI0.SIOS (Arg0)
- } /* End Method(\_PTS) */
-
- /*
- * The following method results in a "not a valid reserved NameSeg"
- * warning so I have commented it out for the duration. It isn't
- * used, so it could be removed.
- *
- *
- * \_GTS OEM Going To Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * -none-
- *
- * Method(\_GTS, 1) {
- * DBGO("\\_GTS\n")
- * DBGO("From S0 to S")
- * DBGO(Arg0)
- * DBGO("\n")
- * }
- */
-
- /*
- * \_BFS OEM Back From Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * -none-
- */
- Method(\_BFS, 1) {
- /* DBGO("\\_BFS\n") */
- /* DBGO("From S") */
- /* DBGO(Arg0) */
- /* DBGO(" to S0\n") */
- }
-
- /*
- * \_WAK System Wake method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * Return package of 2 DWords
- * Dword 1 - Status
- * 0x00000000 wake succeeded
- * 0x00000001 Wake was signaled but failed due to lack of power
- * 0x00000002 Wake was signaled but failed due to thermal condition
- * Dword 2 - Power Supply state
- * if non-zero the effective S-state the power supply entered
- */
- Method(\_WAK, 1) {
- /* DBGO("\\_WAK\n") */
- /* DBGO("From S") */
- /* DBGO(Arg0) */
- /* DBGO(" to S0\n") */
-
- /* Re-enable HPET */
- Store(1,HPDE)
-
- /* Restore PCIRST# so it resets USB */
- if (LEqual(Arg0,3)){
- Store(1,URRE)
- }
-
- /* Arbitrarily clear PciExpWakeStatus */
- Store(PWST, PWST)
-
- /* if(DeRefOf(Index(WKST,0))) {
- * Store(0, Index(WKST,1))
- * } else {
- * Store(Arg0, Index(WKST,1))
- * }
- */
- \_SB.PCI0.SIOW (Arg0)
- Return(WKST)
- } /* End Method(\_WAK) */
-
- Scope(\_GPE) { /* Start Scope GPE */
- /* General event 0 */
- /* Method(_L00) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 1 */
- /* Method(_L01) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 2 */
- /* Method(_L02) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 3 */
- //Method(_L03) {
- // /* DBGO("\\_GPE\\_L00\n") */
- // Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- //}
-
- /* General event 4 */
- /* Method(_L04) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 5 */
- /* Method(_L05) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 6 - Used for GPM6, moved to USB.asl */
- /* Method(_L06) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 7 - Used for GPM7, moved to USB.asl */
- /* Method(_L07) {
- * DBGO("\\_GPE\\_L07\n")
- * }
- */
-
- /* Legacy PM event */
- Method(_L08) {
- /* DBGO("\\_GPE\\_L08\n") */
- }
-
- /* Temp warning (TWarn) event */
- Method(_L09) {
- /* DBGO("\\_GPE\\_L09\n") */
- Notify (\_TZ.TZ00, 0x80)
- }
-
- /* Reserved */
- /* Method(_L0A) {
- * DBGO("\\_GPE\\_L0A\n")
- * }
- */
-
- /* USB controller PME# */
- Method(_L0B) {
- /* DBGO("\\_GPE\\_L0B\n") */
- Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* AC97 controller PME# */
- /* Method(_L0C) {
- * DBGO("\\_GPE\\_L0C\n")
- * }
- */
-
- /* OtherTherm PME# */
- /* Method(_L0D) {
- * DBGO("\\_GPE\\_L0D\n")
- * }
- */
-
- /* GPM9 SCI event - Moved to USB.asl */
- /* Method(_L0E) {
- * DBGO("\\_GPE\\_L0E\n")
- * }
- */
-
- /* PCIe HotPlug event */
- /* Method(_L0F) {
- * DBGO("\\_GPE\\_L0F\n")
- * }
- */
-
- /* ExtEvent0 SCI event */
- Method(_L10) {
- /* DBGO("\\_GPE\\_L10\n") */
- }
-
-
- /* ExtEvent1 SCI event */
- Method(_L11) {
- /* DBGO("\\_GPE\\_L11\n") */
- }
-
- /* PCIe PME# event */
- /* Method(_L12) {
- * DBGO("\\_GPE\\_L12\n")
- * }
- */
-
- /* GPM0 SCI event - Moved to USB.asl */
- /* Method(_L13) {
- * DBGO("\\_GPE\\_L13\n")
- * }
- */
-
- /* GPM1 SCI event - Moved to USB.asl */
- /* Method(_L14) {
- * DBGO("\\_GPE\\_L14\n")
- * }
- */
-
- /* GPM2 SCI event - Moved to USB.asl */
- /* Method(_L15) {
- * DBGO("\\_GPE\\_L15\n")
- * }
- */
-
- /* GPM3 SCI event - Moved to USB.asl */
- /* Method(_L16) {
- * DBGO("\\_GPE\\_L16\n")
- * }
- */
-
- /* GPM8 SCI event - Moved to USB.asl */
- /* Method(_L17) {
- * DBGO("\\_GPE\\_L17\n")
- * }
- */
-
- /* GPIO0 or GEvent8 event */
- Method(_L18) {
- /* DBGO("\\_GPE\\_L18\n") */
- Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* GPM4 SCI event - Moved to USB.asl */
- /* Method(_L19) {
- * DBGO("\\_GPE\\_L19\n")
- * }
- */
-
- /* GPM5 SCI event - Moved to USB.asl */
- /* Method(_L1A) {
- * DBGO("\\_GPE\\_L1A\n")
- * }
- */
-
- /* Azalia SCI event */
- Method(_L1B) {
- /* DBGO("\\_GPE\\_L1B\n") */
- Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* GPM6 SCI event - Reassigned to _L06 */
- /* Method(_L1C) {
- * DBGO("\\_GPE\\_L1C\n")
- * }
- */
-
- /* GPM7 SCI event - Reassigned to _L07 */
- /* Method(_L1D) {
- * DBGO("\\_GPE\\_L1D\n")
- * }
- */
-
- /* GPIO2 or GPIO66 SCI event */
- /* Method(_L1E) {
- * DBGO("\\_GPE\\_L1E\n")
- * }
- */
-
- /* SATA SCI event - Moved to sata.asl */
- /* Method(_L1F) {
- * DBGO("\\_GPE\\_L1F\n")
- * }
- */
-
- } /* End Scope GPE */
-
- Include ("usb.asl")
-
- /* South Bridge */
- Scope(\_SB) { /* Start \_SB scope */
- Include ("globutil.asl") /* global utility methods expected within the \_SB scope */
-
- /* _SB.PCI0 */
- /* Note: Only need HID on Primary Bus */
- Device(PCI0) {
- External (TOM1)
- External (TOM2)
- Name(_HID, EISAID("PNP0A03"))
- Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
- Method(_BBN, 0) { /* Bus number = 0 */
- Return(0)
- }
- Method(_STA, 0) {
- /* DBGO("\\_SB\\PCI0\\_STA\n") */
- Return(0x0B) /* Status is visible */
- }
-
- Method(_PRT,0) {
- If(PMOD){ Return(APR0) } /* APIC mode */
- Return (PR0) /* PIC Mode */
- } /* end _PRT */
-
- /* Describe the Northbridge devices */
- Device(AMRT) {
- Name(_ADR, 0x00000000)
- } /* end AMRT */
-
- /* The internal GFX bridge */
- Device(AGPB) {
- Name(_ADR, 0x00010000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- Return (APR1)
- }
- } /* end AGPB */
-
- /* The external GFX bridge */
- Device(PBR2) {
- Name(_ADR, 0x00020000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS2) } /* APIC mode */
- Return (PS2) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR2 */
-
- /* Dev3 is also an external GFX bridge, not used in Herring */
-
- Device(PBR4) {
- Name(_ADR, 0x00040000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS4) } /* APIC mode */
- Return (PS4) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR4 */
-
- Device(PBR5) {
- Name(_ADR, 0x00050000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS5) } /* APIC mode */
- Return (PS5) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR5 */
-
- Device(PBR6) {
- Name(_ADR, 0x00060000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS6) } /* APIC mode */
- Return (PS6) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR6 */
-
- /* The onboard EtherNet chip */
- Device(PBR7) {
- Name(_ADR, 0x00070000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS7) } /* APIC mode */
- Return (PS7) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR7 */
-
-
- /* PCI slot 1, 2, 3 */
- Device(PIBR) {
- Name(_ADR, 0x00140004)
- Name(_PRW, Package() {0x18, 4})
-
- Method(_PRT, 0) {
- Return (PCIB)
- }
- }
-
- /* Describe the Southbridge devices */
- Device(STCR) {
- Name(_ADR, 0x00120000)
- Include ("sata.asl")
- } /* end STCR */
-
- Device(UOH1) {
- Name(_ADR, 0x00130000)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH1 */
-
- Device(UOH2) {
- Name(_ADR, 0x00130001)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH2 */
-
- Device(UOH3) {
- Name(_ADR, 0x00130002)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH3 */
-
- Device(UOH4) {
- Name(_ADR, 0x00130003)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH4 */
-
- Device(UOH5) {
- Name(_ADR, 0x00130004)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH5 */
-
- Device(UEH1) {
- Name(_ADR, 0x00130005)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UEH1 */
-
- Device(SBUS) {
- Name(_ADR, 0x00140000)
- } /* end SBUS */
-
- /* Primary (and only) IDE channel */
- Device(IDEC) {
- Name(_ADR, 0x00140001)
- Include ("ide.asl")
- } /* end IDEC */
-
- Device(AZHD) {
- Name(_ADR, 0x00140002)
- OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
- Field(AZPD, AnyAcc, NoLock, Preserve) {
- offset (0x42),
- NSDI, 1,
- NSDO, 1,
- NSEN, 1,
- offset (0x44),
- IPCR, 4,
- offset (0x54),
- PWST, 2,
- , 6,
- PMEB, 1,
- , 6,
- PMST, 1,
- offset (0x62),
- MMCR, 1,
- offset (0x64),
- MMLA, 32,
- offset (0x68),
- MMHA, 32,
- offset (0x6C),
- MMDT, 16,
- }
-
- Method(_INI) {
- If(LEqual(OSTP,3)){ /* If we are running Linux */
- Store(zero, NSEN)
- Store(one, NSDO)
- Store(one, NSDI)
- }
- }
- } /* end AZHD */
-
- Device(LIBR) {
- Name(_ADR, 0x00140003)
- /* Method(_INI) {
- * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
- } */ /* End Method(_SB.SBRDG._INI) */
-
- /* Real Time Clock Device */
- Device(RTC0) {
- Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){8}
- IO(Decode16,0x0070, 0x0070, 0, 2)
- /* IO(Decode16,0x0070, 0x0070, 0, 4) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
-
- Device(TMR) { /* Timer */
- Name(_HID,EISAID("PNP0100")) /* System Timer */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){0}
- IO(Decode16, 0x0040, 0x0040, 0, 4)
- /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
-
- Device(SPKR) { /* Speaker */
- Name(_HID,EISAID("PNP0800")) /* AT style speaker */
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x0061, 0x0061, 0, 1)
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
-
- Device(PIC) {
- Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){2}
- IO(Decode16,0x0020, 0x0020, 0, 2)
- IO(Decode16,0x00A0, 0x00A0, 0, 2)
- /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
- /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
-
- Device(MAD) { /* 8257 DMA */
- Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
- Name(_CRS, ResourceTemplate() {
- DMA(Compatibility,BusMaster,Transfer8){4}
- IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
- IO(Decode16, 0x0081, 0x0081, 0x10, 0x03)
- IO(Decode16, 0x0087, 0x0087, 0x10, 0x01)
- IO(Decode16, 0x0089, 0x0089, 0x10, 0x03)
- IO(Decode16, 0x008F, 0x008F, 0x10, 0x01)
- IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
- }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
- } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
-
- Device(COPR) {
- Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
- IRQNoFlags(){13}
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
-
- Device(HPTM) {
- Name(_HID,EISAID("PNP0103"))
- Name(CRS,ResourceTemplate() {
- Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
- })
- Method(_STA, 0) {
- Return(0x0F) /* sata is visible */
- }
- Method(_CRS, 0) {
- CreateDwordField(CRS, ^HPT._BAS, HPBA)
- Store(HPBA, HPBA)
- Return(CRS)
- }
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
- } /* end LIBR */
-
- Device(HPBR) {
- Name(_ADR, 0x00140004)
- } /* end HostPciBr */
-
- Device(ACAD) {
- Name(_ADR, 0x00140005)
- } /* end Ac97audio */
-
- Device(ACMD) {
- Name(_ADR, 0x00140006)
- } /* end Ac97modem */
-
- /* ITE IT8712F Support */
- OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
- Field (IOID, ByteAcc, NoLock, Preserve)
- {
- SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */
- }
-
- IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
- {
- Offset (0x07),
- LDN, 8, /* Logical Device Number */
- Offset (0x20),
- CID1, 8, /* Chip ID Byte 1, 0x87 */
- CID2, 8, /* Chip ID Byte 2, 0x12 */
- Offset (0x30),
- ACTR, 8, /* Function activate */
- Offset (0xF0),
- APC0, 8, /* APC/PME Event Enable Register */
- APC1, 8, /* APC/PME Status Register */
- APC2, 8, /* APC/PME Control Register 1 */
- APC3, 8, /* Environment Controller Special Configuration Register */
- APC4, 8 /* APC/PME Control Register 2 */
- }
-
- /* Enter the IT8712F MB PnP Mode */
- Method (EPNP)
- {
- Store(0x87, SIOI)
- Store(0x01, SIOI)
- Store(0x55, SIOI)
- Store(0x55, SIOI) /* IT8712F magic number */
- }
- /* Exit the IT8712F MB PnP Mode */
- Method (XPNP)
- {
- Store (0x02, SIOI)
- Store (0x02, SIOD)
- }
-
- /*
- * Keyboard PME is routed to SB600 Gevent3. We can wake
- * up the system by pressing the key.
- */
- Method (SIOS, 1)
- {
- /* We only enable KBD PME for S5. */
- If (LLess (Arg0, 0x05))
- {
- EPNP()
- /* DBGO("IT8712F\n") */
-
- Store (0x4, LDN)
- Store (One, ACTR) /* Enable EC */
- /*
- Store (0x4, LDN)
- Store (0x04, APC4)
- */ /* falling edge. which mode? Not sure. */
-
- Store (0x4, LDN)
- Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
- Store (0x4, LDN)
- Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
-
- XPNP()
- }
- }
- Method (SIOW, 1)
- {
- EPNP()
- Store (0x4, LDN)
- Store (Zero, APC0) /* disable keyboard PME */
- Store (0x4, LDN)
- Store (0xFF, APC1) /* clear keyboard PME status */
- XPNP()
- }
-
- Name(CRES, ResourceTemplate() {
- IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0000, /* range minimum */
- 0x0CF7, /* range maximum */
- 0x0000, /* translation */
- 0x0CF8 /* length */
- )
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0D00, /* range minimum */
- 0xFFFF, /* range maximum */
- 0x0000, /* translation */
- 0xF300 /* length */
- )
-
- Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
- Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
- Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
-
- /* DRAM Memory from 1MB to TopMem */
- Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
-
- /* BIOS space just below 4GB */
- DWORDMemory(
- ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000000, /* Max-Min, RLEN */
- ,,
- PCBM
- )
-
- /* DRAM memory from 4GB to TopMem2 */
- QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0xFFFFFFFF, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000000, /* Max-Min, RLEN */
- ,,
- DMHI
- )
-
- /* BIOS space just below 16EB */
- QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0xFFFFFFFF, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000000, /* Max-Min, RLEN */
- ,,
- PEBM
- )
-
- }) /* End Name(_SB.PCI0.CRES) */
-
- Method(_CRS, 0) {
- /* DBGO("\\_SB\\PCI0\\_CRS\n") */
-
- CreateDWordField(CRES, ^EMM1._BAS, EM1B)
- CreateDWordField(CRES, ^EMM1._LEN, EM1L)
- CreateDWordField(CRES, ^DMLO._BAS, DMLB)
- CreateDWordField(CRES, ^DMLO._LEN, DMLL)
- CreateDWordField(CRES, ^PCBM._MIN, PBMB)
- CreateDWordField(CRES, ^PCBM._LEN, PBML)
-
- CreateQWordField(CRES, ^DMHI._MIN, DMHB)
- CreateQWordField(CRES, ^DMHI._LEN, DMHL)
- CreateQWordField(CRES, ^PEBM._MIN, EBMB)
- CreateQWordField(CRES, ^PEBM._LEN, EBML)
-
- If(LGreater(LOMH, 0xC0000)){
- Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
- Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
- }
-
- /* Set size of memory from 1MB to TopMem */
- Subtract(TOM1, 0x100000, DMLL)
-
- /*
- * If(LNotEqual(TOM2, 0x00000000)){
- * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
- * Subtract(TOM2, 0x100000000, DMHL)
- * }
- */
-
- /* If there is no memory above 4GB, put the BIOS just below 4GB */
- If(LEqual(TOM2, 0x00000000)){
- Store(PBAD,PBMB) /* Reserve the "BIOS" space */
- Store(PBLN,PBML)
- }
- Else { /* Otherwise, put the BIOS just below 16EB */
- ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
- Store(PBLN,EBML)
- }
-
- Return(CRES) /* note to change the Name buffer */
- } /* end of Method(_SB.PCI0._CRS) */
-
- /*
- *
- * FIRST METHOD CALLED UPON BOOT
- *
- * 1. If debugging, print current OS and ACPI interpreter.
- * 2. Get PCI Interrupt routing from ACPI VSM, this
- * value is based on user choice in BIOS setup.
- */
- Method(_INI, 0) {
- /* DBGO("\\_SB\\_INI\n") */
- /* DBGO(" DSDT.ASL code from ") */
- /* DBGO(__DATE__) */
- /* DBGO(" ") */
- /* DBGO(__TIME__) */
- /* DBGO("\n Sleep states supported: ") */
- /* DBGO("\n") */
- /* DBGO(" \\_OS=") */
- /* DBGO(\_OS) */
- /* DBGO("\n \\_REV=") */
- /* DBGO(\_REV) */
- /* DBGO("\n") */
-
- /* Determine the OS we're running on */
- CkOT()
-
- /* On older chips, clear PciExpWakeDisEn */
- /*if (LLessEqual(\SBRI, 0x13)) {
- * Store(0,\PWDE)
- * }
- */
- } /* End Method(_SB._INI) */
- } /* End Device(PCI0) */
-
- Device(PWRB) { /* Start Power button device */
- Name(_HID, EISAID("PNP0C0C"))
- Name(_UID, 0xAA)
- //Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
- Name(_STA, 0x0B) /* sata is invisible */
- }
- } /* End \_SB scope */
-
- Scope(\_SI) {
- Method(_SST, 1) {
- /* DBGO("\\_SI\\_SST\n") */
- /* DBGO(" New Indicator state: ") */
- /* DBGO(Arg0) */
- /* DBGO("\n") */
- }
- } /* End Scope SI */
-
- Mutex (SBX0, 0x00)
- OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
- Field (SMB0, ByteAcc, NoLock, Preserve) {
- HSTS, 8, /* SMBUS status */
- SSTS, 8, /* SMBUS slave status */
- HCNT, 8, /* SMBUS control */
- HCMD, 8, /* SMBUS host cmd */
- HADD, 8, /* SMBUS address */
- DAT0, 8, /* SMBUS data0 */
- DAT1, 8, /* SMBUS data1 */
- BLKD, 8, /* SMBUS block data */
- SCNT, 8, /* SMBUS slave control */
- SCMD, 8, /* SMBUS shaow cmd */
- SEVT, 8, /* SMBUS slave event */
- SDAT, 8 /* SMBUS slave data */
- }
-
- Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
- Store (0x1E, HSTS)
- Store (0xFA, Local0)
- While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
- Stall (0x64)
- Decrement (Local0)
- }
-
- Return (Local0)
- }
-
- Method (SWTC, 1, NotSerialized) {
- Store (Arg0, Local0)
- Store (0x07, Local2)
- Store (One, Local1)
- While (LEqual (Local1, One)) {
- Store (And (HSTS, 0x1E), Local3)
- If (LNotEqual (Local3, Zero)) { /* read sucess */
- If (LEqual (Local3, 0x02)) {
- Store (Zero, Local2)
- }
-
- Store (Zero, Local1)
- }
- Else {
- If (LLess (Local0, 0x0A)) { /* read failure */
- Store (0x10, Local2)
- Store (Zero, Local1)
- }
- Else {
- Sleep (0x0A) /* 10 ms, try again */
- Subtract (Local0, 0x0A, Local0)
- }
- }
- }
-
- Return (Local2)
- }
-
- Method (SMBR, 3, NotSerialized) {
- Store (0x07, Local0)
- If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
- Store (WCLR (), Local0) /* clear SMBUS status register before read data */
- If (LEqual (Local0, Zero)) {
- Release (SBX0)
- Return (0x0)
- }
-
- Store (0x1F, HSTS)
- Store (Or (ShiftLeft (Arg1, One), One), HADD)
- Store (Arg2, HCMD)
- If (LEqual (Arg0, 0x07)) {
- Store (0x48, HCNT) /* read byte */
- }
-
- Store (SWTC (0x03E8), Local1) /* 1000 ms */
- If (LEqual (Local1, Zero)) {
- If (LEqual (Arg0, 0x07)) {
- Store (DAT0, Local0)
- }
- }
- Else {
- Store (Local1, Local0)
- }
-
- Release (SBX0)
- }
-
- /* DBGO("the value of SMBusData0 register ") */
- /* DBGO(Arg2) */
- /* DBGO(" is ") */
- /* DBGO(Local0) */
- /* DBGO("\n") */
-
- Return (Local0)
- }
-
- /* THERMAL */
- Scope(\_TZ) {
- Name (KELV, 2732)
- Name (THOT, 800)
- Name (TCRT, 850)
-
- ThermalZone(TZ00) {
- Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
- /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
- Return(Add(0, 2730))
- }
- Method(_AL0,0) { /* Returns package of cooling device to turn on */
- /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
- Return(Package() {\_TZ.TZ00.FAN0})
- }
- Device (FAN0) {
- Name(_HID, EISAID("PNP0C0B"))
- Name(_PR0, Package() {PFN0})
- }
-
- PowerResource(PFN0,0,0) {
- Method(_STA) {
- Store(0xF,Local0)
- Return(Local0)
- }
- Method(_ON) {
- /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
- }
- Method(_OFF) {
- /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
- }
- }
-
- Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
- /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
- Return (Add (THOT, KELV))
- }
- Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
- /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
- Return (Add (TCRT, KELV))
- }
- Method(_TMP,0) { /* return current temp of this zone */
- Store (SMBR (0x07, 0x4C,, 0x00), Local0)
- If (LGreater (Local0, 0x10)) {
- Store (Local0, Local1)
- }
- Else {
- Add (Local0, THOT, Local0)
- Return (Add (400, KELV))
- }
-
- Store (SMBR (0x07, 0x4C, 0x01), Local0)
- /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
- /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
- If (LGreater (Local0, 0x10)) {
- If (LGreater (Local0, Local1)) {
- Store (Local0, Local1)
- }
-
- Multiply (Local1, 10, Local1)
- Return (Add (Local1, KELV))
- }
- Else {
- Add (Local0, THOT, Local0)
- Return (Add (400 , KELV))
- }
- } /* end of _TMP */
- } /* end of TZ00 */
- }
-}
-/* End of ASL file */
/*
Scope(\_SB) {
- Include ("globutil.asl")
+ #include "globutil.asl"
}
*/
Device(PCI0) {
Device(IDEC) {
Name(_ADR, 0x00140001)
- Include ("ide.asl")
+ #include "ide.asl"
}
}
}
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
)
{
- Include ("routing.asl")
+ #include "routing.asl"
}
*/
Device(PCI0) {
Device(SATA) {
Name(_ADR, 0x00120000)
- Include ("sata.asl")
+ #include "sata.asl"
}
}
}
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
)
{
- Include ("usb.asl")
+ #include "usb.asl"
}
*/
Method(UCOC, 0) {
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+ "DSDT.AML", /* Output filename */
+ "DSDT", /* Signature */
+ 0x02, /* DSDT Revision, needs to be 2 for 64bit */
+ "TECHNEXION", /* OEMID */
+ "TIM-5690", /* TABLE ID */
+ 0x00010001 /* OEM Revision */
+ )
+{ /* Start of ASL file */
+ /* #include "acpi/debug.asl" */ /* Include global debug methods if needed */
+
+ /* Data to be patched by the BIOS during POST */
+ /* FIXME the patching is not done yet! */
+ /* Memory related values */
+ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
+ Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+ Name(PBLN, 0x0) /* Length of BIOS area */
+
+ Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
+ Name(HPBA, 0xFED00000) /* Base address of HPET table */
+
+ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+ /* USB overcurrent mapping pins. */
+ Name(UOM0, 0)
+ Name(UOM1, 2)
+ Name(UOM2, 0)
+ Name(UOM3, 7)
+ Name(UOM4, 2)
+ Name(UOM5, 2)
+ Name(UOM6, 6)
+ Name(UOM7, 2)
+ Name(UOM8, 6)
+ Name(UOM9, 6)
+
+ /* Some global data */
+ Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+ Name(OSV, Ones) /* Assume nothing */
+ Name(PMOD, One) /* Assume APIC */
+
+ /* PIC IRQ mapping registers, C00h-C01h */
+ OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
+ Field(PRQM, ByteAcc, NoLock, Preserve) {
+ PRQI, 0x00000008,
+ PRQD, 0x00000008, /* Offset: 1h */
+ }
+ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
+ PINA, 0x00000008, /* Index 0 */
+ PINB, 0x00000008, /* Index 1 */
+ PINC, 0x00000008, /* Index 2 */
+ PIND, 0x00000008, /* Index 3 */
+ AINT, 0x00000008, /* Index 4 */
+ SINT, 0x00000008, /* Index 5 */
+ , 0x00000008, /* Index 6 */
+ AAUD, 0x00000008, /* Index 7 */
+ AMOD, 0x00000008, /* Index 8 */
+ PINE, 0x00000008, /* Index 9 */
+ PINF, 0x00000008, /* Index A */
+ PING, 0x00000008, /* Index B */
+ PINH, 0x00000008, /* Index C */
+ }
+
+ /* PCI Error control register */
+ OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
+ Field(PERC, ByteAcc, NoLock, Preserve) {
+ SENS, 0x00000001,
+ PENS, 0x00000001,
+ SENE, 0x00000001,
+ PENE, 0x00000001,
+ }
+
+ /* Client Management index/data registers */
+ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
+ Field(CMT, ByteAcc, NoLock, Preserve) {
+ CMTI, 8,
+ /* Client Management Data register */
+ G64E, 1,
+ G64O, 1,
+ G32O, 2,
+ , 2,
+ GPSL, 2,
+ }
+
+ /* GPM Port register */
+ OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
+ Field(GPT, ByteAcc, NoLock, Preserve) {
+ GPB0,1,
+ GPB1,1,
+ GPB2,1,
+ GPB3,1,
+ GPB4,1,
+ GPB5,1,
+ GPB6,1,
+ GPB7,1,
+ }
+
+ /* Flash ROM program enable register */
+ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
+ Field(FRE, ByteAcc, NoLock, Preserve) {
+ , 0x00000006,
+ FLRE, 0x00000001,
+ }
+
+ /* PM2 index/data registers */
+ OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
+ Field(PM2R, ByteAcc, NoLock, Preserve) {
+ PM2I, 0x00000008,
+ PM2D, 0x00000008,
+ }
+
+ /* Power Management I/O registers */
+ OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
+ Field(PIOR, ByteAcc, NoLock, Preserve) {
+ PIOI, 0x00000008,
+ PIOD, 0x00000008,
+ }
+ IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
+ Offset(0x00), /* MiscControl */
+ , 1,
+ T1EE, 1,
+ T2EE, 1,
+ Offset(0x01), /* MiscStatus */
+ , 1,
+ T1E, 1,
+ T2E, 1,
+ Offset(0x04), /* SmiWakeUpEventEnable3 */
+ , 7,
+ SSEN, 1,
+ Offset(0x07), /* SmiWakeUpEventStatus3 */
+ , 7,
+ CSSM, 1,
+ Offset(0x10), /* AcpiEnable */
+ , 6,
+ PWDE, 1,
+ Offset(0x1C), /* ProgramIoEnable */
+ , 3,
+ MKME, 1,
+ IO3E, 1,
+ IO2E, 1,
+ IO1E, 1,
+ IO0E, 1,
+ Offset(0x1D), /* IOMonitorStatus */
+ , 3,
+ MKMS, 1,
+ IO3S, 1,
+ IO2S, 1,
+ IO1S, 1,
+ IO0S,1,
+ Offset(0x20), /* AcpiPmEvtBlk */
+ APEB, 16,
+ Offset(0x36), /* GEvtLevelConfig */
+ , 6,
+ ELC6, 1,
+ ELC7, 1,
+ Offset(0x37), /* GPMLevelConfig0 */
+ , 3,
+ PLC0, 1,
+ PLC1, 1,
+ PLC2, 1,
+ PLC3, 1,
+ PLC8, 1,
+ Offset(0x38), /* GPMLevelConfig1 */
+ , 1,
+ PLC4, 1,
+ PLC5, 1,
+ , 1,
+ PLC6, 1,
+ PLC7, 1,
+ Offset(0x3B), /* PMEStatus1 */
+ GP0S, 1,
+ GM4S, 1,
+ GM5S, 1,
+ APS, 1,
+ GM6S, 1,
+ GM7S, 1,
+ GP2S, 1,
+ STSS, 1,
+ Offset(0x55), /* SoftPciRst */
+ SPRE, 1,
+ , 1,
+ , 1,
+ PNAT, 1,
+ PWMK, 1,
+ PWNS, 1,
+
+ /* Offset(0x61), */ /* Options_1 */
+ /* ,7, */
+ /* R617,1, */
+
+ Offset(0x65), /* UsbPMControl */
+ , 4,
+ URRE, 1,
+ Offset(0x68), /* MiscEnable68 */
+ , 3,
+ TMTE, 1,
+ , 1,
+ Offset(0x92), /* GEVENTIN */
+ , 7,
+ E7IS, 1,
+ Offset(0x96), /* GPM98IN */
+ G8IS, 1,
+ G9IS, 1,
+ Offset(0x9A), /* EnhanceControl */
+ ,7,
+ HPDE, 1,
+ Offset(0xA8), /* PIO7654Enable */
+ IO4E, 1,
+ IO5E, 1,
+ IO6E, 1,
+ IO7E, 1,
+ Offset(0xA9), /* PIO7654Status */
+ IO4S, 1,
+ IO5S, 1,
+ IO6S, 1,
+ IO7S, 1,
+ }
+
+ /* PM1 Event Block
+ * First word is PM1_Status, Second word is PM1_Enable
+ */
+ OperationRegion(P1EB, SystemIO, APEB, 0x04)
+ Field(P1EB, ByteAcc, NoLock, Preserve) {
+ TMST, 1,
+ , 3,
+ BMST, 1,
+ GBST, 1,
+ Offset(0x01),
+ PBST, 1,
+ , 1,
+ RTST, 1,
+ , 3,
+ PWST, 1,
+ SPWS, 1,
+ Offset(0x02),
+ TMEN, 1,
+ , 4,
+ GBEN, 1,
+ Offset(0x03),
+ PBEN, 1,
+ , 1,
+ RTEN, 1,
+ , 3,
+ PWDA, 1,
+ }
+
+ Scope(\_SB) {
+
+ /* PCIe Configuration Space for 16 busses */
+ OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
+ Field(PCFG, ByteAcc, NoLock, Preserve) {
+ /* Byte offsets are computed using the following technique:
+ * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
+ * The 8 comes from 8 functions per device, and 4096 bytes per function config space
+ */
+ Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */
+ STB5, 32,
+ Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
+ PT0D, 1,
+ PT1D, 1,
+ PT2D, 1,
+ PT3D, 1,
+ PT4D, 1,
+ PT5D, 1,
+ PT6D, 1,
+ PT7D, 1,
+ PT8D, 1,
+ PT9D, 1,
+ Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
+ SBIE, 1,
+ SBME, 1,
+ Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
+ SBRI, 8,
+ Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
+ SBB1, 32,
+ Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
+ ,14,
+ P92E, 1, /* Port92 decode enable */
+ }
+
+ OperationRegion(SB5, SystemMemory, STB5, 0x1000)
+ Field(SB5, AnyAcc, NoLock, Preserve)
+ {
+ /* Port 0 */
+ Offset(0x120), /* Port 0 Task file status */
+ P0ER, 1,
+ , 2,
+ P0DQ, 1,
+ , 3,
+ P0BY, 1,
+ Offset(0x128), /* Port 0 Serial ATA status */
+ P0DD, 4,
+ , 4,
+ P0IS, 4,
+ Offset(0x12C), /* Port 0 Serial ATA control */
+ P0DI, 4,
+ Offset(0x130), /* Port 0 Serial ATA error */
+ , 16,
+ P0PR, 1,
+
+ /* Port 1 */
+ offset(0x1A0), /* Port 1 Task file status */
+ P1ER, 1,
+ , 2,
+ P1DQ, 1,
+ , 3,
+ P1BY, 1,
+ Offset(0x1A8), /* Port 1 Serial ATA status */
+ P1DD, 4,
+ , 4,
+ P1IS, 4,
+ Offset(0x1AC), /* Port 1 Serial ATA control */
+ P1DI, 4,
+ Offset(0x1B0), /* Port 1 Serial ATA error */
+ , 16,
+ P1PR, 1,
+
+ /* Port 2 */
+ Offset(0x220), /* Port 2 Task file status */
+ P2ER, 1,
+ , 2,
+ P2DQ, 1,
+ , 3,
+ P2BY, 1,
+ Offset(0x228), /* Port 2 Serial ATA status */
+ P2DD, 4,
+ , 4,
+ P2IS, 4,
+ Offset(0x22C), /* Port 2 Serial ATA control */
+ P2DI, 4,
+ Offset(0x230), /* Port 2 Serial ATA error */
+ , 16,
+ P2PR, 1,
+
+ /* Port 3 */
+ Offset(0x2A0), /* Port 3 Task file status */
+ P3ER, 1,
+ , 2,
+ P3DQ, 1,
+ , 3,
+ P3BY, 1,
+ Offset(0x2A8), /* Port 3 Serial ATA status */
+ P3DD, 4,
+ , 4,
+ P3IS, 4,
+ Offset(0x2AC), /* Port 3 Serial ATA control */
+ P3DI, 4,
+ Offset(0x2B0), /* Port 3 Serial ATA error */
+ , 16,
+ P3PR, 1,
+ }
+ }
+
+ #include "acpi/routing.asl"
+
+ Scope(\_SB) {
+
+ Method(CkOT, 0){
+
+ if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */
+
+ if(CondRefOf(\_OSI,Local1))
+ {
+ Store(1, OSTP) /* Assume some form of XP */
+ if (\_OSI("Windows 2006")) /* Vista */
+ {
+ Store(2, OSTP)
+ }
+ } else {
+ If(WCMP(\_OS,"Linux")) {
+ Store(3, OSTP) /* Linux */
+ } Else {
+ Store(4, OSTP) /* Gotta be WinCE */
+ }
+ }
+ Return(OSTP)
+ }
+
+ Method(_PIC, 0x01, NotSerialized)
+ {
+ If (Arg0)
+ {
+ \_SB.CIRQ()
+ }
+ Store(Arg0, PMOD)
+ }
+
+ Method(CIRQ, 0x00, NotSerialized)
+ {
+ Store(0, PINA)
+ Store(0, PINB)
+ Store(0, PINC)
+ Store(0, PIND)
+ Store(0, PINE)
+ Store(0, PINF)
+ Store(0, PING)
+ Store(0, PINH)
+ }
+
+ Name(IRQB, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Shared){15}
+ })
+
+ Name(IRQP, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
+ })
+
+ Name(PITF, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Exclusive){9}
+ })
+
+ Device(INTA) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 1)
+
+ Method(_STA, 0) {
+ if (PINA) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTA._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_DIS\n") */
+ Store(0, PINA)
+ } /* End Method(_SB.INTA._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTA._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINA, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTA._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKA\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINA)
+ } /* End Method(_SB.INTA._SRS) */
+ } /* End Device(INTA) */
+
+ Device(INTB) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 2)
+
+ Method(_STA, 0) {
+ if (PINB) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTB._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_DIS\n") */
+ Store(0, PINB)
+ } /* End Method(_SB.INTB._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTB._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINB, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTB._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKB\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINB)
+ } /* End Method(_SB.INTB._SRS) */
+ } /* End Device(INTB) */
+
+ Device(INTC) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 3)
+
+ Method(_STA, 0) {
+ if (PINC) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTC._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_DIS\n") */
+ Store(0, PINC)
+ } /* End Method(_SB.INTC._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTC._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINC, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTC._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKC\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINC)
+ } /* End Method(_SB.INTC._SRS) */
+ } /* End Device(INTC) */
+
+ Device(INTD) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 4)
+
+ Method(_STA, 0) {
+ if (PIND) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTD._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_DIS\n") */
+ Store(0, PIND)
+ } /* End Method(_SB.INTD._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTD._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIND, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTD._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKD\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIND)
+ } /* End Method(_SB.INTD._SRS) */
+ } /* End Device(INTD) */
+
+ Device(INTE) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 5)
+
+ Method(_STA, 0) {
+ if (PINE) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTE._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_DIS\n") */
+ Store(0, PINE)
+ } /* End Method(_SB.INTE._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTE._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINE, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTE._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKE\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINE)
+ } /* End Method(_SB.INTE._SRS) */
+ } /* End Device(INTE) */
+
+ Device(INTF) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 6)
+
+ Method(_STA, 0) {
+ if (PINF) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTF._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_DIS\n") */
+ Store(0, PINF)
+ } /* End Method(_SB.INTF._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_PRS\n") */
+ Return(PITF)
+ } /* Method(_SB.INTF._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINF, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTF._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKF\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINF)
+ } /* End Method(_SB.INTF._SRS) */
+ } /* End Device(INTF) */
+
+ Device(INTG) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 7)
+
+ Method(_STA, 0) {
+ if (PING) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTG._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKG\\_DIS\n") */
+ Store(0, PING)
+ } /* End Method(_SB.INTG._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKG\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTG._CRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKG\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PING, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTG._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKG\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PING)
+ } /* End Method(_SB.INTG._SRS) */
+ } /* End Device(INTG) */
+
+ Device(INTH) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 8)
+
+ Method(_STA, 0) {
+ if (PINH) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTH._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKH\\_DIS\n") */
+ Store(0, PINH)
+ } /* End Method(_SB.INTH._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKH\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTH._CRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKH\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINH, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTH._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKH\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINH)
+ } /* End Method(_SB.INTH._SRS) */
+ } /* End Device(INTH) */
+
+ } /* End Scope(_SB) */
+
+
+ /* Supported sleep states: */
+ Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
+
+ If (LAnd(SSFG, 0x01)) {
+ Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
+ }
+ If (LAnd(SSFG, 0x02)) {
+ Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
+ }
+ If (LAnd(SSFG, 0x04)) {
+ Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
+ }
+ If (LAnd(SSFG, 0x08)) {
+ Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
+ }
+
+ Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
+
+ Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
+ Name(CSMS, 0) /* Current System State */
+
+ /* Wake status package */
+ Name(WKST,Package(){Zero, Zero})
+
+ /*
+ * \_PTS - Prepare to Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2, etc
+ *
+ * Exit:
+ * -none-
+ *
+ * The _PTS control method is executed at the beginning of the sleep process
+ * for S1-S5. The sleeping value is passed to the _PTS control method. This
+ * control method may be executed a relatively long time before entering the
+ * sleep state and the OS may abort the operation without notification to
+ * the ACPI driver. This method cannot modify the configuration or power
+ * state of any device in the system.
+ */
+ Method(\_PTS, 1) {
+ /* DBGO("\\_PTS\n") */
+ /* DBGO("From S0 to S") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+
+ /* Don't allow PCIRST# to reset USB */
+ if (LEqual(Arg0,3)){
+ Store(0,URRE)
+ }
+
+ /* Clear sleep SMI status flag and enable sleep SMI trap. */
+ /*Store(One, CSSM)
+ Store(One, SSEN)*/
+
+ /* On older chips, clear PciExpWakeDisEn */
+ /*if (LLessEqual(\_SB.SBRI, 0x13)) {
+ * Store(0,\_SB.PWDE)
+ *}
+ */
+
+ /* Clear wake status structure. */
+ Store(0, Index(WKST,0))
+ Store(0, Index(WKST,1))
+ \_SB.PCI0.SIOS (Arg0)
+ } /* End Method(\_PTS) */
+
+ /*
+ * The following method results in a "not a valid reserved NameSeg"
+ * warning so I have commented it out for the duration. It isn't
+ * used, so it could be removed.
+ *
+ *
+ * \_GTS OEM Going To Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * -none-
+ *
+ * Method(\_GTS, 1) {
+ * DBGO("\\_GTS\n")
+ * DBGO("From S0 to S")
+ * DBGO(Arg0)
+ * DBGO("\n")
+ * }
+ */
+
+ /*
+ * \_BFS OEM Back From Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * -none-
+ */
+ Method(\_BFS, 1) {
+ /* DBGO("\\_BFS\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+ }
+
+ /*
+ * \_WAK System Wake method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * Return package of 2 DWords
+ * Dword 1 - Status
+ * 0x00000000 wake succeeded
+ * 0x00000001 Wake was signaled but failed due to lack of power
+ * 0x00000002 Wake was signaled but failed due to thermal condition
+ * Dword 2 - Power Supply state
+ * if non-zero the effective S-state the power supply entered
+ */
+ Method(\_WAK, 1) {
+ /* DBGO("\\_WAK\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+
+ /* Re-enable HPET */
+ Store(1,HPDE)
+
+ /* Restore PCIRST# so it resets USB */
+ if (LEqual(Arg0,3)){
+ Store(1,URRE)
+ }
+
+ /* Arbitrarily clear PciExpWakeStatus */
+ Store(PWST, PWST)
+
+ /* if(DeRefOf(Index(WKST,0))) {
+ * Store(0, Index(WKST,1))
+ * } else {
+ * Store(Arg0, Index(WKST,1))
+ * }
+ */
+ \_SB.PCI0.SIOW (Arg0)
+ Return(WKST)
+ } /* End Method(\_WAK) */
+
+ Scope(\_GPE) { /* Start Scope GPE */
+ /* General event 0 */
+ /* Method(_L00) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 1 */
+ /* Method(_L01) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 2 */
+ /* Method(_L02) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 3 */
+ //Method(_L03) {
+ // /* DBGO("\\_GPE\\_L00\n") */
+ // Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ //}
+
+ /* General event 4 */
+ /* Method(_L04) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 5 */
+ /* Method(_L05) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 6 - Used for GPM6, moved to USB.asl */
+ /* Method(_L06) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 7 - Used for GPM7, moved to USB.asl */
+ /* Method(_L07) {
+ * DBGO("\\_GPE\\_L07\n")
+ * }
+ */
+
+ /* Legacy PM event */
+ Method(_L08) {
+ /* DBGO("\\_GPE\\_L08\n") */
+ }
+
+ /* Temp warning (TWarn) event */
+ Method(_L09) {
+ /* DBGO("\\_GPE\\_L09\n") */
+ Notify (\_TZ.TZ00, 0x80)
+ }
+
+ /* Reserved */
+ /* Method(_L0A) {
+ * DBGO("\\_GPE\\_L0A\n")
+ * }
+ */
+
+ /* USB controller PME# */
+ Method(_L0B) {
+ /* DBGO("\\_GPE\\_L0B\n") */
+ Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* AC97 controller PME# */
+ /* Method(_L0C) {
+ * DBGO("\\_GPE\\_L0C\n")
+ * }
+ */
+
+ /* OtherTherm PME# */
+ /* Method(_L0D) {
+ * DBGO("\\_GPE\\_L0D\n")
+ * }
+ */
+
+ /* GPM9 SCI event - Moved to USB.asl */
+ /* Method(_L0E) {
+ * DBGO("\\_GPE\\_L0E\n")
+ * }
+ */
+
+ /* PCIe HotPlug event */
+ /* Method(_L0F) {
+ * DBGO("\\_GPE\\_L0F\n")
+ * }
+ */
+
+ /* ExtEvent0 SCI event */
+ Method(_L10) {
+ /* DBGO("\\_GPE\\_L10\n") */
+ }
+
+
+ /* ExtEvent1 SCI event */
+ Method(_L11) {
+ /* DBGO("\\_GPE\\_L11\n") */
+ }
+
+ /* PCIe PME# event */
+ /* Method(_L12) {
+ * DBGO("\\_GPE\\_L12\n")
+ * }
+ */
+
+ /* GPM0 SCI event - Moved to USB.asl */
+ /* Method(_L13) {
+ * DBGO("\\_GPE\\_L13\n")
+ * }
+ */
+
+ /* GPM1 SCI event - Moved to USB.asl */
+ /* Method(_L14) {
+ * DBGO("\\_GPE\\_L14\n")
+ * }
+ */
+
+ /* GPM2 SCI event - Moved to USB.asl */
+ /* Method(_L15) {
+ * DBGO("\\_GPE\\_L15\n")
+ * }
+ */
+
+ /* GPM3 SCI event - Moved to USB.asl */
+ /* Method(_L16) {
+ * DBGO("\\_GPE\\_L16\n")
+ * }
+ */
+
+ /* GPM8 SCI event - Moved to USB.asl */
+ /* Method(_L17) {
+ * DBGO("\\_GPE\\_L17\n")
+ * }
+ */
+
+ /* GPIO0 or GEvent8 event */
+ Method(_L18) {
+ /* DBGO("\\_GPE\\_L18\n") */
+ Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* GPM4 SCI event - Moved to USB.asl */
+ /* Method(_L19) {
+ * DBGO("\\_GPE\\_L19\n")
+ * }
+ */
+
+ /* GPM5 SCI event - Moved to USB.asl */
+ /* Method(_L1A) {
+ * DBGO("\\_GPE\\_L1A\n")
+ * }
+ */
+
+ /* Azalia SCI event */
+ Method(_L1B) {
+ /* DBGO("\\_GPE\\_L1B\n") */
+ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* GPM6 SCI event - Reassigned to _L06 */
+ /* Method(_L1C) {
+ * DBGO("\\_GPE\\_L1C\n")
+ * }
+ */
+
+ /* GPM7 SCI event - Reassigned to _L07 */
+ /* Method(_L1D) {
+ * DBGO("\\_GPE\\_L1D\n")
+ * }
+ */
+
+ /* GPIO2 or GPIO66 SCI event */
+ /* Method(_L1E) {
+ * DBGO("\\_GPE\\_L1E\n")
+ * }
+ */
+
+ /* SATA SCI event - Moved to sata.asl */
+ /* Method(_L1F) {
+ * DBGO("\\_GPE\\_L1F\n")
+ * }
+ */
+
+ } /* End Scope GPE */
+
+ #include "acpi/usb.asl"
+
+ /* South Bridge */
+ Scope(\_SB) { /* Start \_SB scope */
+ #include "acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
+
+ /* _SB.PCI0 */
+ /* Note: Only need HID on Primary Bus */
+ Device(PCI0) {
+ External (TOM1)
+ External (TOM2)
+ Name(_HID, EISAID("PNP0A03"))
+ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
+ Method(_BBN, 0) { /* Bus number = 0 */
+ Return(0)
+ }
+ Method(_STA, 0) {
+ /* DBGO("\\_SB\\PCI0\\_STA\n") */
+ Return(0x0B) /* Status is visible */
+ }
+
+ Method(_PRT,0) {
+ If(PMOD){ Return(APR0) } /* APIC mode */
+ Return (PR0) /* PIC Mode */
+ } /* end _PRT */
+
+ /* Describe the Northbridge devices */
+ Device(AMRT) {
+ Name(_ADR, 0x00000000)
+ } /* end AMRT */
+
+ /* The internal GFX bridge */
+ Device(AGPB) {
+ Name(_ADR, 0x00010000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ Return (APR1)
+ }
+ } /* end AGPB */
+
+ /* The external GFX bridge */
+ Device(PBR2) {
+ Name(_ADR, 0x00020000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS2) } /* APIC mode */
+ Return (PS2) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR2 */
+
+ /* Dev3 is also an external GFX bridge, not used in Herring */
+
+ Device(PBR4) {
+ Name(_ADR, 0x00040000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS4) } /* APIC mode */
+ Return (PS4) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR4 */
+
+ Device(PBR5) {
+ Name(_ADR, 0x00050000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS5) } /* APIC mode */
+ Return (PS5) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR5 */
+
+ Device(PBR6) {
+ Name(_ADR, 0x00060000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS6) } /* APIC mode */
+ Return (PS6) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR6 */
+
+ /* The onboard EtherNet chip */
+ Device(PBR7) {
+ Name(_ADR, 0x00070000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS7) } /* APIC mode */
+ Return (PS7) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR7 */
+
+
+ /* PCI slot 1, 2, 3 */
+ Device(PIBR) {
+ Name(_ADR, 0x00140004)
+ Name(_PRW, Package() {0x18, 4})
+
+ Method(_PRT, 0) {
+ Return (PCIB)
+ }
+ }
+
+ /* Describe the Southbridge devices */
+ Device(STCR) {
+ Name(_ADR, 0x00120000)
+ #include "acpi/sata.asl"
+ } /* end STCR */
+
+ Device(UOH1) {
+ Name(_ADR, 0x00130000)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH1 */
+
+ Device(UOH2) {
+ Name(_ADR, 0x00130001)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH2 */
+
+ Device(UOH3) {
+ Name(_ADR, 0x00130002)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH3 */
+
+ Device(UOH4) {
+ Name(_ADR, 0x00130003)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH4 */
+
+ Device(UOH5) {
+ Name(_ADR, 0x00130004)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH5 */
+
+ Device(UEH1) {
+ Name(_ADR, 0x00130005)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UEH1 */
+
+ Device(SBUS) {
+ Name(_ADR, 0x00140000)
+ } /* end SBUS */
+
+ /* Primary (and only) IDE channel */
+ Device(IDEC) {
+ Name(_ADR, 0x00140001)
+ #include "acpi/ide.asl"
+ } /* end IDEC */
+
+ Device(AZHD) {
+ Name(_ADR, 0x00140002)
+ OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
+ Field(AZPD, AnyAcc, NoLock, Preserve) {
+ offset (0x42),
+ NSDI, 1,
+ NSDO, 1,
+ NSEN, 1,
+ offset (0x44),
+ IPCR, 4,
+ offset (0x54),
+ PWST, 2,
+ , 6,
+ PMEB, 1,
+ , 6,
+ PMST, 1,
+ offset (0x62),
+ MMCR, 1,
+ offset (0x64),
+ MMLA, 32,
+ offset (0x68),
+ MMHA, 32,
+ offset (0x6C),
+ MMDT, 16,
+ }
+
+ Method(_INI) {
+ If(LEqual(OSTP,3)){ /* If we are running Linux */
+ Store(zero, NSEN)
+ Store(one, NSDO)
+ Store(one, NSDI)
+ }
+ }
+ } /* end AZHD */
+
+ Device(LIBR) {
+ Name(_ADR, 0x00140003)
+ /* Method(_INI) {
+ * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
+ } */ /* End Method(_SB.SBRDG._INI) */
+
+ /* Real Time Clock Device */
+ Device(RTC0) {
+ Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){8}
+ IO(Decode16,0x0070, 0x0070, 0, 2)
+ /* IO(Decode16,0x0070, 0x0070, 0, 4) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
+
+ Device(TMR) { /* Timer */
+ Name(_HID,EISAID("PNP0100")) /* System Timer */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){0}
+ IO(Decode16, 0x0040, 0x0040, 0, 4)
+ /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
+
+ Device(SPKR) { /* Speaker */
+ Name(_HID,EISAID("PNP0800")) /* AT style speaker */
+ Name(_CRS, ResourceTemplate() {
+ IO(Decode16, 0x0061, 0x0061, 0, 1)
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
+
+ Device(PIC) {
+ Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){2}
+ IO(Decode16,0x0020, 0x0020, 0, 2)
+ IO(Decode16,0x00A0, 0x00A0, 0, 2)
+ /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
+ /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
+
+ Device(MAD) { /* 8257 DMA */
+ Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
+ Name(_CRS, ResourceTemplate() {
+ DMA(Compatibility,BusMaster,Transfer8){4}
+ IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
+ IO(Decode16, 0x0081, 0x0081, 0x10, 0x03)
+ IO(Decode16, 0x0087, 0x0087, 0x10, 0x01)
+ IO(Decode16, 0x0089, 0x0089, 0x10, 0x03)
+ IO(Decode16, 0x008F, 0x008F, 0x10, 0x01)
+ IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
+ }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
+ } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
+
+ Device(COPR) {
+ Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
+ Name(_CRS, ResourceTemplate() {
+ IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
+ IRQNoFlags(){13}
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+
+ Device(HPTM) {
+ Name(_HID,EISAID("PNP0103"))
+ Name(CRS,ResourceTemplate() {
+ Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
+ })
+ Method(_STA, 0) {
+ Return(0x0F) /* sata is visible */
+ }
+ Method(_CRS, 0) {
+ CreateDwordField(CRS, ^HPT._BAS, HPBA)
+ Store(HPBA, HPBA)
+ Return(CRS)
+ }
+ } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+ } /* end LIBR */
+
+ Device(HPBR) {
+ Name(_ADR, 0x00140004)
+ } /* end HostPciBr */
+
+ Device(ACAD) {
+ Name(_ADR, 0x00140005)
+ } /* end Ac97audio */
+
+ Device(ACMD) {
+ Name(_ADR, 0x00140006)
+ } /* end Ac97modem */
+
+ /* ITE IT8712F Support */
+ OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
+ Field (IOID, ByteAcc, NoLock, Preserve)
+ {
+ SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */
+ }
+
+ IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x07),
+ LDN, 8, /* Logical Device Number */
+ Offset (0x20),
+ CID1, 8, /* Chip ID Byte 1, 0x87 */
+ CID2, 8, /* Chip ID Byte 2, 0x12 */
+ Offset (0x30),
+ ACTR, 8, /* Function activate */
+ Offset (0xF0),
+ APC0, 8, /* APC/PME Event Enable Register */
+ APC1, 8, /* APC/PME Status Register */
+ APC2, 8, /* APC/PME Control Register 1 */
+ APC3, 8, /* Environment Controller Special Configuration Register */
+ APC4, 8 /* APC/PME Control Register 2 */
+ }
+
+ /* Enter the IT8712F MB PnP Mode */
+ Method (EPNP)
+ {
+ Store(0x87, SIOI)
+ Store(0x01, SIOI)
+ Store(0x55, SIOI)
+ Store(0x55, SIOI) /* IT8712F magic number */
+ }
+ /* Exit the IT8712F MB PnP Mode */
+ Method (XPNP)
+ {
+ Store (0x02, SIOI)
+ Store (0x02, SIOD)
+ }
+
+ /*
+ * Keyboard PME is routed to SB600 Gevent3. We can wake
+ * up the system by pressing the key.
+ */
+ Method (SIOS, 1)
+ {
+ /* We only enable KBD PME for S5. */
+ If (LLess (Arg0, 0x05))
+ {
+ EPNP()
+ /* DBGO("IT8712F\n") */
+
+ Store (0x4, LDN)
+ Store (One, ACTR) /* Enable EC */
+ /*
+ Store (0x4, LDN)
+ Store (0x04, APC4)
+ */ /* falling edge. which mode? Not sure. */
+
+ Store (0x4, LDN)
+ Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
+ Store (0x4, LDN)
+ Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
+
+ XPNP()
+ }
+ }
+ Method (SIOW, 1)
+ {
+ EPNP()
+ Store (0x4, LDN)
+ Store (Zero, APC0) /* disable keyboard PME */
+ Store (0x4, LDN)
+ Store (0xFF, APC1) /* clear keyboard PME status */
+ XPNP()
+ }
+
+ Name(CRES, ResourceTemplate() {
+ IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
+
+ WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, /* address granularity */
+ 0x0000, /* range minimum */
+ 0x0CF7, /* range maximum */
+ 0x0000, /* translation */
+ 0x0CF8 /* length */
+ )
+
+ WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, /* address granularity */
+ 0x0D00, /* range minimum */
+ 0xFFFF, /* range maximum */
+ 0x0000, /* translation */
+ 0xF300 /* length */
+ )
+
+ Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
+ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
+ Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
+ Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
+
+ /* DRAM Memory from 1MB to TopMem */
+ Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
+
+ /* BIOS space just below 4GB */
+ DWORDMemory(
+ ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00, /* Granularity */
+ 0x00000000, /* Min */
+ 0x00000000, /* Max */
+ 0x00000000, /* Translation */
+ 0x00000000, /* Max-Min, RLEN */
+ ,,
+ PCBM
+ )
+
+ /* DRAM memory from 4GB to TopMem2 */
+ QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0xFFFFFFFF, /* Granularity */
+ 0x00000000, /* Min */
+ 0x00000000, /* Max */
+ 0x00000000, /* Translation */
+ 0x00000000, /* Max-Min, RLEN */
+ ,,
+ DMHI
+ )
+
+ /* BIOS space just below 16EB */
+ QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0xFFFFFFFF, /* Granularity */
+ 0x00000000, /* Min */
+ 0x00000000, /* Max */
+ 0x00000000, /* Translation */
+ 0x00000000, /* Max-Min, RLEN */
+ ,,
+ PEBM
+ )
+
+ }) /* End Name(_SB.PCI0.CRES) */
+
+ Method(_CRS, 0) {
+ /* DBGO("\\_SB\\PCI0\\_CRS\n") */
+
+ CreateDWordField(CRES, ^EMM1._BAS, EM1B)
+ CreateDWordField(CRES, ^EMM1._LEN, EM1L)
+ CreateDWordField(CRES, ^DMLO._BAS, DMLB)
+ CreateDWordField(CRES, ^DMLO._LEN, DMLL)
+ CreateDWordField(CRES, ^PCBM._MIN, PBMB)
+ CreateDWordField(CRES, ^PCBM._LEN, PBML)
+
+ CreateQWordField(CRES, ^DMHI._MIN, DMHB)
+ CreateQWordField(CRES, ^DMHI._LEN, DMHL)
+ CreateQWordField(CRES, ^PEBM._MIN, EBMB)
+ CreateQWordField(CRES, ^PEBM._LEN, EBML)
+
+ If(LGreater(LOMH, 0xC0000)){
+ Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
+ Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
+ }
+
+ /* Set size of memory from 1MB to TopMem */
+ Subtract(TOM1, 0x100000, DMLL)
+
+ /*
+ * If(LNotEqual(TOM2, 0x00000000)){
+ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
+ * Subtract(TOM2, 0x100000000, DMHL)
+ * }
+ */
+
+ /* If there is no memory above 4GB, put the BIOS just below 4GB */
+ If(LEqual(TOM2, 0x00000000)){
+ Store(PBAD,PBMB) /* Reserve the "BIOS" space */
+ Store(PBLN,PBML)
+ }
+ Else { /* Otherwise, put the BIOS just below 16EB */
+ ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
+ Store(PBLN,EBML)
+ }
+
+ Return(CRES) /* note to change the Name buffer */
+ } /* end of Method(_SB.PCI0._CRS) */
+
+ /*
+ *
+ * FIRST METHOD CALLED UPON BOOT
+ *
+ * 1. If debugging, print current OS and ACPI interpreter.
+ * 2. Get PCI Interrupt routing from ACPI VSM, this
+ * value is based on user choice in BIOS setup.
+ */
+ Method(_INI, 0) {
+ /* DBGO("\\_SB\\_INI\n") */
+ /* DBGO(" DSDT.ASL code from ") */
+ /* DBGO(__DATE__) */
+ /* DBGO(" ") */
+ /* DBGO(__TIME__) */
+ /* DBGO("\n Sleep states supported: ") */
+ /* DBGO("\n") */
+ /* DBGO(" \\_OS=") */
+ /* DBGO(\_OS) */
+ /* DBGO("\n \\_REV=") */
+ /* DBGO(\_REV) */
+ /* DBGO("\n") */
+
+ /* Determine the OS we're running on */
+ CkOT()
+
+ /* On older chips, clear PciExpWakeDisEn */
+ /*if (LLessEqual(\SBRI, 0x13)) {
+ * Store(0,\PWDE)
+ * }
+ */
+ } /* End Method(_SB._INI) */
+ } /* End Device(PCI0) */
+
+ Device(PWRB) { /* Start Power button device */
+ Name(_HID, EISAID("PNP0C0C"))
+ Name(_UID, 0xAA)
+ //Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
+ Name(_STA, 0x0B) /* sata is invisible */
+ }
+ } /* End \_SB scope */
+
+ Scope(\_SI) {
+ Method(_SST, 1) {
+ /* DBGO("\\_SI\\_SST\n") */
+ /* DBGO(" New Indicator state: ") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+ }
+ } /* End Scope SI */
+
+ Mutex (SBX0, 0x00)
+ OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
+ Field (SMB0, ByteAcc, NoLock, Preserve) {
+ HSTS, 8, /* SMBUS status */
+ SSTS, 8, /* SMBUS slave status */
+ HCNT, 8, /* SMBUS control */
+ HCMD, 8, /* SMBUS host cmd */
+ HADD, 8, /* SMBUS address */
+ DAT0, 8, /* SMBUS data0 */
+ DAT1, 8, /* SMBUS data1 */
+ BLKD, 8, /* SMBUS block data */
+ SCNT, 8, /* SMBUS slave control */
+ SCMD, 8, /* SMBUS shaow cmd */
+ SEVT, 8, /* SMBUS slave event */
+ SDAT, 8 /* SMBUS slave data */
+ }
+
+ Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
+ Store (0x1E, HSTS)
+ Store (0xFA, Local0)
+ While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
+ Stall (0x64)
+ Decrement (Local0)
+ }
+
+ Return (Local0)
+ }
+
+ Method (SWTC, 1, NotSerialized) {
+ Store (Arg0, Local0)
+ Store (0x07, Local2)
+ Store (One, Local1)
+ While (LEqual (Local1, One)) {
+ Store (And (HSTS, 0x1E), Local3)
+ If (LNotEqual (Local3, Zero)) { /* read sucess */
+ If (LEqual (Local3, 0x02)) {
+ Store (Zero, Local2)
+ }
+
+ Store (Zero, Local1)
+ }
+ Else {
+ If (LLess (Local0, 0x0A)) { /* read failure */
+ Store (0x10, Local2)
+ Store (Zero, Local1)
+ }
+ Else {
+ Sleep (0x0A) /* 10 ms, try again */
+ Subtract (Local0, 0x0A, Local0)
+ }
+ }
+ }
+
+ Return (Local2)
+ }
+
+ Method (SMBR, 3, NotSerialized) {
+ Store (0x07, Local0)
+ If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
+ Store (WCLR (), Local0) /* clear SMBUS status register before read data */
+ If (LEqual (Local0, Zero)) {
+ Release (SBX0)
+ Return (0x0)
+ }
+
+ Store (0x1F, HSTS)
+ Store (Or (ShiftLeft (Arg1, One), One), HADD)
+ Store (Arg2, HCMD)
+ If (LEqual (Arg0, 0x07)) {
+ Store (0x48, HCNT) /* read byte */
+ }
+
+ Store (SWTC (0x03E8), Local1) /* 1000 ms */
+ If (LEqual (Local1, Zero)) {
+ If (LEqual (Arg0, 0x07)) {
+ Store (DAT0, Local0)
+ }
+ }
+ Else {
+ Store (Local1, Local0)
+ }
+
+ Release (SBX0)
+ }
+
+ /* DBGO("the value of SMBusData0 register ") */
+ /* DBGO(Arg2) */
+ /* DBGO(" is ") */
+ /* DBGO(Local0) */
+ /* DBGO("\n") */
+
+ Return (Local0)
+ }
+
+ /* THERMAL */
+ Scope(\_TZ) {
+ Name (KELV, 2732)
+ Name (THOT, 800)
+ Name (TCRT, 850)
+
+ ThermalZone(TZ00) {
+ Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
+ /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
+ Return(Add(0, 2730))
+ }
+ Method(_AL0,0) { /* Returns package of cooling device to turn on */
+ /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
+ Return(Package() {\_TZ.TZ00.FAN0})
+ }
+ Device (FAN0) {
+ Name(_HID, EISAID("PNP0C0B"))
+ Name(_PR0, Package() {PFN0})
+ }
+
+ PowerResource(PFN0,0,0) {
+ Method(_STA) {
+ Store(0xF,Local0)
+ Return(Local0)
+ }
+ Method(_ON) {
+ /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
+ }
+ Method(_OFF) {
+ /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
+ }
+ }
+
+ Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
+ /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
+ Return (Add (THOT, KELV))
+ }
+ Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
+ /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
+ Return (Add (TCRT, KELV))
+ }
+ Method(_TMP,0) { /* return current temp of this zone */
+ Store (SMBR (0x07, 0x4C,, 0x00), Local0)
+ If (LGreater (Local0, 0x10)) {
+ Store (Local0, Local1)
+ }
+ Else {
+ Add (Local0, THOT, Local0)
+ Return (Add (400, KELV))
+ }
+
+ Store (SMBR (0x07, 0x4C, 0x01), Local0)
+ /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
+ /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
+ If (LGreater (Local0, 0x10)) {
+ If (LGreater (Local0, Local1)) {
+ Store (Local0, Local1)
+ }
+
+ Multiply (Local1, 10, Local1)
+ Return (Add (Local1, KELV))
+ }
+ Else {
+ Add (Local0, THOT, Local0)
+ Return (Add (400 , KELV))
+ }
+ } /* end of _TMP */
+ } /* end of TZ00 */
+ }
+}
+/* End of ASL file */
ifdef POST_EVALUATION
-$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/acpi/dsdt.asl
- iasl -p $(obj)/dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/acpi/dsdt.asl
- mv $(obj)/dsdt.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
0x00010001
)
{
- Include ("debug.asl")
+ #include "debug.asl"
}
*/
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* DefinitionBlock Statement */
-DefinitionBlock (
- "DSDT.AML", /* Output filename */
- "DSDT", /* Signature */
- 0x02, /* DSDT Revision, needs to be 2 for 64bit */
- "TECHNEXION", /* OEMID */
- "TIM-8690", /* TABLE ID */
- 0x00010001 /* OEM Revision */
- )
-{ /* Start of ASL file */
- /* Include ("debug.asl") */ /* Include global debug methods if needed */
-
- /* Data to be patched by the BIOS during POST */
- /* FIXME the patching is not done yet! */
- /* Memory related values */
- Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
- Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
- Name(PBLN, 0x0) /* Length of BIOS area */
-
- Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
- Name(HPBA, 0xFED00000) /* Base address of HPET table */
-
- Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
-
- /* USB overcurrent mapping pins. */
- Name(UOM0, 0)
- Name(UOM1, 2)
- Name(UOM2, 0)
- Name(UOM3, 7)
- Name(UOM4, 2)
- Name(UOM5, 2)
- Name(UOM6, 6)
- Name(UOM7, 2)
- Name(UOM8, 6)
- Name(UOM9, 6)
-
- /* Some global data */
- Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
- Name(OSV, Ones) /* Assume nothing */
- Name(PMOD, One) /* Assume APIC */
-
- /* PIC IRQ mapping registers, C00h-C01h */
- OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
- Field(PRQM, ByteAcc, NoLock, Preserve) {
- PRQI, 0x00000008,
- PRQD, 0x00000008, /* Offset: 1h */
- }
- IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
- PINA, 0x00000008, /* Index 0 */
- PINB, 0x00000008, /* Index 1 */
- PINC, 0x00000008, /* Index 2 */
- PIND, 0x00000008, /* Index 3 */
- AINT, 0x00000008, /* Index 4 */
- SINT, 0x00000008, /* Index 5 */
- , 0x00000008, /* Index 6 */
- AAUD, 0x00000008, /* Index 7 */
- AMOD, 0x00000008, /* Index 8 */
- PINE, 0x00000008, /* Index 9 */
- PINF, 0x00000008, /* Index A */
- PING, 0x00000008, /* Index B */
- PINH, 0x00000008, /* Index C */
- }
-
- /* PCI Error control register */
- OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
- Field(PERC, ByteAcc, NoLock, Preserve) {
- SENS, 0x00000001,
- PENS, 0x00000001,
- SENE, 0x00000001,
- PENE, 0x00000001,
- }
-
- /* Client Management index/data registers */
- OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
- Field(CMT, ByteAcc, NoLock, Preserve) {
- CMTI, 8,
- /* Client Management Data register */
- G64E, 1,
- G64O, 1,
- G32O, 2,
- , 2,
- GPSL, 2,
- }
-
- /* GPM Port register */
- OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
- Field(GPT, ByteAcc, NoLock, Preserve) {
- GPB0,1,
- GPB1,1,
- GPB2,1,
- GPB3,1,
- GPB4,1,
- GPB5,1,
- GPB6,1,
- GPB7,1,
- }
-
- /* Flash ROM program enable register */
- OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
- Field(FRE, ByteAcc, NoLock, Preserve) {
- , 0x00000006,
- FLRE, 0x00000001,
- }
-
- /* PM2 index/data registers */
- OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
- Field(PM2R, ByteAcc, NoLock, Preserve) {
- PM2I, 0x00000008,
- PM2D, 0x00000008,
- }
-
- /* Power Management I/O registers */
- OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
- Field(PIOR, ByteAcc, NoLock, Preserve) {
- PIOI, 0x00000008,
- PIOD, 0x00000008,
- }
- IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
- Offset(0x00), /* MiscControl */
- , 1,
- T1EE, 1,
- T2EE, 1,
- Offset(0x01), /* MiscStatus */
- , 1,
- T1E, 1,
- T2E, 1,
- Offset(0x04), /* SmiWakeUpEventEnable3 */
- , 7,
- SSEN, 1,
- Offset(0x07), /* SmiWakeUpEventStatus3 */
- , 7,
- CSSM, 1,
- Offset(0x10), /* AcpiEnable */
- , 6,
- PWDE, 1,
- Offset(0x1C), /* ProgramIoEnable */
- , 3,
- MKME, 1,
- IO3E, 1,
- IO2E, 1,
- IO1E, 1,
- IO0E, 1,
- Offset(0x1D), /* IOMonitorStatus */
- , 3,
- MKMS, 1,
- IO3S, 1,
- IO2S, 1,
- IO1S, 1,
- IO0S,1,
- Offset(0x20), /* AcpiPmEvtBlk */
- APEB, 16,
- Offset(0x36), /* GEvtLevelConfig */
- , 6,
- ELC6, 1,
- ELC7, 1,
- Offset(0x37), /* GPMLevelConfig0 */
- , 3,
- PLC0, 1,
- PLC1, 1,
- PLC2, 1,
- PLC3, 1,
- PLC8, 1,
- Offset(0x38), /* GPMLevelConfig1 */
- , 1,
- PLC4, 1,
- PLC5, 1,
- , 1,
- PLC6, 1,
- PLC7, 1,
- Offset(0x3B), /* PMEStatus1 */
- GP0S, 1,
- GM4S, 1,
- GM5S, 1,
- APS, 1,
- GM6S, 1,
- GM7S, 1,
- GP2S, 1,
- STSS, 1,
- Offset(0x55), /* SoftPciRst */
- SPRE, 1,
- , 1,
- , 1,
- PNAT, 1,
- PWMK, 1,
- PWNS, 1,
-
- /* Offset(0x61), */ /* Options_1 */
- /* ,7, */
- /* R617,1, */
-
- Offset(0x65), /* UsbPMControl */
- , 4,
- URRE, 1,
- Offset(0x68), /* MiscEnable68 */
- , 3,
- TMTE, 1,
- , 1,
- Offset(0x92), /* GEVENTIN */
- , 7,
- E7IS, 1,
- Offset(0x96), /* GPM98IN */
- G8IS, 1,
- G9IS, 1,
- Offset(0x9A), /* EnhanceControl */
- ,7,
- HPDE, 1,
- Offset(0xA8), /* PIO7654Enable */
- IO4E, 1,
- IO5E, 1,
- IO6E, 1,
- IO7E, 1,
- Offset(0xA9), /* PIO7654Status */
- IO4S, 1,
- IO5S, 1,
- IO6S, 1,
- IO7S, 1,
- }
-
- /* PM1 Event Block
- * First word is PM1_Status, Second word is PM1_Enable
- */
- OperationRegion(P1EB, SystemIO, APEB, 0x04)
- Field(P1EB, ByteAcc, NoLock, Preserve) {
- TMST, 1,
- , 3,
- BMST, 1,
- GBST, 1,
- Offset(0x01),
- PBST, 1,
- , 1,
- RTST, 1,
- , 3,
- PWST, 1,
- SPWS, 1,
- Offset(0x02),
- TMEN, 1,
- , 4,
- GBEN, 1,
- Offset(0x03),
- PBEN, 1,
- , 1,
- RTEN, 1,
- , 3,
- PWDA, 1,
- }
-
- Scope(\_SB) {
-
- /* PCIe Configuration Space for 16 busses */
- OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
- Field(PCFG, ByteAcc, NoLock, Preserve) {
- /* Byte offsets are computed using the following technique:
- * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
- * The 8 comes from 8 functions per device, and 4096 bytes per function config space
- */
- Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */
- STB5, 32,
- Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
- PT0D, 1,
- PT1D, 1,
- PT2D, 1,
- PT3D, 1,
- PT4D, 1,
- PT5D, 1,
- PT6D, 1,
- PT7D, 1,
- PT8D, 1,
- PT9D, 1,
- Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
- SBIE, 1,
- SBME, 1,
- Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
- SBRI, 8,
- Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
- SBB1, 32,
- Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
- ,14,
- P92E, 1, /* Port92 decode enable */
- }
-
- OperationRegion(SB5, SystemMemory, STB5, 0x1000)
- Field(SB5, AnyAcc, NoLock, Preserve)
- {
- /* Port 0 */
- Offset(0x120), /* Port 0 Task file status */
- P0ER, 1,
- , 2,
- P0DQ, 1,
- , 3,
- P0BY, 1,
- Offset(0x128), /* Port 0 Serial ATA status */
- P0DD, 4,
- , 4,
- P0IS, 4,
- Offset(0x12C), /* Port 0 Serial ATA control */
- P0DI, 4,
- Offset(0x130), /* Port 0 Serial ATA error */
- , 16,
- P0PR, 1,
-
- /* Port 1 */
- offset(0x1A0), /* Port 1 Task file status */
- P1ER, 1,
- , 2,
- P1DQ, 1,
- , 3,
- P1BY, 1,
- Offset(0x1A8), /* Port 1 Serial ATA status */
- P1DD, 4,
- , 4,
- P1IS, 4,
- Offset(0x1AC), /* Port 1 Serial ATA control */
- P1DI, 4,
- Offset(0x1B0), /* Port 1 Serial ATA error */
- , 16,
- P1PR, 1,
-
- /* Port 2 */
- Offset(0x220), /* Port 2 Task file status */
- P2ER, 1,
- , 2,
- P2DQ, 1,
- , 3,
- P2BY, 1,
- Offset(0x228), /* Port 2 Serial ATA status */
- P2DD, 4,
- , 4,
- P2IS, 4,
- Offset(0x22C), /* Port 2 Serial ATA control */
- P2DI, 4,
- Offset(0x230), /* Port 2 Serial ATA error */
- , 16,
- P2PR, 1,
-
- /* Port 3 */
- Offset(0x2A0), /* Port 3 Task file status */
- P3ER, 1,
- , 2,
- P3DQ, 1,
- , 3,
- P3BY, 1,
- Offset(0x2A8), /* Port 3 Serial ATA status */
- P3DD, 4,
- , 4,
- P3IS, 4,
- Offset(0x2AC), /* Port 3 Serial ATA control */
- P3DI, 4,
- Offset(0x2B0), /* Port 3 Serial ATA error */
- , 16,
- P3PR, 1,
- }
- }
-
- Include ("routing.asl")
-
- Scope(\_SB) {
-
- Method(CkOT, 0){
-
- if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */
-
- if(CondRefOf(\_OSI,Local1))
- {
- Store(1, OSTP) /* Assume some form of XP */
- if (\_OSI("Windows 2006")) /* Vista */
- {
- Store(2, OSTP)
- }
- } else {
- If(WCMP(\_OS,"Linux")) {
- Store(3, OSTP) /* Linux */
- } Else {
- Store(4, OSTP) /* Gotta be WinCE */
- }
- }
- Return(OSTP)
- }
-
- Method(_PIC, 0x01, NotSerialized)
- {
- If (Arg0)
- {
- \_SB.CIRQ()
- }
- Store(Arg0, PMOD)
- }
-
- Method(CIRQ, 0x00, NotSerialized)
- {
- Store(0, PINA)
- Store(0, PINB)
- Store(0, PINC)
- Store(0, PIND)
- Store(0, PINE)
- Store(0, PINF)
- Store(0, PING)
- Store(0, PINH)
- }
-
- Name(IRQB, ResourceTemplate(){
- IRQ(Level,ActiveLow,Shared){15}
- })
-
- Name(IRQP, ResourceTemplate(){
- IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
- })
-
- Name(PITF, ResourceTemplate(){
- IRQ(Level,ActiveLow,Exclusive){9}
- })
-
- Device(INTA) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 1)
-
- Method(_STA, 0) {
- if (PINA) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTA._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKA\\_DIS\n") */
- Store(0, PINA)
- } /* End Method(_SB.INTA._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKA\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTA._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKA\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINA, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTA._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKA\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINA)
- } /* End Method(_SB.INTA._SRS) */
- } /* End Device(INTA) */
-
- Device(INTB) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 2)
-
- Method(_STA, 0) {
- if (PINB) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTB._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKB\\_DIS\n") */
- Store(0, PINB)
- } /* End Method(_SB.INTB._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKB\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTB._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKB\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINB, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTB._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKB\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINB)
- } /* End Method(_SB.INTB._SRS) */
- } /* End Device(INTB) */
-
- Device(INTC) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 3)
-
- Method(_STA, 0) {
- if (PINC) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTC._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKC\\_DIS\n") */
- Store(0, PINC)
- } /* End Method(_SB.INTC._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKC\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTC._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKC\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINC, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTC._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKC\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINC)
- } /* End Method(_SB.INTC._SRS) */
- } /* End Device(INTC) */
-
- Device(INTD) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 4)
-
- Method(_STA, 0) {
- if (PIND) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTD._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKD\\_DIS\n") */
- Store(0, PIND)
- } /* End Method(_SB.INTD._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKD\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTD._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKD\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PIND, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTD._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKD\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PIND)
- } /* End Method(_SB.INTD._SRS) */
- } /* End Device(INTD) */
-
- Device(INTE) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 5)
-
- Method(_STA, 0) {
- if (PINE) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTE._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKE\\_DIS\n") */
- Store(0, PINE)
- } /* End Method(_SB.INTE._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKE\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTE._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKE\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINE, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTE._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKE\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINE)
- } /* End Method(_SB.INTE._SRS) */
- } /* End Device(INTE) */
-
- Device(INTF) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 6)
-
- Method(_STA, 0) {
- if (PINF) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTF._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKF\\_DIS\n") */
- Store(0, PINF)
- } /* End Method(_SB.INTF._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKF\\_PRS\n") */
- Return(PITF)
- } /* Method(_SB.INTF._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKF\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINF, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTF._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKF\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINF)
- } /* End Method(_SB.INTF._SRS) */
- } /* End Device(INTF) */
-
- Device(INTG) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 7)
-
- Method(_STA, 0) {
- if (PING) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTG._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKG\\_DIS\n") */
- Store(0, PING)
- } /* End Method(_SB.INTG._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKG\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTG._CRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKG\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PING, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTG._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKG\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PING)
- } /* End Method(_SB.INTG._SRS) */
- } /* End Device(INTG) */
-
- Device(INTH) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 8)
-
- Method(_STA, 0) {
- if (PINH) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTH._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKH\\_DIS\n") */
- Store(0, PINH)
- } /* End Method(_SB.INTH._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKH\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTH._CRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKH\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINH, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTH._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKH\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINH)
- } /* End Method(_SB.INTH._SRS) */
- } /* End Device(INTH) */
-
- } /* End Scope(_SB) */
-
-
- /* Supported sleep states: */
- Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
-
- If (LAnd(SSFG, 0x01)) {
- Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
- }
- If (LAnd(SSFG, 0x02)) {
- Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
- }
- If (LAnd(SSFG, 0x04)) {
- Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
- }
- If (LAnd(SSFG, 0x08)) {
- Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
- }
-
- Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
-
- Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
- Name(CSMS, 0) /* Current System State */
-
- /* Wake status package */
- Name(WKST,Package(){Zero, Zero})
-
- /*
- * \_PTS - Prepare to Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2, etc
- *
- * Exit:
- * -none-
- *
- * The _PTS control method is executed at the beginning of the sleep process
- * for S1-S5. The sleeping value is passed to the _PTS control method. This
- * control method may be executed a relatively long time before entering the
- * sleep state and the OS may abort the operation without notification to
- * the ACPI driver. This method cannot modify the configuration or power
- * state of any device in the system.
- */
- Method(\_PTS, 1) {
- /* DBGO("\\_PTS\n") */
- /* DBGO("From S0 to S") */
- /* DBGO(Arg0) */
- /* DBGO("\n") */
-
- /* Don't allow PCIRST# to reset USB */
- if (LEqual(Arg0,3)){
- Store(0,URRE)
- }
-
- /* Clear sleep SMI status flag and enable sleep SMI trap. */
- /*Store(One, CSSM)
- Store(One, SSEN)*/
-
- /* On older chips, clear PciExpWakeDisEn */
- /*if (LLessEqual(\_SB.SBRI, 0x13)) {
- * Store(0,\_SB.PWDE)
- *}
- */
-
- /* Clear wake status structure. */
- Store(0, Index(WKST,0))
- Store(0, Index(WKST,1))
- \_SB.PCI0.SIOS (Arg0)
- } /* End Method(\_PTS) */
-
- /*
- * The following method results in a "not a valid reserved NameSeg"
- * warning so I have commented it out for the duration. It isn't
- * used, so it could be removed.
- *
- *
- * \_GTS OEM Going To Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * -none-
- *
- * Method(\_GTS, 1) {
- * DBGO("\\_GTS\n")
- * DBGO("From S0 to S")
- * DBGO(Arg0)
- * DBGO("\n")
- * }
- */
-
- /*
- * \_BFS OEM Back From Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * -none-
- */
- Method(\_BFS, 1) {
- /* DBGO("\\_BFS\n") */
- /* DBGO("From S") */
- /* DBGO(Arg0) */
- /* DBGO(" to S0\n") */
- }
-
- /*
- * \_WAK System Wake method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * Return package of 2 DWords
- * Dword 1 - Status
- * 0x00000000 wake succeeded
- * 0x00000001 Wake was signaled but failed due to lack of power
- * 0x00000002 Wake was signaled but failed due to thermal condition
- * Dword 2 - Power Supply state
- * if non-zero the effective S-state the power supply entered
- */
- Method(\_WAK, 1) {
- /* DBGO("\\_WAK\n") */
- /* DBGO("From S") */
- /* DBGO(Arg0) */
- /* DBGO(" to S0\n") */
-
- /* Re-enable HPET */
- Store(1,HPDE)
-
- /* Restore PCIRST# so it resets USB */
- if (LEqual(Arg0,3)){
- Store(1,URRE)
- }
-
- /* Arbitrarily clear PciExpWakeStatus */
- Store(PWST, PWST)
-
- /* if(DeRefOf(Index(WKST,0))) {
- * Store(0, Index(WKST,1))
- * } else {
- * Store(Arg0, Index(WKST,1))
- * }
- */
- \_SB.PCI0.SIOW (Arg0)
- Return(WKST)
- } /* End Method(\_WAK) */
-
- Scope(\_GPE) { /* Start Scope GPE */
- /* General event 0 */
- /* Method(_L00) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 1 */
- /* Method(_L01) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 2 */
- /* Method(_L02) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 3 */
- Method(_L03) {
- /* DBGO("\\_GPE\\_L00\n") */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* General event 4 */
- /* Method(_L04) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 5 */
- /* Method(_L05) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 6 - Used for GPM6, moved to USB.asl */
- /* Method(_L06) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 7 - Used for GPM7, moved to USB.asl */
- /* Method(_L07) {
- * DBGO("\\_GPE\\_L07\n")
- * }
- */
-
- /* Legacy PM event */
- Method(_L08) {
- /* DBGO("\\_GPE\\_L08\n") */
- }
-
- /* Temp warning (TWarn) event */
- Method(_L09) {
- /* DBGO("\\_GPE\\_L09\n") */
- Notify (\_TZ.TZ00, 0x80)
- }
-
- /* Reserved */
- /* Method(_L0A) {
- * DBGO("\\_GPE\\_L0A\n")
- * }
- */
-
- /* USB controller PME# */
- Method(_L0B) {
- /* DBGO("\\_GPE\\_L0B\n") */
- Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* AC97 controller PME# */
- /* Method(_L0C) {
- * DBGO("\\_GPE\\_L0C\n")
- * }
- */
-
- /* OtherTherm PME# */
- /* Method(_L0D) {
- * DBGO("\\_GPE\\_L0D\n")
- * }
- */
-
- /* GPM9 SCI event - Moved to USB.asl */
- /* Method(_L0E) {
- * DBGO("\\_GPE\\_L0E\n")
- * }
- */
-
- /* PCIe HotPlug event */
- /* Method(_L0F) {
- * DBGO("\\_GPE\\_L0F\n")
- * }
- */
-
- /* ExtEvent0 SCI event */
- Method(_L10) {
- /* DBGO("\\_GPE\\_L10\n") */
- }
-
-
- /* ExtEvent1 SCI event */
- Method(_L11) {
- /* DBGO("\\_GPE\\_L11\n") */
- }
-
- /* PCIe PME# event */
- /* Method(_L12) {
- * DBGO("\\_GPE\\_L12\n")
- * }
- */
-
- /* GPM0 SCI event - Moved to USB.asl */
- /* Method(_L13) {
- * DBGO("\\_GPE\\_L13\n")
- * }
- */
-
- /* GPM1 SCI event - Moved to USB.asl */
- /* Method(_L14) {
- * DBGO("\\_GPE\\_L14\n")
- * }
- */
-
- /* GPM2 SCI event - Moved to USB.asl */
- /* Method(_L15) {
- * DBGO("\\_GPE\\_L15\n")
- * }
- */
-
- /* GPM3 SCI event - Moved to USB.asl */
- /* Method(_L16) {
- * DBGO("\\_GPE\\_L16\n")
- * }
- */
-
- /* GPM8 SCI event - Moved to USB.asl */
- /* Method(_L17) {
- * DBGO("\\_GPE\\_L17\n")
- * }
- */
-
- /* GPIO0 or GEvent8 event */
- Method(_L18) {
- /* DBGO("\\_GPE\\_L18\n") */
- Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* GPM4 SCI event - Moved to USB.asl */
- /* Method(_L19) {
- * DBGO("\\_GPE\\_L19\n")
- * }
- */
-
- /* GPM5 SCI event - Moved to USB.asl */
- /* Method(_L1A) {
- * DBGO("\\_GPE\\_L1A\n")
- * }
- */
-
- /* Azalia SCI event */
- Method(_L1B) {
- /* DBGO("\\_GPE\\_L1B\n") */
- Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* GPM6 SCI event - Reassigned to _L06 */
- /* Method(_L1C) {
- * DBGO("\\_GPE\\_L1C\n")
- * }
- */
-
- /* GPM7 SCI event - Reassigned to _L07 */
- /* Method(_L1D) {
- * DBGO("\\_GPE\\_L1D\n")
- * }
- */
-
- /* GPIO2 or GPIO66 SCI event */
- /* Method(_L1E) {
- * DBGO("\\_GPE\\_L1E\n")
- * }
- */
-
- /* SATA SCI event - Moved to sata.asl */
- /* Method(_L1F) {
- * DBGO("\\_GPE\\_L1F\n")
- * }
- */
-
- } /* End Scope GPE */
-
- Include ("usb.asl")
-
- /* South Bridge */
- Scope(\_SB) { /* Start \_SB scope */
- Include ("globutil.asl") /* global utility methods expected within the \_SB scope */
-
- /* _SB.PCI0 */
- /* Note: Only need HID on Primary Bus */
- Device(PCI0) {
- External (TOM1)
- External (TOM2)
- Name(_HID, EISAID("PNP0A03"))
- Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
- Method(_BBN, 0) { /* Bus number = 0 */
- Return(0)
- }
- Method(_STA, 0) {
- /* DBGO("\\_SB\\PCI0\\_STA\n") */
- Return(0x0B) /* Status is visible */
- }
-
- Method(_PRT,0) {
- If(PMOD){ Return(APR0) } /* APIC mode */
- Return (PR0) /* PIC Mode */
- } /* end _PRT */
-
- /* Describe the Northbridge devices */
- Device(AMRT) {
- Name(_ADR, 0x00000000)
- } /* end AMRT */
-
- /* The internal GFX bridge */
- Device(AGPB) {
- Name(_ADR, 0x00010000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- Return (APR1)
- }
- } /* end AGPB */
-
- /* The external GFX bridge */
- Device(PBR2) {
- Name(_ADR, 0x00020000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS2) } /* APIC mode */
- Return (PS2) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR2 */
-
- /* Dev3 is also an external GFX bridge, not used in Herring */
-
- Device(PBR4) {
- Name(_ADR, 0x00040000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS4) } /* APIC mode */
- Return (PS4) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR4 */
-
- Device(PBR5) {
- Name(_ADR, 0x00050000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS5) } /* APIC mode */
- Return (PS5) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR5 */
-
- Device(PBR6) {
- Name(_ADR, 0x00060000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS6) } /* APIC mode */
- Return (PS6) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR6 */
-
- /* The onboard EtherNet chip */
- Device(PBR7) {
- Name(_ADR, 0x00070000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS7) } /* APIC mode */
- Return (PS7) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR7 */
-
-
- /* PCI slot 1, 2, 3 */
- Device(PIBR) {
- Name(_ADR, 0x00140004)
- Name(_PRW, Package() {0x18, 4})
-
- Method(_PRT, 0) {
- Return (PCIB)
- }
- }
-
- /* Describe the Southbridge devices */
- Device(STCR) {
- Name(_ADR, 0x00120000)
- Include ("sata.asl")
- } /* end STCR */
-
- Device(UOH1) {
- Name(_ADR, 0x00130000)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH1 */
-
- Device(UOH2) {
- Name(_ADR, 0x00130001)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH2 */
-
- Device(UOH3) {
- Name(_ADR, 0x00130002)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH3 */
-
- Device(UOH4) {
- Name(_ADR, 0x00130003)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH4 */
-
- Device(UOH5) {
- Name(_ADR, 0x00130004)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH5 */
-
- Device(UEH1) {
- Name(_ADR, 0x00130005)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UEH1 */
-
- Device(SBUS) {
- Name(_ADR, 0x00140000)
- } /* end SBUS */
-
- /* Primary (and only) IDE channel */
- Device(IDEC) {
- Name(_ADR, 0x00140001)
- Include ("ide.asl")
- } /* end IDEC */
-
- Device(AZHD) {
- Name(_ADR, 0x00140002)
- OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
- Field(AZPD, AnyAcc, NoLock, Preserve) {
- offset (0x42),
- NSDI, 1,
- NSDO, 1,
- NSEN, 1,
- offset (0x44),
- IPCR, 4,
- offset (0x54),
- PWST, 2,
- , 6,
- PMEB, 1,
- , 6,
- PMST, 1,
- offset (0x62),
- MMCR, 1,
- offset (0x64),
- MMLA, 32,
- offset (0x68),
- MMHA, 32,
- offset (0x6C),
- MMDT, 16,
- }
-
- Method(_INI) {
- If(LEqual(OSTP,3)){ /* If we are running Linux */
- Store(zero, NSEN)
- Store(one, NSDO)
- Store(one, NSDI)
- }
- }
- } /* end AZHD */
-
- Device(LIBR) {
- Name(_ADR, 0x00140003)
- /* Method(_INI) {
- * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
- } */ /* End Method(_SB.SBRDG._INI) */
-
- /* Real Time Clock Device */
- Device(RTC0) {
- Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){8}
- IO(Decode16,0x0070, 0x0070, 0, 2)
- /* IO(Decode16,0x0070, 0x0070, 0, 4) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
-
- Device(TMR) { /* Timer */
- Name(_HID,EISAID("PNP0100")) /* System Timer */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){0}
- IO(Decode16, 0x0040, 0x0040, 0, 4)
- /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
-
- Device(SPKR) { /* Speaker */
- Name(_HID,EISAID("PNP0800")) /* AT style speaker */
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x0061, 0x0061, 0, 1)
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
-
- Device(PIC) {
- Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){2}
- IO(Decode16,0x0020, 0x0020, 0, 2)
- IO(Decode16,0x00A0, 0x00A0, 0, 2)
- /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
- /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
-
- Device(MAD) { /* 8257 DMA */
- Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
- Name(_CRS, ResourceTemplate() {
- DMA(Compatibility,BusMaster,Transfer8){4}
- IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
- IO(Decode16, 0x0081, 0x0081, 0x10, 0x03)
- IO(Decode16, 0x0087, 0x0087, 0x10, 0x01)
- IO(Decode16, 0x0089, 0x0089, 0x10, 0x03)
- IO(Decode16, 0x008F, 0x008F, 0x10, 0x01)
- IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
- }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
- } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
-
- Device(COPR) {
- Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
- IRQNoFlags(){13}
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
-
- Device(HPTM) {
- Name(_HID,EISAID("PNP0103"))
- Name(CRS,ResourceTemplate() {
- Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
- })
- Method(_STA, 0) {
- Return(0x0F) /* sata is visible */
- }
- Method(_CRS, 0) {
- CreateDwordField(CRS, ^HPT._BAS, HPBA)
- Store(HPBA, HPBA)
- Return(CRS)
- }
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
- } /* end LIBR */
-
- Device(HPBR) {
- Name(_ADR, 0x00140004)
- } /* end HostPciBr */
-
- Device(ACAD) {
- Name(_ADR, 0x00140005)
- } /* end Ac97audio */
-
- Device(ACMD) {
- Name(_ADR, 0x00140006)
- } /* end Ac97modem */
-
- /* ITE IT8712F Support */
- OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
- Field (IOID, ByteAcc, NoLock, Preserve)
- {
- SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */
- }
-
- IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
- {
- Offset (0x07),
- LDN, 8, /* Logical Device Number */
- Offset (0x20),
- CID1, 8, /* Chip ID Byte 1, 0x87 */
- CID2, 8, /* Chip ID Byte 2, 0x12 */
- Offset (0x30),
- ACTR, 8, /* Function activate */
- Offset (0xF0),
- APC0, 8, /* APC/PME Event Enable Register */
- APC1, 8, /* APC/PME Status Register */
- APC2, 8, /* APC/PME Control Register 1 */
- APC3, 8, /* Environment Controller Special Configuration Register */
- APC4, 8 /* APC/PME Control Register 2 */
- }
-
- /* Enter the IT8712F MB PnP Mode */
- Method (EPNP)
- {
- Store(0x87, SIOI)
- Store(0x01, SIOI)
- Store(0x55, SIOI)
- Store(0x55, SIOI) /* IT8712F magic number */
- }
- /* Exit the IT8712F MB PnP Mode */
- Method (XPNP)
- {
- Store (0x02, SIOI)
- Store (0x02, SIOD)
- }
-
- /*
- * Keyboard PME is routed to SB600 Gevent3. We can wake
- * up the system by pressing the key.
- */
- Method (SIOS, 1)
- {
- /* We only enable KBD PME for S5. */
- If (LLess (Arg0, 0x05))
- {
- EPNP()
- /* DBGO("IT8712F\n") */
-
- Store (0x4, LDN)
- Store (One, ACTR) /* Enable EC */
- /*
- Store (0x4, LDN)
- Store (0x04, APC4)
- */ /* falling edge. which mode? Not sure. */
-
- Store (0x4, LDN)
- Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
- Store (0x4, LDN)
- Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
-
- XPNP()
- }
- }
- Method (SIOW, 1)
- {
- EPNP()
- Store (0x4, LDN)
- Store (Zero, APC0) /* disable keyboard PME */
- Store (0x4, LDN)
- Store (0xFF, APC1) /* clear keyboard PME status */
- XPNP()
- }
-
- Name(CRES, ResourceTemplate() {
- IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0000, /* range minimum */
- 0x0CF7, /* range maximum */
- 0x0000, /* translation */
- 0x0CF8 /* length */
- )
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0D00, /* range minimum */
- 0xFFFF, /* range maximum */
- 0x0000, /* translation */
- 0xF300 /* length */
- )
-
- Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
- Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
- Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
-
- /* DRAM Memory from 1MB to TopMem */
- Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
-
- /* BIOS space just below 4GB */
- DWORDMemory(
- ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000000, /* Max-Min, RLEN */
- ,,
- PCBM
- )
-
- /* DRAM memory from 4GB to TopMem2 */
- QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0xFFFFFFFF, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000000, /* Max-Min, RLEN */
- ,,
- DMHI
- )
-
- /* BIOS space just below 16EB */
- QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0xFFFFFFFF, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000000, /* Max-Min, RLEN */
- ,,
- PEBM
- )
-
- }) /* End Name(_SB.PCI0.CRES) */
-
- Method(_CRS, 0) {
- /* DBGO("\\_SB\\PCI0\\_CRS\n") */
-
- CreateDWordField(CRES, ^EMM1._BAS, EM1B)
- CreateDWordField(CRES, ^EMM1._LEN, EM1L)
- CreateDWordField(CRES, ^DMLO._BAS, DMLB)
- CreateDWordField(CRES, ^DMLO._LEN, DMLL)
- CreateDWordField(CRES, ^PCBM._MIN, PBMB)
- CreateDWordField(CRES, ^PCBM._LEN, PBML)
-
- CreateQWordField(CRES, ^DMHI._MIN, DMHB)
- CreateQWordField(CRES, ^DMHI._LEN, DMHL)
- CreateQWordField(CRES, ^PEBM._MIN, EBMB)
- CreateQWordField(CRES, ^PEBM._LEN, EBML)
-
- If(LGreater(LOMH, 0xC0000)){
- Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
- Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
- }
-
- /* Set size of memory from 1MB to TopMem */
- Subtract(TOM1, 0x100000, DMLL)
-
- /*
- * If(LNotEqual(TOM2, 0x00000000)){
- * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
- * Subtract(TOM2, 0x100000000, DMHL)
- * }
- */
-
- /* If there is no memory above 4GB, put the BIOS just below 4GB */
- If(LEqual(TOM2, 0x00000000)){
- Store(PBAD,PBMB) /* Reserve the "BIOS" space */
- Store(PBLN,PBML)
- }
- Else { /* Otherwise, put the BIOS just below 16EB */
- ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
- Store(PBLN,EBML)
- }
-
- Return(CRES) /* note to change the Name buffer */
- } /* end of Method(_SB.PCI0._CRS) */
-
- /*
- *
- * FIRST METHOD CALLED UPON BOOT
- *
- * 1. If debugging, print current OS and ACPI interpreter.
- * 2. Get PCI Interrupt routing from ACPI VSM, this
- * value is based on user choice in BIOS setup.
- */
- Method(_INI, 0) {
- /* DBGO("\\_SB\\_INI\n") */
- /* DBGO(" DSDT.ASL code from ") */
- /* DBGO(__DATE__) */
- /* DBGO(" ") */
- /* DBGO(__TIME__) */
- /* DBGO("\n Sleep states supported: ") */
- /* DBGO("\n") */
- /* DBGO(" \\_OS=") */
- /* DBGO(\_OS) */
- /* DBGO("\n \\_REV=") */
- /* DBGO(\_REV) */
- /* DBGO("\n") */
-
- /* Determine the OS we're running on */
- CkOT()
-
- /* On older chips, clear PciExpWakeDisEn */
- /*if (LLessEqual(\SBRI, 0x13)) {
- * Store(0,\PWDE)
- * }
- */
- } /* End Method(_SB._INI) */
- } /* End Device(PCI0) */
-
- Device(PWRB) { /* Start Power button device */
- Name(_HID, EISAID("PNP0C0C"))
- Name(_UID, 0xAA)
- Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
- Name(_STA, 0x0B) /* sata is invisible */
- }
- } /* End \_SB scope */
-
- Scope(\_SI) {
- Method(_SST, 1) {
- /* DBGO("\\_SI\\_SST\n") */
- /* DBGO(" New Indicator state: ") */
- /* DBGO(Arg0) */
- /* DBGO("\n") */
- }
- } /* End Scope SI */
-
- Mutex (SBX0, 0x00)
- OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
- Field (SMB0, ByteAcc, NoLock, Preserve) {
- HSTS, 8, /* SMBUS status */
- SSTS, 8, /* SMBUS slave status */
- HCNT, 8, /* SMBUS control */
- HCMD, 8, /* SMBUS host cmd */
- HADD, 8, /* SMBUS address */
- DAT0, 8, /* SMBUS data0 */
- DAT1, 8, /* SMBUS data1 */
- BLKD, 8, /* SMBUS block data */
- SCNT, 8, /* SMBUS slave control */
- SCMD, 8, /* SMBUS shaow cmd */
- SEVT, 8, /* SMBUS slave event */
- SDAT, 8 /* SMBUS slave data */
- }
-
- Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
- Store (0x1E, HSTS)
- Store (0xFA, Local0)
- While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
- Stall (0x64)
- Decrement (Local0)
- }
-
- Return (Local0)
- }
-
- Method (SWTC, 1, NotSerialized) {
- Store (Arg0, Local0)
- Store (0x07, Local2)
- Store (One, Local1)
- While (LEqual (Local1, One)) {
- Store (And (HSTS, 0x1E), Local3)
- If (LNotEqual (Local3, Zero)) { /* read sucess */
- If (LEqual (Local3, 0x02)) {
- Store (Zero, Local2)
- }
-
- Store (Zero, Local1)
- }
- Else {
- If (LLess (Local0, 0x0A)) { /* read failure */
- Store (0x10, Local2)
- Store (Zero, Local1)
- }
- Else {
- Sleep (0x0A) /* 10 ms, try again */
- Subtract (Local0, 0x0A, Local0)
- }
- }
- }
-
- Return (Local2)
- }
-
- Method (SMBR, 3, NotSerialized) {
- Store (0x07, Local0)
- If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
- Store (WCLR (), Local0) /* clear SMBUS status register before read data */
- If (LEqual (Local0, Zero)) {
- Release (SBX0)
- Return (0x0)
- }
-
- Store (0x1F, HSTS)
- Store (Or (ShiftLeft (Arg1, One), One), HADD)
- Store (Arg2, HCMD)
- If (LEqual (Arg0, 0x07)) {
- Store (0x48, HCNT) /* read byte */
- }
-
- Store (SWTC (0x03E8), Local1) /* 1000 ms */
- If (LEqual (Local1, Zero)) {
- If (LEqual (Arg0, 0x07)) {
- Store (DAT0, Local0)
- }
- }
- Else {
- Store (Local1, Local0)
- }
-
- Release (SBX0)
- }
-
- /* DBGO("the value of SMBusData0 register ") */
- /* DBGO(Arg2) */
- /* DBGO(" is ") */
- /* DBGO(Local0) */
- /* DBGO("\n") */
-
- Return (Local0)
- }
-
- /* THERMAL */
- Scope(\_TZ) {
- Name (KELV, 2732)
- Name (THOT, 800)
- Name (TCRT, 850)
-
- ThermalZone(TZ00) {
- Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
- /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
- Return(Add(0, 2730))
- }
- Method(_AL0,0) { /* Returns package of cooling device to turn on */
- /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
- Return(Package() {\_TZ.TZ00.FAN0})
- }
- Device (FAN0) {
- Name(_HID, EISAID("PNP0C0B"))
- Name(_PR0, Package() {PFN0})
- }
-
- PowerResource(PFN0,0,0) {
- Method(_STA) {
- Store(0xF,Local0)
- Return(Local0)
- }
- Method(_ON) {
- /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
- }
- Method(_OFF) {
- /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
- }
- }
-
- Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
- /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
- Return (Add (THOT, KELV))
- }
- Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
- /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
- Return (Add (TCRT, KELV))
- }
- Method(_TMP,0) { /* return current temp of this zone */
- Store (SMBR (0x07, 0x4C,, 0x00), Local0)
- If (LGreater (Local0, 0x10)) {
- Store (Local0, Local1)
- }
- Else {
- Add (Local0, THOT, Local0)
- Return (Add (400, KELV))
- }
-
- Store (SMBR (0x07, 0x4C, 0x01), Local0)
- /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
- /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
- If (LGreater (Local0, 0x10)) {
- If (LGreater (Local0, Local1)) {
- Store (Local0, Local1)
- }
-
- Multiply (Local1, 10, Local1)
- Return (Add (Local1, KELV))
- }
- Else {
- Add (Local0, THOT, Local0)
- Return (Add (400 , KELV))
- }
- } /* end of _TMP */
- } /* end of TZ00 */
- }
-}
-/* End of ASL file */
/*
Scope(\_SB) {
- Include ("globutil.asl")
+ #include "globutil.asl"
}
*/
Device(PCI0) {
Device(IDEC) {
Name(_ADR, 0x00140001)
- Include ("ide.asl")
+ #include "ide.asl"
}
}
}
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
)
{
- Include ("routing.asl")
+ #include "routing.asl"
}
*/
Device(PCI0) {
Device(SATA) {
Name(_ADR, 0x00120000)
- Include ("sata.asl")
+ #include "sata.asl"
}
}
}
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
)
{
- Include ("usb.asl")
+ #include "usb.asl"
}
*/
Method(UCOC, 0) {
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+ "DSDT.AML", /* Output filename */
+ "DSDT", /* Signature */
+ 0x02, /* DSDT Revision, needs to be 2 for 64bit */
+ "TECHNEXION", /* OEMID */
+ "TIM-8690", /* TABLE ID */
+ 0x00010001 /* OEM Revision */
+ )
+{ /* Start of ASL file */
+ /* #include "acpi/debug.asl" */ /* Include global debug methods if needed */
+
+ /* Data to be patched by the BIOS during POST */
+ /* FIXME the patching is not done yet! */
+ /* Memory related values */
+ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
+ Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+ Name(PBLN, 0x0) /* Length of BIOS area */
+
+ Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
+ Name(HPBA, 0xFED00000) /* Base address of HPET table */
+
+ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+ /* USB overcurrent mapping pins. */
+ Name(UOM0, 0)
+ Name(UOM1, 2)
+ Name(UOM2, 0)
+ Name(UOM3, 7)
+ Name(UOM4, 2)
+ Name(UOM5, 2)
+ Name(UOM6, 6)
+ Name(UOM7, 2)
+ Name(UOM8, 6)
+ Name(UOM9, 6)
+
+ /* Some global data */
+ Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+ Name(OSV, Ones) /* Assume nothing */
+ Name(PMOD, One) /* Assume APIC */
+
+ /* PIC IRQ mapping registers, C00h-C01h */
+ OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
+ Field(PRQM, ByteAcc, NoLock, Preserve) {
+ PRQI, 0x00000008,
+ PRQD, 0x00000008, /* Offset: 1h */
+ }
+ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
+ PINA, 0x00000008, /* Index 0 */
+ PINB, 0x00000008, /* Index 1 */
+ PINC, 0x00000008, /* Index 2 */
+ PIND, 0x00000008, /* Index 3 */
+ AINT, 0x00000008, /* Index 4 */
+ SINT, 0x00000008, /* Index 5 */
+ , 0x00000008, /* Index 6 */
+ AAUD, 0x00000008, /* Index 7 */
+ AMOD, 0x00000008, /* Index 8 */
+ PINE, 0x00000008, /* Index 9 */
+ PINF, 0x00000008, /* Index A */
+ PING, 0x00000008, /* Index B */
+ PINH, 0x00000008, /* Index C */
+ }
+
+ /* PCI Error control register */
+ OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
+ Field(PERC, ByteAcc, NoLock, Preserve) {
+ SENS, 0x00000001,
+ PENS, 0x00000001,
+ SENE, 0x00000001,
+ PENE, 0x00000001,
+ }
+
+ /* Client Management index/data registers */
+ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
+ Field(CMT, ByteAcc, NoLock, Preserve) {
+ CMTI, 8,
+ /* Client Management Data register */
+ G64E, 1,
+ G64O, 1,
+ G32O, 2,
+ , 2,
+ GPSL, 2,
+ }
+
+ /* GPM Port register */
+ OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
+ Field(GPT, ByteAcc, NoLock, Preserve) {
+ GPB0,1,
+ GPB1,1,
+ GPB2,1,
+ GPB3,1,
+ GPB4,1,
+ GPB5,1,
+ GPB6,1,
+ GPB7,1,
+ }
+
+ /* Flash ROM program enable register */
+ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
+ Field(FRE, ByteAcc, NoLock, Preserve) {
+ , 0x00000006,
+ FLRE, 0x00000001,
+ }
+
+ /* PM2 index/data registers */
+ OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
+ Field(PM2R, ByteAcc, NoLock, Preserve) {
+ PM2I, 0x00000008,
+ PM2D, 0x00000008,
+ }
+
+ /* Power Management I/O registers */
+ OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
+ Field(PIOR, ByteAcc, NoLock, Preserve) {
+ PIOI, 0x00000008,
+ PIOD, 0x00000008,
+ }
+ IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
+ Offset(0x00), /* MiscControl */
+ , 1,
+ T1EE, 1,
+ T2EE, 1,
+ Offset(0x01), /* MiscStatus */
+ , 1,
+ T1E, 1,
+ T2E, 1,
+ Offset(0x04), /* SmiWakeUpEventEnable3 */
+ , 7,
+ SSEN, 1,
+ Offset(0x07), /* SmiWakeUpEventStatus3 */
+ , 7,
+ CSSM, 1,
+ Offset(0x10), /* AcpiEnable */
+ , 6,
+ PWDE, 1,
+ Offset(0x1C), /* ProgramIoEnable */
+ , 3,
+ MKME, 1,
+ IO3E, 1,
+ IO2E, 1,
+ IO1E, 1,
+ IO0E, 1,
+ Offset(0x1D), /* IOMonitorStatus */
+ , 3,
+ MKMS, 1,
+ IO3S, 1,
+ IO2S, 1,
+ IO1S, 1,
+ IO0S,1,
+ Offset(0x20), /* AcpiPmEvtBlk */
+ APEB, 16,
+ Offset(0x36), /* GEvtLevelConfig */
+ , 6,
+ ELC6, 1,
+ ELC7, 1,
+ Offset(0x37), /* GPMLevelConfig0 */
+ , 3,
+ PLC0, 1,
+ PLC1, 1,
+ PLC2, 1,
+ PLC3, 1,
+ PLC8, 1,
+ Offset(0x38), /* GPMLevelConfig1 */
+ , 1,
+ PLC4, 1,
+ PLC5, 1,
+ , 1,
+ PLC6, 1,
+ PLC7, 1,
+ Offset(0x3B), /* PMEStatus1 */
+ GP0S, 1,
+ GM4S, 1,
+ GM5S, 1,
+ APS, 1,
+ GM6S, 1,
+ GM7S, 1,
+ GP2S, 1,
+ STSS, 1,
+ Offset(0x55), /* SoftPciRst */
+ SPRE, 1,
+ , 1,
+ , 1,
+ PNAT, 1,
+ PWMK, 1,
+ PWNS, 1,
+
+ /* Offset(0x61), */ /* Options_1 */
+ /* ,7, */
+ /* R617,1, */
+
+ Offset(0x65), /* UsbPMControl */
+ , 4,
+ URRE, 1,
+ Offset(0x68), /* MiscEnable68 */
+ , 3,
+ TMTE, 1,
+ , 1,
+ Offset(0x92), /* GEVENTIN */
+ , 7,
+ E7IS, 1,
+ Offset(0x96), /* GPM98IN */
+ G8IS, 1,
+ G9IS, 1,
+ Offset(0x9A), /* EnhanceControl */
+ ,7,
+ HPDE, 1,
+ Offset(0xA8), /* PIO7654Enable */
+ IO4E, 1,
+ IO5E, 1,
+ IO6E, 1,
+ IO7E, 1,
+ Offset(0xA9), /* PIO7654Status */
+ IO4S, 1,
+ IO5S, 1,
+ IO6S, 1,
+ IO7S, 1,
+ }
+
+ /* PM1 Event Block
+ * First word is PM1_Status, Second word is PM1_Enable
+ */
+ OperationRegion(P1EB, SystemIO, APEB, 0x04)
+ Field(P1EB, ByteAcc, NoLock, Preserve) {
+ TMST, 1,
+ , 3,
+ BMST, 1,
+ GBST, 1,
+ Offset(0x01),
+ PBST, 1,
+ , 1,
+ RTST, 1,
+ , 3,
+ PWST, 1,
+ SPWS, 1,
+ Offset(0x02),
+ TMEN, 1,
+ , 4,
+ GBEN, 1,
+ Offset(0x03),
+ PBEN, 1,
+ , 1,
+ RTEN, 1,
+ , 3,
+ PWDA, 1,
+ }
+
+ Scope(\_SB) {
+
+ /* PCIe Configuration Space for 16 busses */
+ OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
+ Field(PCFG, ByteAcc, NoLock, Preserve) {
+ /* Byte offsets are computed using the following technique:
+ * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
+ * The 8 comes from 8 functions per device, and 4096 bytes per function config space
+ */
+ Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */
+ STB5, 32,
+ Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
+ PT0D, 1,
+ PT1D, 1,
+ PT2D, 1,
+ PT3D, 1,
+ PT4D, 1,
+ PT5D, 1,
+ PT6D, 1,
+ PT7D, 1,
+ PT8D, 1,
+ PT9D, 1,
+ Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
+ SBIE, 1,
+ SBME, 1,
+ Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
+ SBRI, 8,
+ Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
+ SBB1, 32,
+ Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
+ ,14,
+ P92E, 1, /* Port92 decode enable */
+ }
+
+ OperationRegion(SB5, SystemMemory, STB5, 0x1000)
+ Field(SB5, AnyAcc, NoLock, Preserve)
+ {
+ /* Port 0 */
+ Offset(0x120), /* Port 0 Task file status */
+ P0ER, 1,
+ , 2,
+ P0DQ, 1,
+ , 3,
+ P0BY, 1,
+ Offset(0x128), /* Port 0 Serial ATA status */
+ P0DD, 4,
+ , 4,
+ P0IS, 4,
+ Offset(0x12C), /* Port 0 Serial ATA control */
+ P0DI, 4,
+ Offset(0x130), /* Port 0 Serial ATA error */
+ , 16,
+ P0PR, 1,
+
+ /* Port 1 */
+ offset(0x1A0), /* Port 1 Task file status */
+ P1ER, 1,
+ , 2,
+ P1DQ, 1,
+ , 3,
+ P1BY, 1,
+ Offset(0x1A8), /* Port 1 Serial ATA status */
+ P1DD, 4,
+ , 4,
+ P1IS, 4,
+ Offset(0x1AC), /* Port 1 Serial ATA control */
+ P1DI, 4,
+ Offset(0x1B0), /* Port 1 Serial ATA error */
+ , 16,
+ P1PR, 1,
+
+ /* Port 2 */
+ Offset(0x220), /* Port 2 Task file status */
+ P2ER, 1,
+ , 2,
+ P2DQ, 1,
+ , 3,
+ P2BY, 1,
+ Offset(0x228), /* Port 2 Serial ATA status */
+ P2DD, 4,
+ , 4,
+ P2IS, 4,
+ Offset(0x22C), /* Port 2 Serial ATA control */
+ P2DI, 4,
+ Offset(0x230), /* Port 2 Serial ATA error */
+ , 16,
+ P2PR, 1,
+
+ /* Port 3 */
+ Offset(0x2A0), /* Port 3 Task file status */
+ P3ER, 1,
+ , 2,
+ P3DQ, 1,
+ , 3,
+ P3BY, 1,
+ Offset(0x2A8), /* Port 3 Serial ATA status */
+ P3DD, 4,
+ , 4,
+ P3IS, 4,
+ Offset(0x2AC), /* Port 3 Serial ATA control */
+ P3DI, 4,
+ Offset(0x2B0), /* Port 3 Serial ATA error */
+ , 16,
+ P3PR, 1,
+ }
+ }
+
+ #include "acpi/routing.asl"
+
+ Scope(\_SB) {
+
+ Method(CkOT, 0){
+
+ if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */
+
+ if(CondRefOf(\_OSI,Local1))
+ {
+ Store(1, OSTP) /* Assume some form of XP */
+ if (\_OSI("Windows 2006")) /* Vista */
+ {
+ Store(2, OSTP)
+ }
+ } else {
+ If(WCMP(\_OS,"Linux")) {
+ Store(3, OSTP) /* Linux */
+ } Else {
+ Store(4, OSTP) /* Gotta be WinCE */
+ }
+ }
+ Return(OSTP)
+ }
+
+ Method(_PIC, 0x01, NotSerialized)
+ {
+ If (Arg0)
+ {
+ \_SB.CIRQ()
+ }
+ Store(Arg0, PMOD)
+ }
+
+ Method(CIRQ, 0x00, NotSerialized)
+ {
+ Store(0, PINA)
+ Store(0, PINB)
+ Store(0, PINC)
+ Store(0, PIND)
+ Store(0, PINE)
+ Store(0, PINF)
+ Store(0, PING)
+ Store(0, PINH)
+ }
+
+ Name(IRQB, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Shared){15}
+ })
+
+ Name(IRQP, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
+ })
+
+ Name(PITF, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Exclusive){9}
+ })
+
+ Device(INTA) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 1)
+
+ Method(_STA, 0) {
+ if (PINA) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTA._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_DIS\n") */
+ Store(0, PINA)
+ } /* End Method(_SB.INTA._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTA._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINA, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTA._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKA\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINA)
+ } /* End Method(_SB.INTA._SRS) */
+ } /* End Device(INTA) */
+
+ Device(INTB) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 2)
+
+ Method(_STA, 0) {
+ if (PINB) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTB._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_DIS\n") */
+ Store(0, PINB)
+ } /* End Method(_SB.INTB._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTB._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINB, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTB._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKB\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINB)
+ } /* End Method(_SB.INTB._SRS) */
+ } /* End Device(INTB) */
+
+ Device(INTC) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 3)
+
+ Method(_STA, 0) {
+ if (PINC) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTC._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_DIS\n") */
+ Store(0, PINC)
+ } /* End Method(_SB.INTC._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTC._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINC, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTC._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKC\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINC)
+ } /* End Method(_SB.INTC._SRS) */
+ } /* End Device(INTC) */
+
+ Device(INTD) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 4)
+
+ Method(_STA, 0) {
+ if (PIND) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTD._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_DIS\n") */
+ Store(0, PIND)
+ } /* End Method(_SB.INTD._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTD._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIND, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTD._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKD\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIND)
+ } /* End Method(_SB.INTD._SRS) */
+ } /* End Device(INTD) */
+
+ Device(INTE) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 5)
+
+ Method(_STA, 0) {
+ if (PINE) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTE._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_DIS\n") */
+ Store(0, PINE)
+ } /* End Method(_SB.INTE._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTE._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINE, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTE._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKE\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINE)
+ } /* End Method(_SB.INTE._SRS) */
+ } /* End Device(INTE) */
+
+ Device(INTF) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 6)
+
+ Method(_STA, 0) {
+ if (PINF) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTF._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_DIS\n") */
+ Store(0, PINF)
+ } /* End Method(_SB.INTF._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_PRS\n") */
+ Return(PITF)
+ } /* Method(_SB.INTF._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINF, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTF._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKF\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINF)
+ } /* End Method(_SB.INTF._SRS) */
+ } /* End Device(INTF) */
+
+ Device(INTG) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 7)
+
+ Method(_STA, 0) {
+ if (PING) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTG._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKG\\_DIS\n") */
+ Store(0, PING)
+ } /* End Method(_SB.INTG._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKG\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTG._CRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKG\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PING, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTG._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKG\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PING)
+ } /* End Method(_SB.INTG._SRS) */
+ } /* End Device(INTG) */
+
+ Device(INTH) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 8)
+
+ Method(_STA, 0) {
+ if (PINH) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTH._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKH\\_DIS\n") */
+ Store(0, PINH)
+ } /* End Method(_SB.INTH._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKH\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTH._CRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKH\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINH, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTH._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKH\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINH)
+ } /* End Method(_SB.INTH._SRS) */
+ } /* End Device(INTH) */
+
+ } /* End Scope(_SB) */
+
+
+ /* Supported sleep states: */
+ Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
+
+ If (LAnd(SSFG, 0x01)) {
+ Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
+ }
+ If (LAnd(SSFG, 0x02)) {
+ Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
+ }
+ If (LAnd(SSFG, 0x04)) {
+ Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
+ }
+ If (LAnd(SSFG, 0x08)) {
+ Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
+ }
+
+ Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
+
+ Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
+ Name(CSMS, 0) /* Current System State */
+
+ /* Wake status package */
+ Name(WKST,Package(){Zero, Zero})
+
+ /*
+ * \_PTS - Prepare to Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2, etc
+ *
+ * Exit:
+ * -none-
+ *
+ * The _PTS control method is executed at the beginning of the sleep process
+ * for S1-S5. The sleeping value is passed to the _PTS control method. This
+ * control method may be executed a relatively long time before entering the
+ * sleep state and the OS may abort the operation without notification to
+ * the ACPI driver. This method cannot modify the configuration or power
+ * state of any device in the system.
+ */
+ Method(\_PTS, 1) {
+ /* DBGO("\\_PTS\n") */
+ /* DBGO("From S0 to S") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+
+ /* Don't allow PCIRST# to reset USB */
+ if (LEqual(Arg0,3)){
+ Store(0,URRE)
+ }
+
+ /* Clear sleep SMI status flag and enable sleep SMI trap. */
+ /*Store(One, CSSM)
+ Store(One, SSEN)*/
+
+ /* On older chips, clear PciExpWakeDisEn */
+ /*if (LLessEqual(\_SB.SBRI, 0x13)) {
+ * Store(0,\_SB.PWDE)
+ *}
+ */
+
+ /* Clear wake status structure. */
+ Store(0, Index(WKST,0))
+ Store(0, Index(WKST,1))
+ \_SB.PCI0.SIOS (Arg0)
+ } /* End Method(\_PTS) */
+
+ /*
+ * The following method results in a "not a valid reserved NameSeg"
+ * warning so I have commented it out for the duration. It isn't
+ * used, so it could be removed.
+ *
+ *
+ * \_GTS OEM Going To Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * -none-
+ *
+ * Method(\_GTS, 1) {
+ * DBGO("\\_GTS\n")
+ * DBGO("From S0 to S")
+ * DBGO(Arg0)
+ * DBGO("\n")
+ * }
+ */
+
+ /*
+ * \_BFS OEM Back From Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * -none-
+ */
+ Method(\_BFS, 1) {
+ /* DBGO("\\_BFS\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+ }
+
+ /*
+ * \_WAK System Wake method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * Return package of 2 DWords
+ * Dword 1 - Status
+ * 0x00000000 wake succeeded
+ * 0x00000001 Wake was signaled but failed due to lack of power
+ * 0x00000002 Wake was signaled but failed due to thermal condition
+ * Dword 2 - Power Supply state
+ * if non-zero the effective S-state the power supply entered
+ */
+ Method(\_WAK, 1) {
+ /* DBGO("\\_WAK\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+
+ /* Re-enable HPET */
+ Store(1,HPDE)
+
+ /* Restore PCIRST# so it resets USB */
+ if (LEqual(Arg0,3)){
+ Store(1,URRE)
+ }
+
+ /* Arbitrarily clear PciExpWakeStatus */
+ Store(PWST, PWST)
+
+ /* if(DeRefOf(Index(WKST,0))) {
+ * Store(0, Index(WKST,1))
+ * } else {
+ * Store(Arg0, Index(WKST,1))
+ * }
+ */
+ \_SB.PCI0.SIOW (Arg0)
+ Return(WKST)
+ } /* End Method(\_WAK) */
+
+ Scope(\_GPE) { /* Start Scope GPE */
+ /* General event 0 */
+ /* Method(_L00) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 1 */
+ /* Method(_L01) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 2 */
+ /* Method(_L02) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 3 */
+ Method(_L03) {
+ /* DBGO("\\_GPE\\_L00\n") */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* General event 4 */
+ /* Method(_L04) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 5 */
+ /* Method(_L05) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 6 - Used for GPM6, moved to USB.asl */
+ /* Method(_L06) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 7 - Used for GPM7, moved to USB.asl */
+ /* Method(_L07) {
+ * DBGO("\\_GPE\\_L07\n")
+ * }
+ */
+
+ /* Legacy PM event */
+ Method(_L08) {
+ /* DBGO("\\_GPE\\_L08\n") */
+ }
+
+ /* Temp warning (TWarn) event */
+ Method(_L09) {
+ /* DBGO("\\_GPE\\_L09\n") */
+ Notify (\_TZ.TZ00, 0x80)
+ }
+
+ /* Reserved */
+ /* Method(_L0A) {
+ * DBGO("\\_GPE\\_L0A\n")
+ * }
+ */
+
+ /* USB controller PME# */
+ Method(_L0B) {
+ /* DBGO("\\_GPE\\_L0B\n") */
+ Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* AC97 controller PME# */
+ /* Method(_L0C) {
+ * DBGO("\\_GPE\\_L0C\n")
+ * }
+ */
+
+ /* OtherTherm PME# */
+ /* Method(_L0D) {
+ * DBGO("\\_GPE\\_L0D\n")
+ * }
+ */
+
+ /* GPM9 SCI event - Moved to USB.asl */
+ /* Method(_L0E) {
+ * DBGO("\\_GPE\\_L0E\n")
+ * }
+ */
+
+ /* PCIe HotPlug event */
+ /* Method(_L0F) {
+ * DBGO("\\_GPE\\_L0F\n")
+ * }
+ */
+
+ /* ExtEvent0 SCI event */
+ Method(_L10) {
+ /* DBGO("\\_GPE\\_L10\n") */
+ }
+
+
+ /* ExtEvent1 SCI event */
+ Method(_L11) {
+ /* DBGO("\\_GPE\\_L11\n") */
+ }
+
+ /* PCIe PME# event */
+ /* Method(_L12) {
+ * DBGO("\\_GPE\\_L12\n")
+ * }
+ */
+
+ /* GPM0 SCI event - Moved to USB.asl */
+ /* Method(_L13) {
+ * DBGO("\\_GPE\\_L13\n")
+ * }
+ */
+
+ /* GPM1 SCI event - Moved to USB.asl */
+ /* Method(_L14) {
+ * DBGO("\\_GPE\\_L14\n")
+ * }
+ */
+
+ /* GPM2 SCI event - Moved to USB.asl */
+ /* Method(_L15) {
+ * DBGO("\\_GPE\\_L15\n")
+ * }
+ */
+
+ /* GPM3 SCI event - Moved to USB.asl */
+ /* Method(_L16) {
+ * DBGO("\\_GPE\\_L16\n")
+ * }
+ */
+
+ /* GPM8 SCI event - Moved to USB.asl */
+ /* Method(_L17) {
+ * DBGO("\\_GPE\\_L17\n")
+ * }
+ */
+
+ /* GPIO0 or GEvent8 event */
+ Method(_L18) {
+ /* DBGO("\\_GPE\\_L18\n") */
+ Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* GPM4 SCI event - Moved to USB.asl */
+ /* Method(_L19) {
+ * DBGO("\\_GPE\\_L19\n")
+ * }
+ */
+
+ /* GPM5 SCI event - Moved to USB.asl */
+ /* Method(_L1A) {
+ * DBGO("\\_GPE\\_L1A\n")
+ * }
+ */
+
+ /* Azalia SCI event */
+ Method(_L1B) {
+ /* DBGO("\\_GPE\\_L1B\n") */
+ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* GPM6 SCI event - Reassigned to _L06 */
+ /* Method(_L1C) {
+ * DBGO("\\_GPE\\_L1C\n")
+ * }
+ */
+
+ /* GPM7 SCI event - Reassigned to _L07 */
+ /* Method(_L1D) {
+ * DBGO("\\_GPE\\_L1D\n")
+ * }
+ */
+
+ /* GPIO2 or GPIO66 SCI event */
+ /* Method(_L1E) {
+ * DBGO("\\_GPE\\_L1E\n")
+ * }
+ */
+
+ /* SATA SCI event - Moved to sata.asl */
+ /* Method(_L1F) {
+ * DBGO("\\_GPE\\_L1F\n")
+ * }
+ */
+
+ } /* End Scope GPE */
+
+ #include "acpi/usb.asl"
+
+ /* South Bridge */
+ Scope(\_SB) { /* Start \_SB scope */
+ #include "acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
+
+ /* _SB.PCI0 */
+ /* Note: Only need HID on Primary Bus */
+ Device(PCI0) {
+ External (TOM1)
+ External (TOM2)
+ Name(_HID, EISAID("PNP0A03"))
+ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
+ Method(_BBN, 0) { /* Bus number = 0 */
+ Return(0)
+ }
+ Method(_STA, 0) {
+ /* DBGO("\\_SB\\PCI0\\_STA\n") */
+ Return(0x0B) /* Status is visible */
+ }
+
+ Method(_PRT,0) {
+ If(PMOD){ Return(APR0) } /* APIC mode */
+ Return (PR0) /* PIC Mode */
+ } /* end _PRT */
+
+ /* Describe the Northbridge devices */
+ Device(AMRT) {
+ Name(_ADR, 0x00000000)
+ } /* end AMRT */
+
+ /* The internal GFX bridge */
+ Device(AGPB) {
+ Name(_ADR, 0x00010000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ Return (APR1)
+ }
+ } /* end AGPB */
+
+ /* The external GFX bridge */
+ Device(PBR2) {
+ Name(_ADR, 0x00020000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS2) } /* APIC mode */
+ Return (PS2) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR2 */
+
+ /* Dev3 is also an external GFX bridge, not used in Herring */
+
+ Device(PBR4) {
+ Name(_ADR, 0x00040000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS4) } /* APIC mode */
+ Return (PS4) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR4 */
+
+ Device(PBR5) {
+ Name(_ADR, 0x00050000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS5) } /* APIC mode */
+ Return (PS5) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR5 */
+
+ Device(PBR6) {
+ Name(_ADR, 0x00060000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS6) } /* APIC mode */
+ Return (PS6) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR6 */
+
+ /* The onboard EtherNet chip */
+ Device(PBR7) {
+ Name(_ADR, 0x00070000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS7) } /* APIC mode */
+ Return (PS7) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR7 */
+
+
+ /* PCI slot 1, 2, 3 */
+ Device(PIBR) {
+ Name(_ADR, 0x00140004)
+ Name(_PRW, Package() {0x18, 4})
+
+ Method(_PRT, 0) {
+ Return (PCIB)
+ }
+ }
+
+ /* Describe the Southbridge devices */
+ Device(STCR) {
+ Name(_ADR, 0x00120000)
+ #include "acpi/sata.asl"
+ } /* end STCR */
+
+ Device(UOH1) {
+ Name(_ADR, 0x00130000)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH1 */
+
+ Device(UOH2) {
+ Name(_ADR, 0x00130001)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH2 */
+
+ Device(UOH3) {
+ Name(_ADR, 0x00130002)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH3 */
+
+ Device(UOH4) {
+ Name(_ADR, 0x00130003)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH4 */
+
+ Device(UOH5) {
+ Name(_ADR, 0x00130004)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH5 */
+
+ Device(UEH1) {
+ Name(_ADR, 0x00130005)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UEH1 */
+
+ Device(SBUS) {
+ Name(_ADR, 0x00140000)
+ } /* end SBUS */
+
+ /* Primary (and only) IDE channel */
+ Device(IDEC) {
+ Name(_ADR, 0x00140001)
+ #include "acpi/ide.asl"
+ } /* end IDEC */
+
+ Device(AZHD) {
+ Name(_ADR, 0x00140002)
+ OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
+ Field(AZPD, AnyAcc, NoLock, Preserve) {
+ offset (0x42),
+ NSDI, 1,
+ NSDO, 1,
+ NSEN, 1,
+ offset (0x44),
+ IPCR, 4,
+ offset (0x54),
+ PWST, 2,
+ , 6,
+ PMEB, 1,
+ , 6,
+ PMST, 1,
+ offset (0x62),
+ MMCR, 1,
+ offset (0x64),
+ MMLA, 32,
+ offset (0x68),
+ MMHA, 32,
+ offset (0x6C),
+ MMDT, 16,
+ }
+
+ Method(_INI) {
+ If(LEqual(OSTP,3)){ /* If we are running Linux */
+ Store(zero, NSEN)
+ Store(one, NSDO)
+ Store(one, NSDI)
+ }
+ }
+ } /* end AZHD */
+
+ Device(LIBR) {
+ Name(_ADR, 0x00140003)
+ /* Method(_INI) {
+ * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
+ } */ /* End Method(_SB.SBRDG._INI) */
+
+ /* Real Time Clock Device */
+ Device(RTC0) {
+ Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){8}
+ IO(Decode16,0x0070, 0x0070, 0, 2)
+ /* IO(Decode16,0x0070, 0x0070, 0, 4) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
+
+ Device(TMR) { /* Timer */
+ Name(_HID,EISAID("PNP0100")) /* System Timer */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){0}
+ IO(Decode16, 0x0040, 0x0040, 0, 4)
+ /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
+
+ Device(SPKR) { /* Speaker */
+ Name(_HID,EISAID("PNP0800")) /* AT style speaker */
+ Name(_CRS, ResourceTemplate() {
+ IO(Decode16, 0x0061, 0x0061, 0, 1)
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
+
+ Device(PIC) {
+ Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){2}
+ IO(Decode16,0x0020, 0x0020, 0, 2)
+ IO(Decode16,0x00A0, 0x00A0, 0, 2)
+ /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
+ /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
+
+ Device(MAD) { /* 8257 DMA */
+ Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
+ Name(_CRS, ResourceTemplate() {
+ DMA(Compatibility,BusMaster,Transfer8){4}
+ IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
+ IO(Decode16, 0x0081, 0x0081, 0x10, 0x03)
+ IO(Decode16, 0x0087, 0x0087, 0x10, 0x01)
+ IO(Decode16, 0x0089, 0x0089, 0x10, 0x03)
+ IO(Decode16, 0x008F, 0x008F, 0x10, 0x01)
+ IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
+ }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
+ } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
+
+ Device(COPR) {
+ Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
+ Name(_CRS, ResourceTemplate() {
+ IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
+ IRQNoFlags(){13}
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+
+ Device(HPTM) {
+ Name(_HID,EISAID("PNP0103"))
+ Name(CRS,ResourceTemplate() {
+ Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
+ })
+ Method(_STA, 0) {
+ Return(0x0F) /* sata is visible */
+ }
+ Method(_CRS, 0) {
+ CreateDwordField(CRS, ^HPT._BAS, HPBA)
+ Store(HPBA, HPBA)
+ Return(CRS)
+ }
+ } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+ } /* end LIBR */
+
+ Device(HPBR) {
+ Name(_ADR, 0x00140004)
+ } /* end HostPciBr */
+
+ Device(ACAD) {
+ Name(_ADR, 0x00140005)
+ } /* end Ac97audio */
+
+ Device(ACMD) {
+ Name(_ADR, 0x00140006)
+ } /* end Ac97modem */
+
+ /* ITE IT8712F Support */
+ OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
+ Field (IOID, ByteAcc, NoLock, Preserve)
+ {
+ SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */
+ }
+
+ IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x07),
+ LDN, 8, /* Logical Device Number */
+ Offset (0x20),
+ CID1, 8, /* Chip ID Byte 1, 0x87 */
+ CID2, 8, /* Chip ID Byte 2, 0x12 */
+ Offset (0x30),
+ ACTR, 8, /* Function activate */
+ Offset (0xF0),
+ APC0, 8, /* APC/PME Event Enable Register */
+ APC1, 8, /* APC/PME Status Register */
+ APC2, 8, /* APC/PME Control Register 1 */
+ APC3, 8, /* Environment Controller Special Configuration Register */
+ APC4, 8 /* APC/PME Control Register 2 */
+ }
+
+ /* Enter the IT8712F MB PnP Mode */
+ Method (EPNP)
+ {
+ Store(0x87, SIOI)
+ Store(0x01, SIOI)
+ Store(0x55, SIOI)
+ Store(0x55, SIOI) /* IT8712F magic number */
+ }
+ /* Exit the IT8712F MB PnP Mode */
+ Method (XPNP)
+ {
+ Store (0x02, SIOI)
+ Store (0x02, SIOD)
+ }
+
+ /*
+ * Keyboard PME is routed to SB600 Gevent3. We can wake
+ * up the system by pressing the key.
+ */
+ Method (SIOS, 1)
+ {
+ /* We only enable KBD PME for S5. */
+ If (LLess (Arg0, 0x05))
+ {
+ EPNP()
+ /* DBGO("IT8712F\n") */
+
+ Store (0x4, LDN)
+ Store (One, ACTR) /* Enable EC */
+ /*
+ Store (0x4, LDN)
+ Store (0x04, APC4)
+ */ /* falling edge. which mode? Not sure. */
+
+ Store (0x4, LDN)
+ Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
+ Store (0x4, LDN)
+ Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
+
+ XPNP()
+ }
+ }
+ Method (SIOW, 1)
+ {
+ EPNP()
+ Store (0x4, LDN)
+ Store (Zero, APC0) /* disable keyboard PME */
+ Store (0x4, LDN)
+ Store (0xFF, APC1) /* clear keyboard PME status */
+ XPNP()
+ }
+
+ Name(CRES, ResourceTemplate() {
+ IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
+
+ WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, /* address granularity */
+ 0x0000, /* range minimum */
+ 0x0CF7, /* range maximum */
+ 0x0000, /* translation */
+ 0x0CF8 /* length */
+ )
+
+ WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, /* address granularity */
+ 0x0D00, /* range minimum */
+ 0xFFFF, /* range maximum */
+ 0x0000, /* translation */
+ 0xF300 /* length */
+ )
+
+ Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
+ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
+ Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
+ Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
+
+ /* DRAM Memory from 1MB to TopMem */
+ Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
+
+ /* BIOS space just below 4GB */
+ DWORDMemory(
+ ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00, /* Granularity */
+ 0x00000000, /* Min */
+ 0x00000000, /* Max */
+ 0x00000000, /* Translation */
+ 0x00000000, /* Max-Min, RLEN */
+ ,,
+ PCBM
+ )
+
+ /* DRAM memory from 4GB to TopMem2 */
+ QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0xFFFFFFFF, /* Granularity */
+ 0x00000000, /* Min */
+ 0x00000000, /* Max */
+ 0x00000000, /* Translation */
+ 0x00000000, /* Max-Min, RLEN */
+ ,,
+ DMHI
+ )
+
+ /* BIOS space just below 16EB */
+ QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0xFFFFFFFF, /* Granularity */
+ 0x00000000, /* Min */
+ 0x00000000, /* Max */
+ 0x00000000, /* Translation */
+ 0x00000000, /* Max-Min, RLEN */
+ ,,
+ PEBM
+ )
+
+ }) /* End Name(_SB.PCI0.CRES) */
+
+ Method(_CRS, 0) {
+ /* DBGO("\\_SB\\PCI0\\_CRS\n") */
+
+ CreateDWordField(CRES, ^EMM1._BAS, EM1B)
+ CreateDWordField(CRES, ^EMM1._LEN, EM1L)
+ CreateDWordField(CRES, ^DMLO._BAS, DMLB)
+ CreateDWordField(CRES, ^DMLO._LEN, DMLL)
+ CreateDWordField(CRES, ^PCBM._MIN, PBMB)
+ CreateDWordField(CRES, ^PCBM._LEN, PBML)
+
+ CreateQWordField(CRES, ^DMHI._MIN, DMHB)
+ CreateQWordField(CRES, ^DMHI._LEN, DMHL)
+ CreateQWordField(CRES, ^PEBM._MIN, EBMB)
+ CreateQWordField(CRES, ^PEBM._LEN, EBML)
+
+ If(LGreater(LOMH, 0xC0000)){
+ Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
+ Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
+ }
+
+ /* Set size of memory from 1MB to TopMem */
+ Subtract(TOM1, 0x100000, DMLL)
+
+ /*
+ * If(LNotEqual(TOM2, 0x00000000)){
+ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
+ * Subtract(TOM2, 0x100000000, DMHL)
+ * }
+ */
+
+ /* If there is no memory above 4GB, put the BIOS just below 4GB */
+ If(LEqual(TOM2, 0x00000000)){
+ Store(PBAD,PBMB) /* Reserve the "BIOS" space */
+ Store(PBLN,PBML)
+ }
+ Else { /* Otherwise, put the BIOS just below 16EB */
+ ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
+ Store(PBLN,EBML)
+ }
+
+ Return(CRES) /* note to change the Name buffer */
+ } /* end of Method(_SB.PCI0._CRS) */
+
+ /*
+ *
+ * FIRST METHOD CALLED UPON BOOT
+ *
+ * 1. If debugging, print current OS and ACPI interpreter.
+ * 2. Get PCI Interrupt routing from ACPI VSM, this
+ * value is based on user choice in BIOS setup.
+ */
+ Method(_INI, 0) {
+ /* DBGO("\\_SB\\_INI\n") */
+ /* DBGO(" DSDT.ASL code from ") */
+ /* DBGO(__DATE__) */
+ /* DBGO(" ") */
+ /* DBGO(__TIME__) */
+ /* DBGO("\n Sleep states supported: ") */
+ /* DBGO("\n") */
+ /* DBGO(" \\_OS=") */
+ /* DBGO(\_OS) */
+ /* DBGO("\n \\_REV=") */
+ /* DBGO(\_REV) */
+ /* DBGO("\n") */
+
+ /* Determine the OS we're running on */
+ CkOT()
+
+ /* On older chips, clear PciExpWakeDisEn */
+ /*if (LLessEqual(\SBRI, 0x13)) {
+ * Store(0,\PWDE)
+ * }
+ */
+ } /* End Method(_SB._INI) */
+ } /* End Device(PCI0) */
+
+ Device(PWRB) { /* Start Power button device */
+ Name(_HID, EISAID("PNP0C0C"))
+ Name(_UID, 0xAA)
+ Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
+ Name(_STA, 0x0B) /* sata is invisible */
+ }
+ } /* End \_SB scope */
+
+ Scope(\_SI) {
+ Method(_SST, 1) {
+ /* DBGO("\\_SI\\_SST\n") */
+ /* DBGO(" New Indicator state: ") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+ }
+ } /* End Scope SI */
+
+ Mutex (SBX0, 0x00)
+ OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
+ Field (SMB0, ByteAcc, NoLock, Preserve) {
+ HSTS, 8, /* SMBUS status */
+ SSTS, 8, /* SMBUS slave status */
+ HCNT, 8, /* SMBUS control */
+ HCMD, 8, /* SMBUS host cmd */
+ HADD, 8, /* SMBUS address */
+ DAT0, 8, /* SMBUS data0 */
+ DAT1, 8, /* SMBUS data1 */
+ BLKD, 8, /* SMBUS block data */
+ SCNT, 8, /* SMBUS slave control */
+ SCMD, 8, /* SMBUS shaow cmd */
+ SEVT, 8, /* SMBUS slave event */
+ SDAT, 8 /* SMBUS slave data */
+ }
+
+ Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
+ Store (0x1E, HSTS)
+ Store (0xFA, Local0)
+ While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
+ Stall (0x64)
+ Decrement (Local0)
+ }
+
+ Return (Local0)
+ }
+
+ Method (SWTC, 1, NotSerialized) {
+ Store (Arg0, Local0)
+ Store (0x07, Local2)
+ Store (One, Local1)
+ While (LEqual (Local1, One)) {
+ Store (And (HSTS, 0x1E), Local3)
+ If (LNotEqual (Local3, Zero)) { /* read sucess */
+ If (LEqual (Local3, 0x02)) {
+ Store (Zero, Local2)
+ }
+
+ Store (Zero, Local1)
+ }
+ Else {
+ If (LLess (Local0, 0x0A)) { /* read failure */
+ Store (0x10, Local2)
+ Store (Zero, Local1)
+ }
+ Else {
+ Sleep (0x0A) /* 10 ms, try again */
+ Subtract (Local0, 0x0A, Local0)
+ }
+ }
+ }
+
+ Return (Local2)
+ }
+
+ Method (SMBR, 3, NotSerialized) {
+ Store (0x07, Local0)
+ If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
+ Store (WCLR (), Local0) /* clear SMBUS status register before read data */
+ If (LEqual (Local0, Zero)) {
+ Release (SBX0)
+ Return (0x0)
+ }
+
+ Store (0x1F, HSTS)
+ Store (Or (ShiftLeft (Arg1, One), One), HADD)
+ Store (Arg2, HCMD)
+ If (LEqual (Arg0, 0x07)) {
+ Store (0x48, HCNT) /* read byte */
+ }
+
+ Store (SWTC (0x03E8), Local1) /* 1000 ms */
+ If (LEqual (Local1, Zero)) {
+ If (LEqual (Arg0, 0x07)) {
+ Store (DAT0, Local0)
+ }
+ }
+ Else {
+ Store (Local1, Local0)
+ }
+
+ Release (SBX0)
+ }
+
+ /* DBGO("the value of SMBusData0 register ") */
+ /* DBGO(Arg2) */
+ /* DBGO(" is ") */
+ /* DBGO(Local0) */
+ /* DBGO("\n") */
+
+ Return (Local0)
+ }
+
+ /* THERMAL */
+ Scope(\_TZ) {
+ Name (KELV, 2732)
+ Name (THOT, 800)
+ Name (TCRT, 850)
+
+ ThermalZone(TZ00) {
+ Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
+ /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
+ Return(Add(0, 2730))
+ }
+ Method(_AL0,0) { /* Returns package of cooling device to turn on */
+ /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
+ Return(Package() {\_TZ.TZ00.FAN0})
+ }
+ Device (FAN0) {
+ Name(_HID, EISAID("PNP0C0B"))
+ Name(_PR0, Package() {PFN0})
+ }
+
+ PowerResource(PFN0,0,0) {
+ Method(_STA) {
+ Store(0xF,Local0)
+ Return(Local0)
+ }
+ Method(_ON) {
+ /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
+ }
+ Method(_OFF) {
+ /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
+ }
+ }
+
+ Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
+ /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
+ Return (Add (THOT, KELV))
+ }
+ Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
+ /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
+ Return (Add (TCRT, KELV))
+ }
+ Method(_TMP,0) { /* return current temp of this zone */
+ Store (SMBR (0x07, 0x4C,, 0x00), Local0)
+ If (LGreater (Local0, 0x10)) {
+ Store (Local0, Local1)
+ }
+ Else {
+ Add (Local0, THOT, Local0)
+ Return (Add (400, KELV))
+ }
+
+ Store (SMBR (0x07, 0x4C, 0x01), Local0)
+ /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
+ /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
+ If (LGreater (Local0, 0x10)) {
+ If (LGreater (Local0, Local1)) {
+ Store (Local0, Local1)
+ }
+
+ Multiply (Local1, 10, Local1)
+ Return (Add (Local1, KELV))
+ }
+ Else {
+ Add (Local0, THOT, Local0)
+ Return (Add (400 , KELV))
+ }
+ } /* end of _TMP */
+ } /* end of TZ00 */
+ }
+}
+/* End of ASL file */
ifdef POST_EVALUATION
-$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.dsl
- iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.dsl
- mv dsdt.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * (C) Copyright 2004 Nick Barker <Nick.Barker9@btinternet.com>
+ * (C) Copyright 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
+ *
+ * ISA portions taken from QEMU acpi-dsdt.dsl.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License v2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1)
+{
+ #include "northbridge/amd/amdk8/amdk8_util.asl"
+
+ /* For now only define 2 power states:
+ * - S0 which is fully on
+ * - S5 which is soft off
+ * Any others would involve declaring the wake up methods.
+ */
+ Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
+ Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
+
+ /* Root of the bus hierarchy */
+ Scope (\_SB)
+ {
+ /* Top PCI device (CK804) */
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A03"))
+ Name (_ADR, 0x00)
+ Name (_UID, 0x00)
+ Name (_BBN, 0x00)
+
+ External (BUSN)
+ External (MMIO)
+ External (PCIO)
+ External (SBLK)
+ External (TOM1)
+ External (HCLK)
+ External (SBDN)
+ External (HCDN)
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ IO (Decode16,
+ 0x0CF8, // Address Range Minimum
+ 0x0CF8, // Address Range Maximum
+ 0x01, // Address Alignment
+ 0x08, // Address Length
+ )
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Address Space Granularity
+ 0x0000, // Address Range Minimum
+ 0x0CF7, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x0CF8, // Address Length
+ ,, , TypeStatic)
+ })
+ /* Methods bellow use SSDT to get actual MMIO regs
+ The IO ports are from 0xd00, optionally an VGA,
+ otherwise the info from MMIO is used.
+ \_SB.GXXX(node, link)
+ */
+ Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
+ Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
+ Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
+ Return (Local3)
+ }
+
+ /* PCI Routing Table */
+ Name (_PRT, Package () {
+ /* Since source is 0, index is IRQ. */
+ /* in ABCD, A=0, B=1, C=2, D=3 */
+ /* SlotFFFF, ABCD, source, index */
+ Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0A }, /* 0x1 SMBUS IRQ 10 */
+ Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 }, /* 0x2 USB IRQ 21 */
+ Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x14 }, /* 0x2 USB IRQ 20 */
+ Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x17 }, /* 0x7 SATA 0 IRQ 23 */
+ Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x16 }, /* 0x8 SATA 1 IRQ 22 */
+ })
+
+ Device (PCIL)
+ {
+ Name (_ADR, 0x00090000)
+ Name (_UID, 0x00)
+ Name (_BBN, 0x01)
+ Name (_PRT, Package () {
+ Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x12 }, /* 1:06 Onboard ATI Rage IRQ 18 */
+ })
+ }
+
+ /* 2:00 PCIe x16 SB IRQ 18 */
+ Device (PE16)
+ {
+ Name (_ADR, 0x000e0000)
+ Name (_UID, 0x00)
+ Name (_BBN, 0x02)
+ Name (_PRT, Package () {
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 }, /* PCIE IRQ16-IRQ19 */
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 },
+ })
+ }
+
+ /* 2:00 PCIe x4 SB IRQ 17 */
+ Device (PE4)
+ {
+ Name (_ADR, 0x000e0000)
+ Name (_UID, 0x00)
+ Name (_BBN, 0x02)
+ Name (_PRT, Package () {
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 }, /* PCIE IRQ16-IRQ19 */
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 },
+ })
+ }
+
+ Device (ISA) {
+ Name (_HID, EisaId ("PNP0A05"))
+ Name (_ADR, 0x00010000)
+
+ /* PS/2 keyboard (seems to be important for WinXP install) */
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+ IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+ IRQNoFlags () {1}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* PS/2 mouse */
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ IRQNoFlags () {12}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* Parallel port */
+ Device (LP0)
+ {
+ Name (_HID, EisaId ("PNP0400")) // "PNP0401" for ECP
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ FixedIO (0x0378, 0x10)
+ IRQNoFlags () {7}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* Floppy controller */
+ Device (FDC0)
+ {
+ Name (_HID, EisaId ("PNP0700"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate () {
+ FixedIO (0x03F0, 0x08)
+ IRQNoFlags () {6}
+ DMA (Compatibility, NotBusMaster, Transfer8) {2}
+ })
+ Return (BUF0)
+ }
+ }
+ }
+ }
+
+ /* AMD 8131 PCI-X tunnel */
+ Device (PCI2)
+ {
+ Name (_HID, EisaId ("PNP0A03"))
+ Name (_ADR, 0x00)
+ Name (_UID, 0x00)
+ Name (_BBN, 0x40)
+
+ /* There is no _PRT Here because I don't know what to
+ * put in it. Since the 8131 has its own APIC, it
+ * isn't wired to other IRQs. */
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ IO (Decode16,
+ 0x0CF8, // Address Range Minimum
+ 0x0CF8, // Address Range Maximum
+ 0x01, // Address Alignment
+ 0x08, // Address Length
+ )
+ })
+ /* Methods bellow use SSDT to get actual MMIO regs
+ The IO ports are from 0xd00, optionally an VGA,
+ otherwise the info from MMIO is used.
+ \_SB.GXXX(node, link)
+ */
+ Concatenate (\_SB.GMEM (0x00, 0x02), BUF0, Local1)
+ Concatenate (\_SB.GIOR (0x00, 0x02), Local1, Local2)
+ Concatenate (\_SB.GWBN (0x00, 0x02), Local2, Local3)
+ Return (Local3)
+ }
+
+ /* Channel A PCIX 133 */
+ Device (PCXF)
+ {
+ Name (_ADR, 0x00000000)
+ Name (_UID, 0x00)
+ Name (_BBN, 0x41)
+ Name (_PRT, Package () {
+ Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 shifted 3*/
+ Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x10 },
+ Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x1a },
+ Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x1b },
+ Package (0x04) { 0x000aFFFF, 0x00, 0x00, 0x1a }, /* PCIE IRQ24-IRQ27 shifted 2*/
+ Package (0x04) { 0x000aFFFF, 0x01, 0x00, 0x1b },
+ Package (0x04) { 0x000aFFFF, 0x02, 0x00, 0x18 },
+ Package (0x04) { 0x000aFFFF, 0x03, 0x00, 0x19 },
+ })
+ }
+
+ /* Channel B PCIX 100 */
+ Device (PCXS) /* Onboard NIC */
+ {
+ Name (_ADR, 0x00010000)
+ Name (_UID, 0x00)
+ Name (_BBN, 0x42)
+ Name (_PRT, Package () {
+ Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x1c }, /* PCIE IRQ28-IRQ31 */
+ Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x1d },
+ Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x1e },
+ Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x1f },
+ })
+ }
+ }
+ }
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * (C) Copyright 2004 Nick Barker <Nick.Barker9@btinternet.com>
- * (C) Copyright 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
- *
- * ISA portions taken from QEMU acpi-dsdt.dsl.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License v2 as published by
- * the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1)
-{
- Include ("../../../../src/northbridge/amd/amdk8/amdk8_util.asl")
-
- /* For now only define 2 power states:
- * - S0 which is fully on
- * - S5 which is soft off
- * Any others would involve declaring the wake up methods.
- */
- Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
- Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
-
- /* Root of the bus hierarchy */
- Scope (\_SB)
- {
- /* Top PCI device (CK804) */
- Device (PCI0)
- {
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00)
- Name (_UID, 0x00)
- Name (_BBN, 0x00)
-
- External (BUSN)
- External (MMIO)
- External (PCIO)
- External (SBLK)
- External (TOM1)
- External (HCLK)
- External (SBDN)
- External (HCDN)
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0CF8, // Address Range Minimum
- 0x0CF8, // Address Range Maximum
- 0x01, // Address Alignment
- 0x08, // Address Length
- )
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x0CF7, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0CF8, // Address Length
- ,, , TypeStatic)
- })
- /* Methods bellow use SSDT to get actual MMIO regs
- The IO ports are from 0xd00, optionally an VGA,
- otherwise the info from MMIO is used.
- \_SB.GXXX(node, link)
- */
- Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
- Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
- Return (Local3)
- }
-
- /* PCI Routing Table */
- Name (_PRT, Package () {
- /* Since source is 0, index is IRQ. */
- /* in ABCD, A=0, B=1, C=2, D=3 */
- /* SlotFFFF, ABCD, source, index */
- Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0A }, /* 0x1 SMBUS IRQ 10 */
- Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 }, /* 0x2 USB IRQ 21 */
- Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x14 }, /* 0x2 USB IRQ 20 */
- Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x17 }, /* 0x7 SATA 0 IRQ 23 */
- Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x16 }, /* 0x8 SATA 1 IRQ 22 */
- })
-
- Device (PCIL)
- {
- Name (_ADR, 0x00090000)
- Name (_UID, 0x00)
- Name (_BBN, 0x01)
- Name (_PRT, Package () {
- Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x12 }, /* 1:06 Onboard ATI Rage IRQ 18 */
- })
- }
-
- /* 2:00 PCIe x16 SB IRQ 18 */
- Device (PE16)
- {
- Name (_ADR, 0x000e0000)
- Name (_UID, 0x00)
- Name (_BBN, 0x02)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 }, /* PCIE IRQ16-IRQ19 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 },
- })
- }
-
- /* 2:00 PCIe x4 SB IRQ 17 */
- Device (PE4)
- {
- Name (_ADR, 0x000e0000)
- Name (_UID, 0x00)
- Name (_BBN, 0x02)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 }, /* PCIE IRQ16-IRQ19 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 },
- })
- }
-
- Device (ISA) {
- Name (_HID, EisaId ("PNP0A05"))
- Name (_ADR, 0x00010000)
-
- /* PS/2 keyboard (seems to be important for WinXP install) */
- Device (KBD)
- {
- Name (_HID, EisaId ("PNP0303"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {1}
- })
- Return (TMP)
- }
- }
-
- /* PS/2 mouse */
- Device (MOU)
- {
- Name (_HID, EisaId ("PNP0F13"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IRQNoFlags () {12}
- })
- Return (TMP)
- }
- }
-
- /* Parallel port */
- Device (LP0)
- {
- Name (_HID, EisaId ("PNP0400")) // "PNP0401" for ECP
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- FixedIO (0x0378, 0x10)
- IRQNoFlags () {7}
- })
- Return (TMP)
- }
- }
-
- /* Floppy controller */
- Device (FDC0)
- {
- Name (_HID, EisaId ("PNP0700"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () {
- FixedIO (0x03F0, 0x08)
- IRQNoFlags () {6}
- DMA (Compatibility, NotBusMaster, Transfer8) {2}
- })
- Return (BUF0)
- }
- }
- }
- }
-
- /* AMD 8131 PCI-X tunnel */
- Device (PCI2)
- {
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00)
- Name (_UID, 0x00)
- Name (_BBN, 0x40)
-
- /* There is no _PRT Here because I don't know what to
- * put in it. Since the 8131 has its own APIC, it
- * isn't wired to other IRQs. */
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0CF8, // Address Range Minimum
- 0x0CF8, // Address Range Maximum
- 0x01, // Address Alignment
- 0x08, // Address Length
- )
- })
- /* Methods bellow use SSDT to get actual MMIO regs
- The IO ports are from 0xd00, optionally an VGA,
- otherwise the info from MMIO is used.
- \_SB.GXXX(node, link)
- */
- Concatenate (\_SB.GMEM (0x00, 0x02), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x00, 0x02), Local1, Local2)
- Concatenate (\_SB.GWBN (0x00, 0x02), Local2, Local3)
- Return (Local3)
- }
-
- /* Channel A PCIX 133 */
- Device (PCXF)
- {
- Name (_ADR, 0x00000000)
- Name (_UID, 0x00)
- Name (_BBN, 0x41)
- Name (_PRT, Package () {
- Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 shifted 3*/
- Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x10 },
- Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x1a },
- Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x1b },
- Package (0x04) { 0x000aFFFF, 0x00, 0x00, 0x1a }, /* PCIE IRQ24-IRQ27 shifted 2*/
- Package (0x04) { 0x000aFFFF, 0x01, 0x00, 0x1b },
- Package (0x04) { 0x000aFFFF, 0x02, 0x00, 0x18 },
- Package (0x04) { 0x000aFFFF, 0x03, 0x00, 0x19 },
- })
- }
-
- /* Channel B PCIX 100 */
- Device (PCXS) /* Onboard NIC */
- {
- Name (_ADR, 0x00010000)
- Name (_UID, 0x00)
- Name (_BBN, 0x42)
- Name (_PRT, Package () {
- Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x1c }, /* PCIE IRQ28-IRQ31 */
- Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x1d },
- Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x1e },
- Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x1f },
- })
- }
- }
- }
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * (C) Copyright 2004 Nick Barker <Nick.Barker9@btinternet.com>
+ * (C) Copyright 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
+ *
+ * ISA portions taken from QEMU acpi-dsdt.dsl.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License v2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1)
+{
+ #include "northbridge/amd/amdk8/amdk8_util.asl"
+
+ /* For now only define 2 power states:
+ * - S0 which is fully on
+ * - S5 which is soft off
+ * Any others would involve declaring the wake up methods.
+ */
+ Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
+ Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
+
+ /* Root of the bus hierarchy */
+ Scope (\_SB)
+ {
+ /* Top PCI device (CK804) */
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A03"))
+ Name (_ADR, 0x00)
+ Name (_UID, 0x00)
+ Name (_BBN, 0x00)
+
+ External (BUSN)
+ External (MMIO)
+ External (PCIO)
+ External (SBLK)
+ External (TOM1)
+ External (HCLK)
+ External (SBDN)
+ External (HCDN)
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ IO (Decode16,
+ 0x0CF8, // Address Range Minimum
+ 0x0CF8, // Address Range Maximum
+ 0x01, // Address Alignment
+ 0x08, // Address Length
+ )
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Address Space Granularity
+ 0x0000, // Address Range Minimum
+ 0x0CF7, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x0CF8, // Address Length
+ ,, , TypeStatic)
+ })
+ /* Methods bellow use SSDT to get actual MMIO regs
+ The IO ports are from 0xd00, optionally an VGA,
+ otherwise the info from MMIO is used.
+ \_SB.GXXX(node, link)
+ */
+ Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
+ Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
+ Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
+ Return (Local3)
+ }
+
+ /* PCI Routing Table */
+ Name (_PRT, Package () {
+ /* Since source is 0, index is IRQ. */
+ /* in ABCD, A=0, B=1, C=2, D=3 */
+ /* SlotFFFF, ABCD, source, index */
+ Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0A }, /* 0x1 SMBUS IRQ 10 */
+ Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 }, /* 0x2 USB IRQ 21 */
+ Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x14 }, /* 0x2 USB IRQ 20 */
+ Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x17 }, /* 0x7 SATA 0 IRQ 23 */
+ Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x16 }, /* 0x8 SATA 1 IRQ 22 */
+ })
+
+ Device (PCIL)
+ {
+ Name (_ADR, 0x00090000)
+ Name (_UID, 0x00)
+ Name (_BBN, 0x01)
+ Name (_PRT, Package () {
+ Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, /* 1:04 PCI 32 IRQ16-IRQ19 */
+ Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 },
+ Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 },
+ Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 },
+ Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x12 }, /* 1:06 Onboard ATI Rage IRQ 18 */
+ Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x12 }, /* 1:08 Onboard Intel NIC IRQ 18 */
+ })
+ }
+
+ /* 2:00 PCIe x16 SB IRQ 18 */
+ Device (PE16)
+ {
+ Name (_ADR, 0x000e0000)
+ Name (_UID, 0x00)
+ Name (_BBN, 0x02)
+ Name (_PRT, Package () {
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 }, /* PCIE IRQ16-IRQ19 */
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 },
+ })
+ }
+
+ /* 2:00 PCIe x4 SB IRQ 17 */
+ Device (PE4)
+ {
+ Name (_ADR, 0x000e0000)
+ Name (_UID, 0x00)
+ Name (_BBN, 0x02)
+ Name (_PRT, Package () {
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 }, /* PCIE IRQ16-IRQ19 */
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 },
+ })
+ }
+
+ Device (ISA) {
+ Name (_HID, EisaId ("PNP0A05"))
+ Name (_ADR, 0x00010000)
+
+ /* PS/2 keyboard (seems to be important for WinXP install) */
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+ IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+ IRQNoFlags () {1}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* PS/2 mouse */
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ IRQNoFlags () {12}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* Parallel port */
+ Device (LP0)
+ {
+ Name (_HID, EisaId ("PNP0400")) // "PNP0401" for ECP
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ FixedIO (0x0378, 0x10)
+ IRQNoFlags () {7}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* Floppy controller */
+ Device (FDC0)
+ {
+ Name (_HID, EisaId ("PNP0700"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate () {
+ FixedIO (0x03F0, 0x08)
+ IRQNoFlags () {6}
+ DMA (Compatibility, NotBusMaster, Transfer8) {2}
+ })
+ Return (BUF0)
+ }
+ }
+ }
+ }
+
+ /* AMD 8131 PCI-X tunnel */
+ Device (PCI2)
+ {
+ Name (_HID, EisaId ("PNP0A03"))
+ Name (_ADR, 0x00)
+ Name (_UID, 0x00)
+ Name (_BBN, 0x40)
+
+ /* There is no _PRT Here because I don't know what to
+ * put in it. Since the 8131 has its own APIC, it
+ * isn't wired to other IRQs. */
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ IO (Decode16,
+ 0x0CF8, // Address Range Minimum
+ 0x0CF8, // Address Range Maximum
+ 0x01, // Address Alignment
+ 0x08, // Address Length
+ )
+ })
+ /* Methods bellow use SSDT to get actual MMIO regs
+ The IO ports are from 0xd00, optionally an VGA,
+ otherwise the info from MMIO is used.
+ \_SB.GXXX(node, link)
+ */
+ Concatenate (\_SB.GMEM (0x00, 0x02), BUF0, Local1)
+ Concatenate (\_SB.GIOR (0x00, 0x02), Local1, Local2)
+ Concatenate (\_SB.GWBN (0x00, 0x02), Local2, Local3)
+ Return (Local3)
+ }
+
+ /* Channel A PCIX 133 */
+ Device (PCXF)
+ {
+ Name (_ADR, 0x00000000)
+ Name (_UID, 0x00)
+ Name (_BBN, 0x41)
+ Name (_PRT, Package () {
+ Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1b }, /* PCIE IRQ24-IRQ27 shifted 3*/
+ Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x18 },
+ Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x19 },
+ Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x1a },
+ Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1a }, /* PCIE IRQ24-IRQ27 shifted 2*/
+ Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1b },
+ Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x18 },
+ Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x19 },
+ })
+ }
+
+ /* Channel B PCIX 100 */
+ Device (PCXS) /* Onboard NIC, SO-DIMM, Slot 4 */
+ {
+ Name (_ADR, 0x00010000)
+ Name (_UID, 0x00)
+ Name (_BBN, 0x42)
+ Name (_PRT, Package () {
+ Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x1c }, /* PCIE IRQ28-IRQ31 */
+ Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x1d },
+ Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x1e },
+ Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x1f },
+ Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x1c }, /* PCIE IRQ28-IRQ31 */
+ Package (0x04) { 0x0007FFFF, 0x01, 0x00, 0x1d },
+ Package (0x04) { 0x0007FFFF, 0x02, 0x00, 0x1e },
+ Package (0x04) { 0x0007FFFF, 0x03, 0x00, 0x1f },
+ Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1d }, /* PCIE IRQ28-IRQ31 shifted 2 */
+ Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1e },
+ Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x1f },
+ Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x1c },
+ })
+ }
+ }
+ }
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * (C) Copyright 2004 Nick Barker <Nick.Barker9@btinternet.com>
- * (C) Copyright 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
- *
- * ISA portions taken from QEMU acpi-dsdt.dsl.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License v2 as published by
- * the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1)
-{
- Include ("../../../../src/northbridge/amd/amdk8/amdk8_util.asl")
-
- /* For now only define 2 power states:
- * - S0 which is fully on
- * - S5 which is soft off
- * Any others would involve declaring the wake up methods.
- */
- Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
- Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
-
- /* Root of the bus hierarchy */
- Scope (\_SB)
- {
- /* Top PCI device (CK804) */
- Device (PCI0)
- {
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00)
- Name (_UID, 0x00)
- Name (_BBN, 0x00)
-
- External (BUSN)
- External (MMIO)
- External (PCIO)
- External (SBLK)
- External (TOM1)
- External (HCLK)
- External (SBDN)
- External (HCDN)
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0CF8, // Address Range Minimum
- 0x0CF8, // Address Range Maximum
- 0x01, // Address Alignment
- 0x08, // Address Length
- )
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x0CF7, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0CF8, // Address Length
- ,, , TypeStatic)
- })
- /* Methods bellow use SSDT to get actual MMIO regs
- The IO ports are from 0xd00, optionally an VGA,
- otherwise the info from MMIO is used.
- \_SB.GXXX(node, link)
- */
- Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
- Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
- Return (Local3)
- }
-
- /* PCI Routing Table */
- Name (_PRT, Package () {
- /* Since source is 0, index is IRQ. */
- /* in ABCD, A=0, B=1, C=2, D=3 */
- /* SlotFFFF, ABCD, source, index */
- Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0A }, /* 0x1 SMBUS IRQ 10 */
- Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 }, /* 0x2 USB IRQ 21 */
- Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x14 }, /* 0x2 USB IRQ 20 */
- Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x17 }, /* 0x7 SATA 0 IRQ 23 */
- Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x16 }, /* 0x8 SATA 1 IRQ 22 */
- })
-
- Device (PCIL)
- {
- Name (_ADR, 0x00090000)
- Name (_UID, 0x00)
- Name (_BBN, 0x01)
- Name (_PRT, Package () {
- Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, /* 1:04 PCI 32 IRQ16-IRQ19 */
- Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 },
- Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x12 }, /* 1:06 Onboard ATI Rage IRQ 18 */
- Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x12 }, /* 1:08 Onboard Intel NIC IRQ 18 */
- })
- }
-
- /* 2:00 PCIe x16 SB IRQ 18 */
- Device (PE16)
- {
- Name (_ADR, 0x000e0000)
- Name (_UID, 0x00)
- Name (_BBN, 0x02)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 }, /* PCIE IRQ16-IRQ19 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 },
- })
- }
-
- /* 2:00 PCIe x4 SB IRQ 17 */
- Device (PE4)
- {
- Name (_ADR, 0x000e0000)
- Name (_UID, 0x00)
- Name (_BBN, 0x02)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 }, /* PCIE IRQ16-IRQ19 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 },
- })
- }
-
- Device (ISA) {
- Name (_HID, EisaId ("PNP0A05"))
- Name (_ADR, 0x00010000)
-
- /* PS/2 keyboard (seems to be important for WinXP install) */
- Device (KBD)
- {
- Name (_HID, EisaId ("PNP0303"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {1}
- })
- Return (TMP)
- }
- }
-
- /* PS/2 mouse */
- Device (MOU)
- {
- Name (_HID, EisaId ("PNP0F13"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IRQNoFlags () {12}
- })
- Return (TMP)
- }
- }
-
- /* Parallel port */
- Device (LP0)
- {
- Name (_HID, EisaId ("PNP0400")) // "PNP0401" for ECP
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- FixedIO (0x0378, 0x10)
- IRQNoFlags () {7}
- })
- Return (TMP)
- }
- }
-
- /* Floppy controller */
- Device (FDC0)
- {
- Name (_HID, EisaId ("PNP0700"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () {
- FixedIO (0x03F0, 0x08)
- IRQNoFlags () {6}
- DMA (Compatibility, NotBusMaster, Transfer8) {2}
- })
- Return (BUF0)
- }
- }
- }
- }
-
- /* AMD 8131 PCI-X tunnel */
- Device (PCI2)
- {
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00)
- Name (_UID, 0x00)
- Name (_BBN, 0x40)
-
- /* There is no _PRT Here because I don't know what to
- * put in it. Since the 8131 has its own APIC, it
- * isn't wired to other IRQs. */
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0CF8, // Address Range Minimum
- 0x0CF8, // Address Range Maximum
- 0x01, // Address Alignment
- 0x08, // Address Length
- )
- })
- /* Methods bellow use SSDT to get actual MMIO regs
- The IO ports are from 0xd00, optionally an VGA,
- otherwise the info from MMIO is used.
- \_SB.GXXX(node, link)
- */
- Concatenate (\_SB.GMEM (0x00, 0x02), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x00, 0x02), Local1, Local2)
- Concatenate (\_SB.GWBN (0x00, 0x02), Local2, Local3)
- Return (Local3)
- }
-
- /* Channel A PCIX 133 */
- Device (PCXF)
- {
- Name (_ADR, 0x00000000)
- Name (_UID, 0x00)
- Name (_BBN, 0x41)
- Name (_PRT, Package () {
- Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1b }, /* PCIE IRQ24-IRQ27 shifted 3*/
- Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x18 },
- Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x19 },
- Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x1a },
- Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1a }, /* PCIE IRQ24-IRQ27 shifted 2*/
- Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1b },
- Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x18 },
- Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x19 },
- })
- }
-
- /* Channel B PCIX 100 */
- Device (PCXS) /* Onboard NIC, SO-DIMM, Slot 4 */
- {
- Name (_ADR, 0x00010000)
- Name (_UID, 0x00)
- Name (_BBN, 0x42)
- Name (_PRT, Package () {
- Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x1c }, /* PCIE IRQ28-IRQ31 */
- Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x1d },
- Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x1e },
- Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x1f },
- Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x1c }, /* PCIE IRQ28-IRQ31 */
- Package (0x04) { 0x0007FFFF, 0x01, 0x00, 0x1d },
- Package (0x04) { 0x0007FFFF, 0x02, 0x00, 0x1e },
- Package (0x04) { 0x0007FFFF, 0x03, 0x00, 0x1f },
- Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1d }, /* PCIE IRQ28-IRQ31 shifted 2 */
- Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1e },
- Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x1f },
- Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x1c },
- })
- }
- }
- }
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * (C) Copyright 2004 Nick Barker <Nick.Barker9@btinternet.com>
+ * (C) Copyright 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
+ *
+ * ISA portions taken from QEMU acpi-dsdt.dsl.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License v2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1)
+{
+ #include "northbridge/amd/amdk8/amdk8_util.asl"
+
+ /* For now only define 2 power states:
+ * - S0 which is fully on
+ * - S5 which is soft off
+ * Any others would involve declaring the wake up methods.
+ */
+ Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
+ Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
+
+ /* Root of the bus hierarchy */
+ Scope (\_SB)
+ {
+ /* Top PCI device (CK804) */
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A03"))
+ Name (_ADR, 0x00)
+ Name (_UID, 0x00)
+ Name (_BBN, 0x00)
+
+ External (BUSN)
+ External (MMIO)
+ External (PCIO)
+ External (SBLK)
+ External (TOM1)
+ External (HCLK)
+ External (SBDN)
+ External (HCDN)
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ IO (Decode16,
+ 0x0CF8, // Address Range Minimum
+ 0x0CF8, // Address Range Maximum
+ 0x01, // Address Alignment
+ 0x08, // Address Length
+ )
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Address Space Granularity
+ 0x0000, // Address Range Minimum
+ 0x0CF7, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x0CF8, // Address Length
+ ,, , TypeStatic)
+ })
+ /* Methods bellow use SSDT to get actual MMIO regs
+ The IO ports are from 0xd00, optionally an VGA,
+ otherwise the info from MMIO is used.
+ \_SB.GXXX(node, link)
+ */
+ Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
+ Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
+ Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
+ Return (Local3)
+ }
+
+ /* PCI Routing Table */
+ Name (_PRT, Package () {
+ /* Since source is 0, index is IRQ. */
+ /* in ABCD, A=0, B=1, C=2, D=3 */
+ /* SlotFFFF, ABCD, source, index */
+ Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0A }, /* 0x1 SMBUS IRQ 10 */
+ Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 }, /* 0x2 USB IRQ 21 */
+ Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x14 }, /* 0x2 USB IRQ 20 */
+ Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x14 }, /* 0x2 AUDIO IRQ 20 */
+ Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x17 }, /* 0x7 SATA 0 IRQ 23 */
+ Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x16 }, /* 0x8 SATA 1 IRQ 22 */
+ Package (0x04) { 0x000aFFFF, 0x00, 0x00, 0x15 }, /* 0xa LAN IRQ 21 */
+ })
+
+ Device (PCIL)
+ {
+ Name (_ADR, 0x00090000)
+ Name (_UID, 0x00)
+ Name (_BBN, 0x01)
+ Name (_PRT, Package () {
+ Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, /* 1:04 PCI 32 IRQ16-IRQ19 */
+ Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 },
+ Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 },
+ Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 },
+ Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x13 }, /* 1:05 IEEE-1394 IRQ 19 */
+ })
+ }
+
+ /* 2:00 PCIe x16 SB IRQ 18 */
+ Device (PE16)
+ {
+ Name (_ADR, 0x000e0000)
+ Name (_UID, 0x00)
+ Name (_BBN, 0x02)
+ Name (_PRT, Package () {
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 }, /* PCIE IRQ16-IRQ19 */
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 },
+ })
+ }
+
+ Device (ISA) {
+ Name (_HID, EisaId ("PNP0A05"))
+ Name (_ADR, 0x00010000)
+
+ /* PS/2 keyboard (seems to be important for WinXP install) */
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+ IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+ IRQNoFlags () {1}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* PS/2 mouse */
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ IRQNoFlags () {12}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* Parallel port */
+ Device (LP0)
+ {
+ Name (_HID, EisaId ("PNP0400")) // "PNP0401" for ECP
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ FixedIO (0x0378, 0x10)
+ IRQNoFlags () {7}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* RTC */
+ Device (RTC)
+ {
+ Name (_HID, EisaId ("PNP0B00"))
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ FixedIO (0x0070, 0x02)
+ IRQNoFlags () {8}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* Floppy controller */
+ Device (FDC0)
+ {
+ Name (_HID, EisaId ("PNP0700"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate () {
+ FixedIO (0x03F0, 0x08)
+ IRQNoFlags () {6}
+ DMA (Compatibility, NotBusMaster, Transfer8) {2}
+ })
+ Return (BUF0)
+ }
+ }
+ }
+ }
+
+ /* CK804 2050 */
+ Device (PCI1)
+ {
+ Name (_HID, EisaId ("PNP0A03"))
+ Name (_ADR, 0x00)
+ Name (_UID, 0x00)
+ Name (_BBN, 0x80)
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ IO (Decode16,
+ 0x0CF8, // Address Range Minimum
+ 0x0CF8, // Address Range Maximum
+ 0x01, // Address Alignment
+ 0x08, // Address Length
+ )
+ })
+ /* Methods bellow use SSDT to get actual MMIO regs
+ The IO ports are from 0xd00, optionally an VGA,
+ otherwise the info from MMIO is used.
+ \_SB.GXXX(node, link)
+ */
+ Concatenate (\_SB.GMEM (0x01, 0x00), BUF0, Local1)
+ Concatenate (\_SB.GIOR (0x01, 0x00), Local1, Local2)
+ Concatenate (\_SB.GWBN (0x01, 0x00), Local2, Local3)
+ Return (Local3)
+ }
+
+ /* PCI Routing Table for this root bus */
+ Name (_PRT, Package () {
+ /* Since source is 0, index is IRQ. */
+ /* in ABCD, A=0, B=1, C=2, D=3 */
+ /* SlotFFFF, ABCD, source, index */
+ Package (0x04) { 0x000aFFFF, 0x00, 0x00, 0x35 }, /* 0xa LAN IRQ 53 */
+ })
+
+ /* PCIe x16 SB2 IRQ 18 */
+ Device (PE16)
+ {
+ Name (_ADR, 0x000e0000)
+ Name (_UID, 0x00)
+ Name (_BBN, 0x81)
+ Name (_PRT, Package () {
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x32 }, /* PCIE IRQ48-IRQ51 */
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x33 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x30 },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x31 },
+ })
+ }
+
+ }
+
+ /* AMD 8131 PCI-X tunnel */
+ Device (PCI2)
+ {
+ Name (_HID, EisaId ("PNP0A03"))
+ Name (_ADR, 0x00)
+ Name (_UID, 0x00)
+ Name (_BBN, 0x40)
+
+ /* There is no _PRT Here because I don't know what to
+ * put in it. Since the 8131 has its own APIC, it
+ * isn't wired to other IRQs. */
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ IO (Decode16,
+ 0x0CF8, // Address Range Minimum
+ 0x0CF8, // Address Range Maximum
+ 0x01, // Address Alignment
+ 0x08, // Address Length
+ )
+ })
+ /* Methods bellow use SSDT to get actual MMIO regs
+ The IO ports are from 0xd00, optionally an VGA,
+ otherwise the info from MMIO is used.
+ \_SB.GXXX(node, link)
+ */
+ Concatenate (\_SB.GMEM (0x00, 0x02), BUF0, Local1)
+ Concatenate (\_SB.GIOR (0x00, 0x02), Local1, Local2)
+ Concatenate (\_SB.GWBN (0x00, 0x02), Local2, Local3)
+ Return (Local3)
+ }
+
+ /* Channel A PCIX 133 */
+ Device (PCXF)
+ {
+ Name (_ADR, 0x00000000)
+ Name (_UID, 0x00)
+ Name (_BBN, 0x41)
+ Name (_PRT, Package () {
+ Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */
+ Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x19 },
+ Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1a },
+ Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1b },
+ })
+ }
+
+ /* Channel B PCIX 100 */
+ Device (PCXS) /* Slot 4, Onboard SCSI, Slot 5 */
+ {
+ Name (_ADR, 0x00010000)
+ Name (_UID, 0x00)
+ Name (_BBN, 0x42)
+ Name (_PRT, Package () {
+ Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1c }, /* PCIE IRQ28-IRQ31 */
+ Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1d },
+ Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1e },
+ Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1f },
+ Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x1e }, /* PCIE IRQ28-IRQ31 shifted 2 */
+ Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x1f },
+ Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x1c },
+ Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x1d },
+ Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x1d }, /* PCIE IRQ28-IRQ31 shifted 1 */
+ Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x1e },
+ Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x1f },
+ Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x1c },
+ })
+ }
+ }
+ }
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * (C) Copyright 2004 Nick Barker <Nick.Barker9@btinternet.com>
- * (C) Copyright 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
- *
- * ISA portions taken from QEMU acpi-dsdt.dsl.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License v2 as published by
- * the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1)
-{
- Include ("../../../../src/northbridge/amd/amdk8/amdk8_util.asl")
-
- /* For now only define 2 power states:
- * - S0 which is fully on
- * - S5 which is soft off
- * Any others would involve declaring the wake up methods.
- */
- Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
- Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
-
- /* Root of the bus hierarchy */
- Scope (\_SB)
- {
- /* Top PCI device (CK804) */
- Device (PCI0)
- {
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00)
- Name (_UID, 0x00)
- Name (_BBN, 0x00)
-
- External (BUSN)
- External (MMIO)
- External (PCIO)
- External (SBLK)
- External (TOM1)
- External (HCLK)
- External (SBDN)
- External (HCDN)
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0CF8, // Address Range Minimum
- 0x0CF8, // Address Range Maximum
- 0x01, // Address Alignment
- 0x08, // Address Length
- )
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x0CF7, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0CF8, // Address Length
- ,, , TypeStatic)
- })
- /* Methods bellow use SSDT to get actual MMIO regs
- The IO ports are from 0xd00, optionally an VGA,
- otherwise the info from MMIO is used.
- \_SB.GXXX(node, link)
- */
- Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
- Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
- Return (Local3)
- }
-
- /* PCI Routing Table */
- Name (_PRT, Package () {
- /* Since source is 0, index is IRQ. */
- /* in ABCD, A=0, B=1, C=2, D=3 */
- /* SlotFFFF, ABCD, source, index */
- Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0A }, /* 0x1 SMBUS IRQ 10 */
- Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 }, /* 0x2 USB IRQ 21 */
- Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x14 }, /* 0x2 USB IRQ 20 */
- Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x14 }, /* 0x2 AUDIO IRQ 20 */
- Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x17 }, /* 0x7 SATA 0 IRQ 23 */
- Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x16 }, /* 0x8 SATA 1 IRQ 22 */
- Package (0x04) { 0x000aFFFF, 0x00, 0x00, 0x15 }, /* 0xa LAN IRQ 21 */
- })
-
- Device (PCIL)
- {
- Name (_ADR, 0x00090000)
- Name (_UID, 0x00)
- Name (_BBN, 0x01)
- Name (_PRT, Package () {
- Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, /* 1:04 PCI 32 IRQ16-IRQ19 */
- Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 },
- Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x13 }, /* 1:05 IEEE-1394 IRQ 19 */
- })
- }
-
- /* 2:00 PCIe x16 SB IRQ 18 */
- Device (PE16)
- {
- Name (_ADR, 0x000e0000)
- Name (_UID, 0x00)
- Name (_BBN, 0x02)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 }, /* PCIE IRQ16-IRQ19 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 },
- })
- }
-
- Device (ISA) {
- Name (_HID, EisaId ("PNP0A05"))
- Name (_ADR, 0x00010000)
-
- /* PS/2 keyboard (seems to be important for WinXP install) */
- Device (KBD)
- {
- Name (_HID, EisaId ("PNP0303"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {1}
- })
- Return (TMP)
- }
- }
-
- /* PS/2 mouse */
- Device (MOU)
- {
- Name (_HID, EisaId ("PNP0F13"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IRQNoFlags () {12}
- })
- Return (TMP)
- }
- }
-
- /* Parallel port */
- Device (LP0)
- {
- Name (_HID, EisaId ("PNP0400")) // "PNP0401" for ECP
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- FixedIO (0x0378, 0x10)
- IRQNoFlags () {7}
- })
- Return (TMP)
- }
- }
-
- /* RTC */
- Device (RTC)
- {
- Name (_HID, EisaId ("PNP0B00"))
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- FixedIO (0x0070, 0x02)
- IRQNoFlags () {8}
- })
- Return (TMP)
- }
- }
-
- /* Floppy controller */
- Device (FDC0)
- {
- Name (_HID, EisaId ("PNP0700"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () {
- FixedIO (0x03F0, 0x08)
- IRQNoFlags () {6}
- DMA (Compatibility, NotBusMaster, Transfer8) {2}
- })
- Return (BUF0)
- }
- }
- }
- }
-
- /* CK804 2050 */
- Device (PCI1)
- {
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00)
- Name (_UID, 0x00)
- Name (_BBN, 0x80)
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0CF8, // Address Range Minimum
- 0x0CF8, // Address Range Maximum
- 0x01, // Address Alignment
- 0x08, // Address Length
- )
- })
- /* Methods bellow use SSDT to get actual MMIO regs
- The IO ports are from 0xd00, optionally an VGA,
- otherwise the info from MMIO is used.
- \_SB.GXXX(node, link)
- */
- Concatenate (\_SB.GMEM (0x01, 0x00), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x01, 0x00), Local1, Local2)
- Concatenate (\_SB.GWBN (0x01, 0x00), Local2, Local3)
- Return (Local3)
- }
-
- /* PCI Routing Table for this root bus */
- Name (_PRT, Package () {
- /* Since source is 0, index is IRQ. */
- /* in ABCD, A=0, B=1, C=2, D=3 */
- /* SlotFFFF, ABCD, source, index */
- Package (0x04) { 0x000aFFFF, 0x00, 0x00, 0x35 }, /* 0xa LAN IRQ 53 */
- })
-
- /* PCIe x16 SB2 IRQ 18 */
- Device (PE16)
- {
- Name (_ADR, 0x000e0000)
- Name (_UID, 0x00)
- Name (_BBN, 0x81)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x32 }, /* PCIE IRQ48-IRQ51 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x33 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x30 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x31 },
- })
- }
-
- }
-
- /* AMD 8131 PCI-X tunnel */
- Device (PCI2)
- {
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00)
- Name (_UID, 0x00)
- Name (_BBN, 0x40)
-
- /* There is no _PRT Here because I don't know what to
- * put in it. Since the 8131 has its own APIC, it
- * isn't wired to other IRQs. */
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0CF8, // Address Range Minimum
- 0x0CF8, // Address Range Maximum
- 0x01, // Address Alignment
- 0x08, // Address Length
- )
- })
- /* Methods bellow use SSDT to get actual MMIO regs
- The IO ports are from 0xd00, optionally an VGA,
- otherwise the info from MMIO is used.
- \_SB.GXXX(node, link)
- */
- Concatenate (\_SB.GMEM (0x00, 0x02), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x00, 0x02), Local1, Local2)
- Concatenate (\_SB.GWBN (0x00, 0x02), Local2, Local3)
- Return (Local3)
- }
-
- /* Channel A PCIX 133 */
- Device (PCXF)
- {
- Name (_ADR, 0x00000000)
- Name (_UID, 0x00)
- Name (_BBN, 0x41)
- Name (_PRT, Package () {
- Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */
- Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x19 },
- Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1a },
- Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1b },
- })
- }
-
- /* Channel B PCIX 100 */
- Device (PCXS) /* Slot 4, Onboard SCSI, Slot 5 */
- {
- Name (_ADR, 0x00010000)
- Name (_UID, 0x00)
- Name (_BBN, 0x42)
- Name (_PRT, Package () {
- Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1c }, /* PCIE IRQ28-IRQ31 */
- Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1d },
- Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1e },
- Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1f },
- Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x1e }, /* PCIE IRQ28-IRQ31 shifted 2 */
- Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x1f },
- Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x1c },
- Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x1d },
- Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x1d }, /* PCIE IRQ28-IRQ31 shifted 1 */
- Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x1e },
- Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x1f },
- Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x1c },
- })
- }
- }
- }
-}
ifdef POST_EVALUATION
-$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
- iasl -p $(obj)/dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
- mv $(obj)/dsdt.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
$(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c -o $@
ifdef POST_EVALUATION
-$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
- iasl -p $(obj)/dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
- mv $(obj)/dsdt.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
$(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c -o $@
ifdef POST_EVALUATION
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
-$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
- iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
- mv dsdt.hex $@
-
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
ifdef POST_EVALUATION
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
-$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
- iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
- mv dsdt.hex $@
-
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
--- /dev/null
+/*
+ * Minimalist ACPI DSDT table for EPIA-N / NL
+ * Basic description of PCI Interrupt Assignments.
+ * This is expected to be included into _SB.PCI0 namespace
+ * (C) Copyright 2009 Jon Harrison <jon.harrison@blueyonder.co.uk>
+ *
+ */
+
+ /* PCI PnP Routing Links */
+
+ /* Define how interrupt Link A is plumbed in */
+ Device (LNKA)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x01)
+ /* Status - always return ready */
+ Method (_STA, 0, NotSerialized)
+ {
+ /* See If Coreboot has allocated INTA# */
+ And (PIRA, 0xF0, Local0)
+ If (LEqual (Local0, 0x00))
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (BUFA, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared, )
+ {3,4,6,7,10,11,12}
+ })
+ Return (BUFA)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUFA, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared, _Y07)
+ {}
+ })
+ /* Read the Binary Encoded Field and Map this */
+ /* onto the bitwise _INT field in the IRQ descriptor */
+ /* See ACPI Spec for detail of _IRQ Descriptor */
+ CreateByteField (BUFA, \_SB.PCI0.LNKA._CRS._Y07._INT, IRA1)
+ CreateByteField (BUFA, 0x02, IRA2)
+ Store (0x00, Local3)
+ Store (0x00, Local4)
+ And (PIRA, 0xF0, Local1)
+ ShiftRight (Local1, 0x04, Local1)
+ If (LNotEqual (Local1, 0x00))
+ {
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local2)
+ ShiftLeft (One, Local2, Local4)
+ }
+ Else
+ {
+ If (LGreater (Local1, 0x00))
+ {
+ ShiftLeft (One, Local1, Local3)
+ }
+ }
+
+ Store (Local3, IRA1)
+ Store (Local4, IRA2)
+ }
+ Return (BUFA)
+ }
+
+ /* Set Resources - dummy function to keep Linux ACPI happy
+ * Linux is more than happy not to tinker with irq
+ * assignments as long as the CRS and STA functions
+ * return good values
+ */
+ Method (_SRS, 1, NotSerialized) {}
+ /* Disable - Set PnP Routing Reg to 0 */
+ Method (_DIS, 0, NotSerialized )
+ {
+ And (PIRA, 0x0F, PIRA)
+ }
+ } // End of LNKA
+
+ Device (LNKB)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x02)
+ Method (_STA, 0, NotSerialized)
+ {
+ /* See If Coreboot has allocated INTB# */
+ And (PIBC, 0x0F, Local0)
+ If (LEqual (Local0, 0x00))
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (BUFB, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared, )
+ {3,4,6,7,10,11,12}
+ })
+ Return (BUFB)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUFB, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared, _Y08)
+ {}
+ })
+ /* Read the Binary Encoded Field and Map this */
+ /* onto the bitwise _INT field in the IRQ descriptor */
+ /* See ACPI Spec for detail of _IRQ Descriptor */
+ CreateByteField (BUFB, \_SB.PCI0.LNKB._CRS._Y08._INT, IRB1)
+ CreateByteField (BUFB, 0x02, IRB2)
+ Store (0x00, Local3)
+ Store (0x00, Local4)
+ And (PIBC, 0x0F, Local1)
+ If (LNotEqual (Local1, 0x00))
+ {
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local2)
+ ShiftLeft (One, Local2, Local4)
+ }
+ Else
+ {
+ If (LGreater (Local1, 0x00))
+ {
+ ShiftLeft (One, Local1, Local3)
+ }
+ }
+
+ Store (Local3, IRB1)
+ Store (Local4, IRB2)
+ }
+ Return (BUFB)
+ }
+
+ /* Set Resources - dummy function to keep Linux ACPI happy
+ * Linux is more than happy not to tinker with irq
+ * assignments as long as the CRS and STA functions
+ * return good values
+ */
+ Method (_SRS, 1, NotSerialized) {}
+ /* Disable - Set PnP Routing Reg to 0 */
+ Method (_DIS, 0, NotSerialized )
+ {
+ And (PIBC, 0xF0, PIBC)
+ }
+
+ } // End of LNKB
+
+ Device (LNKC)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x03)
+ Method (_STA, 0, NotSerialized)
+ {
+ /* See If Coreboot has allocated INTC# */
+ And (PIBC, 0xF0, Local0)
+ If (LEqual (Local0, 0x00))
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (BUFC, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared, )
+ {3,4,6,7,10,11,12}
+ })
+ Return (BUFC)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUFC, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared, _Y09)
+ {}
+ })
+ /* Read the Binary Encoded Field and Map this */
+ /* onto the bitwise _INT field in the IRQ descriptor */
+ /* See ACPI Spec for detail of _IRQ Descriptor */
+ CreateByteField (BUFC, \_SB.PCI0.LNKC._CRS._Y09._INT, IRC1)
+ CreateByteField (BUFC, 0x02, IRC2)
+ Store (0x00, Local3)
+ Store (0x00, Local4)
+ And (PIBC, 0xF0, Local1)
+ ShiftRight (Local1, 0x04, Local1)
+ If (LNotEqual (Local1, 0x00))
+ {
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local2)
+ ShiftLeft (One, Local2, Local4)
+ }
+ Else
+ {
+ If (LGreater (Local1, 0x00))
+ {
+ ShiftLeft (One, Local1, Local3)
+ }
+ }
+
+ Store (Local3, IRC1)
+ Store (Local4, IRC2)
+ }
+ Return (BUFC)
+ }
+
+ /* Set Resources - dummy function to keep Linux ACPI happy
+ * Linux is more than happy not to tinker with irq
+ * assignments as long as the CRS and STA functions
+ * return good values
+ */
+ Method (_SRS, 1, NotSerialized) {}
+ /* Disable - Set PnP Routing Reg to 0 */
+ Method (_DIS, 0, NotSerialized )
+ {
+ And (PIBC, 0x0F, PIBC)
+ }
+
+} // End of LNKC
+
+Device (LNKD)
+{
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x04)
+ Method (_STA, 0, NotSerialized)
+ {
+ /* See If Coreboot has allocated INTD# */
+ And (PIRD, 0xF0, Local0)
+ If (LEqual (Local0, 0x00))
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (BUFD, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared, )
+ {3,4,6,7,10,11,12}
+ })
+ Return (BUFD)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUFD, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared, _Y0A)
+ {}
+ })
+ /* Read the Binary Encoded Field and Map this */
+ /* onto the bitwise _INT field in the IRQ descriptor */
+ /* See ACPI Spec for detail of _IRQ Descriptor */
+ CreateByteField (BUFD, \_SB.PCI0.LNKD._CRS._Y0A._INT, IRD1)
+ CreateByteField (BUFD, 0x02, IRD2)
+ Store (0x00, Local3)
+ Store (0x00, Local4)
+ And (PIRD, 0xF0, Local1)
+ ShiftRight (Local1, 0x04, Local1)
+ If (LNotEqual (Local1, 0x00))
+ {
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local2)
+ ShiftLeft (One, Local2, Local4)
+ }
+ Else
+ {
+ If (LGreater (Local1, 0x00))
+ {
+ ShiftLeft (One, Local1, Local3)
+ }
+ }
+
+ Store (Local3, IRD1)
+ Store (Local4, IRD2)
+ }
+ Return (BUFD)
+ }
+
+ /* Set Resources - dummy function to keep Linux ACPI happy
+ * Linux is more than happy not to tinker with irq
+ * assignments as long as the CRS and STA functions
+ * return good values
+ */
+ Method (_SRS, 1, NotSerialized) {}
+ /* Disable - Set PnP Routing Reg to 0 */
+ Method (_DIS, 0, NotSerialized )
+ {
+ And (PIRD, 0x0F, PIRD)
+ }
+
+} // End of LNKD
+
+
+/* APIC IRQ Links */
+
+Device (ATAI)
+{
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x05)
+ Method (_STA, 0, NotSerialized)
+ {
+ /* ATFL == 0x02 if SATA Enabled */
+ If (LNotEqual (ATFL, 0x02))
+ {
+ /* Double Check By Reading SATA VID */
+ /* Otherwise Compatibility Mode */
+ If (LNotEqual (\_SB.PCI0.SATA.VID, 0x1106))
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+ Else
+ {
+ /* Serial ATA Enabled Check if PATA is in */
+ /* Compatibility Mode */
+ If (LEqual (\_SB.PCI0.PATA.ENAT, 0x0A))
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (ATAN, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, )
+ {
+ 0x00000014,
+ }
+ })
+ Return (ATAN)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (ATAB, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, _Y10)
+ {
+ 0x00000000,
+ }
+ })
+ CreateByteField (ATAB, \_SB.PCI0.ATAI._CRS._Y10._INT, IRAI)
+ Store (0x14, IRAI)
+ Return (ATAB)
+
+ }
+
+ /* Set Resources - dummy function to keep Linux ACPI happy
+ * Linux is more than happy not to tinker with irq
+ * assignments as long as the CRS and STA functions
+ * return good values
+ */
+ Method (_SRS, 1, NotSerialized) {}
+ /* Disable - dummy function to keep Linux ACPI happy */
+ Method (_DIS, 0, NotSerialized ) {}
+
+} // End of ATA Interface Link
+
+
+Device (USBI)
+{
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x0A)
+ Method (_STA, 0, NotSerialized)
+ {
+ /* Check that at least one of the USB */
+ /* functions is enabled */
+ And (IDEB, 0x37, Local0)
+ If (LEqual (Local0, 0x37))
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (USBB, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, )
+ {
+ 0x00000015,
+ }
+ })
+
+ Return(USBB)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (USBB, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, _Y12)
+ {
+ 0x00000000,
+ }
+ })
+ CreateByteField (USBB, \_SB.PCI0.USBI._CRS._Y12._INT, IRBI)
+ Store (0x15, IRBI)
+ Return (USBB)
+ }
+
+
+ /* Set Resources - dummy function to keep Linux ACPI happy
+ * Linux is more than happy not to tinker with irq
+ * assignments as long as the CRS and STA functions
+ * return good values
+ */
+ Method (_SRS, 1, NotSerialized) {}
+ /* Disable - dummy function to keep Linux ACPI happy */
+ Method (_DIS, 0, NotSerialized ) {}
+}
+
+Device (VT8I)
+{
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x0B)
+ Method (_STA, 0, NotSerialized)
+ {
+ /* Check Whether Sound and/or Modem are Activated */
+ If (LEqual (EAMC, 0x03))
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (A97C, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, )
+ {
+ 0x00000016,
+ }
+ })
+ Return (A97C)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (A97B, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, _Y14)
+ {
+ 0x00000000,
+ }
+ })
+ CreateByteField (A97B, \_SB.PCI0.VT8I._CRS._Y14._INT, IRCI)
+ Store (0x16, IRCI)
+ Return (A97B)
+ }
+
+ /* Set Resources - dummy function to keep Linux ACPI happy
+ * Linux is more than happy not to tinker with irq
+ * assignments as long as the CRS and STA functions
+ * return good values
+ */
+ Method (_SRS, 1, NotSerialized) {}
+ /* Disable - dummy function to keep Linux ACPI happy */
+ Method (_DIS, 0, NotSerialized ) {}
+
+}
+
+
+Device (NICI)
+{
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x0C)
+ Method (_STA, 0, NotSerialized)
+ {
+ /* Check if LAN Function is Enabled */
+ /* Note that LAN Enable Polarity is different */
+ /* from other functions in VT8237R !? */
+ If (LEqual (ELAN, 0x00))
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (NICB, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, )
+ {
+ 0x00000017,
+ }
+ })
+ Return (NICB)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (NICD, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, _Y16)
+ {
+ 0x00000000,
+ }
+ })
+ CreateByteField (NICD, \_SB.PCI0.NICI._CRS._Y16._INT, IRDI)
+ Store (0x17, IRDI)
+ Return (NICD)
+ }
+
+ /* Set Resources - dummy function to keep Linux ACPI happy
+ * Linux is more than happy not to tinker with irq
+ * assignments as long as the CRS and STA functions
+ * return good values
+ */
+ Method (_SRS, 1, NotSerialized) {}
+ /* Disable - dummy function to keep Linux ACPI happy */
+ Method (_DIS, 0, NotSerialized ) {}
+
+
+}
--- /dev/null
+/*
+ * Minimalist ACPI DSDT table for EPIA-N / NL
+ * Basic description of some hardware resources to allow
+ * interrupt assignments to be done. This is expected to be included
+ * into the PATA Device definition in ab_physical.asl
+ * (C) Copyright 2009 Jon Harrison <jon.harrison@blueyonder.co.uk>
+ *
+ */
+
+Name (TIM0, Package (0x07)
+{
+ Package (0x05)
+ {
+ 0x78, 0xB4, 0xF0, 0x017F, 0x0258
+ },
+
+ Package (0x05)
+ {
+ 0x20, 0x22, 0x33, 0x47, 0x5D
+ },
+
+ Package (0x05)
+ {
+ 0x04, 0x03, 0x02, 0x01, 0x00
+ },
+
+ Package (0x04)
+ {
+ 0x02, 0x01, 0x00, 0x00
+ },
+
+ Package (0x07)
+ {
+ 0x78, 0x50, 0x3C, 0x2D, 0x1E, 0x14, 0x0F
+ },
+
+ Package (0x0F)
+ {
+ 0x06, 0x05, 0x04, 0x04, 0x03, 0x03, 0x02, 0x02,
+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,0x00
+ },
+
+ Package (0x07)
+ {
+ 0x0E, 0x08, 0x06, 0x04, 0x02, 0x01, 0x00
+ }
+})
+
+
+/* This method sets up the PATA Timing Control*/
+/* Note that a lot of this is done in the */
+/* Coreboot VT8237R Init code, but this is */
+/* already getting very cluttered with board */
+/* specific code. Using ACPI will allow this */
+/* to be de-cluttered a bit (so long as we're */
+/* running a ACPI Capable OS !!!) */
+
+Method (PMEX, 0, Serialized)
+{
+ If (REGF)
+ {
+ /* Check if these regs are still at defaults */
+ /* Board specific timing improvement if not */
+ /* Already changed */
+ If (LEqual (PMPT, 0xA8))
+ {
+ Store (0x5D, PMPT)
+ }
+
+ If (LEqual (PSPT, 0xA8))
+ {
+ Store (0x5D, PSPT)
+ }
+
+ If (LEqual (SMPT, 0xA8))
+ {
+ Store (0x5D, SMPT)
+ }
+
+ If (LEqual (SSPT, 0xA8))
+ {
+ Store (0x5D, SSPT)
+ }
+
+ }
+}
+
+/* This Method Provides the method that is used to */
+/* Reset ATA Drives to POST reset condition */
+Method (GTF, 4, Serialized)
+{
+ Store (Buffer (0x07)
+ {
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF
+ }, Local1)
+ Store (Buffer (0x07)
+ {
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF
+ }, Local2)
+ CreateByteField (Local1, 0x01, MODE)
+ CreateByteField (Local2, 0x01, UMOD)
+ CreateByteField (Local1, 0x05, PCHA)
+ CreateByteField (Local2, 0x05, UCHA)
+ And (Arg0, 0x03, Local3)
+ If (LEqual (And (Local3, 0x01), 0x01))
+ {
+ Store (0xB0, PCHA)
+ Store (0xB0, UCHA)
+ }
+
+ If (Arg1)
+ {
+ Store (DerefOf (Index (DerefOf (Index (TIM0, 0x05)), Arg2)),
+ UMOD)
+ Or (UMOD, 0x40, UMOD)
+ }
+ Else
+ {
+ Store (Match (DerefOf (Index (TIM0, 0x01)), MEQ, Arg3, MTR,
+ 0x00, 0x00), Local0)
+ Or (0x20, DerefOf (Index (DerefOf (Index (TIM0, 0x03)), Local0
+ )), UMOD)
+ }
+
+ Store (Match (DerefOf (Index (TIM0, 0x01)), MEQ, Arg3, MTR,
+ 0x00, 0x00), Local0)
+ Or (0x08, DerefOf (Index (DerefOf (Index (TIM0, 0x02)), Local0
+ )), MODE)
+ Concatenate (Local1, Local2, Local6)
+ Return (Local6)
+}
+
--- /dev/null
+/*
+ * Minimalist ACPI DSDT table for EPIA-N / NL
+ * Basic description of PCI Interrupt Assignments.
+ * This is expected to be included into _SB.PCI0 namespace
+ * (C) Copyright 2009 Jon Harrison <jon.harrison@blueyonder.co.uk>
+ *
+ */
+
+/* This file provides a PCI Bus Initialisation Method that sets
+ * some flags for use in the interrupt link assignment
+ */
+
+Method (\_SB.PCI0._INI, 0, NotSerialized)
+{
+
+ /* Checking for ATA Interface Enabled */
+ Store (0x00, ATFL)
+ If (LEqual (EIDE, 0x01))
+ {
+ Store (0x02, ATFL)
+ }
+ Else
+ {
+ If (LNotEqual (\_SB.PCI0.PATA.VID, 0x1106))
+ {
+ Store (0x01, ATFL)
+ }
+ }
+
+}
--- /dev/null
+/*
+ * Minimalist ACPI DSDT table for EPIA-N / NL
+ * Basic description of some hardware resources to allow
+ * interrupt assignments to be done. This is expected to be included
+ * into _SB.PCI0 namespace
+ * (C) Copyright 2009 Jon Harrison <jon.harrison@blueyonder.co.uk>
+ *
+ */
+
+
+/* Basic description of the VT8237R LPC Interface
+ * PCI Configuration Space
+ */
+
+Device (VT8R)
+{
+ Name (_ADR, 0x00110000)
+ OperationRegion (USBC, PCI_Config, 0x50, 0x02)
+ Scope (\)
+ {
+ Field (\_SB.PCI0.VT8R.USBC, ByteAcc, NoLock, Preserve)
+ {
+ IDEB, 8
+ }
+ }
+
+ OperationRegion (VTSB, PCI_Config, 0x00, 0xE8)
+ Scope (\)
+ {
+ Field (\_SB.PCI0.VT8R.VTSB, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x02),
+ DEID, 16,
+ Offset (0x2C),
+ ID2C, 8,
+ ID2D, 8,
+ ID2E, 8,
+ ID2F, 8,
+ Offset (0x44),
+ PIRE, 4,
+ PIRF, 4,
+ PIRG, 4,
+ PIRH, 4,
+ POLE, 1,
+ POLF, 1,
+ POLG, 1,
+ POLH, 1,
+ ENR8, 1,
+ Offset (0x50),
+ ESB4, 1,
+ ESB3, 1,
+ ESB2, 1,
+ EIDE, 1,
+ EUSB, 1,
+ ESB1, 1,
+ EAMC, 2,
+ EKBC, 1,
+ KBCC, 1,
+ EPS2, 1,
+ ERTC, 1,
+ ELAN, 1,
+ , 2,
+ USBD, 1,
+ SIRQ, 8,
+ Offset (0x55),
+ PIRA, 8,
+ PIBC, 8,
+ PIRD, 8,
+ Offset (0x75),
+ BSAT, 1,
+ Offset (0x94),
+ PWC1, 2,
+ GPO1, 1,
+ GPO2, 1,
+ GPO3, 1,
+ PLLD, 1
+ }
+ }
+}
+
+/* Basic Description of Serial ATA Interface */
+Device (SATA)
+{
+ Name (_ADR, 0x000F0000)
+ Method (_STA, 0, NotSerialized)
+ {
+ If (LNotEqual (\_SB.PCI0.SATA.VID, 0x1106))
+ {
+ Return (0x00)
+ }
+ Else
+ {
+ If (LEqual (\_SB.PCI0.SATA.CMDR, 0x00))
+ {
+ Return (0x0D)
+ }
+ Else
+ {
+ Return (0x0F)
+ }
+ }
+ }
+
+ OperationRegion (SAPR, PCI_Config, 0x00, 0xC2)
+ Field (SAPR, ByteAcc, NoLock, Preserve)
+ {
+ VID, 16,
+ Offset (0x04),
+ CMDR, 3,
+ Offset (0x3C),
+ IDEI, 8,
+ Offset (0x49),
+ , 6,
+ EPHY, 1
+ }
+}
+
+/* Basic Description of Parallel ATA Interface */
+/* An some initialisation of the interface */
+Device (PATA)
+{
+ Name (_ADR, 0x000F0001)
+ Name (REGF, 0x01)
+ Method (_STA, 0, NotSerialized)
+ {
+ If (LNotEqual (\_SB.PCI0.PATA.VID, 0x1106))
+ {
+ Return (0x00)
+ }
+ Else
+ {
+ PMEX ()
+ /* Check if the Interface is Enabled */
+ If (LEqual (\_SB.PCI0.PATA.CMDR, 0x00))
+ {
+ Return (0x0D)
+ }
+ Else
+ {
+ Return (0x0F)
+ }
+ }
+ }
+
+ /* ACPI Spec says to check that regions are accessible */
+ /* before trying to access them */
+ Method (_REG, 2, NotSerialized)
+ {
+ /* Arg0 = Operating Region (0x02 == PCI_Config) */
+ If (LEqual (Arg0, 0x02))
+ {
+ /* Arg1 = Handler Connection Mode (0x01 == Connect) */
+ Store (Arg1, REGF)
+ }
+ }
+
+ #include "pata_methods.asl"
+
+
+ OperationRegion (PAPR, PCI_Config, 0x00, 0xC2)
+ Field (PAPR, ByteAcc, NoLock, Preserve)
+ {
+ VID, 16,
+ Offset (0x04),
+ CMDR, 3,
+ Offset (0x09),
+ ENAT, 4,
+ Offset (0x3C),
+ IDEI, 8,
+ Offset (0x40),
+ ESCH, 1,
+ EPCH, 1,
+ Offset (0x48),
+ SSPT, 8,
+ SMPT, 8,
+ PSPT, 8,
+ PMPT, 8,
+ Offset (0x50),
+ SSUT, 4,
+ SSCT, 1,
+ SSUE, 3,
+ SMUT, 4,
+ SMCT, 1,
+ SMUE, 3,
+ PSUT, 4,
+ PSCT, 1,
+ PSUE, 3,
+ PMUT, 4,
+ PMCT, 1,
+ PMUE, 3
+ }
+
+
+ Device (CHN0)
+ {
+ Name (_ADR, 0x00)
+ Method (_STA, 0, NotSerialized)
+ {
+ If (LNotEqual (\_SB.PCI0.PATA.EPCH, 0x01))
+ {
+ Return (0x00)
+ }
+ Else
+ {
+ Return (0x0F)
+ }
+ }
+
+ Device (DRV0)
+ {
+ Name (_ADR, 0x00)
+ Method (_GTF, 0, NotSerialized)
+ {
+ Return (GTF (0x00, PMUE, PMUT, PMPT))
+ }
+ }
+
+ Device (DRV1)
+ {
+ Name (_ADR, 0x01)
+ Method (_GTF, 0, NotSerialized)
+ {
+ Return (GTF (0x01, PSUE, PSUT, PSPT))
+ }
+ }
+ }
+
+ Device (CHN1)
+ {
+ Name (_ADR, 0x01)
+ Method (_STA, 0, NotSerialized)
+ {
+ If (LNotEqual (ATFL, 0x02))
+ {
+ If (LEqual (\_SB.PCI0.SATA.EPHY, 0x01))
+ {
+ Return (0x00)
+ }
+ Else
+ {
+ If (LNotEqual (\_SB.PCI0.PATA.ESCH, 0x01))
+ {
+ Return (0x00)
+ }
+ Else
+ {
+ Return (0x0F)
+ }
+ }
+ }
+ Else
+ {
+ If (LEqual (ATFL, 0x02))
+ {
+ If (LNotEqual (\_SB.PCI0.PATA.ESCH, 0x01))
+ {
+ Return (0x00)
+ }
+ Else
+ {
+ Return (0x0F)
+ }
+ }
+ Else
+ {
+ Return(0x00)
+ }
+ }
+ }
+
+ Device (DRV0)
+ {
+ Name (_ADR, 0x00)
+ Method (_GTF, 0, NotSerialized)
+ {
+ Return (GTF (0x02, SMUE, SMUT, SMPT))
+ }
+ }
+
+ Device (DRV1)
+ {
+ Name (_ADR, 0x01)
+ Method (_GTF, 0, NotSerialized)
+ {
+ Return (GTF (0x03, SSUE, SSUT, SSPT))
+ }
+ }
+ }
+} // End of PATA Device
+
+
+/* Implement Basic USB Presence detect and */
+/* Power Management Event mask */
+Device (USB0)
+{
+ Name (_ADR, 0x00100000)
+ Name (_PRW, Package (0x02)
+ {
+ 0x0E,
+ 0x03
+ })
+
+ OperationRegion (U2F0, PCI_Config, 0x00, 0xC2)
+ Field (U2F0, ByteAcc, NoLock, Preserve)
+ {
+ VID, 16,
+ Offset (0x04),
+ CMDR, 3,
+ Offset (0x3C),
+ U0IR, 4,
+ Offset (0x84),
+ ECDX, 2
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ If (LNotEqual (\_SB.PCI0.USB0.VID, 0x1106))
+ {
+ Return (0x00)
+ }
+ Else
+ {
+ If (LEqual (\_SB.PCI0.USB0.CMDR, 0x00))
+ {
+ Return (0x0D)
+ }
+ Else
+ {
+ Return (0x0F)
+ }
+ }
+ }
+}
+
+Device (USB1)
+{
+ Name (_ADR, 0x00100001)
+ Name (_PRW, Package (0x02)
+ {
+ 0x0E,
+ 0x03
+ })
+
+ OperationRegion (U2F1, PCI_Config, 0x00, 0xC2)
+ Field (U2F1, ByteAcc, NoLock, Preserve)
+ {
+ VID, 16,
+ Offset (0x04),
+ CMDR, 3,
+ Offset (0x3C),
+ U1IR, 4,
+ Offset (0x84),
+ ECDX, 2
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ If (LNotEqual (\_SB.PCI0.USB1.VID, 0x1106))
+ {
+ Return (0x00)
+ }
+ Else
+ {
+ If (LEqual (\_SB.PCI0.USB1.CMDR, 0x00))
+ {
+ Return (0x0D)
+ }
+ Else
+ {
+ Return (0x0F)
+ }
+ }
+ }
+}
+
+Device (USB2)
+{
+ Name (_ADR, 0x00100002)
+ Name (_PRW, Package (0x02)
+ {
+ 0x0E,
+ 0x03
+ })
+
+ OperationRegion (U2F2, PCI_Config, 0x00, 0xC2)
+ Field (U2F2, ByteAcc, NoLock, Preserve)
+ {
+ VID, 16,
+ Offset (0x04),
+ CMDR, 3,
+ Offset (0x3C),
+ U2IR, 4,
+ Offset (0x84),
+ ECDX, 2
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ If (LNotEqual (\_SB.PCI0.USB2.VID, 0x1106))
+ {
+ Return (0x00)
+ }
+ Else
+ {
+ If (LEqual (\_SB.PCI0.USB2.CMDR, 0x00))
+ {
+ Return (0x0D)
+ }
+ Else
+ {
+ Return (0x0F)
+ }
+ }
+ }
+}
+
+Device (USB3)
+{
+ Name (_ADR, 0x00100003)
+ Name (_PRW, Package (0x02)
+ {
+ 0x0E,
+ 0x03
+ })
+
+ OperationRegion (U2F3, PCI_Config, 0x00, 0xC2)
+ Field (U2F3, ByteAcc, NoLock, Preserve)
+ {
+ VID, 16,
+ Offset (0x04),
+ CMDR, 3,
+ Offset (0x3C),
+ U3IR, 4,
+ Offset (0x84),
+ ECDX, 2
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ If (LNotEqual (\_SB.PCI0.USB3.VID, 0x1106))
+ {
+ Return (0x00)
+ }
+ Else
+ {
+ If (LEqual (\_SB.PCI0.USB3.CMDR, 0x00))
+ {
+ Return (0x0D)
+ }
+ Else
+ {
+ Return (0x0F)
+ }
+ }
+ }
+}
+
+Device (USB4)
+{
+ Name (_ADR, 0x00100004)
+ Name (_PRW, Package (0x02)
+ {
+ 0x0E,
+ 0x03
+ })
+
+ OperationRegion (U2F4, PCI_Config, 0x00, 0xC2)
+ Field (U2F4, ByteAcc, NoLock, Preserve)
+ {
+ VID, 16,
+ Offset (0x04),
+ CMDR, 3,
+ Offset (0x3C),
+ U4IR, 4,
+ Offset (0x84),
+ ECDX, 2
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ If (LNotEqual (\_SB.PCI0.USB4.VID, 0x1106))
+ {
+ Return (0x00)
+ }
+ Else
+ {
+ If (LEqual (\_SB.PCI0.USB4.CMDR, 0x00))
+ {
+ Return (0x0D)
+ }
+ Else
+ {
+ Return (0x0F)
+ }
+ }
+ }
+}
+
+/* Basic Definition of Ethernet Interface */
+Device (NIC0)
+{
+ Name (_ADR, 0x00120000)
+ Name (_PRW, Package (0x02)
+ {
+ 0x03,
+ 0x05
+ })
+
+ OperationRegion (NIC0, PCI_Config, 0x00, 0xC2)
+ Field (NIC0, ByteAcc, NoLock, Preserve)
+ {
+ VID, 16,
+ Offset (0x04),
+ CMDR, 3,
+ Offset (0x3C),
+ NIIR, 4,
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ If (LNotEqual (\_SB.PCI0.NIC0.VID, 0x1106))
+ {
+ Return (0x00)
+ }
+ Else
+ {
+ If (LEqual (\_SB.PCI0.NIC0.CMDR, 0x00))
+ {
+ Return (0x0D)
+ }
+ Else
+ {
+ Return (0x0F)
+ }
+ }
+ }
+}
+
+/* Very Basic Definition of Sound Controller */
+Device (AC97)
+{
+ Name (_ADR, 0x00110005)
+ Name (_PRW, Package (0x02)
+ {
+ 0x0D,
+ 0x05
+ })
+}
})
/* PCI Devices Included Here */
- Include("sb_physical.asl")
+ #include "acpi/sb_physical.asl"
/* Legacy PNP Devices Defined Here */
})
}
- Include("irq_links.asl")
- Include("pci_init.asl")
+ #include "acpi/irq_links.asl"
+ #include "acpi/pci_init.asl"
} //End of PCI0
+++ /dev/null
-/*
- * Minimalist ACPI DSDT table for EPIA-N / NL
- * Basic description of PCI Interrupt Assignments.
- * This is expected to be included into _SB.PCI0 namespace
- * (C) Copyright 2009 Jon Harrison <jon.harrison@blueyonder.co.uk>
- *
- */
-
- /* PCI PnP Routing Links */
-
- /* Define how interrupt Link A is plumbed in */
- Device (LNKA)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x01)
- /* Status - always return ready */
- Method (_STA, 0, NotSerialized)
- {
- /* See If Coreboot has allocated INTA# */
- And (PIRA, 0xF0, Local0)
- If (LEqual (Local0, 0x00))
- {
- Return (0x09)
- }
- Else
- {
- Return (0x0B)
- }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared, )
- {3,4,6,7,10,11,12}
- })
- Return (BUFA)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared, _Y07)
- {}
- })
- /* Read the Binary Encoded Field and Map this */
- /* onto the bitwise _INT field in the IRQ descriptor */
- /* See ACPI Spec for detail of _IRQ Descriptor */
- CreateByteField (BUFA, \_SB.PCI0.LNKA._CRS._Y07._INT, IRA1)
- CreateByteField (BUFA, 0x02, IRA2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (PIRA, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- If (LNotEqual (Local1, 0x00))
- {
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRA1)
- Store (Local4, IRA2)
- }
- Return (BUFA)
- }
-
- /* Set Resources - dummy function to keep Linux ACPI happy
- * Linux is more than happy not to tinker with irq
- * assignments as long as the CRS and STA functions
- * return good values
- */
- Method (_SRS, 1, NotSerialized) {}
- /* Disable - Set PnP Routing Reg to 0 */
- Method (_DIS, 0, NotSerialized )
- {
- And (PIRA, 0x0F, PIRA)
- }
- } // End of LNKA
-
- Device (LNKB)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x02)
- Method (_STA, 0, NotSerialized)
- {
- /* See If Coreboot has allocated INTB# */
- And (PIBC, 0x0F, Local0)
- If (LEqual (Local0, 0x00))
- {
- Return (0x09)
- }
- Else
- {
- Return (0x0B)
- }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFB, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared, )
- {3,4,6,7,10,11,12}
- })
- Return (BUFB)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFB, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared, _Y08)
- {}
- })
- /* Read the Binary Encoded Field and Map this */
- /* onto the bitwise _INT field in the IRQ descriptor */
- /* See ACPI Spec for detail of _IRQ Descriptor */
- CreateByteField (BUFB, \_SB.PCI0.LNKB._CRS._Y08._INT, IRB1)
- CreateByteField (BUFB, 0x02, IRB2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (PIBC, 0x0F, Local1)
- If (LNotEqual (Local1, 0x00))
- {
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRB1)
- Store (Local4, IRB2)
- }
- Return (BUFB)
- }
-
- /* Set Resources - dummy function to keep Linux ACPI happy
- * Linux is more than happy not to tinker with irq
- * assignments as long as the CRS and STA functions
- * return good values
- */
- Method (_SRS, 1, NotSerialized) {}
- /* Disable - Set PnP Routing Reg to 0 */
- Method (_DIS, 0, NotSerialized )
- {
- And (PIBC, 0xF0, PIBC)
- }
-
- } // End of LNKB
-
- Device (LNKC)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x03)
- Method (_STA, 0, NotSerialized)
- {
- /* See If Coreboot has allocated INTC# */
- And (PIBC, 0xF0, Local0)
- If (LEqual (Local0, 0x00))
- {
- Return (0x09)
- }
- Else
- {
- Return (0x0B)
- }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFC, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared, )
- {3,4,6,7,10,11,12}
- })
- Return (BUFC)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFC, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared, _Y09)
- {}
- })
- /* Read the Binary Encoded Field and Map this */
- /* onto the bitwise _INT field in the IRQ descriptor */
- /* See ACPI Spec for detail of _IRQ Descriptor */
- CreateByteField (BUFC, \_SB.PCI0.LNKC._CRS._Y09._INT, IRC1)
- CreateByteField (BUFC, 0x02, IRC2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (PIBC, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- If (LNotEqual (Local1, 0x00))
- {
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRC1)
- Store (Local4, IRC2)
- }
- Return (BUFC)
- }
-
- /* Set Resources - dummy function to keep Linux ACPI happy
- * Linux is more than happy not to tinker with irq
- * assignments as long as the CRS and STA functions
- * return good values
- */
- Method (_SRS, 1, NotSerialized) {}
- /* Disable - Set PnP Routing Reg to 0 */
- Method (_DIS, 0, NotSerialized )
- {
- And (PIBC, 0x0F, PIBC)
- }
-
-} // End of LNKC
-
-Device (LNKD)
-{
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x04)
- Method (_STA, 0, NotSerialized)
- {
- /* See If Coreboot has allocated INTD# */
- And (PIRD, 0xF0, Local0)
- If (LEqual (Local0, 0x00))
- {
- Return (0x09)
- }
- Else
- {
- Return (0x0B)
- }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFD, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared, )
- {3,4,6,7,10,11,12}
- })
- Return (BUFD)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFD, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared, _Y0A)
- {}
- })
- /* Read the Binary Encoded Field and Map this */
- /* onto the bitwise _INT field in the IRQ descriptor */
- /* See ACPI Spec for detail of _IRQ Descriptor */
- CreateByteField (BUFD, \_SB.PCI0.LNKD._CRS._Y0A._INT, IRD1)
- CreateByteField (BUFD, 0x02, IRD2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (PIRD, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- If (LNotEqual (Local1, 0x00))
- {
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRD1)
- Store (Local4, IRD2)
- }
- Return (BUFD)
- }
-
- /* Set Resources - dummy function to keep Linux ACPI happy
- * Linux is more than happy not to tinker with irq
- * assignments as long as the CRS and STA functions
- * return good values
- */
- Method (_SRS, 1, NotSerialized) {}
- /* Disable - Set PnP Routing Reg to 0 */
- Method (_DIS, 0, NotSerialized )
- {
- And (PIRD, 0x0F, PIRD)
- }
-
-} // End of LNKD
-
-
-/* APIC IRQ Links */
-
-Device (ATAI)
-{
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x05)
- Method (_STA, 0, NotSerialized)
- {
- /* ATFL == 0x02 if SATA Enabled */
- If (LNotEqual (ATFL, 0x02))
- {
- /* Double Check By Reading SATA VID */
- /* Otherwise Compatibility Mode */
- If (LNotEqual (\_SB.PCI0.SATA.VID, 0x1106))
- {
- Return (0x09)
- }
- Else
- {
- Return (0x0B)
- }
- }
- Else
- {
- /* Serial ATA Enabled Check if PATA is in */
- /* Compatibility Mode */
- If (LEqual (\_SB.PCI0.PATA.ENAT, 0x0A))
- {
- Return (0x09)
- }
- Else
- {
- Return (0x0B)
- }
- }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (ATAN, ResourceTemplate ()
- {
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, )
- {
- 0x00000014,
- }
- })
- Return (ATAN)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (ATAB, ResourceTemplate ()
- {
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, _Y10)
- {
- 0x00000000,
- }
- })
- CreateByteField (ATAB, \_SB.PCI0.ATAI._CRS._Y10._INT, IRAI)
- Store (0x14, IRAI)
- Return (ATAB)
-
- }
-
- /* Set Resources - dummy function to keep Linux ACPI happy
- * Linux is more than happy not to tinker with irq
- * assignments as long as the CRS and STA functions
- * return good values
- */
- Method (_SRS, 1, NotSerialized) {}
- /* Disable - dummy function to keep Linux ACPI happy */
- Method (_DIS, 0, NotSerialized ) {}
-
-} // End of ATA Interface Link
-
-
-Device (USBI)
-{
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x0A)
- Method (_STA, 0, NotSerialized)
- {
- /* Check that at least one of the USB */
- /* functions is enabled */
- And (IDEB, 0x37, Local0)
- If (LEqual (Local0, 0x37))
- {
- Return (0x09)
- }
- Else
- {
- Return (0x0B)
- }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (USBB, ResourceTemplate ()
- {
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, )
- {
- 0x00000015,
- }
- })
-
- Return(USBB)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (USBB, ResourceTemplate ()
- {
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, _Y12)
- {
- 0x00000000,
- }
- })
- CreateByteField (USBB, \_SB.PCI0.USBI._CRS._Y12._INT, IRBI)
- Store (0x15, IRBI)
- Return (USBB)
- }
-
-
- /* Set Resources - dummy function to keep Linux ACPI happy
- * Linux is more than happy not to tinker with irq
- * assignments as long as the CRS and STA functions
- * return good values
- */
- Method (_SRS, 1, NotSerialized) {}
- /* Disable - dummy function to keep Linux ACPI happy */
- Method (_DIS, 0, NotSerialized ) {}
-}
-
-Device (VT8I)
-{
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x0B)
- Method (_STA, 0, NotSerialized)
- {
- /* Check Whether Sound and/or Modem are Activated */
- If (LEqual (EAMC, 0x03))
- {
- Return (0x09)
- }
- Else
- {
- Return (0x0B)
- }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (A97C, ResourceTemplate ()
- {
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, )
- {
- 0x00000016,
- }
- })
- Return (A97C)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (A97B, ResourceTemplate ()
- {
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, _Y14)
- {
- 0x00000000,
- }
- })
- CreateByteField (A97B, \_SB.PCI0.VT8I._CRS._Y14._INT, IRCI)
- Store (0x16, IRCI)
- Return (A97B)
- }
-
- /* Set Resources - dummy function to keep Linux ACPI happy
- * Linux is more than happy not to tinker with irq
- * assignments as long as the CRS and STA functions
- * return good values
- */
- Method (_SRS, 1, NotSerialized) {}
- /* Disable - dummy function to keep Linux ACPI happy */
- Method (_DIS, 0, NotSerialized ) {}
-
-}
-
-
-Device (NICI)
-{
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x0C)
- Method (_STA, 0, NotSerialized)
- {
- /* Check if LAN Function is Enabled */
- /* Note that LAN Enable Polarity is different */
- /* from other functions in VT8237R !? */
- If (LEqual (ELAN, 0x00))
- {
- Return (0x09)
- }
- Else
- {
- Return (0x0B)
- }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (NICB, ResourceTemplate ()
- {
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, )
- {
- 0x00000017,
- }
- })
- Return (NICB)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (NICD, ResourceTemplate ()
- {
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, _Y16)
- {
- 0x00000000,
- }
- })
- CreateByteField (NICD, \_SB.PCI0.NICI._CRS._Y16._INT, IRDI)
- Store (0x17, IRDI)
- Return (NICD)
- }
-
- /* Set Resources - dummy function to keep Linux ACPI happy
- * Linux is more than happy not to tinker with irq
- * assignments as long as the CRS and STA functions
- * return good values
- */
- Method (_SRS, 1, NotSerialized) {}
- /* Disable - dummy function to keep Linux ACPI happy */
- Method (_DIS, 0, NotSerialized ) {}
-
-
-}
+++ /dev/null
-/*
- * Minimalist ACPI DSDT table for EPIA-N / NL
- * Basic description of some hardware resources to allow
- * interrupt assignments to be done. This is expected to be included
- * into the PATA Device definition in ab_physical.asl
- * (C) Copyright 2009 Jon Harrison <jon.harrison@blueyonder.co.uk>
- *
- */
-
-Name (TIM0, Package (0x07)
-{
- Package (0x05)
- {
- 0x78, 0xB4, 0xF0, 0x017F, 0x0258
- },
-
- Package (0x05)
- {
- 0x20, 0x22, 0x33, 0x47, 0x5D
- },
-
- Package (0x05)
- {
- 0x04, 0x03, 0x02, 0x01, 0x00
- },
-
- Package (0x04)
- {
- 0x02, 0x01, 0x00, 0x00
- },
-
- Package (0x07)
- {
- 0x78, 0x50, 0x3C, 0x2D, 0x1E, 0x14, 0x0F
- },
-
- Package (0x0F)
- {
- 0x06, 0x05, 0x04, 0x04, 0x03, 0x03, 0x02, 0x02,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,0x00
- },
-
- Package (0x07)
- {
- 0x0E, 0x08, 0x06, 0x04, 0x02, 0x01, 0x00
- }
-})
-
-
-/* This method sets up the PATA Timing Control*/
-/* Note that a lot of this is done in the */
-/* Coreboot VT8237R Init code, but this is */
-/* already getting very cluttered with board */
-/* specific code. Using ACPI will allow this */
-/* to be de-cluttered a bit (so long as we're */
-/* running a ACPI Capable OS !!!) */
-
-Method (PMEX, 0, Serialized)
-{
- If (REGF)
- {
- /* Check if these regs are still at defaults */
- /* Board specific timing improvement if not */
- /* Already changed */
- If (LEqual (PMPT, 0xA8))
- {
- Store (0x5D, PMPT)
- }
-
- If (LEqual (PSPT, 0xA8))
- {
- Store (0x5D, PSPT)
- }
-
- If (LEqual (SMPT, 0xA8))
- {
- Store (0x5D, SMPT)
- }
-
- If (LEqual (SSPT, 0xA8))
- {
- Store (0x5D, SSPT)
- }
-
- }
-}
-
-/* This Method Provides the method that is used to */
-/* Reset ATA Drives to POST reset condition */
-Method (GTF, 4, Serialized)
-{
- Store (Buffer (0x07)
- {
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF
- }, Local1)
- Store (Buffer (0x07)
- {
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF
- }, Local2)
- CreateByteField (Local1, 0x01, MODE)
- CreateByteField (Local2, 0x01, UMOD)
- CreateByteField (Local1, 0x05, PCHA)
- CreateByteField (Local2, 0x05, UCHA)
- And (Arg0, 0x03, Local3)
- If (LEqual (And (Local3, 0x01), 0x01))
- {
- Store (0xB0, PCHA)
- Store (0xB0, UCHA)
- }
-
- If (Arg1)
- {
- Store (DerefOf (Index (DerefOf (Index (TIM0, 0x05)), Arg2)),
- UMOD)
- Or (UMOD, 0x40, UMOD)
- }
- Else
- {
- Store (Match (DerefOf (Index (TIM0, 0x01)), MEQ, Arg3, MTR,
- 0x00, 0x00), Local0)
- Or (0x20, DerefOf (Index (DerefOf (Index (TIM0, 0x03)), Local0
- )), UMOD)
- }
-
- Store (Match (DerefOf (Index (TIM0, 0x01)), MEQ, Arg3, MTR,
- 0x00, 0x00), Local0)
- Or (0x08, DerefOf (Index (DerefOf (Index (TIM0, 0x02)), Local0
- )), MODE)
- Concatenate (Local1, Local2, Local6)
- Return (Local6)
-}
-
+++ /dev/null
-/*
- * Minimalist ACPI DSDT table for EPIA-N / NL
- * Basic description of PCI Interrupt Assignments.
- * This is expected to be included into _SB.PCI0 namespace
- * (C) Copyright 2009 Jon Harrison <jon.harrison@blueyonder.co.uk>
- *
- */
-
-/* This file provides a PCI Bus Initialisation Method that sets
- * some flags for use in the interrupt link assignment
- */
-
-Method (\_SB.PCI0._INI, 0, NotSerialized)
-{
-
- /* Checking for ATA Interface Enabled */
- Store (0x00, ATFL)
- If (LEqual (EIDE, 0x01))
- {
- Store (0x02, ATFL)
- }
- Else
- {
- If (LNotEqual (\_SB.PCI0.PATA.VID, 0x1106))
- {
- Store (0x01, ATFL)
- }
- }
-
-}
+++ /dev/null
-/*
- * Minimalist ACPI DSDT table for EPIA-N / NL
- * Basic description of some hardware resources to allow
- * interrupt assignments to be done. This is expected to be included
- * into _SB.PCI0 namespace
- * (C) Copyright 2009 Jon Harrison <jon.harrison@blueyonder.co.uk>
- *
- */
-
-
-/* Basic description of the VT8237R LPC Interface
- * PCI Configuration Space
- */
-
-Device (VT8R)
-{
- Name (_ADR, 0x00110000)
- OperationRegion (USBC, PCI_Config, 0x50, 0x02)
- Scope (\)
- {
- Field (\_SB.PCI0.VT8R.USBC, ByteAcc, NoLock, Preserve)
- {
- IDEB, 8
- }
- }
-
- OperationRegion (VTSB, PCI_Config, 0x00, 0xE8)
- Scope (\)
- {
- Field (\_SB.PCI0.VT8R.VTSB, ByteAcc, NoLock, Preserve)
- {
- Offset (0x02),
- DEID, 16,
- Offset (0x2C),
- ID2C, 8,
- ID2D, 8,
- ID2E, 8,
- ID2F, 8,
- Offset (0x44),
- PIRE, 4,
- PIRF, 4,
- PIRG, 4,
- PIRH, 4,
- POLE, 1,
- POLF, 1,
- POLG, 1,
- POLH, 1,
- ENR8, 1,
- Offset (0x50),
- ESB4, 1,
- ESB3, 1,
- ESB2, 1,
- EIDE, 1,
- EUSB, 1,
- ESB1, 1,
- EAMC, 2,
- EKBC, 1,
- KBCC, 1,
- EPS2, 1,
- ERTC, 1,
- ELAN, 1,
- , 2,
- USBD, 1,
- SIRQ, 8,
- Offset (0x55),
- PIRA, 8,
- PIBC, 8,
- PIRD, 8,
- Offset (0x75),
- BSAT, 1,
- Offset (0x94),
- PWC1, 2,
- GPO1, 1,
- GPO2, 1,
- GPO3, 1,
- PLLD, 1
- }
- }
-}
-
-/* Basic Description of Serial ATA Interface */
-Device (SATA)
-{
- Name (_ADR, 0x000F0000)
- Method (_STA, 0, NotSerialized)
- {
- If (LNotEqual (\_SB.PCI0.SATA.VID, 0x1106))
- {
- Return (0x00)
- }
- Else
- {
- If (LEqual (\_SB.PCI0.SATA.CMDR, 0x00))
- {
- Return (0x0D)
- }
- Else
- {
- Return (0x0F)
- }
- }
- }
-
- OperationRegion (SAPR, PCI_Config, 0x00, 0xC2)
- Field (SAPR, ByteAcc, NoLock, Preserve)
- {
- VID, 16,
- Offset (0x04),
- CMDR, 3,
- Offset (0x3C),
- IDEI, 8,
- Offset (0x49),
- , 6,
- EPHY, 1
- }
-}
-
-/* Basic Description of Parallel ATA Interface */
-/* An some initialisation of the interface */
-Device (PATA)
-{
- Name (_ADR, 0x000F0001)
- Name (REGF, 0x01)
- Method (_STA, 0, NotSerialized)
- {
- If (LNotEqual (\_SB.PCI0.PATA.VID, 0x1106))
- {
- Return (0x00)
- }
- Else
- {
- PMEX ()
- /* Check if the Interface is Enabled */
- If (LEqual (\_SB.PCI0.PATA.CMDR, 0x00))
- {
- Return (0x0D)
- }
- Else
- {
- Return (0x0F)
- }
- }
- }
-
- /* ACPI Spec says to check that regions are accessible */
- /* before trying to access them */
- Method (_REG, 2, NotSerialized)
- {
- /* Arg0 = Operating Region (0x02 == PCI_Config) */
- If (LEqual (Arg0, 0x02))
- {
- /* Arg1 = Handler Connection Mode (0x01 == Connect) */
- Store (Arg1, REGF)
- }
- }
-
- Include("pata_methods.asl")
-
-
- OperationRegion (PAPR, PCI_Config, 0x00, 0xC2)
- Field (PAPR, ByteAcc, NoLock, Preserve)
- {
- VID, 16,
- Offset (0x04),
- CMDR, 3,
- Offset (0x09),
- ENAT, 4,
- Offset (0x3C),
- IDEI, 8,
- Offset (0x40),
- ESCH, 1,
- EPCH, 1,
- Offset (0x48),
- SSPT, 8,
- SMPT, 8,
- PSPT, 8,
- PMPT, 8,
- Offset (0x50),
- SSUT, 4,
- SSCT, 1,
- SSUE, 3,
- SMUT, 4,
- SMCT, 1,
- SMUE, 3,
- PSUT, 4,
- PSCT, 1,
- PSUE, 3,
- PMUT, 4,
- PMCT, 1,
- PMUE, 3
- }
-
-
- Device (CHN0)
- {
- Name (_ADR, 0x00)
- Method (_STA, 0, NotSerialized)
- {
- If (LNotEqual (\_SB.PCI0.PATA.EPCH, 0x01))
- {
- Return (0x00)
- }
- Else
- {
- Return (0x0F)
- }
- }
-
- Device (DRV0)
- {
- Name (_ADR, 0x00)
- Method (_GTF, 0, NotSerialized)
- {
- Return (GTF (0x00, PMUE, PMUT, PMPT))
- }
- }
-
- Device (DRV1)
- {
- Name (_ADR, 0x01)
- Method (_GTF, 0, NotSerialized)
- {
- Return (GTF (0x01, PSUE, PSUT, PSPT))
- }
- }
- }
-
- Device (CHN1)
- {
- Name (_ADR, 0x01)
- Method (_STA, 0, NotSerialized)
- {
- If (LNotEqual (ATFL, 0x02))
- {
- If (LEqual (\_SB.PCI0.SATA.EPHY, 0x01))
- {
- Return (0x00)
- }
- Else
- {
- If (LNotEqual (\_SB.PCI0.PATA.ESCH, 0x01))
- {
- Return (0x00)
- }
- Else
- {
- Return (0x0F)
- }
- }
- }
- Else
- {
- If (LEqual (ATFL, 0x02))
- {
- If (LNotEqual (\_SB.PCI0.PATA.ESCH, 0x01))
- {
- Return (0x00)
- }
- Else
- {
- Return (0x0F)
- }
- }
- Else
- {
- Return(0x00)
- }
- }
- }
-
- Device (DRV0)
- {
- Name (_ADR, 0x00)
- Method (_GTF, 0, NotSerialized)
- {
- Return (GTF (0x02, SMUE, SMUT, SMPT))
- }
- }
-
- Device (DRV1)
- {
- Name (_ADR, 0x01)
- Method (_GTF, 0, NotSerialized)
- {
- Return (GTF (0x03, SSUE, SSUT, SSPT))
- }
- }
- }
-} // End of PATA Device
-
-
-/* Implement Basic USB Presence detect and */
-/* Power Management Event mask */
-Device (USB0)
-{
- Name (_ADR, 0x00100000)
- Name (_PRW, Package (0x02)
- {
- 0x0E,
- 0x03
- })
-
- OperationRegion (U2F0, PCI_Config, 0x00, 0xC2)
- Field (U2F0, ByteAcc, NoLock, Preserve)
- {
- VID, 16,
- Offset (0x04),
- CMDR, 3,
- Offset (0x3C),
- U0IR, 4,
- Offset (0x84),
- ECDX, 2
- }
-
- Method (_STA, 0, NotSerialized)
- {
- If (LNotEqual (\_SB.PCI0.USB0.VID, 0x1106))
- {
- Return (0x00)
- }
- Else
- {
- If (LEqual (\_SB.PCI0.USB0.CMDR, 0x00))
- {
- Return (0x0D)
- }
- Else
- {
- Return (0x0F)
- }
- }
- }
-}
-
-Device (USB1)
-{
- Name (_ADR, 0x00100001)
- Name (_PRW, Package (0x02)
- {
- 0x0E,
- 0x03
- })
-
- OperationRegion (U2F1, PCI_Config, 0x00, 0xC2)
- Field (U2F1, ByteAcc, NoLock, Preserve)
- {
- VID, 16,
- Offset (0x04),
- CMDR, 3,
- Offset (0x3C),
- U1IR, 4,
- Offset (0x84),
- ECDX, 2
- }
-
- Method (_STA, 0, NotSerialized)
- {
- If (LNotEqual (\_SB.PCI0.USB1.VID, 0x1106))
- {
- Return (0x00)
- }
- Else
- {
- If (LEqual (\_SB.PCI0.USB1.CMDR, 0x00))
- {
- Return (0x0D)
- }
- Else
- {
- Return (0x0F)
- }
- }
- }
-}
-
-Device (USB2)
-{
- Name (_ADR, 0x00100002)
- Name (_PRW, Package (0x02)
- {
- 0x0E,
- 0x03
- })
-
- OperationRegion (U2F2, PCI_Config, 0x00, 0xC2)
- Field (U2F2, ByteAcc, NoLock, Preserve)
- {
- VID, 16,
- Offset (0x04),
- CMDR, 3,
- Offset (0x3C),
- U2IR, 4,
- Offset (0x84),
- ECDX, 2
- }
-
- Method (_STA, 0, NotSerialized)
- {
- If (LNotEqual (\_SB.PCI0.USB2.VID, 0x1106))
- {
- Return (0x00)
- }
- Else
- {
- If (LEqual (\_SB.PCI0.USB2.CMDR, 0x00))
- {
- Return (0x0D)
- }
- Else
- {
- Return (0x0F)
- }
- }
- }
-}
-
-Device (USB3)
-{
- Name (_ADR, 0x00100003)
- Name (_PRW, Package (0x02)
- {
- 0x0E,
- 0x03
- })
-
- OperationRegion (U2F3, PCI_Config, 0x00, 0xC2)
- Field (U2F3, ByteAcc, NoLock, Preserve)
- {
- VID, 16,
- Offset (0x04),
- CMDR, 3,
- Offset (0x3C),
- U3IR, 4,
- Offset (0x84),
- ECDX, 2
- }
-
- Method (_STA, 0, NotSerialized)
- {
- If (LNotEqual (\_SB.PCI0.USB3.VID, 0x1106))
- {
- Return (0x00)
- }
- Else
- {
- If (LEqual (\_SB.PCI0.USB3.CMDR, 0x00))
- {
- Return (0x0D)
- }
- Else
- {
- Return (0x0F)
- }
- }
- }
-}
-
-Device (USB4)
-{
- Name (_ADR, 0x00100004)
- Name (_PRW, Package (0x02)
- {
- 0x0E,
- 0x03
- })
-
- OperationRegion (U2F4, PCI_Config, 0x00, 0xC2)
- Field (U2F4, ByteAcc, NoLock, Preserve)
- {
- VID, 16,
- Offset (0x04),
- CMDR, 3,
- Offset (0x3C),
- U4IR, 4,
- Offset (0x84),
- ECDX, 2
- }
-
- Method (_STA, 0, NotSerialized)
- {
- If (LNotEqual (\_SB.PCI0.USB4.VID, 0x1106))
- {
- Return (0x00)
- }
- Else
- {
- If (LEqual (\_SB.PCI0.USB4.CMDR, 0x00))
- {
- Return (0x0D)
- }
- Else
- {
- Return (0x0F)
- }
- }
- }
-}
-
-/* Basic Definition of Ethernet Interface */
-Device (NIC0)
-{
- Name (_ADR, 0x00120000)
- Name (_PRW, Package (0x02)
- {
- 0x03,
- 0x05
- })
-
- OperationRegion (NIC0, PCI_Config, 0x00, 0xC2)
- Field (NIC0, ByteAcc, NoLock, Preserve)
- {
- VID, 16,
- Offset (0x04),
- CMDR, 3,
- Offset (0x3C),
- NIIR, 4,
- }
-
- Method (_STA, 0, NotSerialized)
- {
- If (LNotEqual (\_SB.PCI0.NIC0.VID, 0x1106))
- {
- Return (0x00)
- }
- Else
- {
- If (LEqual (\_SB.PCI0.NIC0.CMDR, 0x00))
- {
- Return (0x0D)
- }
- Else
- {
- Return (0x0F)
- }
- }
- }
-}
-
-/* Very Basic Definition of Sound Controller */
-Device (AC97)
-{
- Name (_ADR, 0x00110005)
- Name (_PRW, Package (0x02)
- {
- 0x0D,
- 0x05
- })
-}
ifdef POST_EVALUATION
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
-$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
- iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
- mv dsdt.hex $@
-
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
ifdef POST_EVALUATION
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.dsl
- iasl -p dsdt -tc $<
- mv dsdt.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Name (PICM, Package () {
+ // _ADR PIN SRC IDX
+
+ Package () { 0x0003FFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x0003FFFF, 0x01, LNKB, 0x00 },
+ Package () { 0x0003FFFF, 0x02, LNKC, 0x00 },
+ Package () { 0x0003FFFF, 0x03, LNKD, 0x00 },
+
+ Package () { 0x0004FFFF, 0x00, LNKB, 0x00 },
+ Package () { 0x0004FFFF, 0x01, LNKC, 0x00 },
+ Package () { 0x0004FFFF, 0x02, LNKD, 0x00 },
+ Package () { 0x0004FFFF, 0x03, LNKA, 0x00 },
+
+ Package () { 0x0005FFFF, 0x00, LNKC, 0x00 },
+ Package () { 0x0005FFFF, 0x01, LNKD, 0x00 },
+ Package () { 0x0005FFFF, 0x02, LNKA, 0x00 },
+ Package () { 0x0005FFFF, 0x03, LNKB, 0x00 },
+
+ Package () { 0x0006FFFF, 0x00, LNKD, 0x00 },
+ Package () { 0x0006FFFF, 0x01, LNKA, 0x00 },
+ Package () { 0x0006FFFF, 0x02, LNKB, 0x00 },
+ Package () { 0x0006FFFF, 0x03, LNKC, 0x00 },
+
+ Package () { 0x0007FFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x0007FFFF, 0x01, LNKB, 0x00 },
+ Package () { 0x0007FFFF, 0x02, LNKC, 0x00 },
+ Package () { 0x0007FFFF, 0x03, LNKD, 0x00 },
+
+ Package () { 0x0008FFFF, 0x00, LNKB, 0x00 },
+ Package () { 0x0008FFFF, 0x01, LNKC, 0x00 },
+ Package () { 0x0008FFFF, 0x02, LNKD, 0x00 },
+ Package () { 0x0008FFFF, 0x03, LNKA, 0x00 },
+})
+
+Name (APIC, Package () {
+ Package () { 0x0003FFFF, 0x00, 0x00, 0x10 },
+ Package () { 0x0003FFFF, 0x01, 0x00, 0x11 },
+ Package () { 0x0003FFFF, 0x02, 0x00, 0x12 },
+ Package () { 0x0003FFFF, 0x03, 0x00, 0x13 },
+
+ Package () { 0x0004FFFF, 0x00, 0x00, 0x11 },
+ Package () { 0x0004FFFF, 0x01, 0x00, 0x12 },
+ Package () { 0x0004FFFF, 0x02, 0x00, 0x13 },
+ Package () { 0x0004FFFF, 0x03, 0x00, 0x10 },
+
+ Package () { 0x0005FFFF, 0x00, 0x00, 0x12 },
+ Package () { 0x0005FFFF, 0x01, 0x00, 0x13 },
+ Package () { 0x0005FFFF, 0x02, 0x00, 0x10 },
+ Package () { 0x0005FFFF, 0x03, 0x00, 0x11 },
+
+ Package () { 0x0006FFFF, 0x00, 0x00, 0x13 },
+ Package () { 0x0006FFFF, 0x01, 0x00, 0x10 },
+ Package () { 0x0006FFFF, 0x02, 0x00, 0x11 },
+ Package () { 0x0006FFFF, 0x03, 0x00, 0x12 },
+
+ Package () { 0x0007FFFF, 0x00, 0x00, 0x10 },
+ Package () { 0x0007FFFF, 0x01, 0x00, 0x11 },
+ Package () { 0x0007FFFF, 0x02, 0x00, 0x12 },
+ Package () { 0x0007FFFF, 0x03, 0x00, 0x13 },
+
+ Package () { 0x0008FFFF, 0x00, 0x00, 0x11 },
+ Package () { 0x0008FFFF, 0x01, 0x00, 0x12 },
+ Package () { 0x0008FFFF, 0x02, 0x00, 0x13 },
+ Package () { 0x0008FFFF, 0x03, 0x00, 0x10 },
+})
+
+
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Name (PICM, Package () {
+ // _ADR PIN SRC IDX
+
+ Package () { 0x0001FFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x0001FFFF, 0x01, LNKB, 0x00 },
+ Package () { 0x0001FFFF, 0x02, LNKC, 0x00 },
+ Package () { 0x0001FFFF, 0x03, LNKD, 0x00 },
+
+ Package () { 0x0008FFFF, 0x00, LNKB, 0x00 },
+ Package () { 0x0008FFFF, 0x01, LNKC, 0x00 },
+ Package () { 0x0008FFFF, 0x02, LNKD, 0x00 },
+ Package () { 0x0008FFFF, 0x03, LNKA, 0x00 },
+
+ Package () { 0x0009FFFF, 0x00, LNKC, 0x00 },
+ Package () { 0x0009FFFF, 0x01, LNKD, 0x00 },
+ Package () { 0x0009FFFF, 0x02, LNKA, 0x00 },
+ Package () { 0x0009FFFF, 0x03, LNKB, 0x00 },
+
+ Package () { 0x000AFFFF, 0x00, LNKD, 0x00 },
+ Package () { 0x000AFFFF, 0x01, LNKA, 0x00 },
+ Package () { 0x000AFFFF, 0x02, LNKB, 0x00 },
+ Package () { 0x000AFFFF, 0x03, LNKC, 0x00 },
+
+ Package () { 0x000BFFFF, 0x00, LNKD, 0x00 },
+ Package () { 0x000BFFFF, 0x01, LNKA, 0x00 },
+ Package () { 0x000BFFFF, 0x02, LNKB, 0x00 },
+ Package () { 0x000BFFFF, 0x03, LNKC, 0x00 },
+
+ Package () { 0x000CFFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x000CFFFF, 0x01, LNKB, 0x00 },
+ Package () { 0x000CFFFF, 0x02, LNKC, 0x00 },
+ Package () { 0x000CFFFF, 0x03, LNKD, 0x00 },
+
+ Package () { 0x000DFFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x000DFFFF, 0x01, LNKB, 0x00 },
+ Package () { 0x000DFFFF, 0x02, LNKC, 0x00 },
+ Package () { 0x000DFFFF, 0x03, LNKD, 0x00 },
+
+ Package () { 0x000FFFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x000FFFFF, 0x01, LNKB, 0x00 },
+ Package () { 0x000FFFFF, 0x02, LNKC, 0x00 },
+ Package () { 0x000FFFFF, 0x03, LNKD, 0x00 },
+
+ /* USB controller */
+ Package () { 0x0010FFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x0010FFFF, 0x01, LNKB, 0x00 },
+ Package () { 0x0010FFFF, 0x02, LNKC, 0x00 },
+ Package () { 0x0010FFFF, 0x03, LNKD, 0x00 },
+
+ Package () { 0x0011FFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x0011FFFF, 0x01, LNKB, 0x00 },
+ Package () { 0x0011FFFF, 0x02, LNKC, 0x00 },
+ Package () { 0x0011FFFF, 0x03, LNKD, 0x00 },
+
+ Package () { 0x0012FFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x0012FFFF, 0x01, LNKB, 0x00 },
+ Package () { 0x0012FFFF, 0x02, LNKC, 0x00 },
+ Package () { 0x0012FFFF, 0x03, LNKD, 0x00 }
+})
+
+Name (APIC, Package () {
+ Package () { 0x0001FFFF, 0x00, 0x00, 0x10 },
+ Package () { 0x0001FFFF, 0x01, 0x00, 0x11 },
+ Package () { 0x0001FFFF, 0x02, 0x00, 0x12 },
+ Package () { 0x0001FFFF, 0x03, 0x00, 0x13 },
+
+ Package () { 0x0008FFFF, 0x00, 0x00, 0x11 },
+ Package () { 0x0008FFFF, 0x01, 0x00, 0x12 },
+ Package () { 0x0008FFFF, 0x02, 0x00, 0x13 },
+ Package () { 0x0008FFFF, 0x03, 0x00, 0x10 },
+
+ Package () { 0x0009FFFF, 0x00, 0x00, 0x12 },
+ Package () { 0x0009FFFF, 0x01, 0x00, 0x13 },
+ Package () { 0x0009FFFF, 0x02, 0x00, 0x10 },
+ Package () { 0x0009FFFF, 0x03, 0x00, 0x11 },
+
+ Package () { 0x000AFFFF, 0x00, 0x00, 0x13 },
+ Package () { 0x000AFFFF, 0x01, 0x00, 0x10 },
+ Package () { 0x000AFFFF, 0x02, 0x00, 0x11 },
+ Package () { 0x000AFFFF, 0x03, 0x00, 0x12 },
+
+ Package () { 0x000BFFFF, 0x00, 0x00, 0x13 },
+ Package () { 0x000BFFFF, 0x01, 0x00, 0x10 },
+ Package () { 0x000BFFFF, 0x02, 0x00, 0x11 },
+ Package () { 0x000BFFFF, 0x03, 0x00, 0x12 },
+
+ Package () { 0x000CFFFF, 0x00, 0x00, 0x10 },
+ Package () { 0x000CFFFF, 0x01, 0x00, 0x11 },
+ Package () { 0x000CFFFF, 0x02, 0x00, 0x12 },
+ Package () { 0x000CFFFF, 0x03, 0x00, 0x13 },
+
+ Package () { 0x000DFFFF, 0x00, 0x00, 0x10 },
+ Package () { 0x000DFFFF, 0x01, 0x00, 0x11 },
+ Package () { 0x000DFFFF, 0x02, 0x00, 0x12 },
+ Package () { 0x000DFFFF, 0x03, 0x00, 0x13 },
+
+ Package () { 0x000FFFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x000FFFFF, 0x01, LNKA, 0x00 },
+ Package () { 0x000FFFFF, 0x02, LNKA, 0x00 },
+ Package () { 0x000FFFFF, 0x03, LNKA, 0x00 },
+
+ /* USB controller. Hardwired in internal
+ APIC mode, see PM pg. 137,
+ "miscellaneous controls", footnote to
+ "IDE interrupt select" */
+ Package () { 0x0010FFFF, 0x00, 0x00, 0x14 },
+ Package () { 0x0010FFFF, 0x01, 0x00, 0x16 },
+ Package () { 0x0010FFFF, 0x02, 0x00, 0x15 },
+ Package () { 0x0010FFFF, 0x03, 0x00, 0x17 },
+
+ Package () { 0x0011FFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x0011FFFF, 0x01, LNKB, 0x00 },
+ Package () { 0x0011FFFF, 0x02, LNKC, 0x00 },
+ Package () { 0x0011FFFF, 0x03, LNKD, 0x00 },
+
+ Package () { 0x0012FFFF, 0x00, LNKD, 0x00 },
+ Package () { 0x0012FFFF, 0x01, LNKD, 0x00 },
+ Package () { 0x0012FFFF, 0x02, LNKD, 0x00 },
+ Package () { 0x0012FFFF, 0x03, LNKD, 0x00 },
+})
+
+
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001)
+{
+ /*
+ * Define the main processor
+ */
+ Scope (\_PR)
+ {
+ Processor (\_PR.CPU0, 0x00, 0x00000410, 0x06) {}
+ }
+
+ /* For now only define 2 power states:
+ * - S0 which is fully on
+ * - S5 which is soft off
+ * any others would involve declaring the wake up methods
+ */
+ Name (\_S0, Package () {0x00, 0x00, 0x00, 0x00 })
+ Name (\_S5, Package () {0x02, 0x02, 0x00, 0x00 })
+
+ Scope (\) {
+ Name (PICF , 0) // Global flag indicating whether to use PIC or APIC mode
+ Method ( _PIC,1) // The OS is calling this
+ {
+ Store( Arg0 , PICF)
+ }
+ } // end of \ scope
+
+ /* Root of the bus hierarchy */
+ Scope (\_SB)
+ {
+ /* Define how interrupt Link A is plumbed in */
+ Device (LNKA)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x01)
+
+ /* Status - always return ready */
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0B)
+ }
+
+ /* Current Resources - return irq set up in BIOS */
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (CRSP, ResourceTemplate () {
+ IRQ (Level, ActiveLow, Shared) {11}
+ })
+ Name (CRSA, ResourceTemplate () {
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {16}
+ })
+
+ If (LNot (PICF)) {
+ Return (CRSP)
+ } Else {
+ Return (CRSA)
+ }
+ }
+ /* Possible Resources - return the range of irqs
+ * we are using for PCI - only here to keep Linux ACPI
+ * happy
+ */
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (PRSP, ResourceTemplate () {
+ IRQ (Level, ActiveLow, Shared) {3,4,6,7,10,11,12}
+ })
+ Name (PRSA, ResourceTemplate () {
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {16,17,18,19,20,21,22,23}
+ })
+
+ If (LNot (PICF)) {
+ Return (PRSP)
+ } Else {
+ Return (PRSA)
+ }
+
+ }
+ /* Set Resources - dummy function to keep Linux ACPI happy
+ * Linux is more than happy not to tinker with irq
+ * assignments as long as the CRS and STA functions
+ * return good values
+ */
+ Method (_SRS, 1, NotSerialized ) {}
+ /* Disable - dummy function to keep Linux ACPI happy */
+ Method (_DIS, 0, NotSerialized ) {}
+
+ } // End of LNKA
+
+ /* Define how interrupt Link B is plumbed in */
+ Device (LNKB)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x02)
+
+ /* Status - always return ready */
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0B)
+ }
+
+ /* Current Resources - return irq set up in BIOS */
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (CRSP, ResourceTemplate () {
+ IRQ (Level, ActiveLow, Shared) {11}
+ })
+ Name (CRSA, ResourceTemplate () {
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {17}
+ })
+
+ If (LNot (PICF)) {
+ Return (CRSP)
+ } Else {
+ Return (CRSA)
+ }
+ }
+ /* Possible Resources - return the range of irqs
+ * we are using for PCI - only here to keep Linux ACPI
+ * happy
+ */
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (PRSP, ResourceTemplate () {
+ IRQ (Level, ActiveLow, Shared) {3,4,6,7,10,11,12}
+ })
+ Name (PRSA, ResourceTemplate () {
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {16,17,18,19,20,21,22,23}
+ })
+
+ If (LNot (PICF)) {
+ Return (PRSP)
+ } Else {
+ Return (PRSA)
+ }
+
+ }
+
+ /* Set Resources - dummy function to keep Linux ACPI happy
+ * Linux is more than happy not to tinker with irq
+ * assignments as long as the CRS and STA functions
+ * return good values
+ */
+ Method (_SRS, 1, NotSerialized ) {}
+ /* Disable - dummy function to keep Linux ACPI happy */
+ Method (_DIS, 0, NotSerialized ) {}
+
+ } // End of LNKB
+
+ /* Define how interrupt Link C is plumbed in */
+ Device (LNKC)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x03)
+
+ /* Status - always return ready */
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0B)
+ }
+
+ /* Current Resources - return irq set up in BIOS */
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (CRSP, ResourceTemplate () {
+ IRQ (Level, ActiveLow, Shared) {10}
+ })
+ Name (CRSA, ResourceTemplate () {
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {18}
+ })
+
+ If (LNot (PICF)) {
+ Return (CRSP)
+ } Else {
+ Return (CRSA)
+ }
+ }
+ /* Possible Resources - return the range of irqs
+ * we are using for PCI - only here to keep Linux ACPI
+ * happy
+ */
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (PRSP, ResourceTemplate () {
+ IRQ (Level, ActiveLow, Shared) {3,4,6,7,10,11,12}
+ })
+ Name (PRSA, ResourceTemplate () {
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {16,17,18,19,20,21,22,23}
+ })
+
+ If (LNot (PICF)) {
+ Return (PRSP)
+ } Else {
+ Return (PRSA)
+ }
+
+ }
+
+ /* Set Resources - dummy function to keep Linux ACPI happy
+ * Linux is more than happy not to tinker with irq
+ * assignments as long as the CRS and STA functions
+ * return good values
+ */
+ Method (_SRS, 1, NotSerialized ) {}
+ /* Disable - dummy function to keep Linux ACPI happy */
+ Method (_DIS, 0, NotSerialized ) {}
+
+ } // End of LNKC
+
+ /* Define how interrupt Link D is plumbed in */
+ Device (LNKD)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x04)
+
+ /* Status - always return ready */
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0B)
+ }
+
+ /* Current Resources - return irq set up in BIOS */
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (CRSP, ResourceTemplate () {
+ IRQ (Level, ActiveLow, Shared) {10}
+ })
+ Name (CRSA, ResourceTemplate () {
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {19}
+ })
+
+ If (LNot (PICF)) {
+ Return (CRSP)
+ } Else {
+ Return (CRSA)
+ }
+ }
+ /* Possible Resources - return the range of irqs
+ * we are using for PCI - only here to keep Linux ACPI
+ * happy
+ */
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (PRSP, ResourceTemplate () {
+ IRQ (Level, ActiveLow, Shared) {3,4,6,7,10,11,12}
+ })
+ Name (PRSA, ResourceTemplate () {
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {16,17,18,19,20,21,22,23}
+ })
+
+ If (LNot (PICF)) {
+ Return (PRSP)
+ } Else {
+ Return (PRSA)
+ }
+
+ }
+
+ /* Set Resources - dummy function to keep Linux ACPI happy
+ * Linux is more than happy not to tinker with irq
+ * assignments as long as the CRS and STA functions
+ * return good values
+ */
+ Method (_SRS, 1, NotSerialized ) {}
+ /* Disable - dummy function to keep Linux ACPI happy */
+ Method (_DIS, 0, NotSerialized ) {}
+
+ } // End of LNKD
+
+ /* PCI Root Bridge */
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A08"))
+ Name (_CID, EisaId ("PNP0A03"))
+ Name (_ADR, 0x00)
+ Name (_UID, 0x00)
+ Name (_BBN, 0x00)
+
+ // Mainboard specific IRQ routing
+ #include "acpi/irq.asl"
+
+ /* PCI Routing Table */
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LNot (PICF))
+ {
+ Return (PICM)
+ }
+ Else
+ {
+ Return (APIC)
+ }
+ }
+
+ Device (P2PB) /* PCI to PCI bridge */
+ {
+ Name (_ADR, 0x00130001)
+
+ #include "acpi/irq-p2p-bridge.asl"
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LNot (PICF))
+ {
+ Return (PICM)
+ }
+ Else
+ {
+ Return (APIC)
+ }
+ }
+ /* Status - always return ready */
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+ }
+ } // End of PCI0
+ } // End of _SB
+} // End of Definition Block
+
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001)
-{
- /*
- * Define the main processor
- */
- Scope (\_PR)
- {
- Processor (\_PR.CPU0, 0x00, 0x00000410, 0x06) {}
- }
-
- /* For now only define 2 power states:
- * - S0 which is fully on
- * - S5 which is soft off
- * any others would involve declaring the wake up methods
- */
- Name (\_S0, Package () {0x00, 0x00, 0x00, 0x00 })
- Name (\_S5, Package () {0x02, 0x02, 0x00, 0x00 })
-
- Scope (\) {
- Name (PICF , 0) // Global flag indicating whether to use PIC or APIC mode
- Method ( _PIC,1) // The OS is calling this
- {
- Store( Arg0 , PICF)
- }
- } // end of \ scope
-
- /* Root of the bus hierarchy */
- Scope (\_SB)
- {
- /* Define how interrupt Link A is plumbed in */
- Device (LNKA)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x01)
-
- /* Status - always return ready */
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0B)
- }
-
- /* Current Resources - return irq set up in BIOS */
- Method (_CRS, 0, NotSerialized)
- {
- Name (CRSP, ResourceTemplate () {
- IRQ (Level, ActiveLow, Shared) {11}
- })
- Name (CRSA, ResourceTemplate () {
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {16}
- })
-
- If (LNot (PICF)) {
- Return (CRSP)
- } Else {
- Return (CRSA)
- }
- }
- /* Possible Resources - return the range of irqs
- * we are using for PCI - only here to keep Linux ACPI
- * happy
- */
- Method (_PRS, 0, NotSerialized)
- {
- Name (PRSP, ResourceTemplate () {
- IRQ (Level, ActiveLow, Shared) {3,4,6,7,10,11,12}
- })
- Name (PRSA, ResourceTemplate () {
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {16,17,18,19,20,21,22,23}
- })
-
- If (LNot (PICF)) {
- Return (PRSP)
- } Else {
- Return (PRSA)
- }
-
- }
- /* Set Resources - dummy function to keep Linux ACPI happy
- * Linux is more than happy not to tinker with irq
- * assignments as long as the CRS and STA functions
- * return good values
- */
- Method (_SRS, 1, NotSerialized ) {}
- /* Disable - dummy function to keep Linux ACPI happy */
- Method (_DIS, 0, NotSerialized ) {}
-
- } // End of LNKA
-
- /* Define how interrupt Link B is plumbed in */
- Device (LNKB)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x02)
-
- /* Status - always return ready */
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0B)
- }
-
- /* Current Resources - return irq set up in BIOS */
- Method (_CRS, 0, NotSerialized)
- {
- Name (CRSP, ResourceTemplate () {
- IRQ (Level, ActiveLow, Shared) {11}
- })
- Name (CRSA, ResourceTemplate () {
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {17}
- })
-
- If (LNot (PICF)) {
- Return (CRSP)
- } Else {
- Return (CRSA)
- }
- }
- /* Possible Resources - return the range of irqs
- * we are using for PCI - only here to keep Linux ACPI
- * happy
- */
- Method (_PRS, 0, NotSerialized)
- {
- Name (PRSP, ResourceTemplate () {
- IRQ (Level, ActiveLow, Shared) {3,4,6,7,10,11,12}
- })
- Name (PRSA, ResourceTemplate () {
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {16,17,18,19,20,21,22,23}
- })
-
- If (LNot (PICF)) {
- Return (PRSP)
- } Else {
- Return (PRSA)
- }
-
- }
-
- /* Set Resources - dummy function to keep Linux ACPI happy
- * Linux is more than happy not to tinker with irq
- * assignments as long as the CRS and STA functions
- * return good values
- */
- Method (_SRS, 1, NotSerialized ) {}
- /* Disable - dummy function to keep Linux ACPI happy */
- Method (_DIS, 0, NotSerialized ) {}
-
- } // End of LNKB
-
- /* Define how interrupt Link C is plumbed in */
- Device (LNKC)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x03)
-
- /* Status - always return ready */
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0B)
- }
-
- /* Current Resources - return irq set up in BIOS */
- Method (_CRS, 0, NotSerialized)
- {
- Name (CRSP, ResourceTemplate () {
- IRQ (Level, ActiveLow, Shared) {10}
- })
- Name (CRSA, ResourceTemplate () {
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {18}
- })
-
- If (LNot (PICF)) {
- Return (CRSP)
- } Else {
- Return (CRSA)
- }
- }
- /* Possible Resources - return the range of irqs
- * we are using for PCI - only here to keep Linux ACPI
- * happy
- */
- Method (_PRS, 0, NotSerialized)
- {
- Name (PRSP, ResourceTemplate () {
- IRQ (Level, ActiveLow, Shared) {3,4,6,7,10,11,12}
- })
- Name (PRSA, ResourceTemplate () {
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {16,17,18,19,20,21,22,23}
- })
-
- If (LNot (PICF)) {
- Return (PRSP)
- } Else {
- Return (PRSA)
- }
-
- }
-
- /* Set Resources - dummy function to keep Linux ACPI happy
- * Linux is more than happy not to tinker with irq
- * assignments as long as the CRS and STA functions
- * return good values
- */
- Method (_SRS, 1, NotSerialized ) {}
- /* Disable - dummy function to keep Linux ACPI happy */
- Method (_DIS, 0, NotSerialized ) {}
-
- } // End of LNKC
-
- /* Define how interrupt Link D is plumbed in */
- Device (LNKD)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x04)
-
- /* Status - always return ready */
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0B)
- }
-
- /* Current Resources - return irq set up in BIOS */
- Method (_CRS, 0, NotSerialized)
- {
- Name (CRSP, ResourceTemplate () {
- IRQ (Level, ActiveLow, Shared) {10}
- })
- Name (CRSA, ResourceTemplate () {
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {19}
- })
-
- If (LNot (PICF)) {
- Return (CRSP)
- } Else {
- Return (CRSA)
- }
- }
- /* Possible Resources - return the range of irqs
- * we are using for PCI - only here to keep Linux ACPI
- * happy
- */
- Method (_PRS, 0, NotSerialized)
- {
- Name (PRSP, ResourceTemplate () {
- IRQ (Level, ActiveLow, Shared) {3,4,6,7,10,11,12}
- })
- Name (PRSA, ResourceTemplate () {
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {16,17,18,19,20,21,22,23}
- })
-
- If (LNot (PICF)) {
- Return (PRSP)
- } Else {
- Return (PRSA)
- }
-
- }
-
- /* Set Resources - dummy function to keep Linux ACPI happy
- * Linux is more than happy not to tinker with irq
- * assignments as long as the CRS and STA functions
- * return good values
- */
- Method (_SRS, 1, NotSerialized ) {}
- /* Disable - dummy function to keep Linux ACPI happy */
- Method (_DIS, 0, NotSerialized ) {}
-
- } // End of LNKD
-
- /* PCI Root Bridge */
- Device (PCI0)
- {
- Name (_HID, EisaId ("PNP0A08"))
- Name (_CID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00)
- Name (_UID, 0x00)
- Name (_BBN, 0x00)
-
- // Mainboard specific IRQ routing
- Include ("irq.dsl")
-
- /* PCI Routing Table */
- Method (_PRT, 0, NotSerialized)
- {
- If (LNot (PICF))
- {
- Return (PICM)
- }
- Else
- {
- Return (APIC)
- }
- }
-
- Device (P2PB) /* PCI to PCI bridge */
- {
- Name (_ADR, 0x00130001)
-
- Include ("irq-p2p-bridge.dsl")
- Method (_PRT, 0, NotSerialized)
- {
- If (LNot (PICF))
- {
- Return (PICM)
- }
- Else
- {
- Return (APIC)
- }
- }
- /* Status - always return ready */
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0F)
- }
- }
- } // End of PCI0
- } // End of _SB
-} // End of Definition Block
-
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-Name (PICM, Package () {
- // _ADR PIN SRC IDX
-
- Package () { 0x0003FFFF, 0x00, LNKA, 0x00 },
- Package () { 0x0003FFFF, 0x01, LNKB, 0x00 },
- Package () { 0x0003FFFF, 0x02, LNKC, 0x00 },
- Package () { 0x0003FFFF, 0x03, LNKD, 0x00 },
-
- Package () { 0x0004FFFF, 0x00, LNKB, 0x00 },
- Package () { 0x0004FFFF, 0x01, LNKC, 0x00 },
- Package () { 0x0004FFFF, 0x02, LNKD, 0x00 },
- Package () { 0x0004FFFF, 0x03, LNKA, 0x00 },
-
- Package () { 0x0005FFFF, 0x00, LNKC, 0x00 },
- Package () { 0x0005FFFF, 0x01, LNKD, 0x00 },
- Package () { 0x0005FFFF, 0x02, LNKA, 0x00 },
- Package () { 0x0005FFFF, 0x03, LNKB, 0x00 },
-
- Package () { 0x0006FFFF, 0x00, LNKD, 0x00 },
- Package () { 0x0006FFFF, 0x01, LNKA, 0x00 },
- Package () { 0x0006FFFF, 0x02, LNKB, 0x00 },
- Package () { 0x0006FFFF, 0x03, LNKC, 0x00 },
-
- Package () { 0x0007FFFF, 0x00, LNKA, 0x00 },
- Package () { 0x0007FFFF, 0x01, LNKB, 0x00 },
- Package () { 0x0007FFFF, 0x02, LNKC, 0x00 },
- Package () { 0x0007FFFF, 0x03, LNKD, 0x00 },
-
- Package () { 0x0008FFFF, 0x00, LNKB, 0x00 },
- Package () { 0x0008FFFF, 0x01, LNKC, 0x00 },
- Package () { 0x0008FFFF, 0x02, LNKD, 0x00 },
- Package () { 0x0008FFFF, 0x03, LNKA, 0x00 },
-})
-
-Name (APIC, Package () {
- Package () { 0x0003FFFF, 0x00, 0x00, 0x10 },
- Package () { 0x0003FFFF, 0x01, 0x00, 0x11 },
- Package () { 0x0003FFFF, 0x02, 0x00, 0x12 },
- Package () { 0x0003FFFF, 0x03, 0x00, 0x13 },
-
- Package () { 0x0004FFFF, 0x00, 0x00, 0x11 },
- Package () { 0x0004FFFF, 0x01, 0x00, 0x12 },
- Package () { 0x0004FFFF, 0x02, 0x00, 0x13 },
- Package () { 0x0004FFFF, 0x03, 0x00, 0x10 },
-
- Package () { 0x0005FFFF, 0x00, 0x00, 0x12 },
- Package () { 0x0005FFFF, 0x01, 0x00, 0x13 },
- Package () { 0x0005FFFF, 0x02, 0x00, 0x10 },
- Package () { 0x0005FFFF, 0x03, 0x00, 0x11 },
-
- Package () { 0x0006FFFF, 0x00, 0x00, 0x13 },
- Package () { 0x0006FFFF, 0x01, 0x00, 0x10 },
- Package () { 0x0006FFFF, 0x02, 0x00, 0x11 },
- Package () { 0x0006FFFF, 0x03, 0x00, 0x12 },
-
- Package () { 0x0007FFFF, 0x00, 0x00, 0x10 },
- Package () { 0x0007FFFF, 0x01, 0x00, 0x11 },
- Package () { 0x0007FFFF, 0x02, 0x00, 0x12 },
- Package () { 0x0007FFFF, 0x03, 0x00, 0x13 },
-
- Package () { 0x0008FFFF, 0x00, 0x00, 0x11 },
- Package () { 0x0008FFFF, 0x01, 0x00, 0x12 },
- Package () { 0x0008FFFF, 0x02, 0x00, 0x13 },
- Package () { 0x0008FFFF, 0x03, 0x00, 0x10 },
-})
-
-
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-Name (PICM, Package () {
- // _ADR PIN SRC IDX
-
- Package () { 0x0001FFFF, 0x00, LNKA, 0x00 },
- Package () { 0x0001FFFF, 0x01, LNKB, 0x00 },
- Package () { 0x0001FFFF, 0x02, LNKC, 0x00 },
- Package () { 0x0001FFFF, 0x03, LNKD, 0x00 },
-
- Package () { 0x0008FFFF, 0x00, LNKB, 0x00 },
- Package () { 0x0008FFFF, 0x01, LNKC, 0x00 },
- Package () { 0x0008FFFF, 0x02, LNKD, 0x00 },
- Package () { 0x0008FFFF, 0x03, LNKA, 0x00 },
-
- Package () { 0x0009FFFF, 0x00, LNKC, 0x00 },
- Package () { 0x0009FFFF, 0x01, LNKD, 0x00 },
- Package () { 0x0009FFFF, 0x02, LNKA, 0x00 },
- Package () { 0x0009FFFF, 0x03, LNKB, 0x00 },
-
- Package () { 0x000AFFFF, 0x00, LNKD, 0x00 },
- Package () { 0x000AFFFF, 0x01, LNKA, 0x00 },
- Package () { 0x000AFFFF, 0x02, LNKB, 0x00 },
- Package () { 0x000AFFFF, 0x03, LNKC, 0x00 },
-
- Package () { 0x000BFFFF, 0x00, LNKD, 0x00 },
- Package () { 0x000BFFFF, 0x01, LNKA, 0x00 },
- Package () { 0x000BFFFF, 0x02, LNKB, 0x00 },
- Package () { 0x000BFFFF, 0x03, LNKC, 0x00 },
-
- Package () { 0x000CFFFF, 0x00, LNKA, 0x00 },
- Package () { 0x000CFFFF, 0x01, LNKB, 0x00 },
- Package () { 0x000CFFFF, 0x02, LNKC, 0x00 },
- Package () { 0x000CFFFF, 0x03, LNKD, 0x00 },
-
- Package () { 0x000DFFFF, 0x00, LNKA, 0x00 },
- Package () { 0x000DFFFF, 0x01, LNKB, 0x00 },
- Package () { 0x000DFFFF, 0x02, LNKC, 0x00 },
- Package () { 0x000DFFFF, 0x03, LNKD, 0x00 },
-
- Package () { 0x000FFFFF, 0x00, LNKA, 0x00 },
- Package () { 0x000FFFFF, 0x01, LNKB, 0x00 },
- Package () { 0x000FFFFF, 0x02, LNKC, 0x00 },
- Package () { 0x000FFFFF, 0x03, LNKD, 0x00 },
-
- /* USB controller */
- Package () { 0x0010FFFF, 0x00, LNKA, 0x00 },
- Package () { 0x0010FFFF, 0x01, LNKB, 0x00 },
- Package () { 0x0010FFFF, 0x02, LNKC, 0x00 },
- Package () { 0x0010FFFF, 0x03, LNKD, 0x00 },
-
- Package () { 0x0011FFFF, 0x00, LNKA, 0x00 },
- Package () { 0x0011FFFF, 0x01, LNKB, 0x00 },
- Package () { 0x0011FFFF, 0x02, LNKC, 0x00 },
- Package () { 0x0011FFFF, 0x03, LNKD, 0x00 },
-
- Package () { 0x0012FFFF, 0x00, LNKA, 0x00 },
- Package () { 0x0012FFFF, 0x01, LNKB, 0x00 },
- Package () { 0x0012FFFF, 0x02, LNKC, 0x00 },
- Package () { 0x0012FFFF, 0x03, LNKD, 0x00 }
-})
-
-Name (APIC, Package () {
- Package () { 0x0001FFFF, 0x00, 0x00, 0x10 },
- Package () { 0x0001FFFF, 0x01, 0x00, 0x11 },
- Package () { 0x0001FFFF, 0x02, 0x00, 0x12 },
- Package () { 0x0001FFFF, 0x03, 0x00, 0x13 },
-
- Package () { 0x0008FFFF, 0x00, 0x00, 0x11 },
- Package () { 0x0008FFFF, 0x01, 0x00, 0x12 },
- Package () { 0x0008FFFF, 0x02, 0x00, 0x13 },
- Package () { 0x0008FFFF, 0x03, 0x00, 0x10 },
-
- Package () { 0x0009FFFF, 0x00, 0x00, 0x12 },
- Package () { 0x0009FFFF, 0x01, 0x00, 0x13 },
- Package () { 0x0009FFFF, 0x02, 0x00, 0x10 },
- Package () { 0x0009FFFF, 0x03, 0x00, 0x11 },
-
- Package () { 0x000AFFFF, 0x00, 0x00, 0x13 },
- Package () { 0x000AFFFF, 0x01, 0x00, 0x10 },
- Package () { 0x000AFFFF, 0x02, 0x00, 0x11 },
- Package () { 0x000AFFFF, 0x03, 0x00, 0x12 },
-
- Package () { 0x000BFFFF, 0x00, 0x00, 0x13 },
- Package () { 0x000BFFFF, 0x01, 0x00, 0x10 },
- Package () { 0x000BFFFF, 0x02, 0x00, 0x11 },
- Package () { 0x000BFFFF, 0x03, 0x00, 0x12 },
-
- Package () { 0x000CFFFF, 0x00, 0x00, 0x10 },
- Package () { 0x000CFFFF, 0x01, 0x00, 0x11 },
- Package () { 0x000CFFFF, 0x02, 0x00, 0x12 },
- Package () { 0x000CFFFF, 0x03, 0x00, 0x13 },
-
- Package () { 0x000DFFFF, 0x00, 0x00, 0x10 },
- Package () { 0x000DFFFF, 0x01, 0x00, 0x11 },
- Package () { 0x000DFFFF, 0x02, 0x00, 0x12 },
- Package () { 0x000DFFFF, 0x03, 0x00, 0x13 },
-
- Package () { 0x000FFFFF, 0x00, LNKA, 0x00 },
- Package () { 0x000FFFFF, 0x01, LNKA, 0x00 },
- Package () { 0x000FFFFF, 0x02, LNKA, 0x00 },
- Package () { 0x000FFFFF, 0x03, LNKA, 0x00 },
-
- /* USB controller. Hardwired in internal
- APIC mode, see PM pg. 137,
- "miscellaneous controls", footnote to
- "IDE interrupt select" */
- Package () { 0x0010FFFF, 0x00, 0x00, 0x14 },
- Package () { 0x0010FFFF, 0x01, 0x00, 0x16 },
- Package () { 0x0010FFFF, 0x02, 0x00, 0x15 },
- Package () { 0x0010FFFF, 0x03, 0x00, 0x17 },
-
- Package () { 0x0011FFFF, 0x00, LNKA, 0x00 },
- Package () { 0x0011FFFF, 0x01, LNKB, 0x00 },
- Package () { 0x0011FFFF, 0x02, LNKC, 0x00 },
- Package () { 0x0011FFFF, 0x03, LNKD, 0x00 },
-
- Package () { 0x0012FFFF, 0x00, LNKD, 0x00 },
- Package () { 0x0012FFFF, 0x01, LNKD, 0x00 },
- Package () { 0x0012FFFF, 0x02, LNKD, 0x00 },
- Package () { 0x0012FFFF, 0x03, LNKD, 0x00 },
-})
-
-
obj-y += get_pci1234.o
-ifdef POST_EVALUATION
-$(obj)/northbridge/amd/amdfam10/ssdt.c: $(src)/northbridge/amd/amdfam10/ssdt.dsl
- iasl -p $(obj)/northbridge/amd/amdfam10/ssdt -tc $<
- perl -pi -e 's/AmlCode/AmlCode_ssdt/g' $(obj)/northbridge/amd/amdfam10/ssdt.hex
- mv $(obj)/northbridge/amd/amdfam10/ssdt.hex $@
-
-$(obj)/northbridge/amd/amdfam10/sspr1.c: $(src)/northbridge/amd/amdfam10/sspr1.dsl
- iasl -p $(obj)/northbridge/amd/amdfam10/sspr1 -tc $<
- perl -pi -e 's/AmlCode/AmlCode_sspr1/g' $(obj)/northbridge/amd/amdfam10/sspr1.hex
- mv $(obj)/northbridge/amd/amdfam10/sspr1.hex $@
-
-$(obj)/northbridge/amd/amdfam10/sspr2.c: $(src)/northbridge/amd/amdfam10/sspr2.dsl
- iasl -p $(obj)/northbridge/amd/amdfam10/sspr2 -tc $<
- perl -pi -e 's/AmlCode/AmlCode_sspr2/g' $(obj)/northbridge/amd/amdfam10/sspr2.hex
- mv $(obj)/northbridge/amd/amdfam10/sspr2.hex $@
-
-$(obj)/northbridge/amd/amdfam10/sspr3.c: $(src)/northbridge/amd/amdfam10/sspr3.dsl
- iasl -p $(obj)/northbridge/amd/amdfam10/sspr3 -tc $<
- perl -pi -e 's/AmlCode/AmlCode_sspr3/g' $(obj)/northbridge/amd/amdfam10/sspr3.hex
- mv $(obj)/northbridge/amd/amdfam10/sspr3.hex $@
-
-$(obj)/northbridge/amd/amdfam10/sspr4.c: $(src)/northbridge/amd/amdfam10/sspr4.dsl
- iasl -p $(obj)/northbridge/amd/amdfam10/sspr4 -tc $<
- perl -pi -e 's/AmlCode/AmlCode_sspr4/g' $(obj)/northbridge/amd/amdfam10/sspr4.hex
- mv $(obj)/northbridge/amd/amdfam10/sspr4.hex $@
-
-$(obj)/northbridge/amd/amdfam10/sspr5.c: $(src)/northbridge/amd/amdfam10/sspr5.dsl
- iasl -p $(obj)/northbridge/amd/amdfam10/sspr5 -tc $<
- perl -pi -e 's/AmlCode/AmlCode_sspr5/g' $(obj)/northbridge/amd/amdfam10/sspr5.hex
- mv $(obj)/northbridge/amd/amdfam10/sspr5.hex $@
-endif
-
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * Make sure HC_NUMS and HC_POSSIBLE_NUM setting is consistent to this file
+ */
+
+DefinitionBlock ("SSDT.aml", "SSDT", 1, "AMD-FAM10", "AMD-ACPI", 100925440)
+{
+ /*
+ * These objects were referenced but not defined in this table
+ */
+ External (\_SB_.PCI0, DeviceObj)
+
+ Scope (\_SB.PCI0)
+ {
+ Name (BUSN, Package (0x20) /* HC_NUMS */
+ {
+ 0x11111111,
+ 0x22222222,
+ 0x33333333,
+ 0x44444444,
+ 0x55555555,
+ 0x66666666,
+ 0x77777777,
+ 0x88888888,
+ 0x99999999,
+ 0xaaaaaaaa,
+ 0xbbbbbbbb,
+ 0xcccccccc,
+ 0xdddddddd,
+ 0xeeeeeeee,
+ 0x10101010,
+ 0x11111111,
+ 0x12121212,
+ 0x13131313,
+ 0x14141414,
+ 0x15151515,
+ 0x11111111,
+ 0x22222222,
+ 0x33333333,
+ 0x44444444,
+ 0x55555555,
+ 0x66666666,
+ 0x77777777,
+ 0x88888888,
+ 0x99999999,
+ 0xaaaaaaaa,
+ 0xbbbbbbbb,
+ 0xcccccccc
+ })
+ Name (MMIO, Package (0x80) /* HC_NUMS * 4 */
+ {
+ 0x11111111,
+ 0x22222222,
+ 0x33333333,
+ 0x44444444,
+ 0x55555555,
+ 0x66666666,
+ 0x77777777,
+ 0x88888888,
+ 0x99999999,
+ 0xaaaaaaaa,
+ 0xbbbbbbbb,
+ 0xcccccccc,
+ 0xdddddddd,
+ 0xeeeeeeee,
+ 0x11111111,
+ 0x22222222,
+ 0x11111111,
+ 0x22222222,
+ 0x33333333,
+ 0x44444444,
+ 0x55555555,
+ 0x66666666,
+ 0x77777777,
+ 0x88888888,
+ 0x99999999,
+ 0xaaaaaaaa,
+ 0xbbbbbbbb,
+ 0xcccccccc,
+ 0xdddddddd,
+ 0xeeeeeeee,
+ 0x11111111,
+ 0x22222222,
+ 0x11111111,
+ 0x22222222,
+ 0x33333333,
+ 0x44444444,
+ 0x55555555,
+ 0x66666666,
+ 0x77777777,
+ 0x88888888,
+ 0x99999999,
+ 0xaaaaaaaa,
+ 0xbbbbbbbb,
+ 0xcccccccc,
+ 0xdddddddd,
+ 0xeeeeeeee,
+ 0x11111111,
+ 0x22222222,
+ 0x11111111,
+ 0x22222222,
+ 0x33333333,
+ 0x44444444,
+ 0x55555555,
+ 0x66666666,
+ 0x77777777,
+ 0x88888888,
+ 0x99999999,
+ 0xaaaaaaaa,
+ 0xbbbbbbbb,
+ 0xcccccccc,
+ 0xdddddddd,
+ 0xeeeeeeee,
+ 0x11111111,
+ 0x22222222,
+ 0x11111111,
+ 0x22222222,
+ 0x33333333,
+ 0x44444444,
+ 0x55555555,
+ 0x66666666,
+ 0x77777777,
+ 0x88888888,
+ 0x99999999,
+ 0xaaaaaaaa,
+ 0xbbbbbbbb,
+ 0xcccccccc,
+ 0xdddddddd,
+ 0xeeeeeeee,
+ 0x11111111,
+ 0x22222222,
+ 0x11111111,
+ 0x22222222,
+ 0x33333333,
+ 0x44444444,
+ 0x55555555,
+ 0x66666666,
+ 0x77777777,
+ 0x88888888,
+ 0x99999999,
+ 0xaaaaaaaa,
+ 0x11111111,
+ 0x22222222,
+ 0x33333333,
+ 0x44444444,
+ 0x55555555,
+ 0x66666666,
+ 0x77777777,
+ 0x88888888,
+ 0x99999999,
+ 0xaaaaaaaa,
+ 0x11111111,
+ 0x22222222,
+ 0x33333333,
+ 0x44444444,
+ 0x55555555,
+ 0x66666666,
+ 0x77777777,
+ 0x88888888,
+ 0x99999999,
+ 0xaaaaaaaa,
+ 0x11111111,
+ 0x22222222,
+ 0x33333333,
+ 0x44444444,
+ 0x55555555,
+ 0x66666666,
+ 0x77777777,
+ 0x88888888,
+ 0x99999999,
+ 0xaaaaaaaa,
+ 0x11111111,
+ 0x22222222,
+ 0x33333333,
+ 0x44444444,
+ 0x55555555,
+ 0x66666666,
+ 0x77777777,
+ 0x88888888
+ })
+ Name (PCIO, Package (0x40) /* HC_NUMS * 2 */
+ {
+ 0x77777777,
+ 0x88888888,
+ 0x99999999,
+ 0xaaaaaaaa,
+ 0xbbbbbbbb,
+ 0xcccccccc,
+ 0xdddddddd,
+ 0xeeeeeeee,
+ 0x77777777,
+ 0x88888888,
+ 0x99999999,
+ 0xaaaaaaaa,
+ 0xbbbbbbbb,
+ 0xcccccccc,
+ 0xdddddddd,
+ 0xeeeeeeee,
+ 0x77777777,
+ 0x88888888,
+ 0x99999999,
+ 0xaaaaaaaa,
+ 0xbbbbbbbb,
+ 0xcccccccc,
+ 0xdddddddd,
+ 0xeeeeeeee,
+ 0x77777777,
+ 0x88888888,
+ 0x99999999,
+ 0xaaaaaaaa,
+ 0xbbbbbbbb,
+ 0xcccccccc,
+ 0xdddddddd,
+ 0xeeeeeeee,
+ 0xaaaaaaaa,
+ 0xbbbbbbbb,
+ 0xcccccccc,
+ 0xdddddddd,
+ 0xeeeeeeee,
+ 0x77777777,
+ 0x88888888,
+ 0x99999999,
+ 0x11111111,
+ 0x22222222,
+ 0x33333333,
+ 0x44444444,
+ 0x55555555,
+ 0x66666666,
+ 0x77777777,
+ 0x88888888,
+ 0x99999999,
+ 0xaaaaaaaa,
+ 0x11111111,
+ 0x22222222,
+ 0x33333333,
+ 0x44444444,
+ 0x55555555,
+ 0x66666666,
+ 0x77777777,
+ 0x88888888,
+ 0x99999999,
+ 0xaaaaaaaa,
+ 0x11111111,
+ 0x22222222,
+ 0x33333333,
+ 0x44444444
+ })
+ Name (SBLK, 0x11)
+ Name (TOM1, 0xaaaaaaaa)
+ Name (SBDN, 0xbbbbbbbb)
+ Name (HCLK, Package (0x20) /* HC_POSSIBLE_NUM */
+ {
+ 0x11111111,
+ 0x22222222,
+ 0x33333333,
+ 0x44444444,
+ 0x55555555,
+ 0x66666666,
+ 0x77777777,
+ 0x88888888,
+ 0x11111111,
+ 0x22222222,
+ 0x33333333,
+ 0x44444444,
+ 0x55555555,
+ 0x66666666,
+ 0x77777777,
+ 0x88888888,
+ 0x11111111,
+ 0x22222222,
+ 0x33333333,
+ 0x44444444,
+ 0x55555555,
+ 0x66666666,
+ 0x77777777,
+ 0x88888888,
+ 0x11111111,
+ 0x22222222,
+ 0x33333333,
+ 0x44444444,
+ 0x55555555,
+ 0x66666666,
+ 0x77777777,
+ 0x88888888
+ })
+ Name (HCDN, Package (0x20) /* HC_POSSIBLE_NUM */
+ {
+ 0x11111111,
+ 0x22222222,
+ 0x33333333,
+ 0x44444444,
+ 0x55555555,
+ 0x66666666,
+ 0x77777777,
+ 0x88888888,
+ 0x11111111,
+ 0x22222222,
+ 0x33333333,
+ 0x44444444,
+ 0x55555555,
+ 0x66666666,
+ 0x77777777,
+ 0x88888888,
+ 0x11111111,
+ 0x22222222,
+ 0x33333333,
+ 0x44444444,
+ 0x55555555,
+ 0x66666666,
+ 0x77777777,
+ 0x88888888,
+ 0x11111111,
+ 0x22222222,
+ 0x33333333,
+ 0x44444444,
+ 0x55555555,
+ 0x66666666,
+ 0x77777777,
+ 0x88888888
+ })
+ Name (CBB, 0x99)
+ Name (CBST, 0x88)
+ Name (CBB2, 0x77)
+ Name (CBS2, 0x66)
+
+ }
+}
+
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/*
- * Make sure HC_NUMS and HC_POSSIBLE_NUM setting is consistent to this file
- */
-
-DefinitionBlock ("SSDT.aml", "SSDT", 1, "AMD-FAM10", "AMD-ACPI", 100925440)
-{
- /*
- * These objects were referenced but not defined in this table
- */
- External (\_SB_.PCI0, DeviceObj)
-
- Scope (\_SB.PCI0)
- {
- Name (BUSN, Package (0x20) /* HC_NUMS */
- {
- 0x11111111,
- 0x22222222,
- 0x33333333,
- 0x44444444,
- 0x55555555,
- 0x66666666,
- 0x77777777,
- 0x88888888,
- 0x99999999,
- 0xaaaaaaaa,
- 0xbbbbbbbb,
- 0xcccccccc,
- 0xdddddddd,
- 0xeeeeeeee,
- 0x10101010,
- 0x11111111,
- 0x12121212,
- 0x13131313,
- 0x14141414,
- 0x15151515,
- 0x11111111,
- 0x22222222,
- 0x33333333,
- 0x44444444,
- 0x55555555,
- 0x66666666,
- 0x77777777,
- 0x88888888,
- 0x99999999,
- 0xaaaaaaaa,
- 0xbbbbbbbb,
- 0xcccccccc
- })
- Name (MMIO, Package (0x80) /* HC_NUMS * 4 */
- {
- 0x11111111,
- 0x22222222,
- 0x33333333,
- 0x44444444,
- 0x55555555,
- 0x66666666,
- 0x77777777,
- 0x88888888,
- 0x99999999,
- 0xaaaaaaaa,
- 0xbbbbbbbb,
- 0xcccccccc,
- 0xdddddddd,
- 0xeeeeeeee,
- 0x11111111,
- 0x22222222,
- 0x11111111,
- 0x22222222,
- 0x33333333,
- 0x44444444,
- 0x55555555,
- 0x66666666,
- 0x77777777,
- 0x88888888,
- 0x99999999,
- 0xaaaaaaaa,
- 0xbbbbbbbb,
- 0xcccccccc,
- 0xdddddddd,
- 0xeeeeeeee,
- 0x11111111,
- 0x22222222,
- 0x11111111,
- 0x22222222,
- 0x33333333,
- 0x44444444,
- 0x55555555,
- 0x66666666,
- 0x77777777,
- 0x88888888,
- 0x99999999,
- 0xaaaaaaaa,
- 0xbbbbbbbb,
- 0xcccccccc,
- 0xdddddddd,
- 0xeeeeeeee,
- 0x11111111,
- 0x22222222,
- 0x11111111,
- 0x22222222,
- 0x33333333,
- 0x44444444,
- 0x55555555,
- 0x66666666,
- 0x77777777,
- 0x88888888,
- 0x99999999,
- 0xaaaaaaaa,
- 0xbbbbbbbb,
- 0xcccccccc,
- 0xdddddddd,
- 0xeeeeeeee,
- 0x11111111,
- 0x22222222,
- 0x11111111,
- 0x22222222,
- 0x33333333,
- 0x44444444,
- 0x55555555,
- 0x66666666,
- 0x77777777,
- 0x88888888,
- 0x99999999,
- 0xaaaaaaaa,
- 0xbbbbbbbb,
- 0xcccccccc,
- 0xdddddddd,
- 0xeeeeeeee,
- 0x11111111,
- 0x22222222,
- 0x11111111,
- 0x22222222,
- 0x33333333,
- 0x44444444,
- 0x55555555,
- 0x66666666,
- 0x77777777,
- 0x88888888,
- 0x99999999,
- 0xaaaaaaaa,
- 0x11111111,
- 0x22222222,
- 0x33333333,
- 0x44444444,
- 0x55555555,
- 0x66666666,
- 0x77777777,
- 0x88888888,
- 0x99999999,
- 0xaaaaaaaa,
- 0x11111111,
- 0x22222222,
- 0x33333333,
- 0x44444444,
- 0x55555555,
- 0x66666666,
- 0x77777777,
- 0x88888888,
- 0x99999999,
- 0xaaaaaaaa,
- 0x11111111,
- 0x22222222,
- 0x33333333,
- 0x44444444,
- 0x55555555,
- 0x66666666,
- 0x77777777,
- 0x88888888,
- 0x99999999,
- 0xaaaaaaaa,
- 0x11111111,
- 0x22222222,
- 0x33333333,
- 0x44444444,
- 0x55555555,
- 0x66666666,
- 0x77777777,
- 0x88888888
- })
- Name (PCIO, Package (0x40) /* HC_NUMS * 2 */
- {
- 0x77777777,
- 0x88888888,
- 0x99999999,
- 0xaaaaaaaa,
- 0xbbbbbbbb,
- 0xcccccccc,
- 0xdddddddd,
- 0xeeeeeeee,
- 0x77777777,
- 0x88888888,
- 0x99999999,
- 0xaaaaaaaa,
- 0xbbbbbbbb,
- 0xcccccccc,
- 0xdddddddd,
- 0xeeeeeeee,
- 0x77777777,
- 0x88888888,
- 0x99999999,
- 0xaaaaaaaa,
- 0xbbbbbbbb,
- 0xcccccccc,
- 0xdddddddd,
- 0xeeeeeeee,
- 0x77777777,
- 0x88888888,
- 0x99999999,
- 0xaaaaaaaa,
- 0xbbbbbbbb,
- 0xcccccccc,
- 0xdddddddd,
- 0xeeeeeeee,
- 0xaaaaaaaa,
- 0xbbbbbbbb,
- 0xcccccccc,
- 0xdddddddd,
- 0xeeeeeeee,
- 0x77777777,
- 0x88888888,
- 0x99999999,
- 0x11111111,
- 0x22222222,
- 0x33333333,
- 0x44444444,
- 0x55555555,
- 0x66666666,
- 0x77777777,
- 0x88888888,
- 0x99999999,
- 0xaaaaaaaa,
- 0x11111111,
- 0x22222222,
- 0x33333333,
- 0x44444444,
- 0x55555555,
- 0x66666666,
- 0x77777777,
- 0x88888888,
- 0x99999999,
- 0xaaaaaaaa,
- 0x11111111,
- 0x22222222,
- 0x33333333,
- 0x44444444
- })
- Name (SBLK, 0x11)
- Name (TOM1, 0xaaaaaaaa)
- Name (SBDN, 0xbbbbbbbb)
- Name (HCLK, Package (0x20) /* HC_POSSIBLE_NUM */
- {
- 0x11111111,
- 0x22222222,
- 0x33333333,
- 0x44444444,
- 0x55555555,
- 0x66666666,
- 0x77777777,
- 0x88888888,
- 0x11111111,
- 0x22222222,
- 0x33333333,
- 0x44444444,
- 0x55555555,
- 0x66666666,
- 0x77777777,
- 0x88888888,
- 0x11111111,
- 0x22222222,
- 0x33333333,
- 0x44444444,
- 0x55555555,
- 0x66666666,
- 0x77777777,
- 0x88888888,
- 0x11111111,
- 0x22222222,
- 0x33333333,
- 0x44444444,
- 0x55555555,
- 0x66666666,
- 0x77777777,
- 0x88888888
- })
- Name (HCDN, Package (0x20) /* HC_POSSIBLE_NUM */
- {
- 0x11111111,
- 0x22222222,
- 0x33333333,
- 0x44444444,
- 0x55555555,
- 0x66666666,
- 0x77777777,
- 0x88888888,
- 0x11111111,
- 0x22222222,
- 0x33333333,
- 0x44444444,
- 0x55555555,
- 0x66666666,
- 0x77777777,
- 0x88888888,
- 0x11111111,
- 0x22222222,
- 0x33333333,
- 0x44444444,
- 0x55555555,
- 0x66666666,
- 0x77777777,
- 0x88888888,
- 0x11111111,
- 0x22222222,
- 0x33333333,
- 0x44444444,
- 0x55555555,
- 0x66666666,
- 0x77777777,
- 0x88888888
- })
- Name (CBB, 0x99)
- Name (CBST, 0x88)
- Name (CBB2, 0x77)
- Name (CBS2, 0x66)
-
- }
-}
-
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+DefinitionBlock ("SSPR.aml", "SSDT", 1, "AMD-FAM10", "AMD-ACPI", 100925441)
+{
+ Scope (\_SB)
+ {
+ Processor (\_SB.CPAA, 0xbb, 0x120, 6) // CPU0 and 0x01 need to be updated
+ {
+ Name(_PCT, Package ()
+ {
+ ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_CTRL
+ ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_STATUS
+ })
+
+ Name(_PSS, Package()
+ {
+ Package(0x06) {0x1111, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
+ })
+ }
+
+ }
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-DefinitionBlock ("SSPR.aml", "SSDT", 1, "AMD-FAM10", "AMD-ACPI", 100925441)
-{
- Scope (\_SB)
- {
- Processor (\_SB.CPAA, 0xbb, 0x120, 6) // CPU0 and 0x01 need to be updated
- {
- Name(_PCT, Package ()
- {
- ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_CTRL
- ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_STATUS
- })
-
- Name(_PSS, Package()
- {
- Package(0x06) {0x1111, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
- })
- }
-
- }
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+DefinitionBlock ("SSPR.aml", "SSDT", 1, "AMD-FAM10", "AMD-ACPI", 100925441)
+{
+ Scope (\_SB)
+ {
+ Processor (\_SB.CPAA, 0xbb, 0x120, 6) // CPU0 and 0x01 need to be updated
+ {
+ Name(_PCT, Package ()
+ {
+ ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_CTRL
+ ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_STATUS
+ })
+
+ Name(_PSS, Package()
+ {
+ Package(0x06) {0x1111, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
+ Package(0x06) {0x7777, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
+ })
+ }
+
+ }
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-DefinitionBlock ("SSPR.aml", "SSDT", 1, "AMD-FAM10", "AMD-ACPI", 100925441)
-{
- Scope (\_SB)
- {
- Processor (\_SB.CPAA, 0xbb, 0x120, 6) // CPU0 and 0x01 need to be updated
- {
- Name(_PCT, Package ()
- {
- ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_CTRL
- ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_STATUS
- })
-
- Name(_PSS, Package()
- {
- Package(0x06) {0x1111, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
- Package(0x06) {0x7777, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
- })
- }
-
- }
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+DefinitionBlock ("SSPR.aml", "SSDT", 1, "AMD-FAM10", "AMD-ACPI", 100925441)
+{
+ Scope (\_SB)
+ {
+ Processor (\_SB.CPAA, 0xbb, 0x120, 6) // CPU0 and 0x01 need to be updated
+ {
+ Name(_PCT, Package ()
+ {
+ ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_CTRL
+ ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_STATUS
+ })
+
+ Name(_PSS, Package()
+ {
+ Package(0x06) {0x1111, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
+ Package(0x06) {0x7777, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
+ Package(0x06) {0x8888, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
+ })
+ }
+
+ }
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-DefinitionBlock ("SSPR.aml", "SSDT", 1, "AMD-FAM10", "AMD-ACPI", 100925441)
-{
- Scope (\_SB)
- {
- Processor (\_SB.CPAA, 0xbb, 0x120, 6) // CPU0 and 0x01 need to be updated
- {
- Name(_PCT, Package ()
- {
- ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_CTRL
- ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_STATUS
- })
-
- Name(_PSS, Package()
- {
- Package(0x06) {0x1111, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
- Package(0x06) {0x7777, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
- Package(0x06) {0x8888, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
- })
- }
-
- }
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+DefinitionBlock ("SSPR.aml", "SSDT", 1, "AMD-FAM10", "AMD-ACPI", 100925441)
+{
+ Scope (\_SB)
+ {
+ Processor (\_SB.CPAA, 0xbb, 0x120, 6) // CPU0 and 0x01 need to be updated
+ {
+ Name(_PCT, Package ()
+ {
+ ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_CTRL
+ ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_STATUS
+ })
+
+ Name(_PSS, Package()
+ {
+ Package(0x06) {0x1111, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
+ Package(0x06) {0x7777, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
+ Package(0x06) {0x8888, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
+ Package(0x06) {0x9999, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
+ })
+ }
+
+ }
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-DefinitionBlock ("SSPR.aml", "SSDT", 1, "AMD-FAM10", "AMD-ACPI", 100925441)
-{
- Scope (\_SB)
- {
- Processor (\_SB.CPAA, 0xbb, 0x120, 6) // CPU0 and 0x01 need to be updated
- {
- Name(_PCT, Package ()
- {
- ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_CTRL
- ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_STATUS
- })
-
- Name(_PSS, Package()
- {
- Package(0x06) {0x1111, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
- Package(0x06) {0x7777, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
- Package(0x06) {0x8888, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
- Package(0x06) {0x9999, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
- })
- }
-
- }
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+DefinitionBlock ("SSPR.aml", "SSDT", 1, "AMD-FAM10", "AMD-ACPI", 100925441)
+{
+ Scope (\_SB)
+ {
+ Processor (\_SB.CPAA, 0xbb, 0x120, 6) // CPU0 and 0x01 need to be updated
+ {
+ Name(_PCT, Package ()
+ {
+ ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_CTRL
+ ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_STATUS
+ })
+
+ Name(_PSS, Package()
+ {
+ Package(0x06) {0x1111, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
+ Package(0x06) {0x7777, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
+ Package(0x06) {0x8888, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
+ Package(0x06) {0x9999, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
+ Package(0x06) {0xaaaa, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
+ })
+ }
+
+ }
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-DefinitionBlock ("SSPR.aml", "SSDT", 1, "AMD-FAM10", "AMD-ACPI", 100925441)
-{
- Scope (\_SB)
- {
- Processor (\_SB.CPAA, 0xbb, 0x120, 6) // CPU0 and 0x01 need to be updated
- {
- Name(_PCT, Package ()
- {
- ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_CTRL
- ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_STATUS
- })
-
- Name(_PSS, Package()
- {
- Package(0x06) {0x1111, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
- Package(0x06) {0x7777, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
- Package(0x06) {0x8888, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
- Package(0x06) {0x9999, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
- Package(0x06) {0xaaaa, 0x222222, 0x3333, 0x4444, 0x55, 0x66 },
- })
- }
-
- }
-}
projects / coreboot.git / commitdiff