Allow selecting the physical USB Debug Port on AMD SB700.

The AMD SB700 allows changing the physical USB port to be used as
USB Debug Port, implement support for this.

Also, fix incorrect PCI device of the SB700 EHCI device. Actually, the
SB700 has _two_ EHCI devices (D18:F2 and D19:F2), but for now we only use
D18:F2. Our generic USBDEBUG code cannot handle multiple EHCI PCI devices
currently, AFAICS.

Hook up all SB700 boards to the CONFIG_USBDEBUG_DEFAULT_PORT facility.

Untested, but should work.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5907 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
index 1321a67bd7bfe60c29f30a6939c46d018af635ce..16ea5f204fd0dbffb9d7510cfbc337e9d3850399 100644 (file)
--- a/src/mainboard/amd/mahogany/romstage.c
+++ b/src/mainboard/amd/mahogany/romstage.c
@@ -128,7 +128,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        uart_init();
 
 #if CONFIG_USBDEBUG
-       sb700_enable_usbdebug(0);
+       sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
        early_usbdebug_init();
 #endif
 

diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 6f47f6628320db3848dca177e19e1b166e9f05ff..ad0d741762b8292930df8d4328db4f7883243bf2 100644 (file)
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -145,7 +145,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        uart_init();
 
 #if CONFIG_USBDEBUG
-       sb700_enable_usbdebug(0);
+       sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
        early_usbdebug_init();
 #endif
 

diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index 3e190fec9c22f4257f2fb73d5c47d3e13082c211..536fe54c121e983a609cc81eb53463651c14a39b 100644 (file)
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -145,7 +145,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        uart_init();
 
 #if CONFIG_USBDEBUG
-       sb700_enable_usbdebug(0);
+       sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
        early_usbdebug_init();
 #endif
 

diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
index ac34a2d50235e06ad0166943be4d86fead74cc77..dac230734ba9cbe3aa5aa301bc5dade6737609ea 100644 (file)
--- a/src/mainboard/asrock/939a785gmh/romstage.c
+++ b/src/mainboard/asrock/939a785gmh/romstage.c
@@ -182,7 +182,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        uart_init();
 
 #if CONFIG_USBDEBUG
-       sb700_enable_usbdebug(0);
+       sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
        early_usbdebug_init();
 #endif
 

diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 770cee1cbe2268aeecb2c731e95f746adcb5d75b..3df523cec6f3629b293165d91457e16cdf4333aa 100644 (file)
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -146,7 +146,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        uart_init();
 
 #if CONFIG_USBDEBUG
-       sb700_enable_usbdebug(0);
+       sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
        early_usbdebug_init();
 #endif
 

diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index 13664418ab70ca9e412f2a855b2c61b93d0d248e..55e1b624920e57346ad1f15a4e6347cdcbdcee9a 100644 (file)
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -141,7 +141,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        uart_init();
 
 #if CONFIG_USBDEBUG
-       sb700_enable_usbdebug(0);
+       sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
        early_usbdebug_init();
 #endif
 

diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index 64b560d683f800f36f7b54e3b80a9681407e404f..9569556228104c20de4e71e712d4ad0c79895b41 100644 (file)
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -145,7 +145,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        uart_init();
 
 #if CONFIG_USBDEBUG
-       sb700_enable_usbdebug(0);
+       sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
        early_usbdebug_init();
 #endif
 

diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index e53ddf4251db1a62c4a399cf1605effb34c4d22d..96a4595cb6b66130521a0de06d87f439b4875e40 100644 (file)
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -148,7 +148,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        uart_init();
 
 #if CONFIG_USBDEBUG
-       sb700_enable_usbdebug(0);
+       sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
        early_usbdebug_init();
 #endif
 

diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index b966c465e8ed4cea54f9a24aac0d3697ee4641eb..f96797d8c05d139924e765c8d28260850aad1a3c 100644 (file)
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -152,7 +152,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        uart_init();
 
 #if CONFIG_USBDEBUG
-       sb700_enable_usbdebug(0);
+       sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
        early_usbdebug_init();
 #endif
 

diff --git a/src/southbridge/amd/sb700/sb700_enable_usbdebug.c b/src/southbridge/amd/sb700/sb700_enable_usbdebug.c
index 0f40d862a7f85bbaad10d10972555e6e0e857a4f..02d3900047120d76d7d406ba71e0431d54df52a7 100644 (file)
--- a/src/southbridge/amd/sb700/sb700_enable_usbdebug.c
+++ b/src/southbridge/amd/sb700/sb700_enable_usbdebug.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -25,22 +26,39 @@
 #define EHCI_BAR_INDEX         0x10            /* TODO: DBUG_PRT[31:29] */
 #define EHCI_DEBUG_OFFSET      0xE0            /* Hardcoded to 0xE0 */
 
-/* Required for successful build, but currently empty. */
+#define EHCI_EOR               (EHCI_BAR + 0x20)
+#define DEBUGPORT_MISC_CONTROL (EHCI_EOR + 0x80)
+
 void set_debug_port(unsigned int port)
 {
-       /* TODO: Allow changing the physical USB port used as Debug Port. */
+       u32 reg32;
+
+       /* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */
+       reg32 = read32(DEBUGPORT_MISC_CONTROL);
+       reg32 &= ~(0xf << 28);
+       reg32 |= (port << 28);
+       reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
+       write32(DEBUGPORT_MISC_CONTROL, reg32);
 }
 
+/*
+ * Note: The SB700 has two EHCI devices, D18:F2 and D19:F2.
+ * This code currently only supports the first one, i.e., USB Debug devices
+ * attached to physical USB ports belonging to the first EHCI device.
+ */
 static void sb700_enable_usbdebug(unsigned int port)
 {
-       device_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */
-
-       /* Select the requested physical USB port (1-15) as the Debug Port. */
-       set_debug_port(port);
+       device_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */
 
        /* Set the EHCI BAR address. */
        pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR);
 
        /* Enable access to the EHCI memory space registers. */
        pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
+
+       /*
+       * Select the requested physical USB port (1-15) as the Debug Port.
+       * Must be called after the EHCI BAR has been set up (see above).
+       */
+       set_debug_port(port);
 }