Patch AMD Fam10 C2 for errata 327, 344, 346, 354, 351.

Removed c2 HT Phy 520a/530a reserved bit.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4359 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h
index 5fc1e66a291fb3e3c468010a276eab703e6191e2..a2ee0cac942fbdb53f75ba9c82741757ee36a2f0 100644 (file)
--- a/src/cpu/amd/model_10xxx/defaults.h
+++ b/src/cpu/amd/model_10xxx/defaults.h
@@ -124,9 +124,40 @@ static const struct {
        { 0, 0xE4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
          0x00002000, 0x00002000 },     /* [13] LdtStopTriEn = 1 */
 
+       /* Link Global Retry Control Register */
+       { 0, 0x150, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+         0x00073900, 0x00073F00 },
+
+       /*  Errata 351
+        * System software should program the Link Extended Control Registers[LS2En]
+        * (F0x[18C:170][8]) to 0b for all links. System software should also
+        * program Link Global Extended Control Register[ForceFullT0]
+        * (F0x16C[15:13]) to 000b */
+
+       { 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL, /* Fix FAM10_ALL when fixed in rev guide */
+         0x00000000, 0x00000100 },
+       { 0, 0x174, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+         0x00000000, 0x00000100 },
+       { 0, 0x178, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+         0x00000000, 0x00000100 },
+       { 0, 0x17C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+         0x00000000, 0x00000100 },
+       { 0, 0x180, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+         0x00000000, 0x00000100 },
+       { 0, 0x184, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+         0x00000000, 0x00000100 },
+       { 0, 0x188, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+         0x00000000, 0x00000100 },
+       { 0, 0x18C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+         0x00000000, 0x00000100 },
+       { 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+         0x00000000, 0x00000100 },
+
        /* Link Global Extended Control Register */
        { 0, 0x16C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
-         0x0000C000, 0x0000E000 },     /* [15:13] ForceFullT0 = 110b */
+         0x00000014, 0x0000003F },     /* [15:13] ForceFullT0 = 0b,
+                                                                * Set T0Time 14h per BKDG */
+
 
        /* Function 1 - Map Init */
 
@@ -257,6 +288,11 @@ static const struct {
                                           [5] DisPciCfgCpuMstAbtRsp = 1,
                                           [1] SyncFloodOnUsPwDataErr = 1 */
 
+       /* errata 346 - Fam10 C2
+        *  System software should set F3x188[22] to 1b. */
+       { 3, 0x188, AMD_RB_C2, AMD_PTYPE_ALL,
+         0x00400000, 0x00400000 },
+
        /* L3 Control Register */
        { 3, 0x1B8, AMD_FAM10_ALL, AMD_PTYPE_ALL,
          0x00001000, 0x00001000 },     /* [12] = L3PrivReplEn */
@@ -279,17 +315,113 @@ static const struct {
        u32 mask;
 } fam10_htphy_default[] = {
 
-       { 0x520A, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       /* Errata 344 - Fam10 C2
+        * System software should set bit 6 of F4x1[9C, 94, 8C, 84]_x[78:70, 68:60]. */
+       { 0x60, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+       { 0x61, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+       { 0x62, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+       { 0x63, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+       { 0x64, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+       { 0x65, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+       { 0x66, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+       { 0x67, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+       { 0x68, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+
+       { 0x70, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+       { 0x71, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+       { 0x72, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+       { 0x73, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+       { 0x74, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+       { 0x75, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+       { 0x76, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+       { 0x77, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+       { 0x78, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+
+       /* Errata 354 - Fam10 C2
+        * System software should set bit 6 of F4x1[9C,94,8C,84]_x[58:50, 48:40] for all links. */
+       { 0x40, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+       { 0x41, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+       { 0x42, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+       { 0x43, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+       { 0x44, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+       { 0x45, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+       { 0x46, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+       { 0x47, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+       { 0x48, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+
+       { 0x50, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+       { 0x51, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+       { 0x52, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+       { 0x53, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+       { 0x54, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+       { 0x55, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+       { 0x56, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+       { 0x57, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+       { 0x58, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00000040, 0x00000040 },
+
+       /* Errata 327 - Fam10 C2
+        * BIOS should set the Link Phy Impedance Register[RttCtl]
+        * (F4x1[9C, 94, 8C, 84]_x[D0, C0][31:29]) to 010b and
+        * Link Phy Impedance Register[RttIndex]
+        * (F4x1[9C, 94, 8C, 84]_x[D0, C0][20:16]) to 00100b */
+       { 0xC0, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x40040000, 0xe01F0000 },
+       { 0xD0, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x40040000, 0xe01F0000 },
+
+       { 0x520A, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00004000, 0x00006000 },     /* HT_PHY_DLL_REG */
+
+       { 0x530A, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x00004000, 0x00006000 },     /* HT_PHY_DLL_REG */
+
+       { 0x520A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00004400, 0x00006400 },     /* HT_PHY_DLL_REG */
 
-       { 0x530A, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x530A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00004400, 0x00006400 },     /* HT_PHY_DLL_REG */
 
-       { 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
          0x00000000, 0x000000FF },     /* Provide clear setting for logical
                                           completeness */
 
-       { 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
          0x00000000, 0x000000FF },     /* Provide clear setting for logical
                                           completeness */
 
@@ -315,4 +447,8 @@ static const struct {
        { 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
          0x04020000, 0x3FFFC000 },     /* [29:22] LfcMax = 10h,
                                           [21:14] LfcMin = 08h */
+
+       { 0xC0, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+         0x40040000, 0xe01F0000 },     /* [31:29] RttCtl = 02h,
+                                                                  [20:16] RttIndex = 04h */
 };