Unify DIMM SPD addressing. For Geode, change the

addressing scheme to match the rest of the tree
(0x50 instead of 0xa0).

abuild tested.

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/include/spd.h b/src/include/spd.h
index 53031c12e4476e357faf2af9e71211588f9c0be8..8aaad6b25dae78cd5df130b2d7264c4e6d7312a5 100644 (file)
--- a/src/include/spd.h
+++ b/src/include/spd.h
@@ -156,5 +156,15 @@
 #define MODULE_BUFFERED                  1
 #define MODULE_REGISTERED                2
 
+/* DIMM SPD addresses */
+#define DIMM0                            0x50
+#define DIMM1                            0x51
+#define DIMM2                            0x52
+#define DIMM3                            0x53
+#define DIMM4                            0x54
+#define DIMM5                            0x55
+#define DIMM6                            0x56
+#define DIMM7                            0x57
+
 #endif /* _SPD_H_ */
 

diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c
index 0f2ec7fce0b0f66ffc84f70a4d1e8af4376812c6..8977b27bd42fa146528907bdc10629e7cbd25fbf 100644 (file)
--- a/src/mainboard/amd/db800/romstage.c
+++ b/src/mainboard/amd/db800/romstage.c
@@ -30,6 +30,7 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
@@ -45,8 +46,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #define ManualConf 0           /* Do automatic strapped PLL config */
 #define PLLMSRhi 0x000005DD    /* Manual settings for the PLL */
 #define PLLMSRlo 0x00DE60EE
-#define DIMM0 0xA0
-#define DIMM1 0xA2
 
 #include "northbridge/amd/lx/raminit.h"
 #include "northbridge/amd/lx/pll_reset.c"

diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c
index 8c8978785c3af91d21a82d62a3bb913e13fa8d45..94d4fc457a0ca80904e845c72982276f66104cbb 100644 (file)
--- a/src/mainboard/amd/dbm690t/romstage.c
+++ b/src/mainboard/amd/dbm690t/romstage.c
@@ -20,9 +20,6 @@
 #define RC0 (6<<8)
 #define RC1 (7<<8)
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-
 #define SMBUS_HUB 0x71
 
 #include <stdint.h>
@@ -43,6 +40,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
+#include <spd.h>
 
 #include <usbdebug.h>
 

diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
index 39e6675496035d062f5851677668a09bd85e5d3b..d4d70abcea5011132c12d95992b9833b14f78353 100644 (file)
--- a/src/mainboard/amd/mahogany/romstage.c
+++ b/src/mainboard/amd/mahogany/romstage.c
@@ -20,9 +20,6 @@
 #define RC0 (6<<8)
 #define RC1 (7<<8)
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-
 #define SMBUS_HUB 0x71
 
 #include <stdint.h>
@@ -34,6 +31,7 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
+#include <spd.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"

diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 3e6466e72c32b89a51539f9f20129b9b3a9652f4..abb2a114f8e5028fb70f4f647a83576f8d4d6cfb 100644 (file)
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -57,6 +57,7 @@ static int smbus_read_byte(u32 device, u32 address);
 #include "southbridge/amd/rs780/rs780_early_setup.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
+#include <spd.h>
 
 static void activate_spd_rom(const struct mem_controller *ctrl)
 {
@@ -90,11 +91,6 @@ static int spd_read_byte(u32 device, u32 address)
 #define RC00  0
 #define RC01  1
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 

diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c
index e957d7ea946400edd70282c2f84cbf535f462a46..1211610421030da224f3263cce5c41f73e362963 100644 (file)
--- a/src/mainboard/amd/norwich/romstage.c
+++ b/src/mainboard/amd/norwich/romstage.c
@@ -30,6 +30,7 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
+#include <spd.h>
 
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
@@ -42,8 +43,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #define ManualConf 0           /* Do automatic strapped PLL config */
 #define PLLMSRhi 0x00001490    /* manual settings for the PLL */
 #define PLLMSRlo 0x02000030
-#define DIMM0 0xA0
-#define DIMM1 0xA2
 
 #include "northbridge/amd/lx/raminit.h"
 #include "northbridge/amd/lx/pll_reset.c"

diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c
index 740b148f7e51efb48e3c5e875681c84cc4e112f0..f1f61c3d0cbcd71e895ee68fa37254fa42ae9981 100644 (file)
--- a/src/mainboard/amd/pistachio/romstage.c
+++ b/src/mainboard/amd/pistachio/romstage.c
@@ -17,9 +17,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -39,6 +36,7 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 #include <usbdebug.h>
+#include <spd.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"

diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c
index f8cd775f024a01416e51cb331d3fa252978012cc..e08d967471214e97f3bbaca2c26227a26a1019f1 100644 (file)
--- a/src/mainboard/amd/rumba/romstage.c
+++ b/src/mainboard/amd/rumba/romstage.c
@@ -9,15 +9,13 @@
 #include "cpu/x86/msr.h"
 #include <cpu/amd/gx2def.h>
 #include <cpu/amd/geode_post_code.h>
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 
-#define DIMM0 0xA0
-#define DIMM1 0xFF /* DIMM1 is not available/used on this board. */
-
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
        if (device != DIMM0)

diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
index 24a4bf44f8a3a278b43ee8a15e86c7138f4f9b90..40f6b7be1c60cfeb55fca940c2a1852d92f1c445 100644 (file)
--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c
@@ -92,22 +92,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "resourcemap.c"
 
 #include "cpu/amd/dualcore/dualcore.c"
+#include <spd.h>
 
 #define RC0 ((1<<0)<<8)
 #define RC1 ((1<<1)<<8)
 #define RC2 ((1<<2)<<8)
 #define RC3 ((1<<3)<<8)
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-#define DIMM4 0x54
-#define DIMM5 0x55
-#define DIMM6 0x56
-#define DIMM7 0x57
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"

diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index eef7c8c46668d155718d8dc00665ad6a4a298dcc..c73a07c357b34336715911c5d90d5cd8fef9c9fc 100644 (file)
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -84,17 +84,13 @@ static int spd_read_byte(u32 device, u32 address)
 
 #include "northbridge/amd/amdfam10/early_ht.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
+#include <spd.h>
 
 //#include "spd_addr.h"
 
 #define RC00  0
 #define RC01  1
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 

diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c
index dc4e3ffe26d254dcc3b7365e804fd7af7b27072b..8303b15f4970b16294e9aa52c5d9dc2c9417b0e8 100644 (file)
--- a/src/mainboard/artecgroup/dbe61/romstage.c
+++ b/src/mainboard/artecgroup/dbe61/romstage.c
@@ -32,13 +32,11 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include "spd_table.h"
+#include <spd.h>
 
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 
-#define DIMM0 0xA0
-#define DIMM1 0xA2
-
 static int spd_read_byte(unsigned device, unsigned address)
 {
        int i;

diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
index da0f9ac92de94c5a02b5c848cae2585608fb7529..7fb3227661f6145f8ae2749101c9ad01c6679ac9 100644 (file)
--- a/src/mainboard/asrock/939a785gmh/romstage.c
+++ b/src/mainboard/asrock/939a785gmh/romstage.c
@@ -21,9 +21,6 @@
 #define RC0 (6<<8)
 #define RC1 (7<<8)
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-
 #define SMBUS_HUB 0x71
 
 #include <stdint.h>
@@ -40,6 +37,7 @@
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
+#include <spd.h>
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"

diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 46b16a3fc5c9dc8f5c787ae68a7ed8ec9e364f18..f6e242b8eac8175011015cf76c00b244260b1484 100644 (file)
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -84,17 +84,13 @@ static int spd_read_byte(u32 device, u32 address)
 
 #include "northbridge/amd/amdfam10/early_ht.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
+#include <spd.h>
 
 //#include "spd_addr.h"
 
 #define RC00  0
 #define RC01  1
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 

diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c
index f55f26567452daacf887c1660fdc778257ed42f1..0a4bc19437251938ad39517d25d7e2c09737c1ad 100644 (file)
--- a/src/mainboard/broadcom/blast/romstage.c
+++ b/src/mainboard/broadcom/blast/romstage.c
@@ -70,16 +70,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "resourcemap.c"
 
 #include "cpu/amd/dualcore/dualcore.c"
+#include <spd.h>
 
 #define RC0 (6<<8)
 #define RC1 (7<<8)
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"

diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c
index 3b2d8f1dbb1dd6a6f742f01152ebaa34e4d99449..6cf6ec6f19f3afb982b980b266bbc7956b3c5b0a 100644 (file)
--- a/src/mainboard/digitallogic/msm800sev/romstage.c
+++ b/src/mainboard/digitallogic/msm800sev/romstage.c
@@ -11,6 +11,7 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
@@ -26,8 +27,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #define ManualConf 0           /* Do automatic strapped PLL config */
 #define PLLMSRhi 0x00001490 /* manual settings for the PLL */
 #define PLLMSRlo 0x02000030
-#define DIMM0 0xA0
-#define DIMM1 0xA2
 #include "northbridge/amd/lx/raminit.h"
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"

diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index 7656d4f12b2aed406711785f8f372b3727c88200..3286e028f440bcd606ea8f88f6a49cf3e1da38d9 100644 (file)
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -80,16 +80,12 @@ static int spd_read_byte(u32 device, u32 address)
 
 #include "northbridge/amd/amdfam10/early_ht.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
+#include <spd.h>
 
 
 #define RC00  0
 #define RC01  1
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 

diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index 555b447a70cb4fc4bb160f095e037f04d2cd04a3..a61be0a9ab7fa4be6db9e2c27fd658d11b08f216 100644 (file)
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -84,16 +84,12 @@ static int spd_read_byte(u32 device, u32 address)
 
 #include "northbridge/amd/amdfam10/early_ht.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
+#include <spd.h>
 
 
 #define RC00  0
 #define RC01  1
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 

diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c
index 2ba791871cbf9970455b86e60f8d887bf023dc62..f5fdf35eb9c4366ab36f70c3a9e485718750d7fd 100644 (file)
--- a/src/mainboard/hp/dl145_g1/romstage.c
+++ b/src/mainboard/hp/dl145_g1/romstage.c
@@ -92,15 +92,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 
 #include "cpu/amd/dualcore/dualcore.c"
+#include <spd.h>
 
 #define RC0 ((1<<1)<<8) // Not sure about these values
 #define RC1 ((1<<2)<<8) // Not sure about these values
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"

diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c
index ca869d2275c745d3498740e03a5aab26d2cd20eb..d2e393cbe137759cf0099010c2c454990b19d468 100644 (file)
--- a/src/mainboard/hp/dl145_g3/romstage.c
+++ b/src/mainboard/hp/dl145_g3/romstage.c
@@ -92,22 +92,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"
 #include "lib/generic_sdram.c"
+#include <spd.h>
 
 #include "cpu/amd/dualcore/dualcore.c"
 
-//first node
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-//second node
-#define DIMM4 0x54
-#define DIMM5 0x55
-#define DIMM6 0x56
-#define DIMM7 0x57
-
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"

diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index 6656977bd444a237a8f0c95970f88fbbe8102b74..e92f29d26c57f755756f4d9a27fc53d86a240226 100644 (file)
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -87,17 +87,13 @@ static int spd_read_byte(u32 device, u32 address)
 
 #include "northbridge/amd/amdfam10/early_ht.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
+#include <spd.h>
 
 //#include "spd_addr.h"
 
 #define RC00  0
 #define RC01  1
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 

diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
index e3351f12949f978b8c0182e5b675a56a46dcee2d..8412e3317084673c3646b8ca31b04c448ded6d09 100644 (file)
--- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
+++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
@@ -30,6 +30,7 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
@@ -50,9 +51,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 /* Hold Count - how long we will sit in reset */
 #define PLLMSRlo 0x00DE6000
 
-#define DIMM0 0xA0
-#define DIMM1 0xA2
-
 #include "northbridge/amd/lx/raminit.h"
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"

diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c
index da48be39b9443b817187a21a2847e172bbba21f0..105b82115c85fb41487c45b6faab67b14d945bac 100644 (file)
--- a/src/mainboard/intel/truxton/romstage.c
+++ b/src/mainboard/intel/truxton/romstage.c
@@ -37,7 +37,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "superio/intel/i3100/i3100_early_serial.c"
 #include "cpu/x86/bist.h"
-#include "spd.h"
+#include <spd.h>
 
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0)
 

diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c
index c40a69de7c789adb5bc43d1777fdb7092bf73e54..be3017d27def87d588638353cc5d89c6cc7de86f 100644 (file)
--- a/src/mainboard/iwill/dk8_htx/romstage.c
+++ b/src/mainboard/iwill/dk8_htx/romstage.c
@@ -81,15 +81,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "resourcemap.c"
 
 #include "cpu/amd/dualcore/dualcore.c"
-
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-#define DIMM4 0x54
-#define DIMM5 0x55
-#define DIMM6 0x56
-#define DIMM7 0x57
+#include <spd.h>
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 

diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c
index b15643adaad065ad3c812fbb3f983cfe34cebdd3..2d4efe27a1ab6cd334817d4fddc4bb47982652ab 100644 (file)
--- a/src/mainboard/iwill/dk8s2/romstage.c
+++ b/src/mainboard/iwill/dk8s2/romstage.c
@@ -81,15 +81,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/resourcemap.c"
 
 #include "cpu/amd/dualcore/dualcore.c"
-
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-#define DIMM4 0x54
-#define DIMM5 0x55
-#define DIMM6 0x56
-#define DIMM7 0x57
+#include <spd.h>
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 

diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c
index b15643adaad065ad3c812fbb3f983cfe34cebdd3..2d4efe27a1ab6cd334817d4fddc4bb47982652ab 100644 (file)
--- a/src/mainboard/iwill/dk8x/romstage.c
+++ b/src/mainboard/iwill/dk8x/romstage.c
@@ -81,15 +81,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/resourcemap.c"
 
 #include "cpu/amd/dualcore/dualcore.c"
-
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-#define DIMM4 0x54
-#define DIMM5 0x55
-#define DIMM6 0x56
-#define DIMM7 0x57
+#include <spd.h>
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 

diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 35cf8436929808e69e91df2675dd2a731d509d2f..6944fcc302e0a8c0c2162ef5910eb5bdc9fffda5 100644 (file)
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -92,17 +92,11 @@ static int spd_read_byte(u32 device, u32 address)
 
 #include "northbridge/amd/amdfam10/early_ht.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
-
-
+#include <spd.h>
 
 #define RC00  0
 #define RC01  1
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 

diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c
index 2545b084117695f6e5f44da3eeebdaaabc416283..29b2b1477a7f28dc6c5d56fda9d0d03965131675 100644 (file)
--- a/src/mainboard/kontron/kt690/romstage.c
+++ b/src/mainboard/kontron/kt690/romstage.c
@@ -21,9 +21,6 @@
 #define RC0 (6<<8)
 #define RC1 (7<<8)
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-
 #define SMBUS_HUB 0x71
 
 #include <stdint.h>
@@ -40,6 +37,7 @@
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
+#include <spd.h>
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"

diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c
index f86abef5a5c844d91afeb3aa58efaffbf1750d1a..2b3ebe2d85a8eb784e9ad6391cc9f11d37d55d71 100644 (file)
--- a/src/mainboard/lippert/frontrunner/romstage.c
+++ b/src/mainboard/lippert/frontrunner/romstage.c
@@ -11,15 +11,13 @@
 #include <cpu/amd/gx2def.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5535/cs5535.h"
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
 #include "southbridge/amd/cs5535/cs5535_early_smbus.c"
 #include "southbridge/amd/cs5535/cs5535_early_setup.c"
 
-#define DIMM0 0xA0
-#define DIMM1 0xFF /* DIMM1 is not available/used on this board. */
-
 static const unsigned char spdbytes[] = {      /* 4x Qimonda HYB25DC512160CF-6 */
        0xFF, 0xFF,                             /* only values used by raminit.c are set */
        [SPD_MEMORY_TYPE]               = SPD_MEMORY_TYPE_SDRAM_DDR,    /* (Fundamental) memory type */

diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c
index b7314bf06f7cc3c0a310df7c1d709a179bce169d..bc6cae005323fb2a82e2adcefea4c6ecdd8ad729 100644 (file)
--- a/src/mainboard/lippert/hurricane-lx/romstage.c
+++ b/src/mainboard/lippert/hurricane-lx/romstage.c
@@ -33,6 +33,7 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
+#include <spd.h>
 
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
@@ -44,8 +45,6 @@
 #define ManualConf 1           /* No automatic strapped PLL config */
 #define PLLMSRhi 0x0000049C    /* Manual settings for the PLL */
 #define PLLMSRlo 0x00DE6001
-#define DIMM0 0xA0
-#define DIMM1 0xA2
 
 static inline int spd_read_byte(unsigned int device, unsigned int address)
 {

diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c
index 9052cb39c283b510049f225e4fa9cf6162467a85..38bac67728566bf95f7297c59b62d4f54e111d66 100644 (file)
--- a/src/mainboard/lippert/literunner-lx/romstage.c
+++ b/src/mainboard/lippert/literunner-lx/romstage.c
@@ -34,6 +34,7 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
+#include <spd.h>
 
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
@@ -49,8 +50,6 @@
 #define ManualConf 1           /* No automatic strapped PLL config */
 #define PLLMSRhi 0x0000059C    /* Manual settings for the PLL */
 #define PLLMSRlo 0x00DE6001
-#define DIMM0 0xA0
-#define DIMM1 0xA2
 
 static const unsigned char spdbytes[] = {      // 4x Promos V58C2512164SA-J5I
        0xFF, 0xFF,                             // only values used by Geode-LX raminit.c are set

diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c
index 11524c4f4c5a38a2922e46842d80004a937abccd..086a61d8f1f0dd2778466ba80f679b100bc9c33b 100644 (file)
--- a/src/mainboard/lippert/roadrunner-lx/romstage.c
+++ b/src/mainboard/lippert/roadrunner-lx/romstage.c
@@ -33,6 +33,7 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
+#include <spd.h>
 
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
@@ -41,8 +42,6 @@
 #define ManualConf 1           /* No automatic strapped PLL config */
 #define PLLMSRhi 0x0000049C    /* Manual settings for the PLL */
 #define PLLMSRlo 0x00DE6001
-#define DIMM0 0xA0
-#define DIMM1 0xA2
 
 static inline int spd_read_byte(unsigned int device, unsigned int address)
 {

diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c
index 2992bcc9db2d9f0c9a7e68faa6baa39f77566816..cc9e7fda98bdfe95731f36da698da7c0f8be9c0b 100644 (file)
--- a/src/mainboard/lippert/spacerunner-lx/romstage.c
+++ b/src/mainboard/lippert/spacerunner-lx/romstage.c
@@ -34,6 +34,7 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
+#include <spd.h>
 
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
@@ -49,8 +50,6 @@
 #define ManualConf 1           /* No automatic strapped PLL config */
 #define PLLMSRhi 0x0000059C    /* Manual settings for the PLL */
 #define PLLMSRlo 0x00DE6001
-#define DIMM0 0xA0
-#define DIMM1 0xA2
 
 static const unsigned char spdbytes[] = {      // 4x Promos V58C2512164SA-J5I
        0xFF, 0xFF,                             // only values used by Geode-LX raminit.c are set

diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c
index 0fa6a65d869afe638b6bc8bb25b2d167a9586f8e..74ec60af0a8732984a84bc353cabdef8e76907ef 100644 (file)
--- a/src/mainboard/msi/ms9185/romstage.c
+++ b/src/mainboard/msi/ms9185/romstage.c
@@ -93,19 +93,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "resourcemap.c"
 
 #include "cpu/amd/dualcore/dualcore.c"
+#include <spd.h>
 
 #define RC0 (0x10<<8)
 #define RC1 (0x01<<8)
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-#define DIMM4 0x54
-#define DIMM5 0x55
-#define DIMM6 0x56
-#define DIMM7 0x57
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"

diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c
index f0c4ed63254bc984bcd46b40f8cc79cf7b130078..4b7d0fde044a61603e87bccc52bbde3676dc9a0d 100644 (file)
--- a/src/mainboard/pcengines/alix1c/romstage.c
+++ b/src/mainboard/pcengines/alix1c/romstage.c
@@ -32,6 +32,7 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
@@ -106,9 +107,6 @@ static u8 spd_read_byte(u8 device, u8 address)
 #define PLLMSRhi       0x00001490      /* Manual settings for the PLL */
 #define PLLMSRlo       0x02000030
 
-#define DIMM0          0xa0
-#define DIMM1          0xa2
-
 #include "northbridge/amd/lx/raminit.h"
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"

diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c
index 10ab27d6627ef0afda622f6d3bd2f1cc1e8b7f83..44e14ac7ec23954fe9c38472978d422f672fb2df 100644 (file)
--- a/src/mainboard/pcengines/alix2d/romstage.c
+++ b/src/mainboard/pcengines/alix2d/romstage.c
@@ -32,6 +32,7 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
@@ -105,9 +106,6 @@ static u8 spd_read_byte(u8 device, u8 address)
 #define PLLMSRhi       0x00001490      /* Manual settings for the PLL */
 #define PLLMSRlo       0x02000030
 
-#define DIMM0          0xa0
-#define DIMM1          0xa2
-
 #include "northbridge/amd/lx/raminit.h"
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"

diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c
index 05ce74da3a17e72dc9fc5ac90fe3fd55fa7cbfb6..de86013b5d2c75cc62fcb37a5f5b7d5312e1dc2c 100644 (file)
--- a/src/mainboard/technexion/tim5690/romstage.c
+++ b/src/mainboard/technexion/tim5690/romstage.c
@@ -20,9 +20,6 @@
 #define RC0 (6<<8)
 #define RC1 (7<<8)
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-
 #define SMBUS_HUB 0x71
 
 #include <stdint.h>
@@ -39,6 +36,7 @@
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
+#include <spd.h>
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"

diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c
index 44c02fb0c8269605aef82455061558eb837f63d0..c97cd6b4d3c90c52d0acd66ba9689f96e560ecd8 100644 (file)
--- a/src/mainboard/technexion/tim8690/romstage.c
+++ b/src/mainboard/technexion/tim8690/romstage.c
@@ -20,9 +20,6 @@
 #define RC0 (6<<8)
 #define RC1 (7<<8)
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-
 #define SMBUS_HUB 0x71
 
 #include <stdint.h>
@@ -39,6 +36,7 @@
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
+#include <spd.h>
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"

diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c
index d5a00a4cbe247fccffccf9067531865d40389771..b3aff80af41f4ced08a1602a882c8732b551d985 100644 (file)
--- a/src/mainboard/traverse/geos/romstage.c
+++ b/src/mainboard/traverse/geos/romstage.c
@@ -31,6 +31,7 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
+#include <spd.h>
 
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
@@ -43,8 +44,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #define ManualConf 1           /* Do automatic strapped PLL config */
 #define PLLMSRhi 0x0000059C    /* manual settings for the PLL */
 #define PLLMSRlo 0x00DE602E
-#define DIMM0 0xA0
-#define DIMM1 0xA2
 
 #include "northbridge/amd/lx/raminit.h"
 #include "northbridge/amd/lx/pll_reset.c"

diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c
index 9fc43beb65b88f534273de506d2431c4c3c70887..157b14a3a688f72a4a4618ddf28da95ca4d5ca4c 100644 (file)
--- a/src/mainboard/tyan/s4880/romstage.c
+++ b/src/mainboard/tyan/s4880/romstage.c
@@ -84,19 +84,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "resourcemap.c"
 
 #include "cpu/amd/dualcore/dualcore.c"
+#include <spd.h>
 
 #define RC0 ((1<<2)<<8)
 #define RC1 ((1<<1)<<8)
 #define RC2 ((1<<4)<<8)
 #define RC3 ((1<<3)<<8)
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"

diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c
index f0c94f9b058af5ae1a0d003fc12980ee73ce7174..ec5e1ddad91790efc80231859f740759b1b3190d 100644 (file)
--- a/src/mainboard/tyan/s4882/romstage.c
+++ b/src/mainboard/tyan/s4882/romstage.c
@@ -92,19 +92,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "resourcemap.c"
 
 #include "cpu/amd/dualcore/dualcore.c"
+#include <spd.h>
 
 #define RC0 ((1<<2)<<8)
 #define RC1 ((1<<1)<<8)
 #define RC2 ((1<<4)<<8)
 #define RC3 ((1<<3)<<8)
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"

diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c
index 76428c5357be33d7cfabada53d7b5ddbd842d42d..6d081e94576ac4d553724f62a1fe01268429f520 100644 (file)
--- a/src/mainboard/winent/pl6064/romstage.c
+++ b/src/mainboard/winent/pl6064/romstage.c
@@ -32,6 +32,7 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
@@ -47,8 +48,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #define ManualConf 0           /* Do automatic strapped PLL config */
 #define PLLMSRhi 0x00001490    /* Manual settings for the PLL */
 #define PLLMSRlo 0x02000030
-#define DIMM0 0xA0
-#define DIMM1 0xA2
 
 #include "northbridge/amd/lx/raminit.h"
 #include "northbridge/amd/lx/pll_reset.c"

diff --git a/src/mainboard/wyse/s50/romstage.c b/src/mainboard/wyse/s50/romstage.c
index 657667cfe8a130d8d65dff859f9ca55901d5c6a1..d2724964629372dbb1aec3d4197a95666ad57ad8 100644 (file)
--- a/src/mainboard/wyse/s50/romstage.c
+++ b/src/mainboard/wyse/s50/romstage.c
@@ -30,13 +30,11 @@
 #include "cpu/x86/msr.h"
 #include <cpu/amd/gx2def.h>
 #include <cpu/amd/geode_post_code.h>
+#include <spd.h>
 
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 
-#define DIMM0 0xA0
-#define DIMM1 0xFF /* DIMM1 is not available/used on this board. */
-
 static inline int spd_read_byte(unsigned int device, unsigned int address)
 {
        if (device != DIMM0)

diff --git a/src/northbridge/via/cx700/cx700_early_smbus.c b/src/northbridge/via/cx700/cx700_early_smbus.c
index b1d6344f6d80e8eefe1a125a8e18c45e132aeda8..4766e59a293f944219a0165890369d15119dd814 100644 (file)
--- a/src/northbridge/via/cx700/cx700_early_smbus.c
+++ b/src/northbridge/via/cx700/cx700_early_smbus.c
@@ -37,7 +37,6 @@
 
 /* Define register settings */
 #define HOST_RESET             0xff
-#define DIMM_BASE              0xa0    // 1010000 is base for DIMM in SMBus
 #define READ_CMD               0x01    // 1 in the 0 bit of SMBHSTADD states to READ
 
 #define SMBUS_TIMEOUT          (100*1000*10)

diff --git a/src/northbridge/via/vx800/vx800_early_smbus.c b/src/northbridge/via/vx800/vx800_early_smbus.c
index b8a3ef772ee465dd3cdc7737a15266da662a8781..421716cb6cd6eeac422004adf1879cd9e86c72d1 100644 (file)
--- a/src/northbridge/via/vx800/vx800_early_smbus.c
+++ b/src/northbridge/via/vx800/vx800_early_smbus.c
@@ -40,7 +40,6 @@
 
 /* Define register settings */
 #define HOST_RESET     0xff
-#define DIMM_BASE              0xa0    // 1010000 is base for DIMM in SMBus
 #define READ_CMD               0x01    // 1 in the 0 bit of SMBHSTADD states to READ
 
 #define SMBUS_TIMEOUT          (100*1000*10)
@@ -121,9 +120,7 @@ static unsigned int get_spd_data(unsigned int dimm, unsigned int offset)
        smbus_wait_until_ready();
 
        /* Do some mathmatic magic */
-       dimm = (dimm << 1);
-       dimm &= 0x0E;
-       dimm |= 0xA0;
+       dimm = (DIMM0 + dimm) << 1;
 
        outb(dimm | 0x1, SMBXMITADD);
        outb(offset, SMBHSTCMD);

diff --git a/src/southbridge/amd/cs5536/cs5536_early_smbus.c b/src/southbridge/amd/cs5536/cs5536_early_smbus.c
index ce8e690567e33ae268a3c37f686998e7506eb4b3..5cb815d2509639b6daef63b311744a81dccd8189 100644 (file)
--- a/src/southbridge/amd/cs5536/cs5536_early_smbus.c
+++ b/src/southbridge/amd/cs5536/cs5536_early_smbus.c
@@ -165,7 +165,7 @@ static unsigned char do_smbus_read_byte(unsigned smbus_io_base,
                goto err;
        }
 
-       if ((smbus_send_slave_address(smbus_io_base, device))) {
+       if ((smbus_send_slave_address(smbus_io_base, device << 1))) {
                error = 3;
                goto err;
        }
@@ -182,7 +182,7 @@ static unsigned char do_smbus_read_byte(unsigned smbus_io_base,
                goto err;
        }
 
-       if ((smbus_send_slave_address(smbus_io_base, device | 0x01))) {
+       if ((smbus_send_slave_address(smbus_io_base, (device << 1) | 0x01))) {
                error = 6;
                goto err;
        }

diff --git a/src/southbridge/via/vt8231/vt8231_early_smbus.c b/src/southbridge/via/vt8231/vt8231_early_smbus.c
index 8ba72a387b1146610425a82364d7a862c3589222..7bf1267b75979e16184c58c0b3048ff1b965d6cf 100644 (file)
--- a/src/southbridge/via/vt8231/vt8231_early_smbus.c
+++ b/src/southbridge/via/vt8231/vt8231_early_smbus.c
@@ -16,7 +16,6 @@
 
 /* Define register settings */
 #define HOST_RESET 0xff
-#define DIMM_BASE 0xa0         // 1010000 is base for DIMM in SMBus
 #define READ_CMD  0x01         // 1 in the 0 bit of SMBHSTADD states to READ
 
 

diff --git a/src/southbridge/via/vt8235/vt8235_early_smbus.c b/src/southbridge/via/vt8235/vt8235_early_smbus.c
index 1876461a3ddc6d6000d46701d57dd7c8af75b6be..7b9d55dced65e182927cf531161871cc5c919160 100644 (file)
--- a/src/southbridge/via/vt8235/vt8235_early_smbus.c
+++ b/src/southbridge/via/vt8235/vt8235_early_smbus.c
@@ -16,7 +16,6 @@
 
 /* Define register settings */
 #define HOST_RESET 0xff
-#define DIMM_BASE 0xa0        // 1010000 is base for DIMM in SMBus
 #define READ_CMD  0x01        // 1 in the 0 bit of SMBHSTADD states to READ