#include <cpu/cpu.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/cache.h>
-#include <cpu/amd/lxdef.h>
static void vsm_end_post_smi(void)
{
static void model_lx_init(device_t dev)
{
-
- msr_t msr;
-
printk_debug("model_lx_init\n");
/* Turn on caching if we haven't already */
- /* Instruction Memory Configuration register
- * set EBE bit, required when L2 cache is enabled
- */
- msr = rdmsr(CPU_IM_CONFIG);
- msr.lo |= 0x400;
- wrmsr(CPU_IM_CONFIG, msr);
-
- /* Data Memory Subsystem Configuration register
- * set EVCTONRPL bit, required when L2 cache is enabled in victim mode
- */
- msr = rdmsr(CPU_DM_CONFIG0);
- msr.lo |= 0x4000;
- wrmsr(CPU_DM_CONFIG0, msr);
-
- /* invalidate L2 cache */
- msr.hi = 0x00;
- msr.lo = 0x10;
- wrmsr(L2_CONFIG_MSR, msr);
-
- /* Enable L2 cache */
- msr.hi = 0x00;
- msr.lo = 0x0f;
- wrmsr(L2_CONFIG_MSR, msr);
-
x86_enable_cache();
/* Enable the local cpu apics */
#define RCONF_DMM_LOWER_RCNORM_SHIFT 0
#define RCONF_DMM_LOWER_EN_SET (1<<8)
+
+
+/* ----- GX3 OK ---- */
+
#define CPU_RCONF0 0x1810
#define CPU_RCONF1 0x1811
#define CPU_RCONF2 0x1812
#define CPU_RCONF5 0x1815
#define CPU_RCONF6 0x1816
#define CPU_RCONF7 0x1817
+
+/* ------------------------ */
+
+/* ----- GX3 OK ---- */
+
#define CPU_CR1_MSR 0x1881
#define CPU_CR2_MSR 0x1882
#define CPU_CR3_MSR 0x1883
#define CPU_CR4_MSR 0x1884
+
+/* ------------------------ */
+
+/* ----- GX3 OK ---- */
+
#define CPU_DC_INDEX 0x1890
#define CPU_DC_DATA 0x1891
#define CPU_DC_TAG 0x1892
#define CPU_DTB_LRU 0x1899
#define CPU_DTB_ENTRY 0x189A
#define CPU_DTB_ENTRY_I 0x189B
+
+/* ------------------------ */
+
#define CPU_L2TB_INDEX 0x189C
#define CPU_L2TB_LRU 0x189D
#define CPU_L2TB_ENTRY 0x189E
config chip.h
chip northbridge/amd/lx
- register "irqmap" = "0xcab9"
- register "setupflash" = "0"
+ register "irqmap" = "0xcba5"
+ register "setupflash" = "1"
device apic_cluster 0 on
chip cpu/amd/model_lx
device apic 0 on end
register "enable_gpio0_inta" = "1"
register "enable_ide_nand_flash" = "1"
register "enable_uarta" = "1"
- register "audio_irq" = "5"
- register "usbf4_irq" = "10"
- register "usbf5_irq" = "10"
- register "usbf6_irq" = "0"
- register "usbf7_irq" = "0"
+ register "audio_irq" = "11"
+ register "usbf4_irq" = "5"
+ register "usbf5_irq" = "5"
+ register "usbf6_irq" = "5"
+ register "usbf7_irq" = "5"
device pci d.0 on end # Realtek 8139 LAN
device pci f.0 on end # ISA Bridge
device pci f.2 on end # IDE Controller
device pci f.3 on end # Audio
device pci f.4 on end # OHCI
device pci f.5 on end # EHCI
- register "unwanted_vpci[0]" = "0x80007E00" # USB/UDC
- register "unwanted_vpci[1]" = "0x80007F00" # USB/OTG
- register "unwanted_vpci[2]" = "0" # End of list has a zero
+ register "unwanted_vpci[0]" = "0" # End of list has a zero
end
end
end
##
## Build code to export a programmable irq routing table
##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=2
+default HAVE_PIRQ_TABLE=0
+default IRQ_SLOT_COUNT=6
+
#object irq_tables.o
##
## The default compiler
##
default CROSS_COMPILE=""
-default CC="$(CROSS_COMPILE)gcc-3.4 -m32"
-default HOSTCC="gcc-3.4"
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
##
## The Serial Console
#include <arch/pirq_routing.h>
-const struct irq_routing_table intel_irq_routing_table = {
+#define ID_SLOT_PCI_NET 1 // ThinCan ethernet
+#define ID_SLOT_PCI_RSVD1 2 // reserved entry 1
+#define ID_SLOT_PCI_RSVD3 3 // reserved entry 2
+#define ID_SLOT_PCI_RSVD2 4 // reserved entry 3
+#define ID_EMBED_PCI 0xff // onboard PCI device
+
+// CS5535 PCI INT[A-D] Interrupt Routing lines.
+#define NO_CONNECT 0 // not used
+#define CS_PCI_INTA 1 // PCI INTA
+#define CS_PCI_INTB 2 // PCI INTB
+#define CS_PCI_INTC 3 // PCI INTC
+#define CS_PCI_INTD 4 // PCI INTD
+
+// IRQ bitmap reference line FEDCBA9876543210
+// 0000110000100000b
+#define PCI_IRQ 0xc20 // PCI allowed IRQs here
+
+const struct irq_routing_table intel_irq_routing_table =
+{
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
- 32+16*2, /* there can be total 2 devices on the bus */
+ 32+16*6, /* there can be total 2 devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
(0x12<<3)|0x0, /* Where the interrupt router lies (dev) */
- 0x800, /* IRQs devoted exclusively to PCI usage */
- 0x1078, /* Vendor */
- 0x2, /* Device */
- 0, /* Crap (miniport) */
+ 0x0800, /* IRQs devoted exclusively to PCI usage */
+ 0x1022, /* Vendor */
+ 0x208f, /* Device */
+ 0x00000000, /* Crap (miniport) */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
{
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00,(0x0e<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
- {0x00,(0x0f<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0},
+ // Geode GX3 Host Bridge and VGA Graphics
+ {0, 0x01<<3, {{CS_PCI_INTA, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}}, ID_EMBED_PCI, 0x0},
+ // Realtek RTL8100/8139 Network Controller
+ {0, 0x0d<<3, {{CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}}, ID_SLOT_PCI_NET, 0x0},
+ // Reserved for future extensions
+ {0, 0x0c<<3, {{CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}}, ID_SLOT_PCI_RSVD1, 0x0},
+ // Geode CS5535/CS5536 IO Companion: USB controllers, IDE, Audio.
+ {0, 0x0f<<3, {{CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}}, ID_EMBED_PCI, 0x0},
+ // Reserved for future extensions
+ {0, 0x0e<<3, {{CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}}, ID_SLOT_PCI_RSVD2, 0x0},
+ // Reserved for future extensions
+ {0, 0x0b<<3, {{CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}}, ID_SLOT_PCI_RSVD3, 0x0}
}
};
+
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr);
#include "chip.h"
-
-static void init(struct device *dev) {
-/*
+static void init(struct device *dev)
+{
unsigned bus = 0;
- unsigned devfn = PCI_DEVFN(0xf, 4);
- device_t usb = NULL;
- unsigned char usbirq = 0xa;
-*/
+ unsigned devNic = PCI_DEVFN(0xd, 0);
+ unsigned devUsb = PCI_DEVFN(0xf, 4);
+ device_t usb = NULL, nic = NULL;
+ unsigned char irqUsb = 0xa, irqNic = 0xb;
printk_debug("ARTECGROUP DBE61 ENTER %s\n", __FUNCTION__);
-#if 0
- /* I can't think of any reason NOT to just set this. If it turns out we want this to be
- * conditional we can make it a config variable later.
- */
-
- printk_debug("%s (%x,%x)SET USB PCI interrupt line to %d\n",
- __FUNCTION__, bus, devfn, usbirq);
- usb = dev_find_slot(bus, devfn);
- if (! usb){
- printk_err("Could not find USB\n");
- } else {
- pci_write_config8(usb, PCI_INTERRUPT_LINE, usbirq);
- }
-#endif
+ // FIXME: do we need to initialize USB OHCI this way?
+ printk_debug("%s (%x,%x) set USB PCI interrupt line to %d\n",
+ __FUNCTION__, bus, devUsb, irqUsb);
+
+ // initialize the USB controller
+ usb = dev_find_slot(bus, devUsb);
+ if (!usb) printk_err("Could not find USB\n");
+ else pci_write_config8(usb, PCI_INTERRUPT_LINE, irqUsb);
+
+ printk_debug("%s (%x,%x) set NIC PCI interrupt line to %d\n",
+ __FUNCTION__, bus, devNic, irqNic);
+
+ // initialize the Realtek NIC
+ nic = dev_find_slot(bus, devNic);
+ if (!nic) printk_err("Could not find USB\n");
+ else pci_write_config8(nic, PCI_INTERRUPT_LINE, irqNic);
+
printk_debug("ARTECGROUP DBE61 EXIT %s\n", __FUNCTION__);
}
#include <bitops.h>
#include "chip.h"
#include "northbridge.h"
+#include <cpu/cpu.h>
#include <cpu/amd/lxdef.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/cache.h>
}
+
+static void enable_L2_cache(void) {
+ msr_t msr;
+
+ /* Instruction Memory Configuration register
+ * set EBE bit, required when L2 cache is enabled
+ */
+ msr = rdmsr(CPU_IM_CONFIG);
+ msr.lo |= 0x400;
+ wrmsr(CPU_IM_CONFIG, msr);
+
+ /* Data Memory Subsystem Configuration register
+ * set EVCTONRPL bit, required when L2 cache is enabled in victim mode
+ */
+ msr = rdmsr(CPU_DM_CONFIG0);
+ msr.lo |= 0x4000;
+ wrmsr(CPU_DM_CONFIG0, msr);
+
+ /* invalidate L2 cache */
+ msr.hi = 0x00;
+ msr.lo = 0x10;
+ wrmsr(L2_CONFIG_MSR, msr);
+
+ /* Enable L2 cache */
+ msr.hi = 0x00;
+ msr.lo = 0x0f;
+ wrmsr(L2_CONFIG_MSR, msr);
+
+ printk_debug("L2 cache enabled\n");
+}
+
+
static void northbridge_init(device_t dev)
{
struct northbridge_amd_lx_config *nb = (struct northbridge_amd_lx_config *)dev->chip_info;
extern void cpubug(void);
printk_debug("DEVICE_PATH_PCI_DOMAIN\n");
/* cpubug MUST be called before setup_lx(), so we force the issue here */
+ enable_L2_cache();
northbridgeinit();
- cpubug();
+ /* cpubug(); GX3*/
chipsetinit(nb);
setup_lx();
/* do this here for now -- this chip really breaks our device model */
#include <cpu/amd/lxdef.h>
-#if 0
+
static void sdram_set_registers(const struct mem_controller *ctrl)
{
}
-#endif
-
-
/* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence
* Section 4.1.4, GX/CS5535 GeodeROM Porting guide */
static void sdram_enable(int controllers, const struct mem_controller *ctrl)
-# Config file for the olpc rev_a
+# Config file for the ThinCan dbe61
target dbe61
mainboard artecgroup/dbe61
-# leave 128k for vsa
+# leave 64k for vsa
option CONFIG_COMPRESSED_ROM_STREAM=0
-option ROM_SIZE=1024*256-128*1024
+option ROM_SIZE=1024*256-64*1024
option FALLBACK_SIZE=ROM_SIZE
option DEFAULT_CONSOLE_LOGLEVEL = 11
projects / coreboot.git / commitdiff