bool
default n
+config HT_CHAIN_UNITID_BASE
+ hex
+ default 0x1
+
+config HT_CHAIN_END_UNITID_BASE
+ hex
+ default 0x20
+
config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
hex
default 0
config SMP
bool
default y if MAX_CPUS != 1
+ default n
config CPU_SOCKET_TYPE
hex
+source src/cpu/via/model_c3/Kconfig
source src/cpu/via/model_c7/Kconfig
source "src/mainboard/jetway/Kconfig"
source "src/mainboard/kontron/Kconfig"
source "src/mainboard/lippert/Kconfig"
+source "src/mainboard/mitac/Kconfig"
source "src/mainboard/motorola/Kconfig"
source "src/mainboard/msi/Kconfig"
source "src/mainboard/nec/Kconfig"
source "src/mainboard/olpc/Kconfig"
source "src/mainboard/pcengines/Kconfig"
source "src/mainboard/rca/Kconfig"
+source "src/mainboard/soyo/Kconfig"
source "src/mainboard/sunw/Kconfig"
source "src/mainboard/supermicro/Kconfig"
source "src/mainboard/technexion/Kconfig"
select CPU_INTEL_SOCKET_PGA370
select NORTHBRIDGE_INTEL_I82810
select SOUTHBRIDGE_INTEL_I82801XX
- select SUPERIO_SMSC_SMSCSUPERIO
+ select SUPERIO_SMSC_LPC47B272
select HAVE_PIRQ_TABLE
select UDELAY_IO
select PCI_ROM_RUN
default "MEW-VM"
depends on BOARD_ASUS_MEW_VM
+config HAVE_OPTION_TABLE
+ bool
+ default n
+ depends on BOARD_ASUS_MEW_VM
+
config IRQ_SLOT_COUNT
int
default 11
select CPU_INTEL_SLOT_2
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
- select SUPERIO_NSC_PC97307
+ # should be SUPERIO_NSC_PC97307!
+ select SUPERIO_NSC_PC97317
select HAVE_PIRQ_TABLE
select UDELAY_IO
select PCI_ROM_RUN
prompt "Mainboard model"
depends on VENDOR_EMULATION
-config BOARD_EMULATION_QEMU_X86
- bool "QEMU x86"
- select ARCH_X86
- select CPU_I586
- select SOUTHBRIDGE_INTEL_I82371EB
- select CPU_EMULATION_QEMU_X86
- select CONSOLE_SERIAL8250
- help
- x86 QEMU variant.
+source "src/mainboard/emulation/qemu-x86/Kconfig"
endchoice
-
-config MAINBOARD_DIR
- string
- default emulation/qemu-x86
- depends on BOARD_EMULATION_QEMU_X86
-
-config MAINBOARD_PART_NUMBER
- string
- default "QEMU-86"
- depends on BOARD_EMULATION_QEMU_X86
--- /dev/null
+config BOARD_EMULATION_QEMU_X86
+ bool "QEMU x86"
+ select ARCH_X86
+ select CPU_I586
+ select SOUTHBRIDGE_INTEL_I82371EB
+ select CPU_EMULATION_QEMU_X86
+ select CONSOLE_SERIAL8250
+ help
+ x86 QEMU variant.
+
+config MAINBOARD_DIR
+ string
+ default emulation/qemu-x86
+ depends on BOARD_EMULATION_QEMU_X86
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "QEMU-86"
+ depends on BOARD_EMULATION_QEMU_X86
--- /dev/null
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Michael Gold <mgold@ncf.ca>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+chip northbridge/intel/i82810 # Northbridge
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/intel/socket_PGA370 # CPU
+ device apic 0 on end # APIC
+ end
+ end
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # Graphics Memory Controller Hub (GMCH)
+ chip drivers/pci/onboard
+ device pci 1.0 on end
+ register "rom_address" = "0xfff80000" # 512 KB image
+ end
+ chip southbridge/intel/i82801xx # Southbridge
+ register "pirqa_routing" = "0x03"
+ register "pirqb_routing" = "0x05"
+ register "pirqc_routing" = "0x09"
+ register "pirqd_routing" = "0x0b"
+
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+
+ device pci 1e.0 on # PCI bridge
+ device pci 5.0 on end # Audio controller (ESS ES1988)
+ end
+ device pci 1f.0 on # ISA bridge
+ chip superio/smsc/smscsuperio # Super I/O (SMSC LPC47U332)
+ device pnp 4e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 4e.3 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+ device pnp 4e.4 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 4e.5 on # MIDI port (MPU-401)
+ io 0x60 = 0x330
+ irq 0x70 = 10
+ end
+ device pnp 4e.7 on # PS/2 keyboard / mouse
+ io 0x60 = 0x60 # XXX: not relocatable
+ io 0x62 = 0x64 # XXX: not relocatable
+ irq 0x70 = 1 # PS/2 keyboard interrupt
+ irq 0x72 = 12 # PS/2 mouse interrupt
+ end
+ device pnp 4e.9 on # Game port
+ io 0x60 = 0x201
+ end
+ device pnp 4e.a on # Runtime registers
+ io 0x60 = 0x400
+ end
+ device pnp 4e.b off end # SMBus
+ end
+ end
+ device pci 1f.1 on end # IDE
+ device pci 1f.2 on end # USB
+ device pci 1f.3 on end # SMbus
+ device pci 1f.5 off end # Audio controller
+ device pci 1f.6 off end # Modem
+ end
+ end
+end
--- /dev/null
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+chip northbridge/intel/i440bx # Northbridge
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
+ device apic 0 on end # APIC
+ end
+ end
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # Host bridge
+ device pci 1.0 on end # PCI/AGP bridge
+ chip southbridge/intel/i82371eb # Southbridge
+ device pci 7.0 on # ISA bridge
+ chip superio/ite/it8671f # Super I/O
+ device pnp 370.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 370.1 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 370.2 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 370.3 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 370.5 on # PS/2 keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 370.6 on # PS/2 mouse
+ irq 0x70 = 12
+ end
+ end
+ end
+ device pci 7.1 on end # IDE
+ device pci 7.2 on end # USB
+ device pci 7.3 on end # ACPI
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ register "ide_legacy_enable" = "1"
+ # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+ register "ide0_drive0_udma33_enable" = "0"
+ register "ide0_drive1_udma33_enable" = "0"
+ register "ide1_drive0_udma33_enable" = "0"
+ register "ide1_drive1_udma33_enable" = "0"
+ end
+ end
+end
default 32
depends on BOARD_VIA_EPIA_N
+config RAMBASE
+ hex
+ default 0x4000
+ depends on BOARD_VIA_EPIA_N
string
default "VT8454C"
depends on BOARD_VIA_VT8454C
+
+config IRQ_SLOT_COUNT
+ int
+ default 15
+ depends on BOARD_VIA_VT8454C
+
+config RAMBASE
+ hex
+ default 0x4000
+ depends on BOARD_VIA_VT8454C
config NORTHBRIDGE_VIA_CN400
bool
default n
+
+config FALLBACK_SIZE
+ int
+ default 0
+ depends on NORTHBRIDGE_VIA_CN400
##
#config chip.h
-obj-$(CONFIG_SUPERIO_SMSC_DEVICE) += superio.o
+obj-$(CONFIG_SUPERIO_SMSC_LPC47B272) += superio.o
# of this archive for more details.
TARGETDIR=kbuildall.results
+BOARD=$1
if [ ! -f util/kbuildall/kbuildall ]; then
echo "This application must be run from the"
yes "" | $MAKE oldconfig
}
-rm -rf $TARGETDIR
-mkdir -p $TARGETDIR
ALLTARGETS=`(cd src/mainboard; ls */*/Config.lb | sed s,/Config.lb,,)`
TARGETCOUNT=`echo $ALLTARGETS | wc -w`
+
+if [ -n "$BOARD" ]; then
+ TARGETCOUNT=1
+ ALLTARGETS=$BOARD
+else
+ rm -rf $TARGETDIR
+fi
+mkdir -p $TARGETDIR
CURRENTARGET=0
for dir in $ALLTARGETS; do
i=`expr $i + 1`
projects / coreboot.git / commitdiff