#ifndef AMDFAM10_SYSCONF_H
#define AMDFAM10_SYSCONF_H
-#include "../../../northbridge/amd/amdfam10/amdfam10_nums.h"
+#include "northbridge/amd/amdfam10/nums.h"
#include <cpu/x86/msr.h>
#include "pc80/udelay_io.c"
#include "lib/delay.c"
#include "cpu/x86/bist.h"
-#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include "superio/winbond/w83977tf/early_serial.c"
#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
#include "pc80/udelay_io.c"
#include "lib/delay.c"
#include "cpu/x86/bist.h"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, W83627HF_SP1)
#include "lib/delay.c"
#include "cpu/x86/bist.h"
/* FIXME: It's a Winbond W83977EF, actually. */
-#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include "superio/winbond/w83977tf/early_serial.c"
#include <lib.h>
/* FIXME: It's a Winbond W83977EF, actually. */
#include <console/console.h>
#include "northbridge/amd/gx1/raminit.c"
#include "cpu/x86/bist.h"
-#include "superio/winbond/w83977f/w83977f_early_serial.c"
+#include "superio/winbond/w83977f/early_serial.c"
#include "southbridge/amd/cs5530/enable_rom.c"
#define SERIAL_DEV PNP_DEV(0x3f0, W83977F_SP1)
#include <spd.h>
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/amdk8_sysconf.h>
-#include "northbridge/amd/amdk8/amdk8_acpi.h"
+#include "northbridge/amd/amdk8/acpi.h"
#include <arch/cpu.h>
#include <cpu/amd/model_fxx_powernow.h>
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/ite/it8712f/it8712f_early_serial.c"
+#include "superio/ite/it8712f/early_serial.c"
#include <spd.h>
#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/amdk8_sysconf.h>
-#include "northbridge/amd/amdk8/amdk8_acpi.h"
+#include "northbridge/amd/amdk8/acpi.h"
#include <arch/cpu.h>
#include <cpu/amd/model_fxx_powernow.h>
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/ite/it8718f/it8718f_early_serial.c"
+#include "superio/ite/it8718f/early_serial.c"
#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
-#include "superio/ite/it8718f/it8718f_early_serial.c"
+#include "superio/ite/it8718f/early_serial.c"
#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/amdfam10_pci.c"
+#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/amdk8_sysconf.h>
-#include "northbridge/amd/amdk8/amdk8_acpi.h"
+#include "northbridge/amd/amdk8/acpi.h"
#include <arch/cpu.h>
#include <cpu/amd/model_fxx_powernow.h>
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/ite/it8712f/it8712f_early_serial.c"
+#include "superio/ite/it8712f/early_serial.c"
#include <usbdebug.h>
#include <spd.h>
#include "cpu/x86/mtrr/earlymtrr.c"
#include <device/pnp_def.h>
#include <arch/hlt.h>
#include <console/console.h>
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/gx2def.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/amdk8_sysconf.h>
-#include "northbridge/amd/amdk8/amdk8_acpi.h"
+#include "northbridge/amd/amdk8/acpi.h"
#include "mb_sysconf.h"
#define DUMP_ACPI_TABLES 0
Z00A, 8
}
- #include "northbridge/amd/amdk8/amdk8_util.asl"
+ #include "northbridge/amd/amdk8/util.asl"
}
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/amd8111/early_ctrl.c"
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdfam10/debug.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/amd8111/early_ctrl.c"
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/amdfam10_pci.c"
+#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
-#include "superio/ite/it8718f/it8718f_early_serial.c"
+#include "superio/ite/it8718f/early_serial.c"
#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/amdfam10_pci.c"
+#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/nsc/pc87360/pc87360_early_serial.c"
+#include "superio/nsc/pc87360/early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include <console/console.h>
#include "northbridge/amd/gx1/raminit.c"
#include "cpu/x86/bist.h"
-#include "superio/nsc/pc87351/pc87351_early_serial.c"
+#include "superio/nsc/pc87351/early_serial.c"
#include "southbridge/amd/cs5530/enable_rom.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1)
#include <arch/hlt.h>
#include <console/console.h>
#include "northbridge/amd/gx1/raminit.c"
-#include "superio/nsc/pc87351/pc87351_early_serial.c"
+#include "superio/nsc/pc87351/early_serial.c"
#include "cpu/x86/bist.h"
#include "southbridge/amd/cs5530/enable_rom.c"
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/amdk8_sysconf.h>
-#include "northbridge/amd/amdk8/amdk8_acpi.h"
+#include "northbridge/amd/amdk8/acpi.h"
#include <arch/cpu.h>
#include <cpu/amd/model_fxx_powernow.h>
)
{ /* Start of ASL file */
/* #include "acpi/debug.asl" */ /* Include global debug methods if needed */
- #include "northbridge/amd/amdk8/amdk8_util.asl"
+ #include "northbridge/amd/amdk8/util.asl"
Name(HPBA, 0xFED00000) /* Base address of HPET table */
#include <spd.h>
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
+#include "superio/winbond/w83627dhg/early_serial.c"
#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include <pc80/mc146818rtc.h>
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/ite/it8712f/it8712f_early_serial.c"
+#include "superio/ite/it8712f/early_serial.c"
#include <cpu/amd/model_fxx_rev.h>
#include <console/console.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/early_ht.c"
-#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
+#include "superio/winbond/w83627ehg/early_serial.c"
#include "southbridge/via/vt8237r/early_smbus.c"
#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/early_ht.c"
-#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
+#include "superio/winbond/w83627ehg/early_serial.c"
#include "southbridge/via/vt8237r/early_smbus.c"
#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */
#include "cpu/x86/mtrr/earlymtrr.c"
#include <device/pci_ids.h>
#include "southbridge/via/vt8237r/vt8237r.h"
#include "southbridge/via/k8t890/k8t890.h"
-#include "northbridge/amd/amdk8/amdk8_acpi.h"
+#include "northbridge/amd/amdk8/acpi.h"
#include <cpu/amd/model_fxx_powernow.h>
extern const unsigned char AmlCode[];
DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
{
- #include "northbridge/amd/amdk8/amdk8_util.asl"
+ #include "northbridge/amd/amdk8/util.asl"
/* For now only define 2 power states:
* - S0 which is fully on
#include "lib/delay.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/ite/it8712f/it8712f_early_serial.c"
+#include "superio/ite/it8712f/early_serial.c"
#include "southbridge/via/vt8237r/early_smbus.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include <device/pci_ids.h>
#include "southbridge/via/vt8237r/vt8237r.h"
#include "southbridge/via/k8t890/k8t890.h"
-#include "northbridge/amd/amdk8/amdk8_acpi.h"
+#include "northbridge/amd/amdk8/acpi.h"
#include <cpu/amd/model_fxx_powernow.h>
extern const unsigned char AmlCode[];
#include "lib/delay.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/ite/it8712f/it8712f_early_serial.c"
+#include "superio/ite/it8712f/early_serial.c"
#include "southbridge/via/vt8237r/early_smbus.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
-#include "superio/ite/it8712f/it8712f_early_serial.c"
+#include "superio/ite/it8712f/early_serial.c"
#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/amdfam10_pci.c"
+#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
-#include "superio/ite/it8712f/it8712f_early_serial.c"
+#include "superio/ite/it8712f/early_serial.c"
#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/amdfam10_pci.c"
+#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "northbridge/intel/i82810/raminit.h"
#include "pc80/udelay_io.c"
#include "cpu/x86/bist.h"
-#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
+#include "superio/smsc/smscsuperio/early_serial.c"
#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
-#include "superio/smsc/lpc47b272/lpc47b272_early_serial.c"
+#include "superio/smsc/lpc47b272/early_serial.c"
#include "northbridge/intel/i82810/raminit.h"
#include "cpu/x86/bist.h"
#include "southbridge/intel/i82801ax/i82801ax.h"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
#include "cpu/x86/bist.h"
-#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include "superio/winbond/w83977tf/early_serial.c"
#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
#include "pc80/udelay_io.c"
#include "lib/delay.c"
#include "cpu/x86/bist.h"
-#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include "superio/winbond/w83977tf/early_serial.c"
#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
#include "lib/delay.c"
#include "cpu/x86/bist.h"
/* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */
-#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include "superio/winbond/w83977tf/early_serial.c"
#include <lib.h>
/* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */
#include "lib/delay.c"
#include "cpu/x86/bist.h"
/* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */
-#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include "superio/winbond/w83977tf/early_serial.c"
#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
#include "pc80/udelay_io.c"
#include "lib/delay.c"
#include "cpu/x86/bist.h"
-#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include "superio/winbond/w83977tf/early_serial.c"
#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
#include "lib/delay.c"
#include "cpu/x86/bist.h"
/* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */
-#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include "superio/winbond/w83977tf/early_serial.c"
#include <lib.h>
/* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */
#include <arch/hlt.h>
#include <console/console.h>
#include "northbridge/amd/gx1/raminit.c"
-#include "superio/nsc/pc97317/pc97317_early_serial.c"
+#include "superio/nsc/pc97317/early_serial.c"
#include "cpu/x86/bist.h"
#include "southbridge/amd/cs5530/enable_rom.c"
#include "lib/delay.c"
#include "cpu/x86/bist.h"
/* FIXME: It's a Winbond W83977EF, actually. */
-#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include "superio/winbond/w83977tf/early_serial.c"
#include <lib.h>
/* FIXME: It's a Winbond W83977EF, actually. */
#include <arch/hlt.h>
#include <console/console.h>
#include "northbridge/amd/gx1/raminit.c"
-#include "superio/nsc/pc97317/pc97317_early_serial.c"
+#include "superio/nsc/pc97317/early_serial.c"
#include "cpu/x86/bist.h"
#include "southbridge/amd/cs5530/enable_rom.c"
#include <lib.h>
#include <spd.h>
#include "southbridge/via/vt8237r/early_smbus.c"
-#include "superio/winbond/w83697hf/w83697hf_early_serial.c"
+#include "superio/winbond/w83697hf/early_serial.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
static inline int spd_read_byte(unsigned device, unsigned address)
#include "pc80/udelay_io.c"
#include "lib/delay.c"
#include "cpu/x86/bist.h"
-#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
+#include "superio/smsc/smscsuperio/early_serial.c"
#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, SMSCSUPERIO_SP1)
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/nsc/pc87417/pc87417_early_serial.c"
+#include "superio/nsc/pc87417/early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "lib/delay.c"
#include "cpu/x86/bist.h"
/* FIXME: This should be PC97307 (but it's buggy at the moment)! */
-#include "superio/nsc/pc97317/pc97317_early_serial.c"
+#include "superio/nsc/pc97317/early_serial.c"
#include <lib.h>
/* FIXME: This should be PC97307 (but it's buggy at the moment)! */
#include <console/console.h>
#include "southbridge/intel/i82801ex/early_smbus.c"
#include "northbridge/intel/e7520/raminit.h"
-#include "superio/nsc/pc8374/pc8374_early_init.c"
+#include "superio/nsc/pc8374/early_init.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "debug.c"
#include "southbridge/intel/i82801dx/early_smbus.c"
#include "northbridge/intel/i855/raminit.h"
#include "northbridge/intel/i855/debug.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include <spd.h>
#include <spd.h>
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
-#include "superio/nsc/pc97317/pc97317_early_serial.c"
+#include "superio/nsc/pc97317/early_serial.c"
#include "cpu/x86/bist.h"
#include "southbridge/amd/cs5530/enable_rom.c"
#include "northbridge/amd/gx1/raminit.c"
#include "northbridge/intel/i82810/raminit.h"
#include "pc80/udelay_io.c"
#include "cpu/x86/bist.h"
-#include "superio/ite/it8712f/it8712f_early_serial.c"
+#include "superio/ite/it8712f/early_serial.c"
#include <lib.h>
void main(unsigned long bist)
#include "lib/delay.c"
#include "cpu/x86/bist.h"
void it8671f_48mhz_clkin(void);
-#include "superio/ite/it8671f/it8671f_early_serial.c"
+#include "superio/ite/it8671f/early_serial.c"
#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, IT8671F_SP1)
#include "lib/delay.c"
#include "cpu/x86/bist.h"
static void it8671f_48mhz_clkin(void);
-#include "superio/ite/it8671f/it8671f_early_serial.c"
+#include "superio/ite/it8671f/early_serial.c"
#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, IT8671F_SP1)
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/ite/it8716f/it8716f_early_serial.c"
-#include "superio/ite/it8716f/it8716f_early_init.c"
+#include "superio/ite/it8716f/early_serial.c"
+#include "superio/ite/it8716f/early_init.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
return smbus_read_byte(device, address);
}
-#include "northbridge/amd/amdk8/amdk8_f.h"
+#include "northbridge/amd/amdk8/f.h"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include <arch/smp/mpspec.h>
#include <device/device.h>
#include <device/pci_ids.h>
-#include "northbridge/amd/amdk8/amdk8_acpi.h"
+#include "northbridge/amd/amdk8/acpi.h"
#include <cpu/amd/model_fxx_powernow.h>
#include <device/pci.h>
#include <cpu/amd/amdk8_sysconf.h>
DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
{
- #include "northbridge/amd/amdk8/amdk8_util.asl"
+ #include "northbridge/amd/amdk8/util.asl"
/* For now only define 2 power states:
* - S0 which is fully on
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/ite/it8716f/it8716f_early_serial.c"
-#include "superio/ite/it8716f/it8716f_early_init.c"
+#include "superio/ite/it8716f/early_serial.c"
+#include "superio/ite/it8716f/early_init.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "southbridge/nvidia/mcp55/early_setup_ss.h"
#include "southbridge/nvidia/mcp55/early_setup_car.c"
-#include "northbridge/amd/amdk8/amdk8_f.h"
+#include "northbridge/amd/amdk8/f.h"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
-#include "superio/ite/it8718f/it8718f_early_serial.c"
+#include "superio/ite/it8718f/early_serial.c"
#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/amdfam10_pci.c"
+#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
-#include "superio/ite/it8718f/it8718f_early_serial.c"
+#include "superio/ite/it8718f/early_serial.c"
#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/amdfam10_pci.c"
+#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/serverengines/pilot/pilot_early_serial.c"
-#include "superio/serverengines/pilot/pilot_early_init.c"
-#include "superio/nsc/pc87417/pc87417_early_serial.c"
+#include "superio/serverengines/pilot/early_serial.c"
+#include "superio/serverengines/pilot/early_init.c"
+#include "superio/nsc/pc87417/early_serial.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
return smbus_read_byte(device, address);
}
-#include "northbridge/amd/amdk8/amdk8_f.h"
+#include "northbridge/amd/amdk8/f.h"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
-#include "superio/serverengines/pilot/pilot_early_serial.c"
-#include "superio/serverengines/pilot/pilot_early_init.c"
-#include "superio/nsc/pc87417/pc87417_early_serial.c"
+#include "superio/serverengines/pilot/early_serial.c"
+#include "superio/serverengines/pilot/early_init.c"
+#include "superio/nsc/pc87417/early_serial.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdfam10/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/amdfam10_pci.c"
+#include "northbridge/amd/amdfam10/pci.c"
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
#include <stdlib.h>
#include <console/console.h>
/* TODO: It's a PC87364 actually! */
-#include "superio/nsc/pc87360/pc87360_early_serial.c"
+#include "superio/nsc/pc87360/early_serial.c"
/* TODO: It's i810E actually! */
#include "northbridge/intel/i82810/raminit.h"
#include "cpu/x86/bist.h"
#include <console/console.h>
#include <usbdebug.h>
#include <cpu/x86/bist.h>
-#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
+#include "superio/winbond/w83627ehg/early_serial.c"
#include "northbridge/intel/i945/i945.h"
#include "northbridge/intel/i945/raminit.h"
#include "southbridge/intel/i82801gx/i82801gx.h"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/nsc/pc87366/pc87366_early_serial.c"
+#include "superio/nsc/pc87366/early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/nsc/pc87366/pc87366_early_serial.c"
+#include "superio/nsc/pc87366/early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
-#include "superio/winbond/w83977f/w83977f_early_serial.c"
+#include "superio/winbond/w83977f/early_serial.c"
#include "southbridge/amd/cs5530/enable_rom.c"
#include "cpu/x86/bist.h"
#include "pc80/udelay_io.c"
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
-#include "superio/fintek/f71859/f71859_early_serial.c"
+#include "superio/fintek/f71859/early_serial.c"
#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/amdfam10_pci.c"
+#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
-#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include "superio/winbond/w83977tf/early_serial.c"
#include "southbridge/amd/cs5530/enable_rom.c"
#include "cpu/x86/bist.h"
#include <spd.h>
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#include "northbridge/intel/i82810/raminit.h"
#include "pc80/udelay_io.c"
#include "cpu/x86/bist.h"
-#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
+#include "superio/smsc/smscsuperio/early_serial.c"
#include "gpio.c"
#include <lib.h>
#include <console/console.h>
#include <usbdebug.h>
#include <cpu/x86/bist.h>
-#include "superio/smsc/lpc47m15x/lpc47m15x_early_serial.c"
+#include "superio/smsc/lpc47m15x/early_serial.c"
#include "northbridge/intel/i945/i945.h"
#include "northbridge/intel/i945/raminit.h"
#include "southbridge/intel/i82801gx/i82801gx.h"
#include "southbridge/intel/i3100/early_smbus.c"
#include "southbridge/intel/i3100/early_lpc.c"
#include "reset.c"
-#include "superio/intel/i3100/i3100_early_serial.c"
-#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
+#include "superio/intel/i3100/early_serial.c"
+#include "superio/smsc/smscsuperio/early_serial.c"
#include "northbridge/intel/i3100/i3100.h"
#include "southbridge/intel/i3100/i3100.h"
#include "reset.c"
#include "power_reset_check.c"
#include "jarrell_fixups.c"
-#include "superio/nsc/pc87427/pc87427_early_init.c"
+#include "superio/nsc/pc87427/early_init.c"
#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
#include <spd.h>
#include "northbridge/intel/i3100/raminit.h"
#include "superio/intel/i3100/i3100.h"
#include "cpu/x86/mtrr/earlymtrr.c"
-#include "superio/intel/i3100/i3100_early_serial.c"
+#include "superio/intel/i3100/early_serial.c"
#include "northbridge/intel/i3100/memory_initialized.c"
#include "cpu/x86/bist.h"
#include <spd.h>
#include "superio/intel/i3100/i3100.h"
#include "cpu/x86/lapic/boot_cpu.c"
#include "cpu/x86/mtrr/earlymtrr.c"
-#include "superio/intel/i3100/i3100_early_serial.c"
+#include "superio/intel/i3100/early_serial.c"
#include "cpu/x86/bist.h"
#include <spd.h>
#include "northbridge/intel/e7501/raminit.h"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/intel/e7501/debug.c"
-#include "superio/smsc/lpc47b272/lpc47b272_early_serial.c"
+#include "superio/smsc/lpc47b272/early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include <spd.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/amdk8_sysconf.h>
-#include "northbridge/amd/amdk8/amdk8_acpi.h"
+#include "northbridge/amd/amdk8/acpi.h"
#include "mb_sysconf.h"
#define DUMP_ACPI_TABLES 0
Z00A, 8
}
- #include "northbridge/amd/amdk8/amdk8_util.asl"
+ #include "northbridge/amd/amdk8/util.asl"
}
#include "lib/delay.c"
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/amd8111/early_ctrl.c"
#include "lib/delay.c"
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/amd8111/early_ctrl.c"
#include "lib/delay.c"
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/amd8111/early_ctrl.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
#include "southbridge/via/vt8237r/early_smbus.c"
-#include "superio/fintek/f71805f/f71805f_early_serial.c"
+#include "superio/fintek/f71805f/early_serial.c"
#include <lib.h>
#include <spd.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
-#include "superio/fintek/f71863fg/f71863fg_early_serial.c"
+#include "superio/fintek/f71863fg/early_serial.c"
#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/amdfam10_pci.c"
+#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "option_table.h"
#include <console/console.h>
#include <cpu/x86/bist.h>
-#include "superio/winbond/w83627thg/w83627thg_early_serial.c"
+#include "superio/winbond/w83627thg/early_serial.c"
#include "northbridge/intel/i945/i945.h"
#include "northbridge/intel/i945/raminit.h"
#include "southbridge/intel/i82801gx/i82801gx.h"
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/amdk8_sysconf.h>
-#include "northbridge/amd/amdk8/amdk8_acpi.h"
+#include "northbridge/amd/amdk8/acpi.h"
#include <arch/cpu.h>
#include <cpu/amd/model_fxx_powernow.h>
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
+#include "superio/winbond/w83627dhg/early_serial.c"
#include <usbdebug.h>
#include <cpu/amd/mtrr.h>
#include "cpu/x86/bist.h"
#include "southbridge/intel/i82801dx/early_smbus.c"
#include "northbridge/intel/i855/raminit.h"
#include "northbridge/intel/i855/debug.c"
-#include "superio/winbond/w83627thg/w83627thg_early_serial.c"
+#include "superio/winbond/w83627thg/early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include <device/pnp_def.h>
#include <arch/hlt.h>
#include <console/console.h>
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/gx2def.h>
#include <spd.h>
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
-#include "superio/ite/it8712f/it8712f_early_serial.c"
+#include "superio/ite/it8712f/early_serial.c"
/* Bit0 enables Spread Spectrum. */
#define SMC_CONFIG 0x01
#include "southbridge/amd/cs5536/cs5536.h"
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
-#include "superio/ite/it8712f/it8712f_early_serial.c"
+#include "superio/ite/it8712f/early_serial.c"
/* Bit0 enables Spread Spectrum, bit1 makes on-board CF slot act as IDE slave. */
#if CONFIG_ONBOARD_IDE_SLAVE
#include <spd.h>
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
-#include "superio/ite/it8712f/it8712f_early_serial.c"
+#include "superio/ite/it8712f/early_serial.c"
#define ManualConf 1 /* No automatic strapped PLL config */
#define PLLMSRhi 0x0000049C /* Manual settings for the PLL */
#include "southbridge/amd/cs5536/cs5536.h"
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
-#include "superio/ite/it8712f/it8712f_early_serial.c"
+#include "superio/ite/it8712f/early_serial.c"
/* Bit0 enables Spread Spectrum, bit1 makes on-board SSD act as IDE slave. */
#if CONFIG_ONBOARD_IDE_SLAVE
#include "pc80/udelay_io.c"
#include "lib/delay.c"
#include "cpu/x86/bist.h"
-#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
+#include "superio/smsc/smscsuperio/early_serial.c"
#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
#include "pc80/udelay_io.c"
#include "lib/delay.c"
#include "cpu/x86/bist.h"
-#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include "superio/winbond/w83977tf/early_serial.c"
#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
#include "pc80/udelay_io.c"
#include "lib/delay.c"
#include <cpu/x86/bist.h>
-#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include "superio/winbond/w83977tf/early_serial.c"
#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
#include "pc80/udelay_io.c"
#include "lib/delay.c"
#include "cpu/x86/bist.h"
-#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include "superio/winbond/w83977tf/early_serial.c"
#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
#include "northbridge/intel/i82810/raminit.h"
#include "cpu/x86/bist.h"
#include "southbridge/intel/i82801ax/i82801ax.h"
#include <pc80/mc146818rtc.h>
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/winbond/w83627thg/w83627thg_early_serial.c"
+#include "superio/winbond/w83627thg/early_serial.c"
#include <cpu/amd/model_fxx_rev.h>
#include <console/console.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include <spd.h>
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
-#include "superio/winbond/w83627ehg/w83627ehg_early_init.c"
+#include "superio/winbond/w83627ehg/early_serial.c"
+#include "superio/winbond/w83627ehg/early_init.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
return smbus_read_byte(device, address);
}
-#include "northbridge/amd/amdk8/amdk8_f.h"
+#include "northbridge/amd/amdk8/f.h"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/nsc/pc87417/pc87417_early_serial.c"
+#include "superio/nsc/pc87417/early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
return smbus_read_byte(device, address);
}
-#include "northbridge/amd/amdk8/amdk8_f.h"
+#include "northbridge/amd/amdk8/f.h"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
+#include "superio/winbond/w83627ehg/early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include <spd.h>
return smbus_read_byte(device, address);
}
-#include "northbridge/amd/amdk8/amdk8_f.h"
+#include "northbridge/amd/amdk8/f.h"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
{
- #include "../../../../src/northbridge/amd/amdk8/amdk8_util.asl"
+ #include "../../../../src/northbridge/amd/amdk8/util.asl"
/* For now only define 2 power states:
* - S0 which is fully on
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
-#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
+#include "superio/winbond/w83627ehg/early_serial.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdfam10/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/amdfam10_pci.c"
+#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
-#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
+#include "superio/smsc/smscsuperio/early_serial.c"
#include "northbridge/intel/i82810/raminit.h"
#include "cpu/x86/bist.h"
#include "southbridge/intel/i82801ax/i82801ax.h"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
#include "cpu/x86/bist.h"
-#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
+#include "superio/smsc/smscsuperio/early_serial.c"
#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, SMSCSUPERIO_SP1)
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
-#include "superio/winbond/w83627ehg/w83627ehg_early_init.c"
+#include "superio/winbond/w83627ehg/early_serial.c"
+#include "superio/winbond/w83627ehg/early_init.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
return smbus_read_byte(device, address);
}
-#include "northbridge/amd/amdk8/amdk8_f.h"
+#include "northbridge/amd/amdk8/f.h"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
static void cs5536_enable_smbus(void) { }
#include "southbridge/amd/cs5536/early_setup.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
/* The part is a Hynix hy5du121622ctp-d43.
*
#include "pc80/udelay_io.c"
#include <console/console.h>
#include <lib.h>
-#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
+#include "superio/smsc/smscsuperio/early_serial.c"
#include "northbridge/intel/i82830/raminit.h"
#include "northbridge/intel/i82830/memory_initialized.c"
#include "southbridge/intel/i82801dx/i82801dx.h"
#include "lib/delay.c"
#include "cpu/x86/bist.h"
void it8671f_48mhz_clkin(void);
-#include "superio/ite/it8671f/it8671f_early_serial.c"
+#include "superio/ite/it8671f/early_serial.c"
#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x370, IT8671F_SP1)
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
+#include "superio/smsc/lpc47b397/early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-#include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
+#include "superio/smsc/lpc47b397/early_gpio.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "superio/winbond/w83627hf/w83627hf_early_init.c"
+#include "superio/winbond/w83627hf/early_serial.c"
+#include "superio/winbond/w83627hf/early_init.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
return smbus_read_byte(device, address);
}
-#include "northbridge/amd/amdk8/amdk8_f.h"
+#include "northbridge/amd/amdk8/f.h"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "superio/winbond/w83627hf/w83627hf_early_init.c"
+#include "superio/winbond/w83627hf/early_serial.c"
+#include "superio/winbond/w83627hf/early_init.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
return smbus_read_byte(device, address);
}
-#include "northbridge/amd/amdk8/amdk8_f.h"
+#include "northbridge/amd/amdk8/f.h"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "superio/winbond/w83627hf/w83627hf_early_init.c"
+#include "superio/winbond/w83627hf/early_serial.c"
+#include "superio/winbond/w83627hf/early_init.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdfam10/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/amdfam10_pci.c"
+#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include "southbridge/nvidia/mcp55/early_setup_ss.h"
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "superio/winbond/w83627hf/w83627hf_early_init.c"
+#include "superio/winbond/w83627hf/early_serial.c"
+#include "superio/winbond/w83627hf/early_init.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdfam10/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/amdfam10_pci.c"
+#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include "southbridge/nvidia/mcp55/early_setup_ss.h"
#include "debug.c"
#include "watchdog.c"
#include "reset.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
#include "northbridge/intel/e7525/memory_initialized.c"
#include "cpu/x86/bist.h"
#include <spd.h>
#include "debug.c"
#include "watchdog.c"
#include "reset.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
#include <spd.h>
#include "debug.c"
#include "watchdog.c"
#include "reset.c"
-#include "superio/nsc/pc87427/pc87427_early_init.c"
+#include "superio/nsc/pc87427/early_init.c"
#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
#include <spd.h>
#include "debug.c"
#include "watchdog.c"
#include "reset.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
#include <spd.h>
#include "debug.c"
#include "watchdog.c"
#include "reset.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
#include <spd.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/amdk8_sysconf.h>
-#include "northbridge/amd/amdk8/amdk8_acpi.h"
+#include "northbridge/amd/amdk8/acpi.h"
#include <arch/cpu.h>
#include <cpu/amd/model_fxx_powernow.h>
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/ite/it8712f/it8712f_early_serial.c"
+#include "superio/ite/it8712f/early_serial.c"
#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/amdk8_sysconf.h>
-#include "northbridge/amd/amdk8/amdk8_acpi.h"
+#include "northbridge/amd/amdk8/acpi.h"
#include <arch/cpu.h>
#include <cpu/amd/model_fxx_powernow.h>
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/ite/it8712f/it8712f_early_serial.c"
+#include "superio/ite/it8712f/early_serial.c"
#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include <arch/hlt.h>
#include <console/console.h>
#include "northbridge/amd/gx1/raminit.c"
-#include "superio/nsc/pc97317/pc97317_early_serial.c"
+#include "superio/nsc/pc97317/early_serial.c"
#include "cpu/x86/bist.h"
#include "southbridge/amd/cs5530/enable_rom.c"
#include "pc80/udelay_io.c"
#include <console/console.h>
#include <lib.h>
-#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
+#include "superio/smsc/smscsuperio/early_serial.c"
#include "northbridge/intel/i82830/raminit.h"
#include "northbridge/intel/i82830/memory_initialized.c"
#include "southbridge/intel/i82801dx/i82801dx.h"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
#include "cpu/x86/bist.h"
-#include "superio/nsc/pc87309/pc87309_early_serial.c"
+#include "superio/nsc/pc87309/early_serial.c"
#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x2e, PC87309_SP1)
#include "southbridge/intel/i82801ex/early_smbus.c"
#include "northbridge/intel/e7501/raminit.h"
#include "northbridge/intel/e7501/debug.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/amdk8_sysconf.h>
-#include "northbridge/amd/amdk8/amdk8_acpi.h"
+#include "northbridge/amd/amdk8/acpi.h"
#include <cpu/amd/model_fxx_powernow.h>
extern const unsigned char AmlCode[];
DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1)
{
- #include "northbridge/amd/amdk8/amdk8_util.asl"
+ #include "northbridge/amd/amdk8/util.asl"
/* For now only define 2 power states:
* - S0 which is fully on
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/amdk8_sysconf.h>
-#include "northbridge/amd/amdk8/amdk8_acpi.h"
+#include "northbridge/amd/amdk8/acpi.h"
#include <cpu/amd/model_fxx_powernow.h>
extern const unsigned char AmlCode[];
DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1)
{
- #include "northbridge/amd/amdk8/amdk8_util.asl"
+ #include "northbridge/amd/amdk8/util.asl"
/* For now only define 2 power states:
* - S0 which is fully on
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/amdk8_sysconf.h>
-#include "northbridge/amd/amdk8/amdk8_acpi.h"
+#include "northbridge/amd/amdk8/acpi.h"
#include <cpu/amd/model_fxx_powernow.h>
extern const unsigned char AmlCode[];
DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1)
{
- #include "northbridge/amd/amdk8/amdk8_util.asl"
+ #include "northbridge/amd/amdk8/util.asl"
/* For now only define 2 power states:
* - S0 which is fully on
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
-#include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
+#include "superio/smsc/lpc47b397/early_serial.c"
+#include "superio/smsc/lpc47b397/early_gpio.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
#include <cpu/amd/mtrr.h>
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "superio/winbond/w83627hf/w83627hf_early_init.c"
+#include "superio/winbond/w83627hf/early_serial.c"
+#include "superio/winbond/w83627hf/early_init.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
return smbus_read_byte(device, address);
}
-#include "northbridge/amd/amdk8/amdk8_f.h"
+#include "northbridge/amd/amdk8/f.h"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "superio/winbond/w83627hf/w83627hf_early_init.c"
+#include "superio/winbond/w83627hf/early_serial.c"
+#include "superio/winbond/w83627hf/early_init.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdfam10/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/amdfam10_pci.c"
+#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "northbridge/via/vx800/raminit.h"
#include "northbridge/via/vx800/raminit.c"
#include "wakeup.h"
-#include "superio/winbond/w83697hf/w83697hf_early_serial.c"
+#include "superio/winbond/w83697hf/early_serial.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
#define DUMMY_DEV PNP_DEV(0x2e, 0)
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "southbridge/via/vt8237r/early_smbus.c"
-#include "superio/winbond/w83697hf/w83697hf_early_serial.c"
+#include "superio/winbond/w83697hf/early_serial.c"
#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
#include "pc80/udelay_io.c"
#include "lib/delay.c"
#include "southbridge/via/vt8237r/early_smbus.c"
-#include "superio/ite/it8716f/it8716f_early_serial.c"
+#include "superio/ite/it8716f/early_serial.c"
#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
#include "cpu/x86/bist.h"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
-#include "northbridge/via/cx700/cx700_early_smbus.c"
+#include "northbridge/via/cx700/early_smbus.c"
#include "lib/debug.c"
-#include "northbridge/via/cx700/cx700_early_serial.c"
+#include "northbridge/via/cx700/early_serial.c"
#include "northbridge/via/cx700/raminit.c"
#include <spd.h>
#include <spd.h>
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
driver-y += northbridge.c
driver-y += misc_control.c
-ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += amdfam10_acpi.c
+ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ssdt.asl
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += sspr1.asl
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += sspr2.asl
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <device/pci.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <cpu/amd/amdfam10_sysconf.h>
+#include "amdfam10.h"
+
+//it seems some functions can be moved arch/i386/boot/acpi.c
+
+unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, u8 lint)
+{
+ device_t cpu;
+ int cpu_index = 0;
+
+ for(cpu = all_devices; cpu; cpu = cpu->next) {
+ if ((cpu->path.type != DEVICE_PATH_APIC) ||
+ (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
+ continue;
+ }
+ if (!cpu->enabled) {
+ continue;
+ }
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, cpu_index, flags, lint);
+ cpu_index++;
+ }
+ return current;
+}
+
+unsigned long acpi_create_srat_lapics(unsigned long current)
+{
+ device_t cpu;
+ int cpu_index = 0;
+
+ for(cpu = all_devices; cpu; cpu = cpu->next) {
+ if ((cpu->path.type != DEVICE_PATH_APIC) ||
+ (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
+ continue;
+ }
+ if (!cpu->enabled) {
+ continue;
+ }
+ printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id);
+ current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, cpu->path.apic.node_id, cpu->path.apic.apic_id);
+ cpu_index++;
+ }
+ return current;
+}
+
+static unsigned long resk(uint64_t value)
+{
+ unsigned long resultk;
+ if (value < (1ULL << 42)) {
+ resultk = value >> 10;
+ } else {
+ resultk = 0xffffffff;
+ }
+ return resultk;
+}
+
+struct acpi_srat_mem_state {
+ unsigned long current;
+};
+
+static void set_srat_mem(void *gp, struct device *dev, struct resource *res)
+{
+ struct acpi_srat_mem_state *state = gp;
+ unsigned long basek, sizek;
+ basek = resk(res->base);
+ sizek = resk(res->size);
+
+ printk(BIOS_DEBUG, "set_srat_mem: dev %s, res->index=%04lx startk=%08lx, sizek=%08lx\n",
+ dev_path(dev), res->index, basek, sizek);
+ /*
+ * 0-640K must be on node 0
+ * next range is from 1M---
+ * So will cut off before 1M in the mem range
+ */
+ if((basek+sizek)<1024) return;
+
+ if(basek<1024) {
+ sizek -= 1024 - basek;
+ basek = 1024;
+ }
+
+ // need to figure out NV
+ state->current += acpi_create_srat_mem((acpi_srat_mem_t *)state->current, (res->index & 0xf), basek, sizek, 1);
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ struct acpi_srat_mem_state srat_mem_state;
+
+ /* create all subtables for processors */
+ current = acpi_create_srat_lapics(current);
+
+ /* create all subteble for memory range */
+
+ /* 0-640K must be on node 0 */
+ current += acpi_create_srat_mem((acpi_srat_mem_t *)current, 0, 0, 640, 1);//enable
+
+ srat_mem_state.current = current;
+ search_global_resources(
+ IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
+ set_srat_mem, &srat_mem_state);
+
+ current = srat_mem_state.current;
+ return current;
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+ /* need to find out the node num at first */
+ /* fill the first 8 byte with that num */
+ /* fill the next num*num byte with distance, local is 10, 1 hop mean 20, and 2 hop with 30.... */
+
+ struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+ u8 *ln = sysinfox->ln;
+
+
+ u8 *p = (u8 *)current;
+ int nodes = sysconf.nodes;
+ int i,j;
+ u32 hops;
+
+ memset(p, 0, 8+nodes*nodes);
+ *p = (u8) nodes;
+ p += 8;
+
+ for(i=0;i<nodes;i++) {
+ for(j=0;j<nodes; j++) {
+ if(i==j) {
+ p[i*nodes+j] = 10;
+ } else {
+ hops = (((ln[i*NODE_NUMS+j]>>4) & 0x7)+1);
+ p[i*nodes+j] = hops * 2 + 10;
+ }
+ }
+ }
+
+ current += 8+nodes*nodes;
+ return current;
+}
+
+// moved from mb acpi_tables.c
+static void intx_to_stream(u32 val, u32 len, u8 *dest)
+{
+ int i;
+ for(i=0;i<len;i++) {
+ *(dest+i) = (val >> (8*i)) & 0xff;
+ }
+}
+
+static void int_to_stream(u32 val, u8 *dest)
+{
+ return intx_to_stream(val, 4, dest);
+}
+
+// used by acpi_tables.h
+void update_ssdt(void *ssdt)
+{
+ u8 *BUSN;
+ u8 *MMIO;
+ u8 *PCIO;
+ u8 *SBLK;
+ u8 *TOM1;
+ u8 *SBDN;
+ u8 *HCLK;
+ u8 *HCDN;
+ u8 *CBST;
+ u8 *CBBX;
+ u8 *CBS2;
+ u8 *CBB2;
+
+
+ int i;
+ u32 dword;
+ msr_t msr;
+
+ // the offset could be different if have different HC_NUMS, and HC_POSSIBLE_NUM and ssdt.asl
+ BUSN = ssdt+0x3b; //+5 will be next BUSN
+ MMIO = ssdt+0xe4; //+5 will be next MMIO
+ PCIO = ssdt+0x36d; //+5 will be next PCIO
+ SBLK = ssdt+0x4b2; // one byte
+ TOM1 = ssdt+0x4b9; //
+ SBDN = ssdt+0x4c3;//
+ HCLK = ssdt+0x4d1; //+5 will be next HCLK
+ HCDN = ssdt+0x57a; //+5 will be next HCDN
+ CBBX = ssdt+0x61f; //
+ CBST = ssdt+0x626;
+ CBB2 = ssdt+0x62d; //
+ CBS2 = ssdt+0x634;
+
+ for(i=0;i<HC_NUMS;i++) {
+ dword = sysconf.ht_c_conf_bus[i];
+ int_to_stream(dword, BUSN+i*5);
+ }
+
+ for(i=0;i<(HC_NUMS*2);i++) { // FIXME: change to more chain
+ dword = sysconf.conf_mmio_addrx[i]; //base
+ int_to_stream(dword, MMIO+(i*2)*5);
+ dword = sysconf.conf_mmio_addr[i]; //mask
+ int_to_stream(dword, MMIO+(i*2+1)*5);
+ }
+ for(i=0;i<HC_NUMS;i++) { // FIXME: change to more chain
+ dword = sysconf.conf_io_addrx[i];
+ int_to_stream(dword, PCIO+(i*2)*5);
+ dword = sysconf.conf_io_addr[i];
+ int_to_stream(dword, PCIO+(i*2+1)*5);
+ }
+
+ *SBLK = (u8)(sysconf.sblk);
+
+ msr = rdmsr(TOP_MEM);
+ int_to_stream(msr.lo, TOM1);
+
+ int_to_stream(sysconf.sbdn, SBDN);
+
+ for(i=0;i<sysconf.hc_possible_num;i++) {
+ int_to_stream(sysconf.pci1234[i], HCLK + i*5);
+ int_to_stream(sysconf.hcdn[i], HCDN + i*5);
+ }
+ for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
+ int_to_stream(0x00000000, HCLK + i*5);
+ int_to_stream(0x20202020, HCDN + i*5);
+ }
+
+ *CBBX = (u8)(CONFIG_CBB);
+
+ if(CONFIG_CBB == 0xff) {
+ *CBST = (u8) (0x0f);
+ } else {
+ if((sysconf.pci1234[0] >> 12) & 0xff) { //sb chain on other than bus 0
+ *CBST = (u8) (0x0f);
+ }
+ else {
+ *CBST = (u8) (0x00);
+ }
+ }
+
+ if((CONFIG_CBB == 0xff) && (sysconf.nodes>32)) {
+ *CBS2 = 0x0f;
+ *CBB2 = (u8)(CONFIG_CBB-1);
+ } else {
+ *CBS2 = 0x00;
+ *CBB2 = 0x00;
+ }
+
+}
+
+void update_ssdtx(void *ssdtx, int i)
+{
+ u8 *PCI;
+ u8 *HCIN;
+ u8 *UID;
+
+ PCI = ssdtx + 0x32;
+ HCIN = ssdtx + 0x39;
+ UID = ssdtx + 0x40;
+
+ if (i < 7) {
+ *PCI = (u8) ('4' + i - 1);
+ } else {
+ *PCI = (u8) ('A' + i - 1 - 6);
+ }
+ *HCIN = (u8) i;
+ *UID = (u8) (i + 3);
+
+ /* FIXME: need to update the GSI id in the ssdtx too */
+
+}
+
+static void update_sspr(void *sspr, u32 nodeid, u32 cpuindex)
+{
+ u8 *CPU;
+ u8 *CPUIN;
+ u8 *COREFREQ;
+ u8 *POWER;
+ u8 *TRANSITION_LAT;
+ u8 *BUSMASTER_LAT;
+ u8 *CONTROL;
+ u8 *STATUS;
+ unsigned offset = 0x94 - 0x7f;
+ int i;
+
+ CPU = sspr + 0x38;
+ CPUIN = sspr + 0x3a;
+
+ COREFREQ = sspr + 0x7f; //2 byte
+ POWER = sspr + 0x82; //3 bytes
+ TRANSITION_LAT = sspr + 0x87; //two bytes
+ BUSMASTER_LAT = sspr + 0x8a; //two bytes
+ CONTROL = sspr + 0x8d;
+ STATUS = sspr + 0x8f;
+
+ sprintf((char*)CPU, "%02x", (char)cpuindex);
+ *CPUIN = (u8) cpuindex;
+
+ for(i=0;i<sysconf.p_state_num;i++) {
+ struct p_state_t *p_state = &sysconf.p_state[nodeid * 5 + i];
+ intx_to_stream(p_state->corefreq, 2, COREFREQ + i*offset);
+ intx_to_stream(p_state->power, 3, POWER + i*offset);
+ intx_to_stream(p_state->transition_lat, 2, TRANSITION_LAT + i*offset);
+ intx_to_stream(p_state->busmaster_lat, 2, BUSMASTER_LAT + i*offset);
+ *((u8 *)(CONTROL + i*offset)) =(u8) p_state->control;
+ *((u8 *)(STATUS + i*offset)) =(u8) p_state->status;
+ }
+}
+
+extern const unsigned char AmlCode_sspr5[];
+extern const unsigned char AmlCode_sspr4[];
+extern const unsigned char AmlCode_sspr3[];
+extern const unsigned char AmlCode_sspr2[];
+extern const unsigned char AmlCode_sspr1[];
+
+/* fixme: find one good way for different p_state_num */
+unsigned long acpi_add_ssdt_pstates(acpi_rsdp_t *rsdp, unsigned long current)
+{
+ device_t cpu;
+ int cpu_index = 0;
+
+ acpi_header_t *ssdt;
+
+ if(!sysconf.p_state_num) return current;
+
+ void *AmlCode_sspr;
+ switch(sysconf.p_state_num) {
+ case 1: AmlCode_sspr = &AmlCode_sspr1; break;
+ case 2: AmlCode_sspr = &AmlCode_sspr2; break;
+ case 3: AmlCode_sspr = &AmlCode_sspr3; break;
+ case 4: AmlCode_sspr = &AmlCode_sspr4; break;
+ default: AmlCode_sspr = &AmlCode_sspr5; break;
+ }
+
+ for(cpu = all_devices; cpu; cpu = cpu->next) {
+ if ((cpu->path.type != DEVICE_PATH_APIC) ||
+ (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
+ continue;
+ }
+ if (!cpu->enabled) {
+ continue;
+ }
+ printk(BIOS_DEBUG, "ACPI: pstate cpu_index=%02x, node_id=%02x, core_id=%02x\n", cpu_index, cpu->path.apic.node_id, cpu->path.apic.core_id);
+
+ current = ( current + 0x0f) & -0x10;
+ ssdt = (acpi_header_t *)current;
+ memcpy(ssdt, AmlCode_sspr, sizeof(acpi_header_t));
+ current += ssdt->length;
+ memcpy(ssdt, AmlCode_sspr, ssdt->length);
+ update_sspr((void*)ssdt,cpu->path.apic.node_id, cpu_index);
+ /* recalculate checksum */
+ ssdt->checksum = 0;
+ ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
+ acpi_add_table(rsdp, ssdt);
+
+ cpu_index++;
+ }
+ return current;
+}
#define F10_APSTATE_STOPPED 0x14 // allow AP to stop
#define F10_APSTATE_RESET 0x01 // waiting for warm reset
-#include "amdfam10_nums.h"
+#include "nums.h"
#ifdef __PRE_RAM__
#if NODE_NUMS==64
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <device/pci.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <cpu/amd/amdfam10_sysconf.h>
-#include "amdfam10.h"
-
-//it seems some functions can be moved arch/i386/boot/acpi.c
-
-unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, u8 lint)
-{
- device_t cpu;
- int cpu_index = 0;
-
- for(cpu = all_devices; cpu; cpu = cpu->next) {
- if ((cpu->path.type != DEVICE_PATH_APIC) ||
- (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
- continue;
- }
- if (!cpu->enabled) {
- continue;
- }
- current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, cpu_index, flags, lint);
- cpu_index++;
- }
- return current;
-}
-
-unsigned long acpi_create_srat_lapics(unsigned long current)
-{
- device_t cpu;
- int cpu_index = 0;
-
- for(cpu = all_devices; cpu; cpu = cpu->next) {
- if ((cpu->path.type != DEVICE_PATH_APIC) ||
- (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
- continue;
- }
- if (!cpu->enabled) {
- continue;
- }
- printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id);
- current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, cpu->path.apic.node_id, cpu->path.apic.apic_id);
- cpu_index++;
- }
- return current;
-}
-
-static unsigned long resk(uint64_t value)
-{
- unsigned long resultk;
- if (value < (1ULL << 42)) {
- resultk = value >> 10;
- } else {
- resultk = 0xffffffff;
- }
- return resultk;
-}
-
-struct acpi_srat_mem_state {
- unsigned long current;
-};
-
-static void set_srat_mem(void *gp, struct device *dev, struct resource *res)
-{
- struct acpi_srat_mem_state *state = gp;
- unsigned long basek, sizek;
- basek = resk(res->base);
- sizek = resk(res->size);
-
- printk(BIOS_DEBUG, "set_srat_mem: dev %s, res->index=%04lx startk=%08lx, sizek=%08lx\n",
- dev_path(dev), res->index, basek, sizek);
- /*
- * 0-640K must be on node 0
- * next range is from 1M---
- * So will cut off before 1M in the mem range
- */
- if((basek+sizek)<1024) return;
-
- if(basek<1024) {
- sizek -= 1024 - basek;
- basek = 1024;
- }
-
- // need to figure out NV
- state->current += acpi_create_srat_mem((acpi_srat_mem_t *)state->current, (res->index & 0xf), basek, sizek, 1);
-}
-
-unsigned long acpi_fill_srat(unsigned long current)
-{
- struct acpi_srat_mem_state srat_mem_state;
-
- /* create all subtables for processors */
- current = acpi_create_srat_lapics(current);
-
- /* create all subteble for memory range */
-
- /* 0-640K must be on node 0 */
- current += acpi_create_srat_mem((acpi_srat_mem_t *)current, 0, 0, 640, 1);//enable
-
- srat_mem_state.current = current;
- search_global_resources(
- IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
- set_srat_mem, &srat_mem_state);
-
- current = srat_mem_state.current;
- return current;
-}
-
-unsigned long acpi_fill_slit(unsigned long current)
-{
- /* need to find out the node num at first */
- /* fill the first 8 byte with that num */
- /* fill the next num*num byte with distance, local is 10, 1 hop mean 20, and 2 hop with 30.... */
-
- struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
- u8 *ln = sysinfox->ln;
-
-
- u8 *p = (u8 *)current;
- int nodes = sysconf.nodes;
- int i,j;
- u32 hops;
-
- memset(p, 0, 8+nodes*nodes);
- *p = (u8) nodes;
- p += 8;
-
- for(i=0;i<nodes;i++) {
- for(j=0;j<nodes; j++) {
- if(i==j) {
- p[i*nodes+j] = 10;
- } else {
- hops = (((ln[i*NODE_NUMS+j]>>4) & 0x7)+1);
- p[i*nodes+j] = hops * 2 + 10;
- }
- }
- }
-
- current += 8+nodes*nodes;
- return current;
-}
-
-// moved from mb acpi_tables.c
-static void intx_to_stream(u32 val, u32 len, u8 *dest)
-{
- int i;
- for(i=0;i<len;i++) {
- *(dest+i) = (val >> (8*i)) & 0xff;
- }
-}
-
-static void int_to_stream(u32 val, u8 *dest)
-{
- return intx_to_stream(val, 4, dest);
-}
-
-// used by acpi_tables.h
-void update_ssdt(void *ssdt)
-{
- u8 *BUSN;
- u8 *MMIO;
- u8 *PCIO;
- u8 *SBLK;
- u8 *TOM1;
- u8 *SBDN;
- u8 *HCLK;
- u8 *HCDN;
- u8 *CBST;
- u8 *CBBX;
- u8 *CBS2;
- u8 *CBB2;
-
-
- int i;
- u32 dword;
- msr_t msr;
-
- // the offset could be different if have different HC_NUMS, and HC_POSSIBLE_NUM and ssdt.asl
- BUSN = ssdt+0x3b; //+5 will be next BUSN
- MMIO = ssdt+0xe4; //+5 will be next MMIO
- PCIO = ssdt+0x36d; //+5 will be next PCIO
- SBLK = ssdt+0x4b2; // one byte
- TOM1 = ssdt+0x4b9; //
- SBDN = ssdt+0x4c3;//
- HCLK = ssdt+0x4d1; //+5 will be next HCLK
- HCDN = ssdt+0x57a; //+5 will be next HCDN
- CBBX = ssdt+0x61f; //
- CBST = ssdt+0x626;
- CBB2 = ssdt+0x62d; //
- CBS2 = ssdt+0x634;
-
- for(i=0;i<HC_NUMS;i++) {
- dword = sysconf.ht_c_conf_bus[i];
- int_to_stream(dword, BUSN+i*5);
- }
-
- for(i=0;i<(HC_NUMS*2);i++) { // FIXME: change to more chain
- dword = sysconf.conf_mmio_addrx[i]; //base
- int_to_stream(dword, MMIO+(i*2)*5);
- dword = sysconf.conf_mmio_addr[i]; //mask
- int_to_stream(dword, MMIO+(i*2+1)*5);
- }
- for(i=0;i<HC_NUMS;i++) { // FIXME: change to more chain
- dword = sysconf.conf_io_addrx[i];
- int_to_stream(dword, PCIO+(i*2)*5);
- dword = sysconf.conf_io_addr[i];
- int_to_stream(dword, PCIO+(i*2+1)*5);
- }
-
- *SBLK = (u8)(sysconf.sblk);
-
- msr = rdmsr(TOP_MEM);
- int_to_stream(msr.lo, TOM1);
-
- int_to_stream(sysconf.sbdn, SBDN);
-
- for(i=0;i<sysconf.hc_possible_num;i++) {
- int_to_stream(sysconf.pci1234[i], HCLK + i*5);
- int_to_stream(sysconf.hcdn[i], HCDN + i*5);
- }
- for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
- int_to_stream(0x00000000, HCLK + i*5);
- int_to_stream(0x20202020, HCDN + i*5);
- }
-
- *CBBX = (u8)(CONFIG_CBB);
-
- if(CONFIG_CBB == 0xff) {
- *CBST = (u8) (0x0f);
- } else {
- if((sysconf.pci1234[0] >> 12) & 0xff) { //sb chain on other than bus 0
- *CBST = (u8) (0x0f);
- }
- else {
- *CBST = (u8) (0x00);
- }
- }
-
- if((CONFIG_CBB == 0xff) && (sysconf.nodes>32)) {
- *CBS2 = 0x0f;
- *CBB2 = (u8)(CONFIG_CBB-1);
- } else {
- *CBS2 = 0x00;
- *CBB2 = 0x00;
- }
-
-}
-
-void update_ssdtx(void *ssdtx, int i)
-{
- u8 *PCI;
- u8 *HCIN;
- u8 *UID;
-
- PCI = ssdtx + 0x32;
- HCIN = ssdtx + 0x39;
- UID = ssdtx + 0x40;
-
- if (i < 7) {
- *PCI = (u8) ('4' + i - 1);
- } else {
- *PCI = (u8) ('A' + i - 1 - 6);
- }
- *HCIN = (u8) i;
- *UID = (u8) (i + 3);
-
- /* FIXME: need to update the GSI id in the ssdtx too */
-
-}
-
-static void update_sspr(void *sspr, u32 nodeid, u32 cpuindex)
-{
- u8 *CPU;
- u8 *CPUIN;
- u8 *COREFREQ;
- u8 *POWER;
- u8 *TRANSITION_LAT;
- u8 *BUSMASTER_LAT;
- u8 *CONTROL;
- u8 *STATUS;
- unsigned offset = 0x94 - 0x7f;
- int i;
-
- CPU = sspr + 0x38;
- CPUIN = sspr + 0x3a;
-
- COREFREQ = sspr + 0x7f; //2 byte
- POWER = sspr + 0x82; //3 bytes
- TRANSITION_LAT = sspr + 0x87; //two bytes
- BUSMASTER_LAT = sspr + 0x8a; //two bytes
- CONTROL = sspr + 0x8d;
- STATUS = sspr + 0x8f;
-
- sprintf((char*)CPU, "%02x", (char)cpuindex);
- *CPUIN = (u8) cpuindex;
-
- for(i=0;i<sysconf.p_state_num;i++) {
- struct p_state_t *p_state = &sysconf.p_state[nodeid * 5 + i];
- intx_to_stream(p_state->corefreq, 2, COREFREQ + i*offset);
- intx_to_stream(p_state->power, 3, POWER + i*offset);
- intx_to_stream(p_state->transition_lat, 2, TRANSITION_LAT + i*offset);
- intx_to_stream(p_state->busmaster_lat, 2, BUSMASTER_LAT + i*offset);
- *((u8 *)(CONTROL + i*offset)) =(u8) p_state->control;
- *((u8 *)(STATUS + i*offset)) =(u8) p_state->status;
- }
-}
-
-extern const unsigned char AmlCode_sspr5[];
-extern const unsigned char AmlCode_sspr4[];
-extern const unsigned char AmlCode_sspr3[];
-extern const unsigned char AmlCode_sspr2[];
-extern const unsigned char AmlCode_sspr1[];
-
-/* fixme: find one good way for different p_state_num */
-unsigned long acpi_add_ssdt_pstates(acpi_rsdp_t *rsdp, unsigned long current)
-{
- device_t cpu;
- int cpu_index = 0;
-
- acpi_header_t *ssdt;
-
- if(!sysconf.p_state_num) return current;
-
- void *AmlCode_sspr;
- switch(sysconf.p_state_num) {
- case 1: AmlCode_sspr = &AmlCode_sspr1; break;
- case 2: AmlCode_sspr = &AmlCode_sspr2; break;
- case 3: AmlCode_sspr = &AmlCode_sspr3; break;
- case 4: AmlCode_sspr = &AmlCode_sspr4; break;
- default: AmlCode_sspr = &AmlCode_sspr5; break;
- }
-
- for(cpu = all_devices; cpu; cpu = cpu->next) {
- if ((cpu->path.type != DEVICE_PATH_APIC) ||
- (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
- continue;
- }
- if (!cpu->enabled) {
- continue;
- }
- printk(BIOS_DEBUG, "ACPI: pstate cpu_index=%02x, node_id=%02x, core_id=%02x\n", cpu_index, cpu->path.apic.node_id, cpu->path.apic.core_id);
-
- current = ( current + 0x0f) & -0x10;
- ssdt = (acpi_header_t *)current;
- memcpy(ssdt, AmlCode_sspr, sizeof(acpi_header_t));
- current += ssdt->length;
- memcpy(ssdt, AmlCode_sspr, ssdt->length);
- update_sspr((void*)ssdt,cpu->path.apic.node_id, cpu_index);
- /* recalculate checksum */
- ssdt->checksum = 0;
- ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
- acpi_add_table(rsdp, ssdt);
-
- cpu_index++;
- }
- return current;
-}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#if defined(__PRE_RAM__)
-typedef struct sys_info sys_info_conf_t;
-#else
-typedef struct amdfam10_sysconf_t sys_info_conf_t;
-#endif
-
-struct dram_base_mask_t {
- u32 base; //[47:27] at [28:8]
- u32 mask; //[47:27] at [28:8] and enable at bit 0
-};
-
-static struct dram_base_mask_t get_dram_base_mask(u32 nodeid)
-{
- device_t dev;
- struct dram_base_mask_t d;
-#if defined(__PRE_RAM__)
- dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1);
-#else
- dev = __f1_dev[0];
-#endif
-
-#if CONFIG_EXT_CONF_SUPPORT == 1
- // I will use ext space only for simple
- pci_write_config32(dev, 0x110, nodeid | (1<<28)); // [47:27] at [28:8]
- d.mask = pci_read_config32(dev, 0x114); // enable is bit 0
- pci_write_config32(dev, 0x110, nodeid | (0<<28));
- d.base = pci_read_config32(dev, 0x114) & 0x1fffff00; //[47:27] at [28:8];
-#else
- u32 temp;
- temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16]
- d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too
- temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
- d.mask |= temp<<21;
-
- temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16]
- d.mask |= (temp & 1); // enable bit
-
- d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too
- temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
- d.base |= temp<<21;
-#endif
- return d;
-}
-
-#if CONFIG_AMDMCT == 0
-static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes)
-{
- u32 i;
- device_t dev;
-#if CONFIG_EXT_CONF_SUPPORT == 1
- // I will use ext space only for simple
- u32 d_base_i, d_base_d, d_mask_i, d_mask_d;
- d_base_i = nodeid | (0<<28);
- d_base_d = d.base | nodeid; //[47:27] at [28:8];
- d_mask_i = nodeid | (1<<28); // [47:27] at [28:8]
- d_mask_d = d.mask; // enable is bit 0
-
-#else
- u32 d_base_lo, d_base_hi, d_mask_lo, d_mask_hi;
- u32 d_base_lo_reg, d_base_hi_reg, d_mask_lo_reg, d_mask_hi_reg;
- d_mask_lo = (((d.mask<<(8+3))|(0x07<<16)) & 0xffff0000)|nodeid; // need to fill DramMask[26:24] with ones
- d_mask_hi = (d.mask>>21) & 0xff;
- d_base_lo = ((d.base<<(8+3)) & 0xffff0000);
- if(d.mask & 1) d_base_lo |= 3;
- d_base_hi = (d.base>>21) & 0xff;
- d_mask_lo_reg = 0x44+(nodeid<<3);
- d_mask_hi_reg = 0x144+(nodeid<<3);
- d_base_lo_reg = 0x40+(nodeid<<3);
- d_base_hi_reg = 0x140+(nodeid<<3);
-#endif
-
- for(i=0;i<nodes;i++) {
-#if defined(__PRE_RAM__)
- dev = NODE_PCI(i, 1);
-#else
- dev = __f1_dev[i];
-#endif
-
-#if CONFIG_EXT_CONF_SUPPORT == 1
- // I will use ext space only for simple
- pci_write_config32(dev, 0x110, d_base_i);
- pci_write_config32(dev, 0x114, d_base_d); //[47:27] at [28:8];
- pci_write_config32(dev, 0x110, d_mask_i); // [47:27] at [28:8]
- pci_write_config32(dev, 0x114, d_mask_d); // enable is bit 0
-#else
- pci_write_config32(dev, d_mask_lo_reg, d_mask_lo); // need to fill DramMask[26:24] with ones
- pci_write_config32(dev, d_mask_hi_reg, d_mask_hi);
- pci_write_config32(dev, d_base_lo_reg, d_base_lo);
- pci_write_config32(dev, d_base_hi_reg, d_base_hi);
-#endif
- }
-
-#if defined(__PRE_RAM__)
- dev = NODE_PCI(nodeid, 1);
-#else
- dev = __f1_dev[nodeid];
-#endif
- pci_write_config32(dev, 0x120, d.base>>8);
- pci_write_config32(dev, 0x124, d.mask>>8);
-
-}
-#endif
-
-#if CONFIG_AMDMCT == 0
-static void set_DctSelBaseAddr(u32 i, u32 sel_m)
-{
- device_t dev;
-#if defined(__PRE_RAM__)
- dev = NODE_PCI(i, 2);
-#else
- dev = __f2_dev[i];
-#endif
- u32 dcs_lo;
- dcs_lo = pci_read_config32(dev, DRAM_CTRL_SEL_LOW);
- dcs_lo &= ~(DCSL_DctSelBaseAddr_47_27_MASK<<DCSL_DctSelBaseAddr_47_27_SHIFT);
- dcs_lo |= (sel_m<<(20+DCSL_DctSelBaseAddr_47_27_SHIFT-27));
- pci_write_config32(dev, DRAM_CTRL_SEL_LOW, dcs_lo);
-
-}
-
-
-static u32 get_DctSelBaseAddr(u32 i)
-{
- device_t dev;
-#if defined(__PRE_RAM__)
- dev = NODE_PCI(i, 2);
-#else
- dev = __f2_dev[i];
-#endif
- u32 sel_m;
- u32 dcs_lo;
- dcs_lo = pci_read_config32(dev, DRAM_CTRL_SEL_LOW);
- dcs_lo &= DCSL_DctSelBaseAddr_47_27_MASK<<DCSL_DctSelBaseAddr_47_27_SHIFT;
- sel_m = dcs_lo>>(20+DCSL_DctSelBaseAddr_47_27_SHIFT-27);
- return sel_m;
-}
-
-#ifdef UNUSED_CODE
-static void set_DctSelHiEn(u32 i, u32 val)
-{
- device_t dev;
-#if defined(__PRE_RAM__)
- dev = NODE_PCI(i, 2);
-#else
- dev = __f2_dev[i];
-#endif
- u32 dcs_lo;
- dcs_lo = pci_read_config32(dev, DRAM_CTRL_SEL_LOW);
- dcs_lo &= ~(7);
- dcs_lo |= (val & 7);
- pci_write_config32(dev, DRAM_CTRL_SEL_LOW, dcs_lo);
-
-}
-#endif
-
-static u32 get_DctSelHiEn(u32 i)
-{
- device_t dev;
-#if defined(__PRE_RAM__)
- dev = NODE_PCI(i, 2);
-#else
- dev = __f2_dev[i];
-#endif
- u32 dcs_lo;
- dcs_lo = pci_read_config32(dev, DRAM_CTRL_SEL_LOW);
- dcs_lo &= 7;
- return dcs_lo;
-
-}
-
-static void set_DctSelBaseOffset(u32 i, u32 sel_off_m)
-{
- device_t dev;
-#if defined(__PRE_RAM__)
- dev = NODE_PCI(i, 2);
-#else
- dev = __f2_dev[i];
-#endif
- u32 dcs_hi;
- dcs_hi = pci_read_config32(dev, DRAM_CTRL_SEL_HIGH);
- dcs_hi &= ~(DCSH_DctSelBaseOffset_47_26_MASK<<DCSH_DctSelBaseOffset_47_26_SHIFT);
- dcs_hi |= sel_off_m<<(20+DCSH_DctSelBaseOffset_47_26_SHIFT-26);
- pci_write_config32(dev, DRAM_CTRL_SEL_HIGH, dcs_hi);
-
-}
-
-#ifdef UNUSED_CODE
-static u32 get_DctSelBaseOffset(u32 i)
-{
- device_t dev;
-#if defined(__PRE_RAM__)
- dev = NODE_PCI(i, 2);
-#else
- dev = __f2_dev[i];
-#endif
- u32 sel_off_m;
- u32 dcs_hi;
- dcs_hi = pci_read_config32(dev, DRAM_CTRL_SEL_HIGH);
- dcs_hi &= DCSH_DctSelBaseOffset_47_26_MASK<<DCSH_DctSelBaseOffset_47_26_SHIFT;
- sel_off_m = dcs_hi>>(20+DCSH_DctSelBaseOffset_47_26_SHIFT-26);
- return sel_off_m;
-}
-#endif
-
-static u32 get_one_DCT(struct mem_info *meminfo)
-{
- u32 one_DCT = 1;
- if(meminfo->is_Width128) {
- one_DCT = 1;
- } else {
- u32 dimm_mask = meminfo->dimm_mask;
- if((dimm_mask >> DIMM_SOCKETS) && (dimm_mask & ((1<<DIMM_SOCKETS)-1))) {
- one_DCT = 0;
- }
- }
-
- return one_DCT;
-}
-
-#if CONFIG_HW_MEM_HOLE_SIZEK != 0
-// See that other copy in northbridge.c
-static u32 hoist_memory(u32 hole_startk, u32 i, u32 one_DCT, u32 nodes)
-{
- u32 ii;
- u32 carry_over;
- device_t dev;
- struct dram_base_mask_t d;
- u32 sel_m;
- u32 sel_hi_en;
- u32 hoist;
-
-
- carry_over = (4*1024*1024) - hole_startk;
-
- for(ii=nodes - 1;ii>i;ii--) {
- d = get_dram_base_mask(ii);
- if(!(d.mask & 1)) continue;
- d.base += (carry_over>>9);
- d.mask += (carry_over>>9);
- set_dram_base_mask(ii, d, nodes);
-
- if(get_DctSelHiEn(ii) & 1) {
- sel_m = get_DctSelBaseAddr(ii);
- sel_m += carry_over>>10;
- set_DctSelBaseAddr(ii, sel_m);
- }
-
- }
- d = get_dram_base_mask(i);
- d.mask += (carry_over>>9);
- set_dram_base_mask(i,d, nodes);
-#if defined(__PRE_RAM__)
- dev = NODE_PCI(i, 1);
-#else
- dev = __f1_dev[i];
-#endif
- sel_hi_en = get_DctSelHiEn(i);
- if(sel_hi_en & 1) {
- sel_m = get_DctSelBaseAddr(i);
- }
- if(d.base == (hole_startk>>9)) {
- //don't need set memhole here, because hole off set will be 0, overflow
- //so need to change base reg instead, new basek will be 4*1024*1024
- d.base = (4*1024*1024)>>9;
- set_dram_base_mask(i, d, nodes);
-
- if(sel_hi_en & 1) {
- sel_m += carry_over>>10;
- set_DctSelBaseAddr(i, sel_m);
- }
- } else {
- hoist = /* hole start address */
- ((hole_startk << 10) & 0xff000000) +
- /* enable */
- 1;
- if(one_DCT||(sel_m>=(hole_startk>>10))) { //one DCT or hole in DCT0
- hoist +=
- /* hole address to memory controller address */
- ((((d.base<<9) + carry_over) >> 6) & 0x0000ff00) ;
-
- if(sel_hi_en & 1) {
- sel_m += (carry_over>>10);
- set_DctSelBaseAddr(i, sel_m);
- set_DctSelBaseOffset(i, sel_m);
- }
- } else { // hole in DCT1 range
- hoist +=
- /* hole address to memory controller address */
- ((((sel_m<<10) + carry_over) >> 6) & 0x0000ff00) ;
- // don't need to update DctSelBaseAddr
- if(sel_hi_en & 1) {
- set_DctSelBaseOffset(i, sel_m);
- }
- }
- pci_write_config32(dev, 0xf0, hoist);
-
- }
-
- return carry_over;
-}
-#endif
-#endif // CONFIG_AMDMCT
-
-
-#if CONFIG_EXT_CONF_SUPPORT
-static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest,
- u32 busn_min, u32 busn_max,
- u32 type)
-{
- device_t dev;
- u32 i;
- u32 tempreg;
- u32 index_min, index_max;
- u32 dest_min, dest_max;
- index_min = busn_min>>2; dest_min = busn_min - (index_min<<2);
- index_max = busn_max>>2; dest_max = busn_max - (index_max<<2);
-
- // three case: index_min==index_max, index_min+1=index_max; index_min+1<index_max
-#if defined(__PRE_RAM__)
- dev = NODE_PCI(nodeid, 1);
-#else
- dev = __f1_dev[nodeid];
-#endif
- if(index_min== index_max) {
- pci_write_config32(dev, 0x110, index_min | (type<<28));
- tempreg = pci_read_config32(dev, 0x114);
- for(i=dest_min; i<=dest_max; i++) {
- tempreg &= ~(0xff<<(i*8));
- tempreg |= (cfg_map_dest<<(i*8));
- }
- pci_write_config32(dev, 0x110, index_min | (type<<28)); // do i need to write it again
- pci_write_config32(dev, 0x114, tempreg);
- } else if(index_min<index_max) {
- pci_write_config32(dev, 0x110, index_min | (type<<28));
- tempreg = pci_read_config32(dev, 0x114);
- for(i=dest_min; i<=3; i++) {
- tempreg &= ~(0xff<<(i*8));
- tempreg |= (cfg_map_dest<<(i*8));
- }
- pci_write_config32(dev, 0x110, index_min | (type<<28)); // do i need to write it again
- pci_write_config32(dev, 0x114, tempreg);
-
- pci_write_config32(dev, 0x110, index_max | (type<<28));
- tempreg = pci_read_config32(dev, 0x114);
- for(i=0; i<=dest_max; i++) {
- tempreg &= ~(0xff<<(i*8));
- tempreg |= (cfg_map_dest<<(i*8));
- }
- pci_write_config32(dev, 0x110, index_max | (type<<28)); // do i need to write it again
- pci_write_config32(dev, 0x114, tempreg);
- if((index_max-index_min)>1) {
- tempreg = 0;
- for(i=0; i<=3; i++) {
- tempreg &= ~(0xff<<(i*8));
- tempreg |= (cfg_map_dest<<(i*8));
- }
- for(i=index_min+1; i<index_max;i++) {
- pci_write_config32(dev, 0x110, i | (type<<28));
- pci_write_config32(dev, 0x114, tempreg);
- }
- }
- }
-}
-#endif
-
-static void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
- u32 busn_min, u32 busn_max, u32 segbit,
- u32 nodes)
-{
- u32 tempreg;
- u32 i;
- device_t dev;
-
- busn_min>>=segbit;
- busn_max>>=segbit;
-
-#if CONFIG_EXT_CONF_SUPPORT
- if(ht_c_index < 4) {
-#endif
- tempreg = 3 | ((nodeid&0xf)<<4) | ((nodeid & 0x30)<<(12-4))|(linkn<<8)|((busn_min & 0xff)<<16)|((busn_max&0xff)<<24);
- for(i=0; i<nodes; i++) {
- #if defined(__PRE_RAM__)
- dev = NODE_PCI(i, 1);
- #else
- dev = __f1_dev[i];
- #endif
- pci_write_config32(dev, 0xe0 + ht_c_index * 4, tempreg);
- }
-#if CONFIG_EXT_CONF_SUPPORT
-
- return;
- }
-
- // if ht_c_index > 3, We should use extend space x114_x6
- u32 cfg_map_dest;
- u32 j;
-
- // for nodeid at first
- cfg_map_dest = (1<<7) | (1<<6) | (linkn<<0);
-
- set_addr_map_reg_4_6_in_one_node(nodeid, cfg_map_dest, busn_min, busn_max, 6);
-
- // all other nodes
- cfg_map_dest = (1<<7) | (0<<6) | (nodeid<<0);
- for(j = 0; j< nodes; j++) {
- if(j== nodeid) continue;
- set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, busn_min, busn_max, 6);
- }
-#endif
-}
-
-static void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
- u32 busn_min, u32 busn_max, u32 nodes)
-{
- u32 i;
- device_t dev;
-
-#if CONFIG_EXT_CONF_SUPPORT
- if(ht_c_index<4) {
-#endif
- for(i=0; i<nodes; i++) {
- #if defined(__PRE_RAM__)
- dev = NODE_PCI(i, 1);
- #else
- dev = __f1_dev[i];
- #endif
- pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0);
- }
-#if CONFIG_EXT_CONF_SUPPORT
- return;
- }
-
- // if hc_c_index >3, We should use busn_min and busn_max to clear extend space
- u32 cfg_map_dest;
- u32 j;
-
-
- // all nodes
- cfg_map_dest = 0;
- for(j = 0; j< nodes; j++) {
- set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, busn_min, busn_max, 6);
- }
-#endif
-
-}
-
-#if CONFIG_PCI_BUS_SEGN_BITS
-static u32 check_segn(device_t dev, u32 segbusn, u32 nodes,
- sys_info_conf_t *sysinfo)
-{
- //check segbusn here, We need every node have the same segn
- if((segbusn & 0xff)>(0xe0-1)) {// use next segn
- u32 segn = (segbusn >> 8) & 0x0f;
- segn++;
- segbusn = segn<<8;
- }
- if(segbusn>>8) {
- u32 val;
- val = pci_read_config32(dev, 0x160);
- val &= ~(0xf<<25);
- val |= (segbusn & 0xf00)<<(25-8);
- pci_write_config32(dev, 0x160, val);
- }
-
- return segbusn;
-}
-#endif
-
-#if defined(__PRE_RAM__)
-static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
- u32 io_min, u32 io_max, u32 nodes)
-{
- u32 i;
- u32 tempreg;
- device_t dev;
-
-#if CONFIG_EXT_CONF_SUPPORT
- if(ht_c_index<4) {
-#endif
- /* io range allocation */
- tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit
- for(i=0; i<nodes; i++) {
- #if defined(__PRE_RAM__)
- dev = NODE_PCI(i, 1);
- #else
- dev = __f1_dev[i];
- #endif
- pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg);
- }
- tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
- for(i=0; i<nodes; i++){
- #if defined(__PRE_RAM__)
- dev = NODE_PCI(i, 1);
- #else
- dev = __f1_dev[i];
- #endif
- pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg);
- }
-#if CONFIG_EXT_CONF_SUPPORT
- return;
- }
-
- u32 cfg_map_dest;
- u32 j;
-
- // if ht_c_index > 3, We should use extend space
-
- if(io_min>io_max) return;
-
- // for nodeid at first
- cfg_map_dest = (1<<7) | (1<<6) | (linkn<<0);
-
- set_addr_map_reg_4_6_in_one_node(nodeid, cfg_map_dest, io_min, io_max, 4);
-
- // all other nodes
- cfg_map_dest = (1<<7) | (0<<6) | (nodeid<<0);
- for(j = 0; j< nodes; j++) {
- if(j== nodeid) continue;
- set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, io_min, io_max, 4);
- }
-#endif
-}
-
-
-static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
- u32 io_min, u32 io_max, u32 nodes)
-{
- u32 i;
- device_t dev;
-#if CONFIG_EXT_CONF_SUPPORT
- if(ht_c_index<4) {
-#endif
- /* io range allocation */
- for(i=0; i<nodes; i++) {
- #if defined(__PRE_RAM__)
- dev = NODE_PCI(i, 1);
- #else
- dev = __f1_dev[i];
- #endif
- pci_write_config32(dev, 0xC4 + ht_c_index * 8, 0);
- pci_write_config32(dev, 0xC0 + ht_c_index * 8, 0);
- }
-#if CONFIG_EXT_CONF_SUPPORT
- return;
- }
- // : if hc_c_index > 3, We should use io_min, io_max to clear extend space
- u32 cfg_map_dest;
- u32 j;
-
-
- // all nodes
- cfg_map_dest = 0;
- for(j = 0; j< nodes; j++) {
- set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, io_min, io_max, 4);
- }
-#endif
-}
-#endif
-
-#ifdef UNUSED_CODE
-static void re_set_all_config_map_reg(u32 nodes, u32 segbit,
- sys_info_conf_t *sysinfo)
-{
- u32 ht_c_index;
- device_t dev;
-
- set_config_map_reg(0, sysinfo->sblk, 0, 0, sysinfo->ht_c_conf_bus[0]>>20, segbit, nodes);
-
- /* clean others */
- for(ht_c_index=1;ht_c_index<4; ht_c_index++) {
- u32 i;
- for(i=0; i<nodes; i++) {
- #if defined(__PRE_RAM__)
- dev = NODE_PCI(i, 1);
- #else
- dev = __f1_dev[i];
- #endif
- pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0);
- }
- }
-#if CONFIG_EXT_CONF_SUPPORT
- u32 j;
- // clear the extend space
- for(j = 0; j< nodes; j++) {
- set_addr_map_reg_4_6_in_one_node(j,0, 0, 0xff, 6);
- }
-#endif
-
- for(ht_c_index = 1; ht_c_index<sysinfo->ht_c_num; ht_c_index++) {
- u32 nodeid, linkn;
- u32 busn_max;
- u32 busn_min;
- nodeid = (sysinfo->ht_c_conf_bus[ht_c_index] >> 2) & 0x3f;
- linkn = (sysinfo->ht_c_conf_bus[ht_c_index]>>8) & 0x7;
- busn_max = sysinfo->ht_c_conf_bus[ht_c_index]>>20;
- busn_min = (sysinfo->ht_c_conf_bus[ht_c_index]>>12) & 0xff;
- busn_min |= busn_max & 0xf00;
- set_config_map_reg(nodeid, linkn, ht_c_index, busn_min, busn_max, segbit, nodes);
- }
-
-}
-#endif
-
-static u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo)
-{
- u32 tempreg;
- u32 ht_c_index = 0;
-
-#if 0
- tempreg = 3 | ((nodeid & 0xf) <<4) | ((nodeid & 0x30)<<(12-4)) | (linkn<<8);
-
- for(ht_c_index=0;ht_c_index<4; ht_c_index++) {
- reg = pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1), 0xe0 + ht_c_index * 4);
- if(((reg & 0xffff) == 0x0000)) { /*found free*/
- break;
- }
- }
-#endif
- tempreg = 3 | ((nodeid & 0x3f)<<2) | (linkn<<8);
- for(ht_c_index=0; ht_c_index<32; ht_c_index++) {
- if(((sysinfo->ht_c_conf_bus[ht_c_index] & 0xfff) == tempreg)){
- return ht_c_index;
- }
- }
-
- for(ht_c_index=0; ht_c_index<32; ht_c_index++) {
- if((sysinfo->ht_c_conf_bus[ht_c_index] == 0)){
- return ht_c_index;
- }
- }
-
- return -1;
-
-}
-
-static void store_ht_c_conf_bus(u32 nodeid, u32 linkn, u32 ht_c_index,
- u32 busn_min, u32 busn_max,
- sys_info_conf_t *sysinfo)
-{
- u32 val;
- val = 3 | ((nodeid & 0x3f)<<2) | (linkn<<8);
- sysinfo->ht_c_conf_bus[ht_c_index] = val | ((busn_min & 0xff) <<12) | (busn_max<<20); // same node need segn are same
-
-}
-
-#ifdef UNUSED_CODE
-static void set_BusSegmentEn(u32 node, u32 segbit)
-{
-#if CONFIG_PCI_BUS_SEGN_BITS
- u32 dword;
- device_t dev;
-
-#if defined(__PRE_RAM__)
- dev = NODE_PCI(node, 0);
-#else
- dev = __f0_dev[node];
-#endif
-
- dword = pci_read_config32(dev, 0x68);
- dword &= ~(7<<28);
- dword |= (segbit<<28); /* bus segment enable */
- pci_write_config32(dev, 0x68, dword);
-#endif
-}
-#endif
-
-#if !defined(__PRE_RAM__)
-static u32 get_io_addr_index(u32 nodeid, u32 linkn)
-{
- u32 index;
-
- for(index=0; index<256; index++) {
- if((sysconf.conf_io_addrx[index+4] == 0)){
- sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ;
- sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4);
- return index;
- }
- }
-
- return 0;
-
-}
-
-static u32 get_mmio_addr_index(u32 nodeid, u32 linkn)
-{
- u32 index;
-
-
- for(index=0; index<64; index++) {
- if((sysconf.conf_mmio_addrx[index+8] == 0)){
- sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ;
- sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4);
- return index;
- }
- }
-
- return 0;
-
-}
-
-static void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index,
- u32 io_min, u32 io_max)
-{
- u32 val;
-#if CONFIG_EXT_CONF_SUPPORT
- if(reg!=0x110) {
-#endif
- /* io range allocation */
- index = (reg-0xc0)>>3;
-#if CONFIG_EXT_CONF_SUPPORT
- } else {
- index+=4;
- }
-#endif
-
- val = (nodeid & 0x3f); // 6 bits used
- sysconf.conf_io_addr[index] = val | ((io_max<<8) & 0xfffff000); //limit : with nodeid
- val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used
- sysconf.conf_io_addrx[index] = val | ((io_min<<8) & 0xfffff000); // base : with enable bit
-
- if( sysconf.io_addr_num<(index+1))
- sysconf.io_addr_num = index+1;
-}
-
-
-static void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index,
- u32 mmio_min, u32 mmio_max)
-{
- u32 val;
-#if CONFIG_EXT_CONF_SUPPORT
- if(reg!=0x110) {
-#endif
- /* io range allocation */
- index = (reg-0x80)>>3;
-#if CONFIG_EXT_CONF_SUPPORT
- } else {
- index+=8;
- }
-#endif
-
- val = (nodeid & 0x3f) ; // 6 bits used
- sysconf.conf_mmio_addr[index] = val | (mmio_max & 0xffffff00); //limit : with nodeid and linkn
- val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used
- sysconf.conf_mmio_addrx[index] = val | (mmio_min & 0xffffff00); // base : with enable bit
-
- if( sysconf.mmio_addr_num<(index+1))
- sysconf.mmio_addr_num = index+1;
-}
-
-
-static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
- u32 io_min, u32 io_max)
-{
-
- u32 i;
- u32 tempreg;
-#if CONFIG_EXT_CONF_SUPPORT
- if(reg!=0x110) {
-#endif
- /* io range allocation */
- tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit
- for(i=0; i<sysconf.nodes; i++)
- pci_write_config32(__f1_dev[i], reg+4, tempreg);
-
- tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
-#if 0
- // FIXME: can we use VGA reg instead?
- if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
- printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n",
- __func__, dev_path(dev), link);
- tempreg |= PCI_IO_BASE_VGA_EN;
- }
- if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
- tempreg |= PCI_IO_BASE_NO_ISA;
- }
-#endif
- for(i=0; i<sysconf.nodes; i++)
- pci_write_config32(__f1_dev[i], reg, tempreg);
-#if CONFIG_EXT_CONF_SUPPORT
- return;
- }
-
- u32 cfg_map_dest;
- u32 j;
- // if ht_c_index > 3, We should use extend space
- if(io_min>io_max) return;
- // for nodeid at first
- cfg_map_dest = (1<<7) | (1<<6) | (linkn<<0);
-
- set_addr_map_reg_4_6_in_one_node(nodeid, cfg_map_dest, io_min, io_max, 4);
-
- // all other nodes
- cfg_map_dest = (1<<7) | (0<<6) | (nodeid<<0);
- for(j = 0; j< sysconf.nodes; j++) {
- if(j== nodeid) continue;
- set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, io_min, io_max, 4);
- }
-#endif
-
-}
-static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes)
-{
-
- u32 i;
- u32 tempreg;
-#if CONFIG_EXT_CONF_SUPPORT
- if(reg!=0x110) {
-#endif
- /* io range allocation */
- tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit
- for(i=0; i<nodes; i++)
- pci_write_config32(__f1_dev[i], reg+4, tempreg);
- tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
- for(i=0; i<sysconf.nodes; i++)
- pci_write_config32(__f1_dev[i], reg, tempreg);
-#if CONFIG_EXT_CONF_SUPPORT
- return;
- }
-
- device_t dev;
- u32 j;
- // if ht_c_index > 3, We should use extend space
- // for nodeid at first
- u32 enable;
-
- if(mmio_min>mmio_max) {
- return;
- }
-
- enable = 1;
-
- dev = __f1_dev[nodeid];
- tempreg = ((mmio_min>>3) & 0x1fffff00)| (1<<6) | (linkn<<0);
- pci_write_config32(dev, 0x110, index | (2<<28));
- pci_write_config32(dev, 0x114, tempreg);
-
- tempreg = ((mmio_max>>3) & 0x1fffff00) | enable;
- pci_write_config32(dev, 0x110, index | (3<<28));
- pci_write_config32(dev, 0x114, tempreg);
-
-
- // all other nodes
- tempreg = ((mmio_min>>3) & 0x1fffff00) | (0<<6) | (nodeid<<0);
- for(j = 0; j< sysconf.nodes; j++) {
- if(j== nodeid) continue;
- dev = __f1_dev[j];
- pci_write_config32(dev, 0x110, index | (2<<28));
- pci_write_config32(dev, 0x114, tempreg);
- }
-
- tempreg = ((mmio_max>>3) & 0x1fffff00) | enable;
- for(j = 0; j< sysconf.nodes; j++) {
- if(j==nodeid) continue;
- dev = __f1_dev[j];
- pci_write_config32(dev, 0x110, index | (3<<28));
- pci_write_config32(dev, 0x114, tempreg);
- }
-#endif
-}
-
-#endif
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef AMDFAM10_NUMS_H
-
-#define AMDFAM10_NUMS_H
-
-#if CONFIG_MAX_PHYSICAL_CPUS > 8
- #if CONFIG_MAX_PHYSICAL_CPUS > 32
- #define NODE_NUMS 64
- #else
- #define NODE_NUMS 32
- #endif
-#else
- #define NODE_NUMS 8
-#endif
-
-// max HC installed at the same time. ...could be bigger than (48+24) if we have 3x4x4
-#define HC_NUMS 32
-
-//it could be more bigger
-#define HC_POSSIBLE_NUM 32
-
-#endif
-
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-#ifndef AMDFAM10_PCI_C
-#define AMDFAM10_PCI_C
-/* bit [10,8] are dev func, bit[1,0] are dev index */
-
-
-static u32 pci_read_config32_index(device_t dev, u32 index_reg, u32 index)
-{
- u32 dword;
-
- pci_write_config32(dev, index_reg, index);
- dword = pci_read_config32(dev, index_reg+0x4);
- return dword;
-}
-
-#ifdef UNUSED_CODE
-static void pci_write_config32_index(device_t dev, u32 index_reg, u32 index, u32 data)
-{
-
- pci_write_config32(dev, index_reg, index);
-
- pci_write_config32(dev, index_reg + 0x4, data);
-
-}
-#endif
-
-static u32 pci_read_config32_index_wait(device_t dev, u32 index_reg, u32 index)
-{
-
- u32 dword;
-
- index &= ~(1<<30);
- pci_write_config32(dev, index_reg, index);
- do {
- dword = pci_read_config32(dev, index_reg);
- } while (!(dword & (1<<31)));
- dword = pci_read_config32(dev, index_reg+0x4);
- return dword;
-}
-
-#ifdef UNUSED_CODE
-static void pci_write_config32_index_wait(device_t dev, u32 index_reg, u32 index, u32 data)
-{
-
- u32 dword;
-
- pci_write_config32(dev, index_reg + 0x4, data);
- index |= (1<<30);
- pci_write_config32(dev, index_reg, index);
- do {
- dword = pci_read_config32(dev, index_reg);
- } while (!(dword & (1<<31)));
-
-}
-#endif
-#endif
-
-
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#if defined(__PRE_RAM__)
+typedef struct sys_info sys_info_conf_t;
+#else
+typedef struct amdfam10_sysconf_t sys_info_conf_t;
+#endif
+
+struct dram_base_mask_t {
+ u32 base; //[47:27] at [28:8]
+ u32 mask; //[47:27] at [28:8] and enable at bit 0
+};
+
+static struct dram_base_mask_t get_dram_base_mask(u32 nodeid)
+{
+ device_t dev;
+ struct dram_base_mask_t d;
+#if defined(__PRE_RAM__)
+ dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1);
+#else
+ dev = __f1_dev[0];
+#endif
+
+#if CONFIG_EXT_CONF_SUPPORT == 1
+ // I will use ext space only for simple
+ pci_write_config32(dev, 0x110, nodeid | (1<<28)); // [47:27] at [28:8]
+ d.mask = pci_read_config32(dev, 0x114); // enable is bit 0
+ pci_write_config32(dev, 0x110, nodeid | (0<<28));
+ d.base = pci_read_config32(dev, 0x114) & 0x1fffff00; //[47:27] at [28:8];
+#else
+ u32 temp;
+ temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16]
+ d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too
+ temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
+ d.mask |= temp<<21;
+
+ temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16]
+ d.mask |= (temp & 1); // enable bit
+
+ d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too
+ temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
+ d.base |= temp<<21;
+#endif
+ return d;
+}
+
+#if CONFIG_AMDMCT == 0
+static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes)
+{
+ u32 i;
+ device_t dev;
+#if CONFIG_EXT_CONF_SUPPORT == 1
+ // I will use ext space only for simple
+ u32 d_base_i, d_base_d, d_mask_i, d_mask_d;
+ d_base_i = nodeid | (0<<28);
+ d_base_d = d.base | nodeid; //[47:27] at [28:8];
+ d_mask_i = nodeid | (1<<28); // [47:27] at [28:8]
+ d_mask_d = d.mask; // enable is bit 0
+
+#else
+ u32 d_base_lo, d_base_hi, d_mask_lo, d_mask_hi;
+ u32 d_base_lo_reg, d_base_hi_reg, d_mask_lo_reg, d_mask_hi_reg;
+ d_mask_lo = (((d.mask<<(8+3))|(0x07<<16)) & 0xffff0000)|nodeid; // need to fill DramMask[26:24] with ones
+ d_mask_hi = (d.mask>>21) & 0xff;
+ d_base_lo = ((d.base<<(8+3)) & 0xffff0000);
+ if(d.mask & 1) d_base_lo |= 3;
+ d_base_hi = (d.base>>21) & 0xff;
+ d_mask_lo_reg = 0x44+(nodeid<<3);
+ d_mask_hi_reg = 0x144+(nodeid<<3);
+ d_base_lo_reg = 0x40+(nodeid<<3);
+ d_base_hi_reg = 0x140+(nodeid<<3);
+#endif
+
+ for(i=0;i<nodes;i++) {
+#if defined(__PRE_RAM__)
+ dev = NODE_PCI(i, 1);
+#else
+ dev = __f1_dev[i];
+#endif
+
+#if CONFIG_EXT_CONF_SUPPORT == 1
+ // I will use ext space only for simple
+ pci_write_config32(dev, 0x110, d_base_i);
+ pci_write_config32(dev, 0x114, d_base_d); //[47:27] at [28:8];
+ pci_write_config32(dev, 0x110, d_mask_i); // [47:27] at [28:8]
+ pci_write_config32(dev, 0x114, d_mask_d); // enable is bit 0
+#else
+ pci_write_config32(dev, d_mask_lo_reg, d_mask_lo); // need to fill DramMask[26:24] with ones
+ pci_write_config32(dev, d_mask_hi_reg, d_mask_hi);
+ pci_write_config32(dev, d_base_lo_reg, d_base_lo);
+ pci_write_config32(dev, d_base_hi_reg, d_base_hi);
+#endif
+ }
+
+#if defined(__PRE_RAM__)
+ dev = NODE_PCI(nodeid, 1);
+#else
+ dev = __f1_dev[nodeid];
+#endif
+ pci_write_config32(dev, 0x120, d.base>>8);
+ pci_write_config32(dev, 0x124, d.mask>>8);
+
+}
+#endif
+
+#if CONFIG_AMDMCT == 0
+static void set_DctSelBaseAddr(u32 i, u32 sel_m)
+{
+ device_t dev;
+#if defined(__PRE_RAM__)
+ dev = NODE_PCI(i, 2);
+#else
+ dev = __f2_dev[i];
+#endif
+ u32 dcs_lo;
+ dcs_lo = pci_read_config32(dev, DRAM_CTRL_SEL_LOW);
+ dcs_lo &= ~(DCSL_DctSelBaseAddr_47_27_MASK<<DCSL_DctSelBaseAddr_47_27_SHIFT);
+ dcs_lo |= (sel_m<<(20+DCSL_DctSelBaseAddr_47_27_SHIFT-27));
+ pci_write_config32(dev, DRAM_CTRL_SEL_LOW, dcs_lo);
+
+}
+
+
+static u32 get_DctSelBaseAddr(u32 i)
+{
+ device_t dev;
+#if defined(__PRE_RAM__)
+ dev = NODE_PCI(i, 2);
+#else
+ dev = __f2_dev[i];
+#endif
+ u32 sel_m;
+ u32 dcs_lo;
+ dcs_lo = pci_read_config32(dev, DRAM_CTRL_SEL_LOW);
+ dcs_lo &= DCSL_DctSelBaseAddr_47_27_MASK<<DCSL_DctSelBaseAddr_47_27_SHIFT;
+ sel_m = dcs_lo>>(20+DCSL_DctSelBaseAddr_47_27_SHIFT-27);
+ return sel_m;
+}
+
+#ifdef UNUSED_CODE
+static void set_DctSelHiEn(u32 i, u32 val)
+{
+ device_t dev;
+#if defined(__PRE_RAM__)
+ dev = NODE_PCI(i, 2);
+#else
+ dev = __f2_dev[i];
+#endif
+ u32 dcs_lo;
+ dcs_lo = pci_read_config32(dev, DRAM_CTRL_SEL_LOW);
+ dcs_lo &= ~(7);
+ dcs_lo |= (val & 7);
+ pci_write_config32(dev, DRAM_CTRL_SEL_LOW, dcs_lo);
+
+}
+#endif
+
+static u32 get_DctSelHiEn(u32 i)
+{
+ device_t dev;
+#if defined(__PRE_RAM__)
+ dev = NODE_PCI(i, 2);
+#else
+ dev = __f2_dev[i];
+#endif
+ u32 dcs_lo;
+ dcs_lo = pci_read_config32(dev, DRAM_CTRL_SEL_LOW);
+ dcs_lo &= 7;
+ return dcs_lo;
+
+}
+
+static void set_DctSelBaseOffset(u32 i, u32 sel_off_m)
+{
+ device_t dev;
+#if defined(__PRE_RAM__)
+ dev = NODE_PCI(i, 2);
+#else
+ dev = __f2_dev[i];
+#endif
+ u32 dcs_hi;
+ dcs_hi = pci_read_config32(dev, DRAM_CTRL_SEL_HIGH);
+ dcs_hi &= ~(DCSH_DctSelBaseOffset_47_26_MASK<<DCSH_DctSelBaseOffset_47_26_SHIFT);
+ dcs_hi |= sel_off_m<<(20+DCSH_DctSelBaseOffset_47_26_SHIFT-26);
+ pci_write_config32(dev, DRAM_CTRL_SEL_HIGH, dcs_hi);
+
+}
+
+#ifdef UNUSED_CODE
+static u32 get_DctSelBaseOffset(u32 i)
+{
+ device_t dev;
+#if defined(__PRE_RAM__)
+ dev = NODE_PCI(i, 2);
+#else
+ dev = __f2_dev[i];
+#endif
+ u32 sel_off_m;
+ u32 dcs_hi;
+ dcs_hi = pci_read_config32(dev, DRAM_CTRL_SEL_HIGH);
+ dcs_hi &= DCSH_DctSelBaseOffset_47_26_MASK<<DCSH_DctSelBaseOffset_47_26_SHIFT;
+ sel_off_m = dcs_hi>>(20+DCSH_DctSelBaseOffset_47_26_SHIFT-26);
+ return sel_off_m;
+}
+#endif
+
+static u32 get_one_DCT(struct mem_info *meminfo)
+{
+ u32 one_DCT = 1;
+ if(meminfo->is_Width128) {
+ one_DCT = 1;
+ } else {
+ u32 dimm_mask = meminfo->dimm_mask;
+ if((dimm_mask >> DIMM_SOCKETS) && (dimm_mask & ((1<<DIMM_SOCKETS)-1))) {
+ one_DCT = 0;
+ }
+ }
+
+ return one_DCT;
+}
+
+#if CONFIG_HW_MEM_HOLE_SIZEK != 0
+// See that other copy in northbridge.c
+static u32 hoist_memory(u32 hole_startk, u32 i, u32 one_DCT, u32 nodes)
+{
+ u32 ii;
+ u32 carry_over;
+ device_t dev;
+ struct dram_base_mask_t d;
+ u32 sel_m;
+ u32 sel_hi_en;
+ u32 hoist;
+
+
+ carry_over = (4*1024*1024) - hole_startk;
+
+ for(ii=nodes - 1;ii>i;ii--) {
+ d = get_dram_base_mask(ii);
+ if(!(d.mask & 1)) continue;
+ d.base += (carry_over>>9);
+ d.mask += (carry_over>>9);
+ set_dram_base_mask(ii, d, nodes);
+
+ if(get_DctSelHiEn(ii) & 1) {
+ sel_m = get_DctSelBaseAddr(ii);
+ sel_m += carry_over>>10;
+ set_DctSelBaseAddr(ii, sel_m);
+ }
+
+ }
+ d = get_dram_base_mask(i);
+ d.mask += (carry_over>>9);
+ set_dram_base_mask(i,d, nodes);
+#if defined(__PRE_RAM__)
+ dev = NODE_PCI(i, 1);
+#else
+ dev = __f1_dev[i];
+#endif
+ sel_hi_en = get_DctSelHiEn(i);
+ if(sel_hi_en & 1) {
+ sel_m = get_DctSelBaseAddr(i);
+ }
+ if(d.base == (hole_startk>>9)) {
+ //don't need set memhole here, because hole off set will be 0, overflow
+ //so need to change base reg instead, new basek will be 4*1024*1024
+ d.base = (4*1024*1024)>>9;
+ set_dram_base_mask(i, d, nodes);
+
+ if(sel_hi_en & 1) {
+ sel_m += carry_over>>10;
+ set_DctSelBaseAddr(i, sel_m);
+ }
+ } else {
+ hoist = /* hole start address */
+ ((hole_startk << 10) & 0xff000000) +
+ /* enable */
+ 1;
+ if(one_DCT||(sel_m>=(hole_startk>>10))) { //one DCT or hole in DCT0
+ hoist +=
+ /* hole address to memory controller address */
+ ((((d.base<<9) + carry_over) >> 6) & 0x0000ff00) ;
+
+ if(sel_hi_en & 1) {
+ sel_m += (carry_over>>10);
+ set_DctSelBaseAddr(i, sel_m);
+ set_DctSelBaseOffset(i, sel_m);
+ }
+ } else { // hole in DCT1 range
+ hoist +=
+ /* hole address to memory controller address */
+ ((((sel_m<<10) + carry_over) >> 6) & 0x0000ff00) ;
+ // don't need to update DctSelBaseAddr
+ if(sel_hi_en & 1) {
+ set_DctSelBaseOffset(i, sel_m);
+ }
+ }
+ pci_write_config32(dev, 0xf0, hoist);
+
+ }
+
+ return carry_over;
+}
+#endif
+#endif // CONFIG_AMDMCT
+
+
+#if CONFIG_EXT_CONF_SUPPORT
+static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest,
+ u32 busn_min, u32 busn_max,
+ u32 type)
+{
+ device_t dev;
+ u32 i;
+ u32 tempreg;
+ u32 index_min, index_max;
+ u32 dest_min, dest_max;
+ index_min = busn_min>>2; dest_min = busn_min - (index_min<<2);
+ index_max = busn_max>>2; dest_max = busn_max - (index_max<<2);
+
+ // three case: index_min==index_max, index_min+1=index_max; index_min+1<index_max
+#if defined(__PRE_RAM__)
+ dev = NODE_PCI(nodeid, 1);
+#else
+ dev = __f1_dev[nodeid];
+#endif
+ if(index_min== index_max) {
+ pci_write_config32(dev, 0x110, index_min | (type<<28));
+ tempreg = pci_read_config32(dev, 0x114);
+ for(i=dest_min; i<=dest_max; i++) {
+ tempreg &= ~(0xff<<(i*8));
+ tempreg |= (cfg_map_dest<<(i*8));
+ }
+ pci_write_config32(dev, 0x110, index_min | (type<<28)); // do i need to write it again
+ pci_write_config32(dev, 0x114, tempreg);
+ } else if(index_min<index_max) {
+ pci_write_config32(dev, 0x110, index_min | (type<<28));
+ tempreg = pci_read_config32(dev, 0x114);
+ for(i=dest_min; i<=3; i++) {
+ tempreg &= ~(0xff<<(i*8));
+ tempreg |= (cfg_map_dest<<(i*8));
+ }
+ pci_write_config32(dev, 0x110, index_min | (type<<28)); // do i need to write it again
+ pci_write_config32(dev, 0x114, tempreg);
+
+ pci_write_config32(dev, 0x110, index_max | (type<<28));
+ tempreg = pci_read_config32(dev, 0x114);
+ for(i=0; i<=dest_max; i++) {
+ tempreg &= ~(0xff<<(i*8));
+ tempreg |= (cfg_map_dest<<(i*8));
+ }
+ pci_write_config32(dev, 0x110, index_max | (type<<28)); // do i need to write it again
+ pci_write_config32(dev, 0x114, tempreg);
+ if((index_max-index_min)>1) {
+ tempreg = 0;
+ for(i=0; i<=3; i++) {
+ tempreg &= ~(0xff<<(i*8));
+ tempreg |= (cfg_map_dest<<(i*8));
+ }
+ for(i=index_min+1; i<index_max;i++) {
+ pci_write_config32(dev, 0x110, i | (type<<28));
+ pci_write_config32(dev, 0x114, tempreg);
+ }
+ }
+ }
+}
+#endif
+
+static void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
+ u32 busn_min, u32 busn_max, u32 segbit,
+ u32 nodes)
+{
+ u32 tempreg;
+ u32 i;
+ device_t dev;
+
+ busn_min>>=segbit;
+ busn_max>>=segbit;
+
+#if CONFIG_EXT_CONF_SUPPORT
+ if(ht_c_index < 4) {
+#endif
+ tempreg = 3 | ((nodeid&0xf)<<4) | ((nodeid & 0x30)<<(12-4))|(linkn<<8)|((busn_min & 0xff)<<16)|((busn_max&0xff)<<24);
+ for(i=0; i<nodes; i++) {
+ #if defined(__PRE_RAM__)
+ dev = NODE_PCI(i, 1);
+ #else
+ dev = __f1_dev[i];
+ #endif
+ pci_write_config32(dev, 0xe0 + ht_c_index * 4, tempreg);
+ }
+#if CONFIG_EXT_CONF_SUPPORT
+
+ return;
+ }
+
+ // if ht_c_index > 3, We should use extend space x114_x6
+ u32 cfg_map_dest;
+ u32 j;
+
+ // for nodeid at first
+ cfg_map_dest = (1<<7) | (1<<6) | (linkn<<0);
+
+ set_addr_map_reg_4_6_in_one_node(nodeid, cfg_map_dest, busn_min, busn_max, 6);
+
+ // all other nodes
+ cfg_map_dest = (1<<7) | (0<<6) | (nodeid<<0);
+ for(j = 0; j< nodes; j++) {
+ if(j== nodeid) continue;
+ set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, busn_min, busn_max, 6);
+ }
+#endif
+}
+
+static void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
+ u32 busn_min, u32 busn_max, u32 nodes)
+{
+ u32 i;
+ device_t dev;
+
+#if CONFIG_EXT_CONF_SUPPORT
+ if(ht_c_index<4) {
+#endif
+ for(i=0; i<nodes; i++) {
+ #if defined(__PRE_RAM__)
+ dev = NODE_PCI(i, 1);
+ #else
+ dev = __f1_dev[i];
+ #endif
+ pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0);
+ }
+#if CONFIG_EXT_CONF_SUPPORT
+ return;
+ }
+
+ // if hc_c_index >3, We should use busn_min and busn_max to clear extend space
+ u32 cfg_map_dest;
+ u32 j;
+
+
+ // all nodes
+ cfg_map_dest = 0;
+ for(j = 0; j< nodes; j++) {
+ set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, busn_min, busn_max, 6);
+ }
+#endif
+
+}
+
+#if CONFIG_PCI_BUS_SEGN_BITS
+static u32 check_segn(device_t dev, u32 segbusn, u32 nodes,
+ sys_info_conf_t *sysinfo)
+{
+ //check segbusn here, We need every node have the same segn
+ if((segbusn & 0xff)>(0xe0-1)) {// use next segn
+ u32 segn = (segbusn >> 8) & 0x0f;
+ segn++;
+ segbusn = segn<<8;
+ }
+ if(segbusn>>8) {
+ u32 val;
+ val = pci_read_config32(dev, 0x160);
+ val &= ~(0xf<<25);
+ val |= (segbusn & 0xf00)<<(25-8);
+ pci_write_config32(dev, 0x160, val);
+ }
+
+ return segbusn;
+}
+#endif
+
+#if defined(__PRE_RAM__)
+static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
+ u32 io_min, u32 io_max, u32 nodes)
+{
+ u32 i;
+ u32 tempreg;
+ device_t dev;
+
+#if CONFIG_EXT_CONF_SUPPORT
+ if(ht_c_index<4) {
+#endif
+ /* io range allocation */
+ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit
+ for(i=0; i<nodes; i++) {
+ #if defined(__PRE_RAM__)
+ dev = NODE_PCI(i, 1);
+ #else
+ dev = __f1_dev[i];
+ #endif
+ pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg);
+ }
+ tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
+ for(i=0; i<nodes; i++){
+ #if defined(__PRE_RAM__)
+ dev = NODE_PCI(i, 1);
+ #else
+ dev = __f1_dev[i];
+ #endif
+ pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg);
+ }
+#if CONFIG_EXT_CONF_SUPPORT
+ return;
+ }
+
+ u32 cfg_map_dest;
+ u32 j;
+
+ // if ht_c_index > 3, We should use extend space
+
+ if(io_min>io_max) return;
+
+ // for nodeid at first
+ cfg_map_dest = (1<<7) | (1<<6) | (linkn<<0);
+
+ set_addr_map_reg_4_6_in_one_node(nodeid, cfg_map_dest, io_min, io_max, 4);
+
+ // all other nodes
+ cfg_map_dest = (1<<7) | (0<<6) | (nodeid<<0);
+ for(j = 0; j< nodes; j++) {
+ if(j== nodeid) continue;
+ set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, io_min, io_max, 4);
+ }
+#endif
+}
+
+
+static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
+ u32 io_min, u32 io_max, u32 nodes)
+{
+ u32 i;
+ device_t dev;
+#if CONFIG_EXT_CONF_SUPPORT
+ if(ht_c_index<4) {
+#endif
+ /* io range allocation */
+ for(i=0; i<nodes; i++) {
+ #if defined(__PRE_RAM__)
+ dev = NODE_PCI(i, 1);
+ #else
+ dev = __f1_dev[i];
+ #endif
+ pci_write_config32(dev, 0xC4 + ht_c_index * 8, 0);
+ pci_write_config32(dev, 0xC0 + ht_c_index * 8, 0);
+ }
+#if CONFIG_EXT_CONF_SUPPORT
+ return;
+ }
+ // : if hc_c_index > 3, We should use io_min, io_max to clear extend space
+ u32 cfg_map_dest;
+ u32 j;
+
+
+ // all nodes
+ cfg_map_dest = 0;
+ for(j = 0; j< nodes; j++) {
+ set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, io_min, io_max, 4);
+ }
+#endif
+}
+#endif
+
+#ifdef UNUSED_CODE
+static void re_set_all_config_map_reg(u32 nodes, u32 segbit,
+ sys_info_conf_t *sysinfo)
+{
+ u32 ht_c_index;
+ device_t dev;
+
+ set_config_map_reg(0, sysinfo->sblk, 0, 0, sysinfo->ht_c_conf_bus[0]>>20, segbit, nodes);
+
+ /* clean others */
+ for(ht_c_index=1;ht_c_index<4; ht_c_index++) {
+ u32 i;
+ for(i=0; i<nodes; i++) {
+ #if defined(__PRE_RAM__)
+ dev = NODE_PCI(i, 1);
+ #else
+ dev = __f1_dev[i];
+ #endif
+ pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0);
+ }
+ }
+#if CONFIG_EXT_CONF_SUPPORT
+ u32 j;
+ // clear the extend space
+ for(j = 0; j< nodes; j++) {
+ set_addr_map_reg_4_6_in_one_node(j,0, 0, 0xff, 6);
+ }
+#endif
+
+ for(ht_c_index = 1; ht_c_index<sysinfo->ht_c_num; ht_c_index++) {
+ u32 nodeid, linkn;
+ u32 busn_max;
+ u32 busn_min;
+ nodeid = (sysinfo->ht_c_conf_bus[ht_c_index] >> 2) & 0x3f;
+ linkn = (sysinfo->ht_c_conf_bus[ht_c_index]>>8) & 0x7;
+ busn_max = sysinfo->ht_c_conf_bus[ht_c_index]>>20;
+ busn_min = (sysinfo->ht_c_conf_bus[ht_c_index]>>12) & 0xff;
+ busn_min |= busn_max & 0xf00;
+ set_config_map_reg(nodeid, linkn, ht_c_index, busn_min, busn_max, segbit, nodes);
+ }
+
+}
+#endif
+
+static u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo)
+{
+ u32 tempreg;
+ u32 ht_c_index = 0;
+
+#if 0
+ tempreg = 3 | ((nodeid & 0xf) <<4) | ((nodeid & 0x30)<<(12-4)) | (linkn<<8);
+
+ for(ht_c_index=0;ht_c_index<4; ht_c_index++) {
+ reg = pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1), 0xe0 + ht_c_index * 4);
+ if(((reg & 0xffff) == 0x0000)) { /*found free*/
+ break;
+ }
+ }
+#endif
+ tempreg = 3 | ((nodeid & 0x3f)<<2) | (linkn<<8);
+ for(ht_c_index=0; ht_c_index<32; ht_c_index++) {
+ if(((sysinfo->ht_c_conf_bus[ht_c_index] & 0xfff) == tempreg)){
+ return ht_c_index;
+ }
+ }
+
+ for(ht_c_index=0; ht_c_index<32; ht_c_index++) {
+ if((sysinfo->ht_c_conf_bus[ht_c_index] == 0)){
+ return ht_c_index;
+ }
+ }
+
+ return -1;
+
+}
+
+static void store_ht_c_conf_bus(u32 nodeid, u32 linkn, u32 ht_c_index,
+ u32 busn_min, u32 busn_max,
+ sys_info_conf_t *sysinfo)
+{
+ u32 val;
+ val = 3 | ((nodeid & 0x3f)<<2) | (linkn<<8);
+ sysinfo->ht_c_conf_bus[ht_c_index] = val | ((busn_min & 0xff) <<12) | (busn_max<<20); // same node need segn are same
+
+}
+
+#ifdef UNUSED_CODE
+static void set_BusSegmentEn(u32 node, u32 segbit)
+{
+#if CONFIG_PCI_BUS_SEGN_BITS
+ u32 dword;
+ device_t dev;
+
+#if defined(__PRE_RAM__)
+ dev = NODE_PCI(node, 0);
+#else
+ dev = __f0_dev[node];
+#endif
+
+ dword = pci_read_config32(dev, 0x68);
+ dword &= ~(7<<28);
+ dword |= (segbit<<28); /* bus segment enable */
+ pci_write_config32(dev, 0x68, dword);
+#endif
+}
+#endif
+
+#if !defined(__PRE_RAM__)
+static u32 get_io_addr_index(u32 nodeid, u32 linkn)
+{
+ u32 index;
+
+ for(index=0; index<256; index++) {
+ if((sysconf.conf_io_addrx[index+4] == 0)){
+ sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ;
+ sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4);
+ return index;
+ }
+ }
+
+ return 0;
+
+}
+
+static u32 get_mmio_addr_index(u32 nodeid, u32 linkn)
+{
+ u32 index;
+
+
+ for(index=0; index<64; index++) {
+ if((sysconf.conf_mmio_addrx[index+8] == 0)){
+ sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ;
+ sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4);
+ return index;
+ }
+ }
+
+ return 0;
+
+}
+
+static void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index,
+ u32 io_min, u32 io_max)
+{
+ u32 val;
+#if CONFIG_EXT_CONF_SUPPORT
+ if(reg!=0x110) {
+#endif
+ /* io range allocation */
+ index = (reg-0xc0)>>3;
+#if CONFIG_EXT_CONF_SUPPORT
+ } else {
+ index+=4;
+ }
+#endif
+
+ val = (nodeid & 0x3f); // 6 bits used
+ sysconf.conf_io_addr[index] = val | ((io_max<<8) & 0xfffff000); //limit : with nodeid
+ val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used
+ sysconf.conf_io_addrx[index] = val | ((io_min<<8) & 0xfffff000); // base : with enable bit
+
+ if( sysconf.io_addr_num<(index+1))
+ sysconf.io_addr_num = index+1;
+}
+
+
+static void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index,
+ u32 mmio_min, u32 mmio_max)
+{
+ u32 val;
+#if CONFIG_EXT_CONF_SUPPORT
+ if(reg!=0x110) {
+#endif
+ /* io range allocation */
+ index = (reg-0x80)>>3;
+#if CONFIG_EXT_CONF_SUPPORT
+ } else {
+ index+=8;
+ }
+#endif
+
+ val = (nodeid & 0x3f) ; // 6 bits used
+ sysconf.conf_mmio_addr[index] = val | (mmio_max & 0xffffff00); //limit : with nodeid and linkn
+ val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used
+ sysconf.conf_mmio_addrx[index] = val | (mmio_min & 0xffffff00); // base : with enable bit
+
+ if( sysconf.mmio_addr_num<(index+1))
+ sysconf.mmio_addr_num = index+1;
+}
+
+
+static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
+ u32 io_min, u32 io_max)
+{
+
+ u32 i;
+ u32 tempreg;
+#if CONFIG_EXT_CONF_SUPPORT
+ if(reg!=0x110) {
+#endif
+ /* io range allocation */
+ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit
+ for(i=0; i<sysconf.nodes; i++)
+ pci_write_config32(__f1_dev[i], reg+4, tempreg);
+
+ tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
+#if 0
+ // FIXME: can we use VGA reg instead?
+ if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
+ printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n",
+ __func__, dev_path(dev), link);
+ tempreg |= PCI_IO_BASE_VGA_EN;
+ }
+ if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
+ tempreg |= PCI_IO_BASE_NO_ISA;
+ }
+#endif
+ for(i=0; i<sysconf.nodes; i++)
+ pci_write_config32(__f1_dev[i], reg, tempreg);
+#if CONFIG_EXT_CONF_SUPPORT
+ return;
+ }
+
+ u32 cfg_map_dest;
+ u32 j;
+ // if ht_c_index > 3, We should use extend space
+ if(io_min>io_max) return;
+ // for nodeid at first
+ cfg_map_dest = (1<<7) | (1<<6) | (linkn<<0);
+
+ set_addr_map_reg_4_6_in_one_node(nodeid, cfg_map_dest, io_min, io_max, 4);
+
+ // all other nodes
+ cfg_map_dest = (1<<7) | (0<<6) | (nodeid<<0);
+ for(j = 0; j< sysconf.nodes; j++) {
+ if(j== nodeid) continue;
+ set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, io_min, io_max, 4);
+ }
+#endif
+
+}
+static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes)
+{
+
+ u32 i;
+ u32 tempreg;
+#if CONFIG_EXT_CONF_SUPPORT
+ if(reg!=0x110) {
+#endif
+ /* io range allocation */
+ tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit
+ for(i=0; i<nodes; i++)
+ pci_write_config32(__f1_dev[i], reg+4, tempreg);
+ tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
+ for(i=0; i<sysconf.nodes; i++)
+ pci_write_config32(__f1_dev[i], reg, tempreg);
+#if CONFIG_EXT_CONF_SUPPORT
+ return;
+ }
+
+ device_t dev;
+ u32 j;
+ // if ht_c_index > 3, We should use extend space
+ // for nodeid at first
+ u32 enable;
+
+ if(mmio_min>mmio_max) {
+ return;
+ }
+
+ enable = 1;
+
+ dev = __f1_dev[nodeid];
+ tempreg = ((mmio_min>>3) & 0x1fffff00)| (1<<6) | (linkn<<0);
+ pci_write_config32(dev, 0x110, index | (2<<28));
+ pci_write_config32(dev, 0x114, tempreg);
+
+ tempreg = ((mmio_max>>3) & 0x1fffff00) | enable;
+ pci_write_config32(dev, 0x110, index | (3<<28));
+ pci_write_config32(dev, 0x114, tempreg);
+
+
+ // all other nodes
+ tempreg = ((mmio_min>>3) & 0x1fffff00) | (0<<6) | (nodeid<<0);
+ for(j = 0; j< sysconf.nodes; j++) {
+ if(j== nodeid) continue;
+ dev = __f1_dev[j];
+ pci_write_config32(dev, 0x110, index | (2<<28));
+ pci_write_config32(dev, 0x114, tempreg);
+ }
+
+ tempreg = ((mmio_max>>3) & 0x1fffff00) | enable;
+ for(j = 0; j< sysconf.nodes; j++) {
+ if(j==nodeid) continue;
+ dev = __f1_dev[j];
+ pci_write_config32(dev, 0x110, index | (3<<28));
+ pci_write_config32(dev, 0x114, tempreg);
+ }
+#endif
+}
+
+#endif
* Generic FAM10 debug code, used by mainboard specific romstage.c
*/
-#include "amdfam10_pci.c"
+#include "pci.c"
#include <delay.h>
static inline void print_debug_addr(const char *str, void *val)
#endif
}
-#include "amdfam10_conf.c"
+#include "conf.c"
static void set_vga_enable_reg(u32 nodeid, u32 linkn)
{
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef AMDFAM10_NUMS_H
+
+#define AMDFAM10_NUMS_H
+
+#if CONFIG_MAX_PHYSICAL_CPUS > 8
+ #if CONFIG_MAX_PHYSICAL_CPUS > 32
+ #define NODE_NUMS 64
+ #else
+ #define NODE_NUMS 32
+ #endif
+#else
+ #define NODE_NUMS 8
+#endif
+
+// max HC installed at the same time. ...could be bigger than (48+24) if we have 3x4x4
+#define HC_NUMS 32
+
+//it could be more bigger
+#define HC_POSSIBLE_NUM 32
+
+#endif
+
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#ifndef AMDFAM10_PCI_C
+#define AMDFAM10_PCI_C
+/* bit [10,8] are dev func, bit[1,0] are dev index */
+
+
+static u32 pci_read_config32_index(device_t dev, u32 index_reg, u32 index)
+{
+ u32 dword;
+
+ pci_write_config32(dev, index_reg, index);
+ dword = pci_read_config32(dev, index_reg+0x4);
+ return dword;
+}
+
+#ifdef UNUSED_CODE
+static void pci_write_config32_index(device_t dev, u32 index_reg, u32 index, u32 data)
+{
+
+ pci_write_config32(dev, index_reg, index);
+
+ pci_write_config32(dev, index_reg + 0x4, data);
+
+}
+#endif
+
+static u32 pci_read_config32_index_wait(device_t dev, u32 index_reg, u32 index)
+{
+
+ u32 dword;
+
+ index &= ~(1<<30);
+ pci_write_config32(dev, index_reg, index);
+ do {
+ dword = pci_read_config32(dev, index_reg);
+ } while (!(dword & (1<<31)));
+ dword = pci_read_config32(dev, index_reg+0x4);
+ return dword;
+}
+
+#ifdef UNUSED_CODE
+static void pci_write_config32_index_wait(device_t dev, u32 index_reg, u32 index, u32 data)
+{
+
+ u32 dword;
+
+ pci_write_config32(dev, index_reg + 0x4, data);
+ index |= (1<<30);
+ pci_write_config32(dev, index_reg, index);
+ do {
+ dword = pci_read_config32(dev, index_reg);
+ } while (!(dword & (1<<31)));
+
+}
+#endif
+#endif
+
+
driver-y += northbridge.c
driver-y += misc_control.c
ramstage-y += get_sblk_pci1234.c
-ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += amdk8_acpi.c
+ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
# Enable this if you want to check the values of the PCI routing registers.
# Call show_all_routes() anywhere amdk8.h is included.
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * Description: Add madt lapic creat dynamically and SRAT related by yhlu
+*/
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <device/pci.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <cpu/amd/amdk8_sysconf.h>
+#include "acpi.h"
+
+//it seems some functions can be moved arch/i386/boot/acpi.c
+
+unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, u8 lint)
+{
+ device_t cpu;
+ int cpu_index = 0;
+
+ for(cpu = all_devices; cpu; cpu = cpu->next) {
+ if ((cpu->path.type != DEVICE_PATH_APIC) ||
+ (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
+ continue;
+ }
+ if (!cpu->enabled) {
+ continue;
+ }
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, cpu_index, flags, lint);
+ cpu_index++;
+ }
+ return current;
+}
+
+unsigned long acpi_create_srat_lapics(unsigned long current)
+{
+ device_t cpu;
+ int cpu_index = 0;
+
+ for(cpu = all_devices; cpu; cpu = cpu->next) {
+ if ((cpu->path.type != DEVICE_PATH_APIC) ||
+ (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
+ continue;
+ }
+ if (!cpu->enabled) {
+ continue;
+ }
+ printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id);
+ current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, cpu->path.apic.node_id, cpu->path.apic.apic_id);
+ cpu_index++;
+ }
+ return current;
+}
+
+static unsigned long resk(uint64_t value)
+{
+ unsigned long resultk;
+ if (value < (1ULL << 42)) {
+ resultk = value >> 10;
+ } else {
+ resultk = 0xffffffff;
+ }
+ return resultk;
+}
+
+struct acpi_srat_mem_state {
+ unsigned long current;
+};
+
+static void set_srat_mem(void *gp, struct device *dev, struct resource *res)
+{
+ struct acpi_srat_mem_state *state = gp;
+ unsigned long basek, sizek;
+ basek = resk(res->base);
+ sizek = resk(res->size);
+
+ printk(BIOS_DEBUG, "set_srat_mem: dev %s, res->index=%04lx startk=%08lx, sizek=%08lx\n",
+ dev_path(dev), res->index, basek, sizek);
+ /*
+ * 0-640K must be on node 0
+ * next range is from 1M---
+ * So will cut off before 1M in the mem range
+ */
+ if((basek+sizek)<1024) return;
+
+ if(basek<1024) {
+ sizek -= 1024 - basek;
+ basek = 1024;
+ }
+
+ // need to figure out NV
+ state->current += acpi_create_srat_mem((acpi_srat_mem_t *)state->current, (res->index & 0xf), basek, sizek, 1);
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ struct acpi_srat_mem_state srat_mem_state;
+
+ /* create all subtables for processors */
+ current = acpi_create_srat_lapics(current);
+
+ /* create all subteble for memory range */
+
+ /* 0-640K must be on node 0 */
+ current += acpi_create_srat_mem((acpi_srat_mem_t *)current, 0, 0, 640, 1);//enable
+
+ srat_mem_state.current = current;
+ search_global_resources(
+ IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
+ set_srat_mem, &srat_mem_state);
+
+ current = srat_mem_state.current;
+ return current;
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+ /* need to find out the node num at first */
+ /* fill the first 8 byte with that num */
+ /* fill the next num*num byte with distance, local is 10, 1 hop mean 20, and 2 hop with 30.... */
+
+ /* because We has assume that we know the topology of the HT connection, So we can have set if we know the node_num */
+ static u8 hops_8[] = { 0, 1, 1, 2, 2, 3, 3, 4,
+ 1, 0, 2, 1, 3, 2, 4, 3,
+ 1, 2, 0, 1, 1, 2, 2, 3,
+ 2, 1, 1, 0, 2, 1, 3, 2,
+ 2, 3, 1, 2, 0, 1, 1, 2,
+ 3, 2, 2, 1, 1, 0, 2, 1,
+ 3, 4, 2, 3, 1, 2, 0, 1,
+ 4, 4, 3, 2, 2, 1, 1, 0 };
+
+// u8 outer_node[8];
+
+ u8 *p = (u8 *)current;
+ int nodes = sysconf.nodes;
+ int i,j;
+ memset(p, 0, 8+nodes*nodes);
+// memset((u8 *)outer_node, 0, 8);
+ *p = (u8) nodes;
+ p += 8;
+
+#if 0
+ for(i=0;i<sysconf.hc_possible_num;i++) {
+ if((sysconf.pci1234[i]&1) !=1 ) continue;
+ outer_node[(sysconf.pci1234[i] >> 4) & 0xf] = 1; // mark the outer node
+ }
+#endif
+
+ for(i=0;i<nodes;i++) {
+ for(j=0;j<nodes; j++) {
+ if(i==j) {
+ p[i*nodes+j] = 10;
+ } else {
+#if 0
+ int k;
+ u8 latency_factor = 0;
+ int k_start, k_end;
+ if(i<j) {
+ k_start = i;
+ k_end = j;
+ } else {
+ k_start = j;
+ k_end = i;
+ }
+ for(k=k_start;k<=k_end; k++) {
+ if(outer_node[k]) {
+ latency_factor = 1;
+ break;
+ }
+ }
+ p[i*nodes+j] = hops_8[i*nodes+j] * 2 + latency_factor + 10;
+#else
+ p[i*nodes+j] = hops_8[i*nodes+j] * 2 + 10;
+#endif
+
+ }
+ }
+ }
+
+ current += 8+nodes*nodes;
+
+ return current;
+}
+
+static int k8acpi_write_HT(void) {
+ int len, lenp, i;
+
+ len = acpigen_write_name("HCLK");
+ lenp = acpigen_write_package(HC_POSSIBLE_NUM);
+
+ for(i=0;i<sysconf.hc_possible_num;i++) {
+ lenp += acpigen_write_dword(sysconf.pci1234[i]);
+ }
+ for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
+ lenp += acpigen_write_dword(0x0);
+ }
+
+ acpigen_patch_len(lenp - 1);
+ len += lenp;
+
+ len += acpigen_write_name("HCDN");
+ lenp = acpigen_write_package(HC_POSSIBLE_NUM);
+
+ for(i=0;i<sysconf.hc_possible_num;i++) {
+ lenp += acpigen_write_dword(sysconf.hcdn[i]);
+ }
+ for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
+ lenp += acpigen_write_dword(0x20202020);
+ }
+ acpigen_patch_len(lenp - 1);
+ len += lenp;
+
+ return len;
+}
+
+static int k8acpi_write_pci_data(int dlen, const char *name, int offset) {
+ device_t dev;
+ uint32_t dword;
+ int len, lenp, i;
+
+ dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
+
+ len = acpigen_write_name(name);
+ lenp = acpigen_write_package(dlen);
+ for(i=0; i<dlen; i++) {
+ dword = pci_read_config32(dev, offset+i*4);
+ lenp += acpigen_write_dword(dword);
+ }
+ // minus the opcode
+ acpigen_patch_len(lenp - 1);
+ return len + lenp;
+}
+
+int k8acpi_write_vars(void)
+{
+ int lens;
+ msr_t msr;
+ char pscope[] = "\\_SB.PCI0";
+
+ lens = acpigen_write_scope(pscope);
+ lens += k8acpi_write_pci_data(4, "BUSN", 0xe0);
+ lens += k8acpi_write_pci_data(8, "PCIO", 0xc0);
+ lens += k8acpi_write_pci_data(16, "MMIO", 0x80);
+ lens += acpigen_write_name_byte("SBLK", sysconf.sblk);
+ lens += acpigen_write_name_byte("CBST",
+ ((sysconf.pci1234[0] >> 12) & 0xff) ? 0xf : 0x0);
+ lens += acpigen_write_name_dword("SBDN", sysconf.sbdn);
+ msr = rdmsr(TOP_MEM);
+ lens += acpigen_write_name_dword("TOM1", msr.lo);
+ msr = rdmsr(TOP_MEM2);
+ /*
+ * Since XP only implements parts of ACPI 2.0, we can't use a qword
+ * here.
+ * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
+ * slide 22ff.
+ * Shift value right by 20 bit to make it fit into 32bit,
+ * giving us 1MB granularity and a limit of almost 4Exabyte of memory.
+ */
+ lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
+
+ lens += k8acpi_write_HT();
+ //minus opcode
+ acpigen_patch_len(lens - 1);
+ return lens;
+}
+
+void update_ssdtx(void *ssdtx, int i)
+{
+ u8 *PCI;
+ u8 *HCIN;
+ u8 *UID;
+
+ PCI = ssdtx + 0x32;
+ HCIN = ssdtx + 0x39;
+ UID = ssdtx + 0x40;
+
+ if (i < 7) {
+ *PCI = (u8) ('4' + i - 1);
+ } else {
+ *PCI = (u8) ('A' + i - 1 - 6);
+ }
+ *HCIN = (u8) i;
+ *UID = (u8) (i + 3);
+
+ /* FIXME: need to update the GSI id in the ssdtx too */
+
+}
+
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Rudolf Marek <r.marek@assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef AMDK8_ACPI_H
+#define AMDK8_ACPI_H
+#include <arch/acpigen.h>
+
+int k8acpi_write_vars(void);
+
+#endif
#define AMDK8_H
#if CONFIG_K8_REV_F_SUPPORT == 1
- #include "amdk8_f.h"
+ #include "f.h"
#else
- #include "amdk8_pre_f.h"
+ #include "pre_f.h"
#endif
#ifdef __PRE_RAM__
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 Advanced Micro Devices, Inc.
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/*
- * Description: Add madt lapic creat dynamically and SRAT related by yhlu
-*/
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
-#include <device/pci.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <cpu/amd/amdk8_sysconf.h>
-#include "amdk8_acpi.h"
-
-//it seems some functions can be moved arch/i386/boot/acpi.c
-
-unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, u8 lint)
-{
- device_t cpu;
- int cpu_index = 0;
-
- for(cpu = all_devices; cpu; cpu = cpu->next) {
- if ((cpu->path.type != DEVICE_PATH_APIC) ||
- (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
- continue;
- }
- if (!cpu->enabled) {
- continue;
- }
- current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, cpu_index, flags, lint);
- cpu_index++;
- }
- return current;
-}
-
-unsigned long acpi_create_srat_lapics(unsigned long current)
-{
- device_t cpu;
- int cpu_index = 0;
-
- for(cpu = all_devices; cpu; cpu = cpu->next) {
- if ((cpu->path.type != DEVICE_PATH_APIC) ||
- (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
- continue;
- }
- if (!cpu->enabled) {
- continue;
- }
- printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id);
- current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, cpu->path.apic.node_id, cpu->path.apic.apic_id);
- cpu_index++;
- }
- return current;
-}
-
-static unsigned long resk(uint64_t value)
-{
- unsigned long resultk;
- if (value < (1ULL << 42)) {
- resultk = value >> 10;
- } else {
- resultk = 0xffffffff;
- }
- return resultk;
-}
-
-struct acpi_srat_mem_state {
- unsigned long current;
-};
-
-static void set_srat_mem(void *gp, struct device *dev, struct resource *res)
-{
- struct acpi_srat_mem_state *state = gp;
- unsigned long basek, sizek;
- basek = resk(res->base);
- sizek = resk(res->size);
-
- printk(BIOS_DEBUG, "set_srat_mem: dev %s, res->index=%04lx startk=%08lx, sizek=%08lx\n",
- dev_path(dev), res->index, basek, sizek);
- /*
- * 0-640K must be on node 0
- * next range is from 1M---
- * So will cut off before 1M in the mem range
- */
- if((basek+sizek)<1024) return;
-
- if(basek<1024) {
- sizek -= 1024 - basek;
- basek = 1024;
- }
-
- // need to figure out NV
- state->current += acpi_create_srat_mem((acpi_srat_mem_t *)state->current, (res->index & 0xf), basek, sizek, 1);
-}
-
-unsigned long acpi_fill_srat(unsigned long current)
-{
- struct acpi_srat_mem_state srat_mem_state;
-
- /* create all subtables for processors */
- current = acpi_create_srat_lapics(current);
-
- /* create all subteble for memory range */
-
- /* 0-640K must be on node 0 */
- current += acpi_create_srat_mem((acpi_srat_mem_t *)current, 0, 0, 640, 1);//enable
-
- srat_mem_state.current = current;
- search_global_resources(
- IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
- set_srat_mem, &srat_mem_state);
-
- current = srat_mem_state.current;
- return current;
-}
-
-unsigned long acpi_fill_slit(unsigned long current)
-{
- /* need to find out the node num at first */
- /* fill the first 8 byte with that num */
- /* fill the next num*num byte with distance, local is 10, 1 hop mean 20, and 2 hop with 30.... */
-
- /* because We has assume that we know the topology of the HT connection, So we can have set if we know the node_num */
- static u8 hops_8[] = { 0, 1, 1, 2, 2, 3, 3, 4,
- 1, 0, 2, 1, 3, 2, 4, 3,
- 1, 2, 0, 1, 1, 2, 2, 3,
- 2, 1, 1, 0, 2, 1, 3, 2,
- 2, 3, 1, 2, 0, 1, 1, 2,
- 3, 2, 2, 1, 1, 0, 2, 1,
- 3, 4, 2, 3, 1, 2, 0, 1,
- 4, 4, 3, 2, 2, 1, 1, 0 };
-
-// u8 outer_node[8];
-
- u8 *p = (u8 *)current;
- int nodes = sysconf.nodes;
- int i,j;
- memset(p, 0, 8+nodes*nodes);
-// memset((u8 *)outer_node, 0, 8);
- *p = (u8) nodes;
- p += 8;
-
-#if 0
- for(i=0;i<sysconf.hc_possible_num;i++) {
- if((sysconf.pci1234[i]&1) !=1 ) continue;
- outer_node[(sysconf.pci1234[i] >> 4) & 0xf] = 1; // mark the outer node
- }
-#endif
-
- for(i=0;i<nodes;i++) {
- for(j=0;j<nodes; j++) {
- if(i==j) {
- p[i*nodes+j] = 10;
- } else {
-#if 0
- int k;
- u8 latency_factor = 0;
- int k_start, k_end;
- if(i<j) {
- k_start = i;
- k_end = j;
- } else {
- k_start = j;
- k_end = i;
- }
- for(k=k_start;k<=k_end; k++) {
- if(outer_node[k]) {
- latency_factor = 1;
- break;
- }
- }
- p[i*nodes+j] = hops_8[i*nodes+j] * 2 + latency_factor + 10;
-#else
- p[i*nodes+j] = hops_8[i*nodes+j] * 2 + 10;
-#endif
-
- }
- }
- }
-
- current += 8+nodes*nodes;
-
- return current;
-}
-
-static int k8acpi_write_HT(void) {
- int len, lenp, i;
-
- len = acpigen_write_name("HCLK");
- lenp = acpigen_write_package(HC_POSSIBLE_NUM);
-
- for(i=0;i<sysconf.hc_possible_num;i++) {
- lenp += acpigen_write_dword(sysconf.pci1234[i]);
- }
- for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
- lenp += acpigen_write_dword(0x0);
- }
-
- acpigen_patch_len(lenp - 1);
- len += lenp;
-
- len += acpigen_write_name("HCDN");
- lenp = acpigen_write_package(HC_POSSIBLE_NUM);
-
- for(i=0;i<sysconf.hc_possible_num;i++) {
- lenp += acpigen_write_dword(sysconf.hcdn[i]);
- }
- for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
- lenp += acpigen_write_dword(0x20202020);
- }
- acpigen_patch_len(lenp - 1);
- len += lenp;
-
- return len;
-}
-
-static int k8acpi_write_pci_data(int dlen, const char *name, int offset) {
- device_t dev;
- uint32_t dword;
- int len, lenp, i;
-
- dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
-
- len = acpigen_write_name(name);
- lenp = acpigen_write_package(dlen);
- for(i=0; i<dlen; i++) {
- dword = pci_read_config32(dev, offset+i*4);
- lenp += acpigen_write_dword(dword);
- }
- // minus the opcode
- acpigen_patch_len(lenp - 1);
- return len + lenp;
-}
-
-int k8acpi_write_vars(void)
-{
- int lens;
- msr_t msr;
- char pscope[] = "\\_SB.PCI0";
-
- lens = acpigen_write_scope(pscope);
- lens += k8acpi_write_pci_data(4, "BUSN", 0xe0);
- lens += k8acpi_write_pci_data(8, "PCIO", 0xc0);
- lens += k8acpi_write_pci_data(16, "MMIO", 0x80);
- lens += acpigen_write_name_byte("SBLK", sysconf.sblk);
- lens += acpigen_write_name_byte("CBST",
- ((sysconf.pci1234[0] >> 12) & 0xff) ? 0xf : 0x0);
- lens += acpigen_write_name_dword("SBDN", sysconf.sbdn);
- msr = rdmsr(TOP_MEM);
- lens += acpigen_write_name_dword("TOM1", msr.lo);
- msr = rdmsr(TOP_MEM2);
- /*
- * Since XP only implements parts of ACPI 2.0, we can't use a qword
- * here.
- * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
- * slide 22ff.
- * Shift value right by 20 bit to make it fit into 32bit,
- * giving us 1MB granularity and a limit of almost 4Exabyte of memory.
- */
- lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
-
- lens += k8acpi_write_HT();
- //minus opcode
- acpigen_patch_len(lens - 1);
- return lens;
-}
-
-void update_ssdtx(void *ssdtx, int i)
-{
- u8 *PCI;
- u8 *HCIN;
- u8 *UID;
-
- PCI = ssdtx + 0x32;
- HCIN = ssdtx + 0x39;
- UID = ssdtx + 0x40;
-
- if (i < 7) {
- *PCI = (u8) ('4' + i - 1);
- } else {
- *PCI = (u8) ('A' + i - 1 - 6);
- }
- *HCIN = (u8) i;
- *UID = (u8) (i + 3);
-
- /* FIXME: need to update the GSI id in the ssdtx too */
-
-}
-
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef AMDK8_ACPI_H
-#define AMDK8_ACPI_H
-#include <arch/acpigen.h>
-
-int k8acpi_write_vars(void);
-
-#endif
+++ /dev/null
-#ifndef AMDK8_F_H
-#define AMDK8_F_H
-
-/* Definitions of various K8 registers */
-/* Function 0 */
-#define HT_TRANSACTION_CONTROL 0x68
-#define HTTC_DIS_RD_B_P (1 << 0)
-#define HTTC_DIS_RD_DW_P (1 << 1)
-#define HTTC_DIS_WR_B_P (1 << 2)
-#define HTTC_DIS_WR_DW_P (1 << 3)
-#define HTTC_DIS_MTS (1 << 4)
-#define HTTC_CPU1_EN (1 << 5)
-#define HTTC_CPU_REQ_PASS_PW (1 << 6)
-#define HTTC_CPU_RD_RSP_PASS_PW (1 << 7)
-#define HTTC_DIS_P_MEM_C (1 << 8)
-#define HTTC_DIS_RMT_MEM_C (1 << 9)
-#define HTTC_DIS_FILL_P (1 << 10)
-#define HTTC_RSP_PASS_PW (1 << 11)
-#define HTTC_CHG_ISOC_TO_ORD (1 << 12)
-#define HTTC_BUF_REL_PRI_SHIFT 13
-#define HTTC_BUF_REL_PRI_MASK 3
-#define HTTC_BUF_REL_PRI_64 0
-#define HTTC_BUF_REL_PRI_16 1
-#define HTTC_BUF_REL_PRI_8 2
-#define HTTC_BUF_REL_PRI_2 3
-#define HTTC_LIMIT_CLDT_CFG (1 << 15)
-#define HTTC_LINT_EN (1 << 16)
-#define HTTC_APIC_EXT_BRD_CST (1 << 17)
-#define HTTC_APIC_EXT_ID (1 << 18)
-#define HTTC_APIC_EXT_SPUR (1 << 19)
-#define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20)
-#define HTTC_DS_NP_REQ_LIMIT_SHIFT 21
-#define HTTC_DS_NP_REQ_LIMIT_MASK 3
-#define HTTC_DS_NP_REQ_LIMIT_NONE 0
-#define HTTC_DS_NP_REQ_LIMIT_1 1
-#define HTTC_DS_NP_REQ_LIMIT_4 2
-#define HTTC_DS_NP_REQ_LIMIT_8 3
-#define HTTC_MED_PRI_BYP_CNT_SHIFT 24
-#define HTTC_MED_PRI_BYP_CNT_MASK 3
-#define HTTC_HI_PRI_BYP_CNT_SHIFT 26
-#define HTTC_HI_PRI_BYP_CNT_MASK 3
-
-
-/* Function 1 */
-#define PCI_IO_BASE0 0xc0
-#define PCI_IO_BASE1 0xc8
-#define PCI_IO_BASE2 0xd0
-#define PCI_IO_BASE3 0xd8
-#define PCI_IO_BASE_VGA_EN (1 << 4)
-#define PCI_IO_BASE_NO_ISA (1 << 5)
-
-
-/* Function 2 */
-#define DRAM_CSBASE 0x40
-#define DRAM_CSMASK 0x60
-#define DRAM_BANK_ADDR_MAP 0x80
-
-#define DRAM_CTRL 0x78
-#define DC_RdPtrInit_SHIFT 0
-#define DC_RdPrtInit_MASK 0xf
-#define DC_RdPadRcvFifoDly_SHIFT 4
-#define DC_RdPadRcvFifoDly_MASK 7
-#define DC_RdPadRcvFiloDly_1_5_CLK 2
-#define DC_RdPadRcvFiloDly_2_CLK 3
-#define DC_RdPadRcvFiloDly_2_5_CLK 4
-#define DC_RdPadRcvFiloDly_3_CLK 5
-#define DC_RdPadRcvFiloDly_3_5_CLK 6
-#define DC_AltVidC3MemClkTriEn (1<<16)
-#define DC_DllTempAdjTime_SHIFT 17
-#define DC_DllTempAdjTime_MASK 1
-#define DC_DllTempAdjTime_5_MS 0
-#define DC_DllTempAdjTime_1_MS 1
-#define DC_DqsRcvEnTrain (1<<18)
-
-#define DRAM_INIT 0x7c
-#define DI_MrsAddress_SHIFT 0
-#define DI_MrsAddress_MASK 0xffff
-#define DI_MrsBank_SHIFT 16
-#define DI_MrsBank_MASK 7
-#define DI_SendRchgAll (1<<24)
-#define DI_SendAutoRefresh (1<<25)
-#define DI_SendMrsCmd (1<<26)
-#define DI_DeassertMemRstX (1<<27)
-#define DI_AssertCke (1<<28)
-#define DI_EnDramInit (1<<31)
-
-#define DRAM_TIMING_LOW 0x88
-#define DTL_TCL_SHIFT 0
-#define DTL_TCL_MASK 7
-#define DTL_TCL_BASE 1
-#define DTL_TCL_MIN 3
-#define DTL_TCL_MAX 6
-#define DTL_TRCD_SHIFT 4
-#define DTL_TRCD_MASK 3
-#define DTL_TRCD_BASE 3
-#define DTL_TRCD_MIN 3
-#define DTL_TRCD_MAX 6
-#define DTL_TRP_SHIFT 8
-#define DTL_TRP_MASK 3
-#define DTL_TRP_BASE 3
-#define DTL_TRP_MIN 3
-#define DTL_TRP_MAX 6
-#define DTL_TRTP_SHIFT 11
-#define DTL_TRTP_MASK 1
-#define DTL_TRTP_BASE 2
-#define DTL_TRTP_MIN 2 /* 4 for 64 bytes*/
-#define DTL_TRTP_MAX 3 /* 5 for 64 bytes */
-#define DTL_TRAS_SHIFT 12
-#define DTL_TRAS_MASK 0xf
-#define DTL_TRAS_BASE 3
-#define DTL_TRAS_MIN 5
-#define DTL_TRAS_MAX 18
-#define DTL_TRC_SHIFT 16
-#define DTL_TRC_MASK 0xf
-#define DTL_TRC_BASE 11
-#define DTL_TRC_MIN 11
-#define DTL_TRC_MAX 26
-#define DTL_TWR_SHIFT 20
-#define DTL_TWR_MASK 3
-#define DTL_TWR_BASE 3
-#define DTL_TWR_MIN 3
-#define DTL_TWR_MAX 6
-#define DTL_TRRD_SHIFT 22
-#define DTL_TRRD_MASK 3
-#define DTL_TRRD_BASE 2
-#define DTL_TRRD_MIN 2
-#define DTL_TRRD_MAX 5
-#define DTL_MemClkDis_SHIFT 24 /* Channel A */
-#define DTL_MemClkDis3 (1 << 26)
-#define DTL_MemClkDis2 (1 << 27)
-#define DTL_MemClkDis1 (1 << 28)
-#define DTL_MemClkDis0 (1 << 29)
-#define DTL_MemClkDis1_AM2 (0x51 << 24)
-#define DTL_MemClkDis0_AM2 (0xa2 << 24)
-#define DTL_MemClkDis0_S1g1 (0xa2 << 24)
-
-/* DTL_MemClkDis for m2 and s1g1 is different */
-
-#define DRAM_TIMING_HIGH 0x8c
-#define DTH_TRWTTO_SHIFT 4
-#define DTH_TRWTTO_MASK 7
-#define DTH_TRWTTO_BASE 2
-#define DTH_TRWTTO_MIN 2
-#define DTH_TRWTTO_MAX 9
-#define DTH_TWTR_SHIFT 8
-#define DTH_TWTR_MASK 3
-#define DTH_TWTR_BASE 0
-#define DTH_TWTR_MIN 1
-#define DTH_TWTR_MAX 3
-#define DTH_TWRRD_SHIFT 10
-#define DTH_TWRRD_MASK 3
-#define DTH_TWRRD_BASE 0
-#define DTH_TWRRD_MIN 0
-#define DTH_TWRRD_MAX 3
-#define DTH_TWRWR_SHIFT 12
-#define DTH_TWRWR_MASK 3
-#define DTH_TWRWR_BASE 1
-#define DTH_TWRWR_MIN 1
-#define DTH_TWRWR_MAX 3
-#define DTH_TRDRD_SHIFT 14
-#define DTH_TRDRD_MASK 3
-#define DTH_TRDRD_BASE 2
-#define DTH_TRDRD_MIN 2
-#define DTH_TRDRD_MAX 5
-#define DTH_TREF_SHIFT 16
-#define DTH_TREF_MASK 3
-#define DTH_TREF_7_8_US 2
-#define DTH_TREF_3_9_US 3
-#define DTH_TRFC0_SHIFT 20 /* for Logical DIMM0 */
-#define DTH_TRFC_MASK 7
-#define DTH_TRFC_75_256M 0
-#define DTH_TRFC_105_512M 1
-#define DTH_TRFC_127_5_1G 2
-#define DTH_TRFC_195_2G 3
-#define DTH_TRFC_327_5_4G 4
-#define DTH_TRFC1_SHIFT 23 /*for Logical DIMM1 */
-#define DTH_TRFC2_SHIFT 26 /*for Logical DIMM2 */
-#define DTH_TRFC3_SHIFT 29 /*for Logical DIMM3 */
-
-#define DRAM_CONFIG_LOW 0x90
-#define DCL_InitDram (1<<0)
-#define DCL_ExitSelfRef (1<<1)
-#define DCL_DramTerm_SHIFT 4
-#define DCL_DramTerm_MASK 3
-#define DCL_DramTerm_No 0
-#define DCL_DramTerm_75_OH 1
-#define DCL_DramTerm_150_OH 2
-#define DCL_DramTerm_50_OH 3
-#define DCL_DrvWeak (1<<7)
-#define DCL_ParEn (1<<8)
-#define DCL_SelfRefRateEn (1<<9)
-#define DCL_BurstLength32 (1<<10)
-#define DCL_Width128 (1<<11)
-#define DCL_X4Dimm_SHIFT 12
-#define DCL_X4Dimm_MASK 0xf
-#define DCL_UnBuffDimm (1<<16)
-#define DCL_DimmEccEn (1<<19)
-
-#define DRAM_CONFIG_HIGH 0x94
-#define DCH_MemClkFreq_SHIFT 0
-#define DCH_MemClkFreq_MASK 7
-#define DCH_MemClkFreq_200MHz 0
-#define DCH_MemClkFreq_266MHz 1
-#define DCH_MemClkFreq_333MHz 2
-#define DCH_MemClkFreq_400MHz 3
-#define DCH_MemClkFreqVal (1<<3)
-#define DCH_MaxAsyncLat_SHIFT 4
-#define DCH_MaxAsyncLat_MASK 0xf
-#define DCH_MaxAsyncLat_BASE 0
-#define DCH_MaxAsyncLat_MIN 0
-#define DCH_MaxAsyncLat_MAX 15
-#define DCH_RDqsEn (1<<12)
-#define DCH_DisDramInterface (1<<14)
-#define DCH_PowerDownEn (1<<15)
-#define DCH_PowerDownMode_SHIFT 16
-#define DCH_PowerDownMode_MASK 1
-#define DCH_PowerDownMode_Channel_CKE 0
-#define DCH_PowerDownMode_ChipSelect_CKE 1
-#define DCH_FourRankSODimm (1<<17)
-#define DCH_FourRankRDimm (1<<18)
-#define DCH_SlowAccessMode (1<<19)
-#define DCH_BankSwizzleMode (1<<22)
-#define DCH_DcqBypassMax_SHIFT 24
-#define DCH_DcqBypassMax_MASK 0xf
-#define DCH_DcqBypassMax_BASE 0
-#define DCH_DcqBypassMax_MIN 0
-#define DCH_DcqBypassMax_MAX 15
-#define DCH_FourActWindow_SHIFT 28
-#define DCH_FourActWindow_MASK 0xf
-#define DCH_FourActWindow_BASE 7
-#define DCH_FourActWindow_MIN 8
-#define DCH_FourActWindow_MAX 20
-
-
-// for 0x98 index and 0x9c data
-#define DRAM_CTRL_ADDI_DATA_OFFSET 0x98
-#define DCAO_DctOffset_SHIFT 0
-#define DCAO_DctOffset_MASK 0x3fffffff
-#define DCAO_DctAccessWrite (1<<30)
-#define DCAO_DctAccessDone (1<<31)
-
-#define DRAM_CTRL_ADDI_DATA_PORT 0x9c
-
-#define DRAM_OUTPUT_DRV_COMP_CTRL 0x00
-#define DODCC_CkeDrvStren_SHIFT 0
-#define DODCC_CkeDrvStren_MASK 3
-#define DODCC_CkeDrvStren_1_0X 0
-#define DODCC_CkeDrvStren_1_25X 1
-#define DODCC_CkeDrvStren_1_5X 2
-#define DODCC_CkeDrvStren_2_0X 3
-#define DODCC_CsOdtDrvStren_SHIFT 4
-#define DODCC_CsOdtDrvStren_MASK 3
-#define DODCC_CsOdtDrvStren_1_0X 0
-#define DODCC_CsOdtDrvStren_1_25X 1
-#define DODCC_CsOdtDrvStren_1_5X 2
-#define DODCC_CsOdtDrvStren_2_0X 3
-#define DODCC_AddrCmdDrvStren_SHIFT 8
-#define DODCC_AddrCmdDrvStren_MASK 3
-#define DODCC_AddrCmdDrvStren_1_0X 0
-#define DODCC_AddrCmdDrvStren_1_25X 1
-#define DODCC_AddrCmdDrvStren_1_5X 2
-#define DODCC_AddrCmdDrvStren_2_0X 3
-#define DODCC_ClkDrvStren_SHIFT 12
-#define DODCC_ClkDrvStren_MASK 3
-#define DODCC_ClkDrvStren_0_75X 0
-#define DODCC_ClkDrvStren_1_0X 1
-#define DODCC_ClkDrvStren_1_25X 2
-#define DODCC_ClkDrvStren_1_5X 3
-#define DODCC_DataDrvStren_SHIFT 16
-#define DODCC_DataDrvStren_MASK 3
-#define DODCC_DataDrvStren_0_75X 0
-#define DODCC_DataDrvStren_1_0X 1
-#define DODCC_DataDrvStren_1_25X 2
-#define DODCC_DataDrvStren_1_5X 3
-#define DODCC_DqsDrvStren_SHIFT 20
-#define DODCC_DqsDrvStren_MASK 3
-#define DODCC_DqsDrvStren_0_75X 0
-#define DODCC_DqsDrvStren_1_0X 1
-#define DODCC_DqsDrvStren_1_25X 2
-#define DODCC_DqsDrvStren_1_5X 3
-#define DODCC_ProcOdt_SHIFT 28
-#define DODCC_ProcOdt_MASK 3
-#define DODCC_ProcOdt_300_OHMS 0
-#define DODCC_ProcOdt_150_OHMS 1
-#define DODCC_ProcOdt_75_OHMS 2
-
-#define DRAM_WRITE_DATA_TIMING_CTRL_LOW 0x01
-#define DWDTCL_WrDatTimeByte0_SHIFT 0
-#define DWDTC_WrDatTimeByte_MASK 0x3f
-#define DWDTC_WrDatTimeByte_BASE 0
-#define DWDTC_WrDatTimeByte_MIN 0
-#define DWDTC_WrDatTimeByte_MAX 47
-#define DWDTCL_WrDatTimeByte1_SHIFT 8
-#define DWDTCL_WrDatTimeByte2_SHIFT 16
-#define DWDTCL_WrDatTimeByte3_SHIFT 24
-
-#define DRAM_WRITE_DATA_TIMING_CTRL_HIGH 0x02
-#define DWDTCH_WrDatTimeByte4_SHIFT 0
-#define DWDTCH_WrDatTimeByte5_SHIFT 8
-#define DWDTCH_WrDatTimeByte6_SHIFT 16
-#define DWDTCH_WrDatTimeByte7_SHIFT 24
-
-#define DRAM_WRITE_DATA_ECC_TIMING_CTRL 0x03
-#define DWDETC_WrChkTime_SHIFT 0
-#define DWDETC_WrChkTime_MASK 0x3f
-#define DWDETC_WrChkTime_BASE 0
-#define DWDETC_WrChkTime_MIN 0
-#define DWDETC_WrChkTime_MAX 47
-
-#define DRAM_ADDR_TIMING_CTRL 0x04
-#define DATC_CkeFineDelay_SHIFT 0
-#define DATC_CkeFineDelay_MASK 0x1f
-#define DATC_CkeFineDelay_BASE 0
-#define DATC_CkeFineDelay_MIN 0
-#define DATC_CkeFineDelay_MAX 31
-#define DATC_CkeSetup (1<<5)
-#define DATC_CsOdtFineDelay_SHIFT 8
-#define DATC_CsOdtFineDelay_MASK 0x1f
-#define DATC_CsOdtFineDelay_BASE 0
-#define DATC_CsOdtFineDelay_MIN 0
-#define DATC_CsOdtFineDelay_MAX 31
-#define DATC_CsOdtSetup (1<<13)
-#define DATC_AddrCmdFineDelay_SHIFT 16
-#define DATC_AddrCmdFineDelay_MASK 0x1f
-#define DATC_AddrCmdFineDelay_BASE 0
-#define DATC_AddrCmdFineDelay_MIN 0
-#define DATC_AddrCmdFineDelay_MAX 31
-#define DATC_AddrCmdSetup (1<<21)
-
-#define DRAM_READ_DQS_TIMING_CTRL_LOW 0x05
-#define DRDTCL_RdDqsTimeByte0_SHIFT 0
-#define DRDTC_RdDqsTimeByte_MASK 0x3f
-#define DRDTC_RdDqsTimeByte_BASE 0
-#define DRDTC_RdDqsTimeByte_MIN 0
-#define DRDTC_RdDqsTimeByte_MAX 47
-#define DRDTCL_RdDqsTimeByte1_SHIFT 8
-#define DRDTCL_RdDqsTimeByte2_SHIFT 16
-#define DRDTCL_RdDqsTimeByte3_SHIFT 24
-
-#define DRAM_READ_DQS_TIMING_CTRL_HIGH 0x06
-#define DRDTCH_RdDqsTimeByte4_SHIFT 0
-#define DRDTCH_RdDqsTimeByte5_SHIFT 8
-#define DRDTCH_RdDqsTimeByte6_SHIFT 16
-#define DRDTCH_RdDqsTimeByte7_SHIFT 24
-
-#define DRAM_READ_DQS_ECC_TIMING_CTRL 0x07
-#define DRDETC_RdDqsTimeCheck_SHIFT 0
-#define DRDETC_RdDqsTimeCheck_MASK 0x3f
-#define DRDETC_RdDqsTimeCheck_BASE 0
-#define DRDETC_RdDqsTimeCheck_MIN 0
-#define DRDETC_RdDqsTimeCheck_MAX 47
-
-#define DRAM_DQS_RECV_ENABLE_TIME0 0x10
-#define DDRET_DqsRcvEnDelay_SHIFT 0
-#define DDRET_DqsRcvEnDelay_MASK 0xff
-#define DDRET_DqsRcvEnDelay_BASE 0
-#define DDRET_DqsRcvEnDelay_MIN 0
-#define DDRET_DqsRcvEnDelay_MAX 0xae /* unit is 50ps */
-
-#define DRAM_DQS_RECV_ENABLE_TIME1 0x13
-#define DRAM_DQS_RECV_ENABLE_TIME2 0x16
-#define DRAM_DQS_RECV_ENABLE_TIME3 0x19
-
-/* there are index 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x30, 0x33, 0x36, 0x39
-that are corresponding to 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x10, 0x13, 0x16, 0x19
-*/
-#define DRAM_CTRL_MISC 0xa0
-#define DCM_MemClrStatus (1<<0)
-#define DCM_DisableJitter (1<<1)
-#define DCM_RdWrQByp_SHIFT 2
-#define DCM_RdWrQByp_MASK 3
-#define DCM_RdWrQByp_2 0
-#define DCM_RdWrQByp_4 1
-#define DCM_RdWrQByp_8 2
-#define DCM_RdWrQByp_16 3
-#define DCM_Mode64BitMux (1<<4)
-#define DCM_DCC_EN (1<<5)
-#define DCM_ILD_lmt_SHIFT 6
-#define DCM_ILD_lmt_MASK 7
-#define DCM_ILD_lmt_0 0
-#define DCM_ILD_lmt_4 1
-#define DCM_ILD_lmt_8 2
-#define DCM_ILD_lmt_16 3
-#define DCM_ILD_lmt_32 4
-#define DCM_ILD_lmt_64 5
-#define DCM_ILD_lmt_128 6
-#define DCM_ILD_lmt_256 7
-#define DCM_DramEnabled (1<<9)
-#define DCM_MemClkDis_SHIFT 24 /* Channel B */
-#define DCM_MemClkDis3 (1 << 26)
-#define DCM_MemClkDis2 (1 << 27)
-#define DCM_MemClkDis1 (1 << 28)
-#define DCM_MemClkDis0 (1 << 29)
-
-
-/* Function 3 */
-#define MCA_NB_CONFIG 0x44
-#define MNC_ECC_EN (1 << 22)
-#define MNC_CHIPKILL_EN (1 << 23)
-
-#define SCRUB_CONTROL 0x58
-#define SCRUB_NONE 0
-#define SCRUB_40ns 1
-#define SCRUB_80ns 2
-#define SCRUB_160ns 3
-#define SCRUB_320ns 4
-#define SCRUB_640ns 5
-#define SCRUB_1_28us 6
-#define SCRUB_2_56us 7
-#define SCRUB_5_12us 8
-#define SCRUB_10_2us 9
-#define SCRUB_20_5us 10
-#define SCRUB_41_0us 11
-#define SCRUB_81_9us 12
-#define SCRUB_163_8us 13
-#define SCRUB_327_7us 14
-#define SCRUB_655_4us 15
-#define SCRUB_1_31ms 16
-#define SCRUB_2_62ms 17
-#define SCRUB_5_24ms 18
-#define SCRUB_10_49ms 19
-#define SCRUB_20_97ms 20
-#define SCRUB_42ms 21
-#define SCRUB_84ms 22
-#define SC_DRAM_SCRUB_RATE_SHFIT 0
-#define SC_DRAM_SCRUB_RATE_MASK 0x1f
-#define SC_L2_SCRUB_RATE_SHIFT 8
-#define SC_L2_SCRUB_RATE_MASK 0x1f
-#define SC_L1D_SCRUB_RATE_SHIFT 16
-#define SC_L1D_SCRUB_RATE_MASK 0x1f
-
-#define SCRUB_ADDR_LOW 0x5C
-
-#define SCRUB_ADDR_HIGH 0x60
-
-#define NORTHBRIDGE_CAP 0xE8
-#define NBCAP_128Bit (1 << 0)
-#define NBCAP_MP (1 << 1)
-#define NBCAP_BIG_MP (1 << 2)
-#define NBCAP_ECC (1 << 3)
-#define NBCAP_CHIPKILL_ECC (1 << 4)
-#define NBCAP_MEMCLK_SHIFT 5
-#define NBCAP_MEMCLK_MASK 3
-#define NBCAP_MEMCLK_200MHZ 3
-#define NBCAP_MEMCLK_266MHZ 2
-#define NBCAP_MEMCLK_333MHZ 1
-#define NBCAP_MEMCLK_NOLIMIT 0
-#define NBCAP_MEMCTRL (1 << 8)
-#define NBCAP_HtcCap (1<<10)
-#define NBCAP_CmpCap_SHIFT 12
-#define NBCAP_CmpCap_MASK 3
-
-
-#define LinkConnected (1 << 0)
-#define InitComplete (1 << 1)
-#define NonCoherent (1 << 2)
-#define ConnectionPending (1 << 4)
-
-#include "raminit.h"
-//struct definitions
-
-struct dimm_size {
- uint8_t per_rank; // it is rows + col + bank_lines + data lines */
- uint8_t rows;
- uint8_t col;
- uint8_t bank; //1, 2, 3 mean 2, 4, 8
- uint8_t rank;
-} __attribute__((packed));
-
-struct mem_info { // pernode
- uint32_t dimm_mask;
- struct dimm_size sz[DIMM_SOCKETS];
- uint32_t x4_mask;
- uint32_t x16_mask;
- uint32_t single_rank_mask;
- uint32_t page_1k_mask;
-// uint32_t ecc_mask;
-// uint32_t registered_mask;
- uint8_t is_opteron;
- uint8_t is_registered;
- uint8_t is_ecc;
- uint8_t is_Width128;
- uint8_t is_64MuxMode;
- uint8_t memclk_set; // we need to use this to retrieve the mem param
- uint8_t rsv[2];
-} __attribute__((packed));
-
-struct link_pair_st {
- device_t udev;
- uint32_t upos;
- uint32_t uoffs;
- device_t dev;
- uint32_t pos;
- uint32_t offs;
-
-} __attribute__((packed));
-
-struct sys_info {
- uint8_t ctrl_present[NODE_NUMS];
- struct mem_info meminfo[NODE_NUMS];
- struct mem_controller ctrl[NODE_NUMS];
- uint8_t mem_trained[NODE_NUMS]; //0: no dimm, 1: trained, 0x80: not started, 0x81: recv1 fail, 0x82: Pos Fail, 0x83:recv2 fail
- uint32_t tom_k;
- uint32_t tom2_k;
-
- uint32_t mem_base[NODE_NUMS];
- uint32_t cs_base[NODE_NUMS*8]; //8 cs_idx
- uint32_t hole_reg[NODE_NUMS]; // can we spare it to one, and put ctrl idx in it
-
- uint8_t dqs_delay_a[NODE_NUMS*2*2*9]; //8 node channel 2, direction 2 , bytelane *9
- uint8_t dqs_rcvr_dly_a[NODE_NUMS*2*8]; //8 node, channel 2, receiver 8
- uint32_t nodes;
- struct link_pair_st link_pair[16];// enough? only in_conherent
- uint32_t link_pair_num;
- uint32_t ht_c_num;
- uint32_t sbdn;
- uint32_t sblk;
- uint32_t sbbusn;
-} __attribute__((packed));
-
-#include <reset.h>
-
-#if ((CONFIG_MEM_TRAIN_SEQ != 1) && defined(__PRE_RAM__)) || \
- ((CONFIG_MEM_TRAIN_SEQ == 1) && !defined(__PRE_RAM__))
-static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo)
-{
-
- int i;
- uint32_t mask = 0;
- unsigned needs_reset = 0;
-
-
- if(sysinfo->nodes == 1) return; // in case only one cpu installed
-
- for(i=1; i<sysinfo->nodes; i++) {
- /* Skip everything if I don't have any memory on this controller */
- if(sysinfo->mem_trained[i]==0x00) continue;
-
- mask |= (1<<i);
-
- }
-
- i = 1;
- while(1) {
- if(mask & (1<<i)) {
- if((sysinfo->mem_trained[i])!=0x80) {
- mask &= ~(1<<i);
- }
- }
-
- if(!mask) break;
-
-#if 0
- /* cpu_relax */
- __asm__ __volatile__("rep;nop": : :"memory");
-#endif
-
- i++;
- i%=sysinfo->nodes;
- }
-
- for(i=0; i<sysinfo->nodes; i++) {
-#ifdef __PRE_RAM__
- print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\n");
-#else
- printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
-#endif
- switch(sysinfo->mem_trained[i]) {
- case 0: //don't need train
- case 1: //trained
- break;
- case 0x81: //recv1: fail
- case 0x82: //Pos :fail
- case 0x83: //recv2: fail
- needs_reset = 1;
- break;
- }
- }
- if(needs_reset) {
-#ifdef __PRE_RAM__
- print_debug("mem trained failed\n");
- soft_reset();
-#else
- printk(BIOS_DEBUG, "mem trained failed\n");
- hard_reset();
-#endif
- }
-
-}
-#endif
-
-#endif /* AMDK8_F_H */
+++ /dev/null
-#ifndef AMDK8_F_PCI_C
-#define AMDK8_F_PCI_C
-
-#ifdef UNUSED_CODE
-/* bit [10,8] are dev func, bit[1,0] are dev index */
-static uint32_t pci_read_config32_index(device_t dev, uint32_t index_reg, uint32_t index)
-{
- uint32_t dword;
-
- pci_write_config32(dev, index_reg, index);
-
- dword = pci_read_config32(dev, index_reg+0x4);
-
- return dword;
-}
-
-static void pci_write_config32_index(device_t dev, uint32_t index_reg, uint32_t index, uint32_t data)
-{
- pci_write_config32(dev, index_reg, index);
-
- pci_write_config32(dev, index_reg + 0x4, data);
-}
-#endif
-
-static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index)
-{
- uint32_t dword;
-
- index &= ~(1<<30);
- pci_write_config32(dev, index_reg, index);
-
- do {
- dword = pci_read_config32(dev, index_reg);
- } while (!(dword & (1<<31)));
-
- dword = pci_read_config32(dev, index_reg+0x4);
-
- return dword;
-}
-
-static void pci_write_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index, uint32_t data)
-{
- uint32_t dword;
-
- pci_write_config32(dev, index_reg + 0x4, data);
-
- index |= (1<<30);
- pci_write_config32(dev, index_reg, index);
- do {
- dword = pci_read_config32(dev, index_reg);
- } while (!(dword & (1<<31)));
-}
-
-#endif
+++ /dev/null
-#ifndef AMDK8_PRE_F_H
-#define AMDK8_PRE_F_H
-
-/* Definitions of various K8 registers */
-/* Function 0 */
-#define HT_TRANSACTION_CONTROL 0x68
-#define HTTC_DIS_RD_B_P (1 << 0)
-#define HTTC_DIS_RD_DW_P (1 << 1)
-#define HTTC_DIS_WR_B_P (1 << 2)
-#define HTTC_DIS_WR_DW_P (1 << 3)
-#define HTTC_DIS_MTS (1 << 4)
-#define HTTC_CPU1_EN (1 << 5)
-#define HTTC_CPU_REQ_PASS_PW (1 << 6)
-#define HTTC_CPU_RD_RSP_PASS_PW (1 << 7)
-#define HTTC_DIS_P_MEM_C (1 << 8)
-#define HTTC_DIS_RMT_MEM_C (1 << 9)
-#define HTTC_DIS_FILL_P (1 << 10)
-#define HTTC_RSP_PASS_PW (1 << 11)
-#define HTTC_CHG_ISOC_TO_ORD (1 << 12)
-#define HTTC_BUF_REL_PRI_SHIFT 13
-#define HTTC_BUF_REL_PRI_MASK 3
-#define HTTC_BUF_REL_PRI_64 0
-#define HTTC_BUF_REL_PRI_16 1
-#define HTTC_BUF_REL_PRI_8 2
-#define HTTC_BUF_REL_PRI_2 3
-#define HTTC_LIMIT_CLDT_CFG (1 << 15)
-#define HTTC_LINT_EN (1 << 16)
-#define HTTC_APIC_EXT_BRD_CST (1 << 17)
-#define HTTC_APIC_EXT_ID (1 << 18)
-#define HTTC_APIC_EXT_SPUR (1 << 19)
-#define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20)
-#define HTTC_DS_NP_REQ_LIMIT_SHIFT 21
-#define HTTC_DS_NP_REQ_LIMIT_MASK 3
-#define HTTC_DS_NP_REQ_LIMIT_NONE 0
-#define HTTC_DS_NP_REQ_LIMIT_1 1
-#define HTTC_DS_NP_REQ_LIMIT_4 2
-#define HTTC_DS_NP_REQ_LIMIT_8 3
-#define HTTC_MED_PRI_BYP_CNT_SHIFT 24
-#define HTTC_MED_PRI_BYP_CNT_MASK 3
-#define HTTC_HI_PRI_BYP_CNT_SHIFT 26
-#define HTTC_HI_PRI_BYP_CNT_MASK 3
-
-
-/* Function 1 */
-#define PCI_IO_BASE0 0xc0
-#define PCI_IO_BASE1 0xc8
-#define PCI_IO_BASE2 0xd0
-#define PCI_IO_BASE3 0xd8
-#define PCI_IO_BASE_VGA_EN (1 << 4)
-#define PCI_IO_BASE_NO_ISA (1 << 5)
-
-
-/* Function 2 */
-#define DRAM_CSBASE 0x40
-#define DRAM_CSMASK 0x60
-#define DRAM_BANK_ADDR_MAP 0x80
-
-#define DRAM_TIMING_LOW 0x88
-#define DTL_TCL_SHIFT 0
-#define DTL_TCL_MASK 0x7
-#define DTL_CL_2 1
-#define DTL_CL_3 2
-#define DTL_CL_2_5 5
-#define DTL_TRC_SHIFT 4
-#define DTL_TRC_MASK 0xf
-#define DTL_TRC_BASE 7
-#define DTL_TRC_MIN 7
-#define DTL_TRC_MAX 22
-#define DTL_TRFC_SHIFT 8
-#define DTL_TRFC_MASK 0xf
-#define DTL_TRFC_BASE 9
-#define DTL_TRFC_MIN 9
-#define DTL_TRFC_MAX 24
-#define DTL_TRCD_SHIFT 12
-#define DTL_TRCD_MASK 0x7
-#define DTL_TRCD_BASE 0
-#define DTL_TRCD_MIN 2
-#define DTL_TRCD_MAX 6
-#define DTL_TRRD_SHIFT 16
-#define DTL_TRRD_MASK 0x7
-#define DTL_TRRD_BASE 0
-#define DTL_TRRD_MIN 2
-#define DTL_TRRD_MAX 4
-#define DTL_TRAS_SHIFT 20
-#define DTL_TRAS_MASK 0xf
-#define DTL_TRAS_BASE 0
-#define DTL_TRAS_MIN 5
-#define DTL_TRAS_MAX 15
-#define DTL_TRP_SHIFT 24
-#define DTL_TRP_MASK 0x7
-#define DTL_TRP_BASE 0
-#define DTL_TRP_MIN 2
-#define DTL_TRP_MAX 6
-#define DTL_TWR_SHIFT 28
-#define DTL_TWR_MASK 0x1
-#define DTL_TWR_BASE 2
-#define DTL_TWR_MIN 2
-#define DTL_TWR_MAX 3
-
-#define DRAM_TIMING_HIGH 0x8c
-#define DTH_TWTR_SHIFT 0
-#define DTH_TWTR_MASK 0x1
-#define DTH_TWTR_BASE 1
-#define DTH_TWTR_MIN 1
-#define DTH_TWTR_MAX 2
-#define DTH_TRWT_SHIFT 4
-#define DTH_TRWT_MASK 0x7
-#define DTH_TRWT_BASE 1
-#define DTH_TRWT_MIN 1
-#define DTH_TRWT_MAX 6
-#define DTH_TREF_SHIFT 8
-#define DTH_TREF_MASK 0x1f
-#define DTH_TREF_100MHZ_4K 0x00
-#define DTH_TREF_133MHZ_4K 0x01
-#define DTH_TREF_166MHZ_4K 0x02
-#define DTH_TREF_200MHZ_4K 0x03
-#define DTH_TREF_100MHZ_8K 0x08
-#define DTH_TREF_133MHZ_8K 0x09
-#define DTH_TREF_166MHZ_8K 0x0A
-#define DTH_TREF_200MHZ_8K 0x0B
-#define DTH_TWCL_SHIFT 20
-#define DTH_TWCL_MASK 0x7
-#define DTH_TWCL_BASE 1
-#define DTH_TWCL_MIN 1
-#define DTH_TWCL_MAX 2
-
-#define DRAM_CONFIG_LOW 0x90
-#define DCL_DLL_Disable (1<<0)
-#define DCL_D_DRV (1<<1)
-#define DCL_QFC_EN (1<<2)
-#define DCL_DisDqsHys (1<<3)
-#define DCL_Burst2Opt (1<<5)
-#define DCL_DramInit (1<<8)
-#define DCL_DualDIMMen (1<<9)
-#define DCL_DramEnable (1<<10)
-#define DCL_MemClrStatus (1<<11)
-#define DCL_ESR (1<<12)
-#define DCL_SRS (1<<13)
-#define DCL_128BitEn (1<<16)
-#define DCL_DimmEccEn (1<<17)
-#define DCL_UnBuffDimm (1<<18)
-#define DCL_32ByteEn (1<<19)
-#define DCL_x4DIMM_SHIFT 20
-#define DCL_DisInRcvrs (1<<24)
-#define DCL_BypMax_SHIFT 25
-#define DCL_En2T (1<<28)
-#define DCL_UpperCSMap (1<<29)
-
-#define DRAM_CONFIG_HIGH 0x94
-#define DCH_ASYNC_LAT_SHIFT 0
-#define DCH_ASYNC_LAT_MASK 0xf
-#define DCH_ASYNC_LAT_BASE 0
-#define DCH_ASYNC_LAT_MIN 0
-#define DCH_ASYNC_LAT_MAX 15
-#define DCH_RDPREAMBLE_SHIFT 8
-#define DCH_RDPREAMBLE_MASK 0xf
-#define DCH_RDPREAMBLE_BASE ((2<<1)+0) /* 2.0 ns */
-#define DCH_RDPREAMBLE_MIN ((2<<1)+0) /* 2.0 ns */
-#define DCH_RDPREAMBLE_MAX ((9<<1)+1) /* 9.5 ns */
-#define DCH_IDLE_LIMIT_SHIFT 16
-#define DCH_IDLE_LIMIT_MASK 0x7
-#define DCH_IDLE_LIMIT_0 0
-#define DCH_IDLE_LIMIT_4 1
-#define DCH_IDLE_LIMIT_8 2
-#define DCH_IDLE_LIMIT_16 3
-#define DCH_IDLE_LIMIT_32 4
-#define DCH_IDLE_LIMIT_64 5
-#define DCH_IDLE_LIMIT_128 6
-#define DCH_IDLE_LIMIT_256 7
-#define DCH_DYN_IDLE_CTR_EN (1 << 19)
-#define DCH_MEMCLK_SHIFT 20
-#define DCH_MEMCLK_MASK 0x7
-#define DCH_MEMCLK_100MHZ 0
-#define DCH_MEMCLK_133MHZ 2
-#define DCH_MEMCLK_166MHZ 5
-#define DCH_MEMCLK_200MHZ 7
-#define DCH_MEMCLK_VALID (1 << 25)
-#define DCH_MEMCLK_EN0 (1 << 26)
-#define DCH_MEMCLK_EN1 (1 << 27)
-#define DCH_MEMCLK_EN2 (1 << 28)
-#define DCH_MEMCLK_EN3 (1 << 29)
-
-/* Function 3 */
-#define MCA_NB_CONFIG 0x44
-#define MNC_ECC_EN (1 << 22)
-#define MNC_CHIPKILL_EN (1 << 23)
-#define SCRUB_CONTROL 0x58
-#define SCRUB_NONE 0
-#define SCRUB_40ns 1
-#define SCRUB_80ns 2
-#define SCRUB_160ns 3
-#define SCRUB_320ns 4
-#define SCRUB_640ns 5
-#define SCRUB_1_28us 6
-#define SCRUB_2_56us 7
-#define SCRUB_5_12us 8
-#define SCRUB_10_2us 9
-#define SCRUB_20_5us 10
-#define SCRUB_41_0us 11
-#define SCRUB_81_9us 12
-#define SCRUB_163_8us 13
-#define SCRUB_327_7us 14
-#define SCRUB_655_4us 15
-#define SCRUB_1_31ms 16
-#define SCRUB_2_62ms 17
-#define SCRUB_5_24ms 18
-#define SCRUB_10_49ms 19
-#define SCRUB_20_97ms 20
-#define SCRUB_42ms 21
-#define SCRUB_84ms 22
-#define SC_DRAM_SCRUB_RATE_SHFIT 0
-#define SC_DRAM_SCRUB_RATE_MASK 0x1f
-#define SC_L2_SCRUB_RATE_SHIFT 8
-#define SC_L2_SCRUB_RATE_MASK 0x1f
-#define SC_L1D_SCRUB_RATE_SHIFT 16
-#define SC_L1D_SCRUB_RATE_MASK 0x1f
-#define SCRUB_ADDR_LOW 0x5C
-#define SCRUB_ADDR_HIGH 0x60
-#define NORTHBRIDGE_CAP 0xE8
-#define NBCAP_128Bit (1 << 0)
-#define NBCAP_MP (1 << 1)
-#define NBCAP_BIG_MP (1 << 2)
-#define NBCAP_ECC (1 << 3)
-#define NBCAP_CHIPKILL_ECC (1 << 4)
-#define NBCAP_MEMCLK_SHIFT 5
-#define NBCAP_MEMCLK_MASK 3
-#define NBCAP_MEMCLK_100MHZ 3
-#define NBCAP_MEMCLK_133MHZ 2
-#define NBCAP_MEMCLK_166MHZ 1
-#define NBCAP_MEMCLK_200MHZ 0
-#define NBCAP_MEMCTRL (1 << 8)
-
-
-#define LinkConnected (1 << 0)
-#define InitComplete (1 << 1)
-#define NonCoherent (1 << 2)
-#define ConnectionPending (1 << 4)
-
-#include "raminit.h"
-//struct definitions
-
-struct link_pair_st {
- device_t udev;
- uint32_t upos;
- uint32_t uoffs;
- device_t dev;
- uint32_t pos;
- uint32_t offs;
-
-} __attribute__((packed));
-
-struct sys_info {
- uint8_t ctrl_present[NODE_NUMS];
- struct mem_controller ctrl[NODE_NUMS];
-
- uint32_t nodes;
- struct link_pair_st link_pair[16];// enough? only in_conherent
- uint32_t link_pair_num;
- uint32_t ht_c_num;
- uint32_t sbdn;
- uint32_t sblk;
- uint32_t sbbusn;
-} __attribute__((packed));
-
-#endif /* AMDK8_PRE_F_H */
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-
-//AMD k8 util for BUSB and res range
-
-Scope (\_SB)
-{
-
- Name (OSTB, Ones)
- Method (OSTP, 0, NotSerialized)
- {
- If (LEqual (^OSTB, Ones))
- {
- Store (0x00, ^OSTB)
- }
-
- Return (^OSTB)
- }
-
- Method (SEQL, 2, Serialized)
- {
- Store (SizeOf (Arg0), Local0)
- Store (SizeOf (Arg1), Local1)
- If (LNot (LEqual (Local0, Local1))) { Return (Zero) }
-
- Name (BUF0, Buffer (Local0) {})
- Store (Arg0, BUF0)
- Name (BUF1, Buffer (Local0) {})
- Store (Arg1, BUF1)
- Store (Zero, Local2)
- While (LLess (Local2, Local0))
- {
- Store (DerefOf (Index (BUF0, Local2)), Local3)
- Store (DerefOf (Index (BUF1, Local2)), Local4)
- If (LNot (LEqual (Local3, Local4))) { Return (Zero) }
-
- Increment (Local2)
- }
-
- Return (One)
- }
-
-
- Method (DADD, 2, NotSerialized)
- {
- Store( Arg1, Local0)
- Store( Arg0, Local1)
- Add( ShiftLeft(Local1,16), Local0, Local0)
- Return (Local0)
- }
-
-
- Method (GHCE, 1, NotSerialized) // check if the HC enabled
- {
- Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
- if(LEqual ( And(Local1, 0x01), 0x01)) { Return (0x0F) }
- Else { Return (0x00) }
- }
-
- Method (GHCN, 1, NotSerialized) // get the node num for the HC
- {
- Store (0x00, Local0)
- Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
- Store (ShiftRight( And (Local1, 0xf0), 0x04), Local0)
- Return (Local0)
- }
-
- Method (GHCL, 1, NotSerialized) // get the link num on node for the HC
- {
- Store (0x00, Local0)
- Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
- Store (ShiftRight( And (Local1, 0xf00), 0x08), Local0)
- Return (Local0)
- }
-
- Method (GHCD, 2, NotSerialized) // get the unit id base for the HT device in HC
- {
- Store (0x00, Local0)
- Store (DerefOf (Index (\_SB.PCI0.HCDN, Arg0)), Local1)
- Store (Arg1, Local2) // Arg1 could be 3, 2, 1, 0
- Multiply (Local2, 0x08, Local2) // change to 24, 16, 8, 0
- Store (And (ShiftRight( Local1, Local2), 0xff), Local0)
- Return (Local0)
- }
-
- /* GetBus(Node, Link) */
- Method (GBUS, 2, NotSerialized)
- {
- Store (0x00, Local0)
- While (LLess (Local0, 0x04))
- {
- Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1)
- If (LEqual (And (Local1, 0x03), 0x03))
- {
- If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04)))
- {
- If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08))))
- {
- Return (ShiftRight (And (Local1, 0x00FF0000), 0x10))
- }
- }
- }
-
- Increment (Local0)
- }
-
- Return (0x00)
- }
-
- /* GetBusResources(Node, Link) */
- Method (GWBN, 2, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x0000, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0001,,,)
- })
- CreateWordField (BUF0, 0x08, BMIN)
- CreateWordField (BUF0, 0x0A, BMAX)
- CreateWordField (BUF0, 0x0E, BLEN)
- Store (0x00, Local0)
- While (LLess (Local0, 0x04))
- {
- Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1)
- If (LEqual (And (Local1, 0x03), 0x03))
- {
- If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04)))
- {
- If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08))))
- {
- Store (ShiftRight (And (Local1, 0x00FF0000), 0x10), BMIN)
- Store (ShiftRight (Local1, 0x18), BMAX)
- Subtract (BMAX, BMIN, BLEN)
- Increment (BLEN)
- Return (RTAG (BUF0))
- }
- }
- }
-
- Increment (Local0)
- }
-
- Return (RTAG (BUF0))
- }
-
- /* GetMemoryResources(Node, Link) */
- Method (GMEM, 2, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
- 0x00000000, // Address Space Granularity
- 0x00000000, // Address Range Minimum
- 0x00000000, // Address Range Maximum
- 0x00000000, // Address Translation Offset
- 0x00000001,,,
- , AddressRangeMemory, TypeStatic)
- })
- CreateDWordField (BUF0, 0x0A, MMIN)
- CreateDWordField (BUF0, 0x0E, MMAX)
- CreateDWordField (BUF0, 0x16, MLEN)
- Store (0x00, Local0)
- Store (0x00, Local4)
- Store (0x00, Local3)
- While (LLess (Local0, 0x10))
- {
- /* Get value of the first register */
- Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local1)
- Increment (Local0)
- Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local2)
- If (LEqual (And (Local1, 0x03), 0x03)) /* Pair enabled? */
- {
- If (LEqual (Arg0, And (Local2, 0x07))) /* Node matches? */
- {
- /* If Link Matches (or we got passed 0xFF) */
- If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04))))
- {
- /* Extract the Base and Limit values */
- Store (ShiftLeft (And (Local1, 0xFFFFFF00), 0x08), MMIN)
- Store (ShiftLeft (And (Local2, 0xFFFFFF00), 0x08), MMAX)
- Or (MMAX, 0xFFFF, MMAX)
- Subtract (MMAX, MMIN, MLEN)
- Increment (MLEN)
-
- If (Local4) /* I've already done this once */
- {
- Concatenate (RTAG (BUF0), Local3, Local5)
- Store (Local5, Local3)
- }
- Else
- {
- Store (RTAG (BUF0), Local3)
- }
-
- Increment (Local4)
- }
- }
- }
-
- Increment (Local0)
- }
-
- If (LNot (Local4)) /* No resources for this node and link. */
- {
- Store (RTAG (BUF0), Local3)
- }
-
- Return (Local3)
- }
-
- /* GetIOResources(Node, Link) */
- Method (GIOR, 2, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x00000000, // Address Space Granularity
- 0x00000000, // Address Range Minimum
- 0x00000000, // Address Range Maximum
- 0x00000000, // Address Translation Offset
- 0x00000001,,,
- , TypeStatic)
- })
- CreateDWordField (BUF0, 0x0A, PMIN)
- CreateDWordField (BUF0, 0x0E, PMAX)
- CreateDWordField (BUF0, 0x16, PLEN)
- Store (0x00, Local0)
- Store (0x00, Local4)
- Store (0x00, Local3)
- While (LLess (Local0, 0x08))
- {
- Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local1)
- Increment (Local0)
- Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local2)
- If (LEqual (And (Local1, 0x03), 0x03)) /* Pair enabled? */
- {
- If (LEqual (Arg0, And (Local2, 0x07))) /* Node matches? */
- {
- /* If Link Matches (or we got passed 0xFF) */
- If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04))))
- {
- /* Extract the Base and Limit values */
- Store (And (Local1, 0x01FFF000), PMIN)
- Store (And (Local2, 0x01FFF000), PMAX)
- Or (PMAX, 0x0FFF, PMAX)
- Subtract (PMAX, PMIN, PLEN)
- Increment (PLEN)
-
- If (Local4) /* I've already done this once */
- {
- Concatenate (RTAG (BUF0), Local3, Local5)
- Store (Local5, Local3)
- }
- Else
- {
- If (LGreater (PMAX, PMIN))
- {
- If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK)))
- {
- Store (0x0D00, PMIN)
- Subtract (PMAX, PMIN, PLEN)
- Increment (PLEN)
- }
-
- Store (RTAG (BUF0), Local3)
- Increment (Local4)
- }
-
- If (And (Local1, 0x10))
- {
- Store (0x03B0, PMIN)
- Store (0x03DF, PMAX)
- Store (0x30, PLEN)
-
- If (Local4)
- {
- Concatenate (RTAG (BUF0), Local3, Local5)
- Store (Local5, Local3)
- }
- Else
- {
- Store (RTAG (BUF0), Local3)
- }
- }
- }
-
- Increment (Local4)
- }
- }
- }
-
- Increment (Local0)
- }
-
- If (LNot (Local4)) /* No resources for this node and link. */
- {
- Store (RTAG (BUF0), Local3)
- }
-
- Return (Local3)
- }
-
- Method (RTAG, 1, NotSerialized)
- {
- Store (Arg0, Local0)
- Store (SizeOf (Local0), Local1)
- Subtract (Local1, 0x02, Local1)
- Multiply (Local1, 0x08, Local1)
- CreateField (Local0, 0x00, Local1, RETB)
- Store (RETB, Local2)
- Return (Local2)
- }
-}
--- /dev/null
+#ifndef AMDK8_F_H
+#define AMDK8_F_H
+
+/* Definitions of various K8 registers */
+/* Function 0 */
+#define HT_TRANSACTION_CONTROL 0x68
+#define HTTC_DIS_RD_B_P (1 << 0)
+#define HTTC_DIS_RD_DW_P (1 << 1)
+#define HTTC_DIS_WR_B_P (1 << 2)
+#define HTTC_DIS_WR_DW_P (1 << 3)
+#define HTTC_DIS_MTS (1 << 4)
+#define HTTC_CPU1_EN (1 << 5)
+#define HTTC_CPU_REQ_PASS_PW (1 << 6)
+#define HTTC_CPU_RD_RSP_PASS_PW (1 << 7)
+#define HTTC_DIS_P_MEM_C (1 << 8)
+#define HTTC_DIS_RMT_MEM_C (1 << 9)
+#define HTTC_DIS_FILL_P (1 << 10)
+#define HTTC_RSP_PASS_PW (1 << 11)
+#define HTTC_CHG_ISOC_TO_ORD (1 << 12)
+#define HTTC_BUF_REL_PRI_SHIFT 13
+#define HTTC_BUF_REL_PRI_MASK 3
+#define HTTC_BUF_REL_PRI_64 0
+#define HTTC_BUF_REL_PRI_16 1
+#define HTTC_BUF_REL_PRI_8 2
+#define HTTC_BUF_REL_PRI_2 3
+#define HTTC_LIMIT_CLDT_CFG (1 << 15)
+#define HTTC_LINT_EN (1 << 16)
+#define HTTC_APIC_EXT_BRD_CST (1 << 17)
+#define HTTC_APIC_EXT_ID (1 << 18)
+#define HTTC_APIC_EXT_SPUR (1 << 19)
+#define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20)
+#define HTTC_DS_NP_REQ_LIMIT_SHIFT 21
+#define HTTC_DS_NP_REQ_LIMIT_MASK 3
+#define HTTC_DS_NP_REQ_LIMIT_NONE 0
+#define HTTC_DS_NP_REQ_LIMIT_1 1
+#define HTTC_DS_NP_REQ_LIMIT_4 2
+#define HTTC_DS_NP_REQ_LIMIT_8 3
+#define HTTC_MED_PRI_BYP_CNT_SHIFT 24
+#define HTTC_MED_PRI_BYP_CNT_MASK 3
+#define HTTC_HI_PRI_BYP_CNT_SHIFT 26
+#define HTTC_HI_PRI_BYP_CNT_MASK 3
+
+
+/* Function 1 */
+#define PCI_IO_BASE0 0xc0
+#define PCI_IO_BASE1 0xc8
+#define PCI_IO_BASE2 0xd0
+#define PCI_IO_BASE3 0xd8
+#define PCI_IO_BASE_VGA_EN (1 << 4)
+#define PCI_IO_BASE_NO_ISA (1 << 5)
+
+
+/* Function 2 */
+#define DRAM_CSBASE 0x40
+#define DRAM_CSMASK 0x60
+#define DRAM_BANK_ADDR_MAP 0x80
+
+#define DRAM_CTRL 0x78
+#define DC_RdPtrInit_SHIFT 0
+#define DC_RdPrtInit_MASK 0xf
+#define DC_RdPadRcvFifoDly_SHIFT 4
+#define DC_RdPadRcvFifoDly_MASK 7
+#define DC_RdPadRcvFiloDly_1_5_CLK 2
+#define DC_RdPadRcvFiloDly_2_CLK 3
+#define DC_RdPadRcvFiloDly_2_5_CLK 4
+#define DC_RdPadRcvFiloDly_3_CLK 5
+#define DC_RdPadRcvFiloDly_3_5_CLK 6
+#define DC_AltVidC3MemClkTriEn (1<<16)
+#define DC_DllTempAdjTime_SHIFT 17
+#define DC_DllTempAdjTime_MASK 1
+#define DC_DllTempAdjTime_5_MS 0
+#define DC_DllTempAdjTime_1_MS 1
+#define DC_DqsRcvEnTrain (1<<18)
+
+#define DRAM_INIT 0x7c
+#define DI_MrsAddress_SHIFT 0
+#define DI_MrsAddress_MASK 0xffff
+#define DI_MrsBank_SHIFT 16
+#define DI_MrsBank_MASK 7
+#define DI_SendRchgAll (1<<24)
+#define DI_SendAutoRefresh (1<<25)
+#define DI_SendMrsCmd (1<<26)
+#define DI_DeassertMemRstX (1<<27)
+#define DI_AssertCke (1<<28)
+#define DI_EnDramInit (1<<31)
+
+#define DRAM_TIMING_LOW 0x88
+#define DTL_TCL_SHIFT 0
+#define DTL_TCL_MASK 7
+#define DTL_TCL_BASE 1
+#define DTL_TCL_MIN 3
+#define DTL_TCL_MAX 6
+#define DTL_TRCD_SHIFT 4
+#define DTL_TRCD_MASK 3
+#define DTL_TRCD_BASE 3
+#define DTL_TRCD_MIN 3
+#define DTL_TRCD_MAX 6
+#define DTL_TRP_SHIFT 8
+#define DTL_TRP_MASK 3
+#define DTL_TRP_BASE 3
+#define DTL_TRP_MIN 3
+#define DTL_TRP_MAX 6
+#define DTL_TRTP_SHIFT 11
+#define DTL_TRTP_MASK 1
+#define DTL_TRTP_BASE 2
+#define DTL_TRTP_MIN 2 /* 4 for 64 bytes*/
+#define DTL_TRTP_MAX 3 /* 5 for 64 bytes */
+#define DTL_TRAS_SHIFT 12
+#define DTL_TRAS_MASK 0xf
+#define DTL_TRAS_BASE 3
+#define DTL_TRAS_MIN 5
+#define DTL_TRAS_MAX 18
+#define DTL_TRC_SHIFT 16
+#define DTL_TRC_MASK 0xf
+#define DTL_TRC_BASE 11
+#define DTL_TRC_MIN 11
+#define DTL_TRC_MAX 26
+#define DTL_TWR_SHIFT 20
+#define DTL_TWR_MASK 3
+#define DTL_TWR_BASE 3
+#define DTL_TWR_MIN 3
+#define DTL_TWR_MAX 6
+#define DTL_TRRD_SHIFT 22
+#define DTL_TRRD_MASK 3
+#define DTL_TRRD_BASE 2
+#define DTL_TRRD_MIN 2
+#define DTL_TRRD_MAX 5
+#define DTL_MemClkDis_SHIFT 24 /* Channel A */
+#define DTL_MemClkDis3 (1 << 26)
+#define DTL_MemClkDis2 (1 << 27)
+#define DTL_MemClkDis1 (1 << 28)
+#define DTL_MemClkDis0 (1 << 29)
+#define DTL_MemClkDis1_AM2 (0x51 << 24)
+#define DTL_MemClkDis0_AM2 (0xa2 << 24)
+#define DTL_MemClkDis0_S1g1 (0xa2 << 24)
+
+/* DTL_MemClkDis for m2 and s1g1 is different */
+
+#define DRAM_TIMING_HIGH 0x8c
+#define DTH_TRWTTO_SHIFT 4
+#define DTH_TRWTTO_MASK 7
+#define DTH_TRWTTO_BASE 2
+#define DTH_TRWTTO_MIN 2
+#define DTH_TRWTTO_MAX 9
+#define DTH_TWTR_SHIFT 8
+#define DTH_TWTR_MASK 3
+#define DTH_TWTR_BASE 0
+#define DTH_TWTR_MIN 1
+#define DTH_TWTR_MAX 3
+#define DTH_TWRRD_SHIFT 10
+#define DTH_TWRRD_MASK 3
+#define DTH_TWRRD_BASE 0
+#define DTH_TWRRD_MIN 0
+#define DTH_TWRRD_MAX 3
+#define DTH_TWRWR_SHIFT 12
+#define DTH_TWRWR_MASK 3
+#define DTH_TWRWR_BASE 1
+#define DTH_TWRWR_MIN 1
+#define DTH_TWRWR_MAX 3
+#define DTH_TRDRD_SHIFT 14
+#define DTH_TRDRD_MASK 3
+#define DTH_TRDRD_BASE 2
+#define DTH_TRDRD_MIN 2
+#define DTH_TRDRD_MAX 5
+#define DTH_TREF_SHIFT 16
+#define DTH_TREF_MASK 3
+#define DTH_TREF_7_8_US 2
+#define DTH_TREF_3_9_US 3
+#define DTH_TRFC0_SHIFT 20 /* for Logical DIMM0 */
+#define DTH_TRFC_MASK 7
+#define DTH_TRFC_75_256M 0
+#define DTH_TRFC_105_512M 1
+#define DTH_TRFC_127_5_1G 2
+#define DTH_TRFC_195_2G 3
+#define DTH_TRFC_327_5_4G 4
+#define DTH_TRFC1_SHIFT 23 /*for Logical DIMM1 */
+#define DTH_TRFC2_SHIFT 26 /*for Logical DIMM2 */
+#define DTH_TRFC3_SHIFT 29 /*for Logical DIMM3 */
+
+#define DRAM_CONFIG_LOW 0x90
+#define DCL_InitDram (1<<0)
+#define DCL_ExitSelfRef (1<<1)
+#define DCL_DramTerm_SHIFT 4
+#define DCL_DramTerm_MASK 3
+#define DCL_DramTerm_No 0
+#define DCL_DramTerm_75_OH 1
+#define DCL_DramTerm_150_OH 2
+#define DCL_DramTerm_50_OH 3
+#define DCL_DrvWeak (1<<7)
+#define DCL_ParEn (1<<8)
+#define DCL_SelfRefRateEn (1<<9)
+#define DCL_BurstLength32 (1<<10)
+#define DCL_Width128 (1<<11)
+#define DCL_X4Dimm_SHIFT 12
+#define DCL_X4Dimm_MASK 0xf
+#define DCL_UnBuffDimm (1<<16)
+#define DCL_DimmEccEn (1<<19)
+
+#define DRAM_CONFIG_HIGH 0x94
+#define DCH_MemClkFreq_SHIFT 0
+#define DCH_MemClkFreq_MASK 7
+#define DCH_MemClkFreq_200MHz 0
+#define DCH_MemClkFreq_266MHz 1
+#define DCH_MemClkFreq_333MHz 2
+#define DCH_MemClkFreq_400MHz 3
+#define DCH_MemClkFreqVal (1<<3)
+#define DCH_MaxAsyncLat_SHIFT 4
+#define DCH_MaxAsyncLat_MASK 0xf
+#define DCH_MaxAsyncLat_BASE 0
+#define DCH_MaxAsyncLat_MIN 0
+#define DCH_MaxAsyncLat_MAX 15
+#define DCH_RDqsEn (1<<12)
+#define DCH_DisDramInterface (1<<14)
+#define DCH_PowerDownEn (1<<15)
+#define DCH_PowerDownMode_SHIFT 16
+#define DCH_PowerDownMode_MASK 1
+#define DCH_PowerDownMode_Channel_CKE 0
+#define DCH_PowerDownMode_ChipSelect_CKE 1
+#define DCH_FourRankSODimm (1<<17)
+#define DCH_FourRankRDimm (1<<18)
+#define DCH_SlowAccessMode (1<<19)
+#define DCH_BankSwizzleMode (1<<22)
+#define DCH_DcqBypassMax_SHIFT 24
+#define DCH_DcqBypassMax_MASK 0xf
+#define DCH_DcqBypassMax_BASE 0
+#define DCH_DcqBypassMax_MIN 0
+#define DCH_DcqBypassMax_MAX 15
+#define DCH_FourActWindow_SHIFT 28
+#define DCH_FourActWindow_MASK 0xf
+#define DCH_FourActWindow_BASE 7
+#define DCH_FourActWindow_MIN 8
+#define DCH_FourActWindow_MAX 20
+
+
+// for 0x98 index and 0x9c data
+#define DRAM_CTRL_ADDI_DATA_OFFSET 0x98
+#define DCAO_DctOffset_SHIFT 0
+#define DCAO_DctOffset_MASK 0x3fffffff
+#define DCAO_DctAccessWrite (1<<30)
+#define DCAO_DctAccessDone (1<<31)
+
+#define DRAM_CTRL_ADDI_DATA_PORT 0x9c
+
+#define DRAM_OUTPUT_DRV_COMP_CTRL 0x00
+#define DODCC_CkeDrvStren_SHIFT 0
+#define DODCC_CkeDrvStren_MASK 3
+#define DODCC_CkeDrvStren_1_0X 0
+#define DODCC_CkeDrvStren_1_25X 1
+#define DODCC_CkeDrvStren_1_5X 2
+#define DODCC_CkeDrvStren_2_0X 3
+#define DODCC_CsOdtDrvStren_SHIFT 4
+#define DODCC_CsOdtDrvStren_MASK 3
+#define DODCC_CsOdtDrvStren_1_0X 0
+#define DODCC_CsOdtDrvStren_1_25X 1
+#define DODCC_CsOdtDrvStren_1_5X 2
+#define DODCC_CsOdtDrvStren_2_0X 3
+#define DODCC_AddrCmdDrvStren_SHIFT 8
+#define DODCC_AddrCmdDrvStren_MASK 3
+#define DODCC_AddrCmdDrvStren_1_0X 0
+#define DODCC_AddrCmdDrvStren_1_25X 1
+#define DODCC_AddrCmdDrvStren_1_5X 2
+#define DODCC_AddrCmdDrvStren_2_0X 3
+#define DODCC_ClkDrvStren_SHIFT 12
+#define DODCC_ClkDrvStren_MASK 3
+#define DODCC_ClkDrvStren_0_75X 0
+#define DODCC_ClkDrvStren_1_0X 1
+#define DODCC_ClkDrvStren_1_25X 2
+#define DODCC_ClkDrvStren_1_5X 3
+#define DODCC_DataDrvStren_SHIFT 16
+#define DODCC_DataDrvStren_MASK 3
+#define DODCC_DataDrvStren_0_75X 0
+#define DODCC_DataDrvStren_1_0X 1
+#define DODCC_DataDrvStren_1_25X 2
+#define DODCC_DataDrvStren_1_5X 3
+#define DODCC_DqsDrvStren_SHIFT 20
+#define DODCC_DqsDrvStren_MASK 3
+#define DODCC_DqsDrvStren_0_75X 0
+#define DODCC_DqsDrvStren_1_0X 1
+#define DODCC_DqsDrvStren_1_25X 2
+#define DODCC_DqsDrvStren_1_5X 3
+#define DODCC_ProcOdt_SHIFT 28
+#define DODCC_ProcOdt_MASK 3
+#define DODCC_ProcOdt_300_OHMS 0
+#define DODCC_ProcOdt_150_OHMS 1
+#define DODCC_ProcOdt_75_OHMS 2
+
+#define DRAM_WRITE_DATA_TIMING_CTRL_LOW 0x01
+#define DWDTCL_WrDatTimeByte0_SHIFT 0
+#define DWDTC_WrDatTimeByte_MASK 0x3f
+#define DWDTC_WrDatTimeByte_BASE 0
+#define DWDTC_WrDatTimeByte_MIN 0
+#define DWDTC_WrDatTimeByte_MAX 47
+#define DWDTCL_WrDatTimeByte1_SHIFT 8
+#define DWDTCL_WrDatTimeByte2_SHIFT 16
+#define DWDTCL_WrDatTimeByte3_SHIFT 24
+
+#define DRAM_WRITE_DATA_TIMING_CTRL_HIGH 0x02
+#define DWDTCH_WrDatTimeByte4_SHIFT 0
+#define DWDTCH_WrDatTimeByte5_SHIFT 8
+#define DWDTCH_WrDatTimeByte6_SHIFT 16
+#define DWDTCH_WrDatTimeByte7_SHIFT 24
+
+#define DRAM_WRITE_DATA_ECC_TIMING_CTRL 0x03
+#define DWDETC_WrChkTime_SHIFT 0
+#define DWDETC_WrChkTime_MASK 0x3f
+#define DWDETC_WrChkTime_BASE 0
+#define DWDETC_WrChkTime_MIN 0
+#define DWDETC_WrChkTime_MAX 47
+
+#define DRAM_ADDR_TIMING_CTRL 0x04
+#define DATC_CkeFineDelay_SHIFT 0
+#define DATC_CkeFineDelay_MASK 0x1f
+#define DATC_CkeFineDelay_BASE 0
+#define DATC_CkeFineDelay_MIN 0
+#define DATC_CkeFineDelay_MAX 31
+#define DATC_CkeSetup (1<<5)
+#define DATC_CsOdtFineDelay_SHIFT 8
+#define DATC_CsOdtFineDelay_MASK 0x1f
+#define DATC_CsOdtFineDelay_BASE 0
+#define DATC_CsOdtFineDelay_MIN 0
+#define DATC_CsOdtFineDelay_MAX 31
+#define DATC_CsOdtSetup (1<<13)
+#define DATC_AddrCmdFineDelay_SHIFT 16
+#define DATC_AddrCmdFineDelay_MASK 0x1f
+#define DATC_AddrCmdFineDelay_BASE 0
+#define DATC_AddrCmdFineDelay_MIN 0
+#define DATC_AddrCmdFineDelay_MAX 31
+#define DATC_AddrCmdSetup (1<<21)
+
+#define DRAM_READ_DQS_TIMING_CTRL_LOW 0x05
+#define DRDTCL_RdDqsTimeByte0_SHIFT 0
+#define DRDTC_RdDqsTimeByte_MASK 0x3f
+#define DRDTC_RdDqsTimeByte_BASE 0
+#define DRDTC_RdDqsTimeByte_MIN 0
+#define DRDTC_RdDqsTimeByte_MAX 47
+#define DRDTCL_RdDqsTimeByte1_SHIFT 8
+#define DRDTCL_RdDqsTimeByte2_SHIFT 16
+#define DRDTCL_RdDqsTimeByte3_SHIFT 24
+
+#define DRAM_READ_DQS_TIMING_CTRL_HIGH 0x06
+#define DRDTCH_RdDqsTimeByte4_SHIFT 0
+#define DRDTCH_RdDqsTimeByte5_SHIFT 8
+#define DRDTCH_RdDqsTimeByte6_SHIFT 16
+#define DRDTCH_RdDqsTimeByte7_SHIFT 24
+
+#define DRAM_READ_DQS_ECC_TIMING_CTRL 0x07
+#define DRDETC_RdDqsTimeCheck_SHIFT 0
+#define DRDETC_RdDqsTimeCheck_MASK 0x3f
+#define DRDETC_RdDqsTimeCheck_BASE 0
+#define DRDETC_RdDqsTimeCheck_MIN 0
+#define DRDETC_RdDqsTimeCheck_MAX 47
+
+#define DRAM_DQS_RECV_ENABLE_TIME0 0x10
+#define DDRET_DqsRcvEnDelay_SHIFT 0
+#define DDRET_DqsRcvEnDelay_MASK 0xff
+#define DDRET_DqsRcvEnDelay_BASE 0
+#define DDRET_DqsRcvEnDelay_MIN 0
+#define DDRET_DqsRcvEnDelay_MAX 0xae /* unit is 50ps */
+
+#define DRAM_DQS_RECV_ENABLE_TIME1 0x13
+#define DRAM_DQS_RECV_ENABLE_TIME2 0x16
+#define DRAM_DQS_RECV_ENABLE_TIME3 0x19
+
+/* there are index 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x30, 0x33, 0x36, 0x39
+that are corresponding to 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x10, 0x13, 0x16, 0x19
+*/
+#define DRAM_CTRL_MISC 0xa0
+#define DCM_MemClrStatus (1<<0)
+#define DCM_DisableJitter (1<<1)
+#define DCM_RdWrQByp_SHIFT 2
+#define DCM_RdWrQByp_MASK 3
+#define DCM_RdWrQByp_2 0
+#define DCM_RdWrQByp_4 1
+#define DCM_RdWrQByp_8 2
+#define DCM_RdWrQByp_16 3
+#define DCM_Mode64BitMux (1<<4)
+#define DCM_DCC_EN (1<<5)
+#define DCM_ILD_lmt_SHIFT 6
+#define DCM_ILD_lmt_MASK 7
+#define DCM_ILD_lmt_0 0
+#define DCM_ILD_lmt_4 1
+#define DCM_ILD_lmt_8 2
+#define DCM_ILD_lmt_16 3
+#define DCM_ILD_lmt_32 4
+#define DCM_ILD_lmt_64 5
+#define DCM_ILD_lmt_128 6
+#define DCM_ILD_lmt_256 7
+#define DCM_DramEnabled (1<<9)
+#define DCM_MemClkDis_SHIFT 24 /* Channel B */
+#define DCM_MemClkDis3 (1 << 26)
+#define DCM_MemClkDis2 (1 << 27)
+#define DCM_MemClkDis1 (1 << 28)
+#define DCM_MemClkDis0 (1 << 29)
+
+
+/* Function 3 */
+#define MCA_NB_CONFIG 0x44
+#define MNC_ECC_EN (1 << 22)
+#define MNC_CHIPKILL_EN (1 << 23)
+
+#define SCRUB_CONTROL 0x58
+#define SCRUB_NONE 0
+#define SCRUB_40ns 1
+#define SCRUB_80ns 2
+#define SCRUB_160ns 3
+#define SCRUB_320ns 4
+#define SCRUB_640ns 5
+#define SCRUB_1_28us 6
+#define SCRUB_2_56us 7
+#define SCRUB_5_12us 8
+#define SCRUB_10_2us 9
+#define SCRUB_20_5us 10
+#define SCRUB_41_0us 11
+#define SCRUB_81_9us 12
+#define SCRUB_163_8us 13
+#define SCRUB_327_7us 14
+#define SCRUB_655_4us 15
+#define SCRUB_1_31ms 16
+#define SCRUB_2_62ms 17
+#define SCRUB_5_24ms 18
+#define SCRUB_10_49ms 19
+#define SCRUB_20_97ms 20
+#define SCRUB_42ms 21
+#define SCRUB_84ms 22
+#define SC_DRAM_SCRUB_RATE_SHFIT 0
+#define SC_DRAM_SCRUB_RATE_MASK 0x1f
+#define SC_L2_SCRUB_RATE_SHIFT 8
+#define SC_L2_SCRUB_RATE_MASK 0x1f
+#define SC_L1D_SCRUB_RATE_SHIFT 16
+#define SC_L1D_SCRUB_RATE_MASK 0x1f
+
+#define SCRUB_ADDR_LOW 0x5C
+
+#define SCRUB_ADDR_HIGH 0x60
+
+#define NORTHBRIDGE_CAP 0xE8
+#define NBCAP_128Bit (1 << 0)
+#define NBCAP_MP (1 << 1)
+#define NBCAP_BIG_MP (1 << 2)
+#define NBCAP_ECC (1 << 3)
+#define NBCAP_CHIPKILL_ECC (1 << 4)
+#define NBCAP_MEMCLK_SHIFT 5
+#define NBCAP_MEMCLK_MASK 3
+#define NBCAP_MEMCLK_200MHZ 3
+#define NBCAP_MEMCLK_266MHZ 2
+#define NBCAP_MEMCLK_333MHZ 1
+#define NBCAP_MEMCLK_NOLIMIT 0
+#define NBCAP_MEMCTRL (1 << 8)
+#define NBCAP_HtcCap (1<<10)
+#define NBCAP_CmpCap_SHIFT 12
+#define NBCAP_CmpCap_MASK 3
+
+
+#define LinkConnected (1 << 0)
+#define InitComplete (1 << 1)
+#define NonCoherent (1 << 2)
+#define ConnectionPending (1 << 4)
+
+#include "raminit.h"
+//struct definitions
+
+struct dimm_size {
+ uint8_t per_rank; // it is rows + col + bank_lines + data lines */
+ uint8_t rows;
+ uint8_t col;
+ uint8_t bank; //1, 2, 3 mean 2, 4, 8
+ uint8_t rank;
+} __attribute__((packed));
+
+struct mem_info { // pernode
+ uint32_t dimm_mask;
+ struct dimm_size sz[DIMM_SOCKETS];
+ uint32_t x4_mask;
+ uint32_t x16_mask;
+ uint32_t single_rank_mask;
+ uint32_t page_1k_mask;
+// uint32_t ecc_mask;
+// uint32_t registered_mask;
+ uint8_t is_opteron;
+ uint8_t is_registered;
+ uint8_t is_ecc;
+ uint8_t is_Width128;
+ uint8_t is_64MuxMode;
+ uint8_t memclk_set; // we need to use this to retrieve the mem param
+ uint8_t rsv[2];
+} __attribute__((packed));
+
+struct link_pair_st {
+ device_t udev;
+ uint32_t upos;
+ uint32_t uoffs;
+ device_t dev;
+ uint32_t pos;
+ uint32_t offs;
+
+} __attribute__((packed));
+
+struct sys_info {
+ uint8_t ctrl_present[NODE_NUMS];
+ struct mem_info meminfo[NODE_NUMS];
+ struct mem_controller ctrl[NODE_NUMS];
+ uint8_t mem_trained[NODE_NUMS]; //0: no dimm, 1: trained, 0x80: not started, 0x81: recv1 fail, 0x82: Pos Fail, 0x83:recv2 fail
+ uint32_t tom_k;
+ uint32_t tom2_k;
+
+ uint32_t mem_base[NODE_NUMS];
+ uint32_t cs_base[NODE_NUMS*8]; //8 cs_idx
+ uint32_t hole_reg[NODE_NUMS]; // can we spare it to one, and put ctrl idx in it
+
+ uint8_t dqs_delay_a[NODE_NUMS*2*2*9]; //8 node channel 2, direction 2 , bytelane *9
+ uint8_t dqs_rcvr_dly_a[NODE_NUMS*2*8]; //8 node, channel 2, receiver 8
+ uint32_t nodes;
+ struct link_pair_st link_pair[16];// enough? only in_conherent
+ uint32_t link_pair_num;
+ uint32_t ht_c_num;
+ uint32_t sbdn;
+ uint32_t sblk;
+ uint32_t sbbusn;
+} __attribute__((packed));
+
+#include <reset.h>
+
+#if ((CONFIG_MEM_TRAIN_SEQ != 1) && defined(__PRE_RAM__)) || \
+ ((CONFIG_MEM_TRAIN_SEQ == 1) && !defined(__PRE_RAM__))
+static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo)
+{
+
+ int i;
+ uint32_t mask = 0;
+ unsigned needs_reset = 0;
+
+
+ if(sysinfo->nodes == 1) return; // in case only one cpu installed
+
+ for(i=1; i<sysinfo->nodes; i++) {
+ /* Skip everything if I don't have any memory on this controller */
+ if(sysinfo->mem_trained[i]==0x00) continue;
+
+ mask |= (1<<i);
+
+ }
+
+ i = 1;
+ while(1) {
+ if(mask & (1<<i)) {
+ if((sysinfo->mem_trained[i])!=0x80) {
+ mask &= ~(1<<i);
+ }
+ }
+
+ if(!mask) break;
+
+#if 0
+ /* cpu_relax */
+ __asm__ __volatile__("rep;nop": : :"memory");
+#endif
+
+ i++;
+ i%=sysinfo->nodes;
+ }
+
+ for(i=0; i<sysinfo->nodes; i++) {
+#ifdef __PRE_RAM__
+ print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\n");
+#else
+ printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
+#endif
+ switch(sysinfo->mem_trained[i]) {
+ case 0: //don't need train
+ case 1: //trained
+ break;
+ case 0x81: //recv1: fail
+ case 0x82: //Pos :fail
+ case 0x83: //recv2: fail
+ needs_reset = 1;
+ break;
+ }
+ }
+ if(needs_reset) {
+#ifdef __PRE_RAM__
+ print_debug("mem trained failed\n");
+ soft_reset();
+#else
+ printk(BIOS_DEBUG, "mem trained failed\n");
+ hard_reset();
+#endif
+ }
+
+}
+#endif
+
+#endif /* AMDK8_F_H */
--- /dev/null
+#ifndef AMDK8_F_PCI_C
+#define AMDK8_F_PCI_C
+
+#ifdef UNUSED_CODE
+/* bit [10,8] are dev func, bit[1,0] are dev index */
+static uint32_t pci_read_config32_index(device_t dev, uint32_t index_reg, uint32_t index)
+{
+ uint32_t dword;
+
+ pci_write_config32(dev, index_reg, index);
+
+ dword = pci_read_config32(dev, index_reg+0x4);
+
+ return dword;
+}
+
+static void pci_write_config32_index(device_t dev, uint32_t index_reg, uint32_t index, uint32_t data)
+{
+ pci_write_config32(dev, index_reg, index);
+
+ pci_write_config32(dev, index_reg + 0x4, data);
+}
+#endif
+
+static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index)
+{
+ uint32_t dword;
+
+ index &= ~(1<<30);
+ pci_write_config32(dev, index_reg, index);
+
+ do {
+ dword = pci_read_config32(dev, index_reg);
+ } while (!(dword & (1<<31)));
+
+ dword = pci_read_config32(dev, index_reg+0x4);
+
+ return dword;
+}
+
+static void pci_write_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index, uint32_t data)
+{
+ uint32_t dword;
+
+ pci_write_config32(dev, index_reg + 0x4, data);
+
+ index |= (1<<30);
+ pci_write_config32(dev, index_reg, index);
+ do {
+ dword = pci_read_config32(dev, index_reg);
+ } while (!(dword & (1<<31)));
+}
+
+#endif
--- /dev/null
+#ifndef AMDK8_PRE_F_H
+#define AMDK8_PRE_F_H
+
+/* Definitions of various K8 registers */
+/* Function 0 */
+#define HT_TRANSACTION_CONTROL 0x68
+#define HTTC_DIS_RD_B_P (1 << 0)
+#define HTTC_DIS_RD_DW_P (1 << 1)
+#define HTTC_DIS_WR_B_P (1 << 2)
+#define HTTC_DIS_WR_DW_P (1 << 3)
+#define HTTC_DIS_MTS (1 << 4)
+#define HTTC_CPU1_EN (1 << 5)
+#define HTTC_CPU_REQ_PASS_PW (1 << 6)
+#define HTTC_CPU_RD_RSP_PASS_PW (1 << 7)
+#define HTTC_DIS_P_MEM_C (1 << 8)
+#define HTTC_DIS_RMT_MEM_C (1 << 9)
+#define HTTC_DIS_FILL_P (1 << 10)
+#define HTTC_RSP_PASS_PW (1 << 11)
+#define HTTC_CHG_ISOC_TO_ORD (1 << 12)
+#define HTTC_BUF_REL_PRI_SHIFT 13
+#define HTTC_BUF_REL_PRI_MASK 3
+#define HTTC_BUF_REL_PRI_64 0
+#define HTTC_BUF_REL_PRI_16 1
+#define HTTC_BUF_REL_PRI_8 2
+#define HTTC_BUF_REL_PRI_2 3
+#define HTTC_LIMIT_CLDT_CFG (1 << 15)
+#define HTTC_LINT_EN (1 << 16)
+#define HTTC_APIC_EXT_BRD_CST (1 << 17)
+#define HTTC_APIC_EXT_ID (1 << 18)
+#define HTTC_APIC_EXT_SPUR (1 << 19)
+#define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20)
+#define HTTC_DS_NP_REQ_LIMIT_SHIFT 21
+#define HTTC_DS_NP_REQ_LIMIT_MASK 3
+#define HTTC_DS_NP_REQ_LIMIT_NONE 0
+#define HTTC_DS_NP_REQ_LIMIT_1 1
+#define HTTC_DS_NP_REQ_LIMIT_4 2
+#define HTTC_DS_NP_REQ_LIMIT_8 3
+#define HTTC_MED_PRI_BYP_CNT_SHIFT 24
+#define HTTC_MED_PRI_BYP_CNT_MASK 3
+#define HTTC_HI_PRI_BYP_CNT_SHIFT 26
+#define HTTC_HI_PRI_BYP_CNT_MASK 3
+
+
+/* Function 1 */
+#define PCI_IO_BASE0 0xc0
+#define PCI_IO_BASE1 0xc8
+#define PCI_IO_BASE2 0xd0
+#define PCI_IO_BASE3 0xd8
+#define PCI_IO_BASE_VGA_EN (1 << 4)
+#define PCI_IO_BASE_NO_ISA (1 << 5)
+
+
+/* Function 2 */
+#define DRAM_CSBASE 0x40
+#define DRAM_CSMASK 0x60
+#define DRAM_BANK_ADDR_MAP 0x80
+
+#define DRAM_TIMING_LOW 0x88
+#define DTL_TCL_SHIFT 0
+#define DTL_TCL_MASK 0x7
+#define DTL_CL_2 1
+#define DTL_CL_3 2
+#define DTL_CL_2_5 5
+#define DTL_TRC_SHIFT 4
+#define DTL_TRC_MASK 0xf
+#define DTL_TRC_BASE 7
+#define DTL_TRC_MIN 7
+#define DTL_TRC_MAX 22
+#define DTL_TRFC_SHIFT 8
+#define DTL_TRFC_MASK 0xf
+#define DTL_TRFC_BASE 9
+#define DTL_TRFC_MIN 9
+#define DTL_TRFC_MAX 24
+#define DTL_TRCD_SHIFT 12
+#define DTL_TRCD_MASK 0x7
+#define DTL_TRCD_BASE 0
+#define DTL_TRCD_MIN 2
+#define DTL_TRCD_MAX 6
+#define DTL_TRRD_SHIFT 16
+#define DTL_TRRD_MASK 0x7
+#define DTL_TRRD_BASE 0
+#define DTL_TRRD_MIN 2
+#define DTL_TRRD_MAX 4
+#define DTL_TRAS_SHIFT 20
+#define DTL_TRAS_MASK 0xf
+#define DTL_TRAS_BASE 0
+#define DTL_TRAS_MIN 5
+#define DTL_TRAS_MAX 15
+#define DTL_TRP_SHIFT 24
+#define DTL_TRP_MASK 0x7
+#define DTL_TRP_BASE 0
+#define DTL_TRP_MIN 2
+#define DTL_TRP_MAX 6
+#define DTL_TWR_SHIFT 28
+#define DTL_TWR_MASK 0x1
+#define DTL_TWR_BASE 2
+#define DTL_TWR_MIN 2
+#define DTL_TWR_MAX 3
+
+#define DRAM_TIMING_HIGH 0x8c
+#define DTH_TWTR_SHIFT 0
+#define DTH_TWTR_MASK 0x1
+#define DTH_TWTR_BASE 1
+#define DTH_TWTR_MIN 1
+#define DTH_TWTR_MAX 2
+#define DTH_TRWT_SHIFT 4
+#define DTH_TRWT_MASK 0x7
+#define DTH_TRWT_BASE 1
+#define DTH_TRWT_MIN 1
+#define DTH_TRWT_MAX 6
+#define DTH_TREF_SHIFT 8
+#define DTH_TREF_MASK 0x1f
+#define DTH_TREF_100MHZ_4K 0x00
+#define DTH_TREF_133MHZ_4K 0x01
+#define DTH_TREF_166MHZ_4K 0x02
+#define DTH_TREF_200MHZ_4K 0x03
+#define DTH_TREF_100MHZ_8K 0x08
+#define DTH_TREF_133MHZ_8K 0x09
+#define DTH_TREF_166MHZ_8K 0x0A
+#define DTH_TREF_200MHZ_8K 0x0B
+#define DTH_TWCL_SHIFT 20
+#define DTH_TWCL_MASK 0x7
+#define DTH_TWCL_BASE 1
+#define DTH_TWCL_MIN 1
+#define DTH_TWCL_MAX 2
+
+#define DRAM_CONFIG_LOW 0x90
+#define DCL_DLL_Disable (1<<0)
+#define DCL_D_DRV (1<<1)
+#define DCL_QFC_EN (1<<2)
+#define DCL_DisDqsHys (1<<3)
+#define DCL_Burst2Opt (1<<5)
+#define DCL_DramInit (1<<8)
+#define DCL_DualDIMMen (1<<9)
+#define DCL_DramEnable (1<<10)
+#define DCL_MemClrStatus (1<<11)
+#define DCL_ESR (1<<12)
+#define DCL_SRS (1<<13)
+#define DCL_128BitEn (1<<16)
+#define DCL_DimmEccEn (1<<17)
+#define DCL_UnBuffDimm (1<<18)
+#define DCL_32ByteEn (1<<19)
+#define DCL_x4DIMM_SHIFT 20
+#define DCL_DisInRcvrs (1<<24)
+#define DCL_BypMax_SHIFT 25
+#define DCL_En2T (1<<28)
+#define DCL_UpperCSMap (1<<29)
+
+#define DRAM_CONFIG_HIGH 0x94
+#define DCH_ASYNC_LAT_SHIFT 0
+#define DCH_ASYNC_LAT_MASK 0xf
+#define DCH_ASYNC_LAT_BASE 0
+#define DCH_ASYNC_LAT_MIN 0
+#define DCH_ASYNC_LAT_MAX 15
+#define DCH_RDPREAMBLE_SHIFT 8
+#define DCH_RDPREAMBLE_MASK 0xf
+#define DCH_RDPREAMBLE_BASE ((2<<1)+0) /* 2.0 ns */
+#define DCH_RDPREAMBLE_MIN ((2<<1)+0) /* 2.0 ns */
+#define DCH_RDPREAMBLE_MAX ((9<<1)+1) /* 9.5 ns */
+#define DCH_IDLE_LIMIT_SHIFT 16
+#define DCH_IDLE_LIMIT_MASK 0x7
+#define DCH_IDLE_LIMIT_0 0
+#define DCH_IDLE_LIMIT_4 1
+#define DCH_IDLE_LIMIT_8 2
+#define DCH_IDLE_LIMIT_16 3
+#define DCH_IDLE_LIMIT_32 4
+#define DCH_IDLE_LIMIT_64 5
+#define DCH_IDLE_LIMIT_128 6
+#define DCH_IDLE_LIMIT_256 7
+#define DCH_DYN_IDLE_CTR_EN (1 << 19)
+#define DCH_MEMCLK_SHIFT 20
+#define DCH_MEMCLK_MASK 0x7
+#define DCH_MEMCLK_100MHZ 0
+#define DCH_MEMCLK_133MHZ 2
+#define DCH_MEMCLK_166MHZ 5
+#define DCH_MEMCLK_200MHZ 7
+#define DCH_MEMCLK_VALID (1 << 25)
+#define DCH_MEMCLK_EN0 (1 << 26)
+#define DCH_MEMCLK_EN1 (1 << 27)
+#define DCH_MEMCLK_EN2 (1 << 28)
+#define DCH_MEMCLK_EN3 (1 << 29)
+
+/* Function 3 */
+#define MCA_NB_CONFIG 0x44
+#define MNC_ECC_EN (1 << 22)
+#define MNC_CHIPKILL_EN (1 << 23)
+#define SCRUB_CONTROL 0x58
+#define SCRUB_NONE 0
+#define SCRUB_40ns 1
+#define SCRUB_80ns 2
+#define SCRUB_160ns 3
+#define SCRUB_320ns 4
+#define SCRUB_640ns 5
+#define SCRUB_1_28us 6
+#define SCRUB_2_56us 7
+#define SCRUB_5_12us 8
+#define SCRUB_10_2us 9
+#define SCRUB_20_5us 10
+#define SCRUB_41_0us 11
+#define SCRUB_81_9us 12
+#define SCRUB_163_8us 13
+#define SCRUB_327_7us 14
+#define SCRUB_655_4us 15
+#define SCRUB_1_31ms 16
+#define SCRUB_2_62ms 17
+#define SCRUB_5_24ms 18
+#define SCRUB_10_49ms 19
+#define SCRUB_20_97ms 20
+#define SCRUB_42ms 21
+#define SCRUB_84ms 22
+#define SC_DRAM_SCRUB_RATE_SHFIT 0
+#define SC_DRAM_SCRUB_RATE_MASK 0x1f
+#define SC_L2_SCRUB_RATE_SHIFT 8
+#define SC_L2_SCRUB_RATE_MASK 0x1f
+#define SC_L1D_SCRUB_RATE_SHIFT 16
+#define SC_L1D_SCRUB_RATE_MASK 0x1f
+#define SCRUB_ADDR_LOW 0x5C
+#define SCRUB_ADDR_HIGH 0x60
+#define NORTHBRIDGE_CAP 0xE8
+#define NBCAP_128Bit (1 << 0)
+#define NBCAP_MP (1 << 1)
+#define NBCAP_BIG_MP (1 << 2)
+#define NBCAP_ECC (1 << 3)
+#define NBCAP_CHIPKILL_ECC (1 << 4)
+#define NBCAP_MEMCLK_SHIFT 5
+#define NBCAP_MEMCLK_MASK 3
+#define NBCAP_MEMCLK_100MHZ 3
+#define NBCAP_MEMCLK_133MHZ 2
+#define NBCAP_MEMCLK_166MHZ 1
+#define NBCAP_MEMCLK_200MHZ 0
+#define NBCAP_MEMCTRL (1 << 8)
+
+
+#define LinkConnected (1 << 0)
+#define InitComplete (1 << 1)
+#define NonCoherent (1 << 2)
+#define ConnectionPending (1 << 4)
+
+#include "raminit.h"
+//struct definitions
+
+struct link_pair_st {
+ device_t udev;
+ uint32_t upos;
+ uint32_t uoffs;
+ device_t dev;
+ uint32_t pos;
+ uint32_t offs;
+
+} __attribute__((packed));
+
+struct sys_info {
+ uint8_t ctrl_present[NODE_NUMS];
+ struct mem_controller ctrl[NODE_NUMS];
+
+ uint32_t nodes;
+ struct link_pair_st link_pair[16];// enough? only in_conherent
+ uint32_t link_pair_num;
+ uint32_t ht_c_num;
+ uint32_t sbdn;
+ uint32_t sblk;
+ uint32_t sbbusn;
+} __attribute__((packed));
+
+#endif /* AMDK8_PRE_F_H */
#include <stdlib.h>
#include "raminit.h"
-#include "amdk8_f.h"
+#include "f.h"
#include <spd_ddr2.h>
#if CONFIG_HAVE_OPTION_TABLE
#include "option_table.h"
# error "CONFIG_RAMTOP must be a power of 2"
#endif
-#include "amdk8_f_pci.c"
+#include "f_pci.c"
/* for PCI_ADDR(0, 0x18, 2, 0x98) index,
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+
+//AMD k8 util for BUSB and res range
+
+Scope (\_SB)
+{
+
+ Name (OSTB, Ones)
+ Method (OSTP, 0, NotSerialized)
+ {
+ If (LEqual (^OSTB, Ones))
+ {
+ Store (0x00, ^OSTB)
+ }
+
+ Return (^OSTB)
+ }
+
+ Method (SEQL, 2, Serialized)
+ {
+ Store (SizeOf (Arg0), Local0)
+ Store (SizeOf (Arg1), Local1)
+ If (LNot (LEqual (Local0, Local1))) { Return (Zero) }
+
+ Name (BUF0, Buffer (Local0) {})
+ Store (Arg0, BUF0)
+ Name (BUF1, Buffer (Local0) {})
+ Store (Arg1, BUF1)
+ Store (Zero, Local2)
+ While (LLess (Local2, Local0))
+ {
+ Store (DerefOf (Index (BUF0, Local2)), Local3)
+ Store (DerefOf (Index (BUF1, Local2)), Local4)
+ If (LNot (LEqual (Local3, Local4))) { Return (Zero) }
+
+ Increment (Local2)
+ }
+
+ Return (One)
+ }
+
+
+ Method (DADD, 2, NotSerialized)
+ {
+ Store( Arg1, Local0)
+ Store( Arg0, Local1)
+ Add( ShiftLeft(Local1,16), Local0, Local0)
+ Return (Local0)
+ }
+
+
+ Method (GHCE, 1, NotSerialized) // check if the HC enabled
+ {
+ Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
+ if(LEqual ( And(Local1, 0x01), 0x01)) { Return (0x0F) }
+ Else { Return (0x00) }
+ }
+
+ Method (GHCN, 1, NotSerialized) // get the node num for the HC
+ {
+ Store (0x00, Local0)
+ Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
+ Store (ShiftRight( And (Local1, 0xf0), 0x04), Local0)
+ Return (Local0)
+ }
+
+ Method (GHCL, 1, NotSerialized) // get the link num on node for the HC
+ {
+ Store (0x00, Local0)
+ Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
+ Store (ShiftRight( And (Local1, 0xf00), 0x08), Local0)
+ Return (Local0)
+ }
+
+ Method (GHCD, 2, NotSerialized) // get the unit id base for the HT device in HC
+ {
+ Store (0x00, Local0)
+ Store (DerefOf (Index (\_SB.PCI0.HCDN, Arg0)), Local1)
+ Store (Arg1, Local2) // Arg1 could be 3, 2, 1, 0
+ Multiply (Local2, 0x08, Local2) // change to 24, 16, 8, 0
+ Store (And (ShiftRight( Local1, Local2), 0xff), Local0)
+ Return (Local0)
+ }
+
+ /* GetBus(Node, Link) */
+ Method (GBUS, 2, NotSerialized)
+ {
+ Store (0x00, Local0)
+ While (LLess (Local0, 0x04))
+ {
+ Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1)
+ If (LEqual (And (Local1, 0x03), 0x03))
+ {
+ If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04)))
+ {
+ If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08))))
+ {
+ Return (ShiftRight (And (Local1, 0x00FF0000), 0x10))
+ }
+ }
+ }
+
+ Increment (Local0)
+ }
+
+ Return (0x00)
+ }
+
+ /* GetBusResources(Node, Link) */
+ Method (GWBN, 2, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Address Space Granularity
+ 0x0000, // Address Range Minimum
+ 0x0000, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x0001,,,)
+ })
+ CreateWordField (BUF0, 0x08, BMIN)
+ CreateWordField (BUF0, 0x0A, BMAX)
+ CreateWordField (BUF0, 0x0E, BLEN)
+ Store (0x00, Local0)
+ While (LLess (Local0, 0x04))
+ {
+ Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1)
+ If (LEqual (And (Local1, 0x03), 0x03))
+ {
+ If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04)))
+ {
+ If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08))))
+ {
+ Store (ShiftRight (And (Local1, 0x00FF0000), 0x10), BMIN)
+ Store (ShiftRight (Local1, 0x18), BMAX)
+ Subtract (BMAX, BMIN, BLEN)
+ Increment (BLEN)
+ Return (RTAG (BUF0))
+ }
+ }
+ }
+
+ Increment (Local0)
+ }
+
+ Return (RTAG (BUF0))
+ }
+
+ /* GetMemoryResources(Node, Link) */
+ Method (GMEM, 2, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Address Space Granularity
+ 0x00000000, // Address Range Minimum
+ 0x00000000, // Address Range Maximum
+ 0x00000000, // Address Translation Offset
+ 0x00000001,,,
+ , AddressRangeMemory, TypeStatic)
+ })
+ CreateDWordField (BUF0, 0x0A, MMIN)
+ CreateDWordField (BUF0, 0x0E, MMAX)
+ CreateDWordField (BUF0, 0x16, MLEN)
+ Store (0x00, Local0)
+ Store (0x00, Local4)
+ Store (0x00, Local3)
+ While (LLess (Local0, 0x10))
+ {
+ /* Get value of the first register */
+ Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local1)
+ Increment (Local0)
+ Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local2)
+ If (LEqual (And (Local1, 0x03), 0x03)) /* Pair enabled? */
+ {
+ If (LEqual (Arg0, And (Local2, 0x07))) /* Node matches? */
+ {
+ /* If Link Matches (or we got passed 0xFF) */
+ If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04))))
+ {
+ /* Extract the Base and Limit values */
+ Store (ShiftLeft (And (Local1, 0xFFFFFF00), 0x08), MMIN)
+ Store (ShiftLeft (And (Local2, 0xFFFFFF00), 0x08), MMAX)
+ Or (MMAX, 0xFFFF, MMAX)
+ Subtract (MMAX, MMIN, MLEN)
+ Increment (MLEN)
+
+ If (Local4) /* I've already done this once */
+ {
+ Concatenate (RTAG (BUF0), Local3, Local5)
+ Store (Local5, Local3)
+ }
+ Else
+ {
+ Store (RTAG (BUF0), Local3)
+ }
+
+ Increment (Local4)
+ }
+ }
+ }
+
+ Increment (Local0)
+ }
+
+ If (LNot (Local4)) /* No resources for this node and link. */
+ {
+ Store (RTAG (BUF0), Local3)
+ }
+
+ Return (Local3)
+ }
+
+ /* GetIOResources(Node, Link) */
+ Method (GIOR, 2, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x00000000, // Address Space Granularity
+ 0x00000000, // Address Range Minimum
+ 0x00000000, // Address Range Maximum
+ 0x00000000, // Address Translation Offset
+ 0x00000001,,,
+ , TypeStatic)
+ })
+ CreateDWordField (BUF0, 0x0A, PMIN)
+ CreateDWordField (BUF0, 0x0E, PMAX)
+ CreateDWordField (BUF0, 0x16, PLEN)
+ Store (0x00, Local0)
+ Store (0x00, Local4)
+ Store (0x00, Local3)
+ While (LLess (Local0, 0x08))
+ {
+ Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local1)
+ Increment (Local0)
+ Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local2)
+ If (LEqual (And (Local1, 0x03), 0x03)) /* Pair enabled? */
+ {
+ If (LEqual (Arg0, And (Local2, 0x07))) /* Node matches? */
+ {
+ /* If Link Matches (or we got passed 0xFF) */
+ If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04))))
+ {
+ /* Extract the Base and Limit values */
+ Store (And (Local1, 0x01FFF000), PMIN)
+ Store (And (Local2, 0x01FFF000), PMAX)
+ Or (PMAX, 0x0FFF, PMAX)
+ Subtract (PMAX, PMIN, PLEN)
+ Increment (PLEN)
+
+ If (Local4) /* I've already done this once */
+ {
+ Concatenate (RTAG (BUF0), Local3, Local5)
+ Store (Local5, Local3)
+ }
+ Else
+ {
+ If (LGreater (PMAX, PMIN))
+ {
+ If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK)))
+ {
+ Store (0x0D00, PMIN)
+ Subtract (PMAX, PMIN, PLEN)
+ Increment (PLEN)
+ }
+
+ Store (RTAG (BUF0), Local3)
+ Increment (Local4)
+ }
+
+ If (And (Local1, 0x10))
+ {
+ Store (0x03B0, PMIN)
+ Store (0x03DF, PMAX)
+ Store (0x30, PLEN)
+
+ If (Local4)
+ {
+ Concatenate (RTAG (BUF0), Local3, Local5)
+ Store (Local5, Local3)
+ }
+ Else
+ {
+ Store (RTAG (BUF0), Local3)
+ }
+ }
+ }
+
+ Increment (Local4)
+ }
+ }
+ }
+
+ Increment (Local0)
+ }
+
+ If (LNot (Local4)) /* No resources for this node and link. */
+ {
+ Store (RTAG (BUF0), Local3)
+ }
+
+ Return (Local3)
+ }
+
+ Method (RTAG, 1, NotSerialized)
+ {
+ Store (Arg0, Local0)
+ Store (SizeOf (Local0), Local1)
+ Subtract (Local1, 0x02, Local1)
+ Multiply (Local1, 0x08, Local1)
+ CreateField (Local0, 0x00, Local1, RETB)
+ Store (RETB, Local2)
+ Return (Local2)
+ }
+}
driver-y += northbridge.c
driver-y += vga.c
-smm-$(CONFIG_HAVE_SMI_HANDLER) += i82830_smihandler.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <types.h>
-#include <string.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <console/console.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/smm.h>
-#include <device/pci_def.h>
-#include "i82830.h"
-
-extern unsigned char *mbi;
-extern u32 mbi_len;
-
-// #define DEBUG_SMI_I82830
-
-/* If YABEL is enabled and it's not running at 0x00000000, we have to add some
- * offset to all our mbi object memory accesses
- */
-#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL && !CONFIG_YABEL_DIRECTHW
-#define OBJ_OFFSET CONFIG_YABEL_VIRTMEM_LOCATION
-#else
-#define OBJ_OFFSET 0x00000
-#endif
-
-/* I830M */
-#define SMRAM 0x90
-#define D_OPEN (1 << 6)
-#define D_CLS (1 << 5)
-#define D_LCK (1 << 4)
-#define G_SMRANE (1 << 3)
-#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
-
-
-typedef struct {
- u32 mhid;
- u32 function;
- u32 retsts;
- u32 rfu;
-} __attribute__((packed)) banner_id_t;
-
-#define MSH_OK 0x0000
-#define MSH_OK_RESTART 0x0001
-#define MSH_FWH_ERR 0x00ff
-#define MSH_IF_BAD_ID 0x0100
-#define MSH_IF_BAD_FUNC 0x0101
-#define MSH_IF_MBI_CORRUPT 0x0102
-#define MSH_IF_BAD_HANDLE 0x0103
-#define MSH_ALRDY_ATCHED 0x0104
-#define MSH_NOT_ATCHED 0x0105
-#define MSH_IF 0x0106
-#define MSH_IF_INVADDR 0x0107
-#define MSH_IF_UKN_TYPE 0x0108
-#define MSH_IF_NOT_FOUND 0x0109
-#define MSH_IF_NO_KEY 0x010a
-#define MSH_IF_BUF_SIZE 0x010b
-#define MSH_IF_NOT_PENDING 0x010c
-
-#ifdef DEBUG_SMI_I82830
-static void
-dump(u8 * addr, u32 len)
-{
- printk(BIOS_DEBUG, "\n%s(%p, %x):\n", __func__, addr, len);
- while (len) {
- unsigned int tmpCnt = len;
- unsigned char x;
- if (tmpCnt > 8)
- tmpCnt = 8;
- printk(BIOS_DEBUG, "\n%p: ", addr);
- // print hex
- while (tmpCnt--) {
- x = *addr++;
- printk(BIOS_DEBUG, "%02x ", x);
- }
- tmpCnt = len;
- if (tmpCnt > 8)
- tmpCnt = 8;
- len -= tmpCnt;
- //reset addr ptr to print ascii
- addr = addr - tmpCnt;
- // print ascii
- while (tmpCnt--) {
- x = *addr++;
- if ((x < 32) || (x >= 127)) {
- //non-printable char
- x = '.';
- }
- printk(BIOS_DEBUG, "%c", x);
- }
- }
- printk(BIOS_DEBUG, "\n");
-}
-#endif
-
-typedef struct {
- banner_id_t banner;
- u16 versionmajor;
- u16 versionminor;
- u32 smicombuffersize;
-} __attribute__((packed)) version_t;
-
-typedef struct {
- u16 header_id;
- u16 attributes;
- u16 size;
- u8 name_len;
- u8 reserved;
- u32 type;
- u32 header_ext;
- u8 name[0];
-} __attribute__((packed)) mbi_header_t;
-
-typedef struct {
- banner_id_t banner;
- u64 handle;
- u32 objnum;
- mbi_header_t header;
-} __attribute__((packed)) obj_header_t;
-
-typedef struct {
- banner_id_t banner;
- u64 handle;
- u32 objnum;
- u32 start;
- u32 numbytes;
- u32 buflen;
- u32 buffer;
-} __attribute__((packed)) get_object_t;
-
-static void mbi_call(u8 subf, banner_id_t *banner_id)
-{
-#ifdef DEBUG_SMI_I82830
- printk(BIOS_DEBUG, "MBI\n");
- printk(BIOS_DEBUG, "|- sub function %x\n", subf);
- printk(BIOS_DEBUG, "|- banner id @ %x\n", (u32)banner_id);
- printk(BIOS_DEBUG, "| |- mhid %x\n", banner_id->mhid);
- printk(BIOS_DEBUG, "| |- function %x\n", banner_id->function);
- printk(BIOS_DEBUG, "| |- return status %x\n", banner_id->retsts);
- printk(BIOS_DEBUG, "| |- rfu %x\n", banner_id->rfu);
-#endif
-
- switch(banner_id->function) {
- case 0x0001: {
- version_t *version;
- printk(BIOS_DEBUG, "|- MBI_QueryInterface\n");
- version = (version_t *)banner_id;
- version->banner.retsts = MSH_OK;
- version->versionmajor=1;
- version->versionminor=3;
- version->smicombuffersize=0x1000;
- break;
- }
- case 0x0002:
- printk(BIOS_DEBUG, "|- MBI_Attach\n");
- printk(BIOS_DEBUG, "|Â |- Not Implemented!\n");
- break;
- case 0x0003:
- printk(BIOS_DEBUG, "|- MBI_Detach\n");
- printk(BIOS_DEBUG, "|Â |- Not Implemented!\n");
- break;
- case 0x0201: {
- obj_header_t *obj_header = (obj_header_t *)banner_id;
- mbi_header_t *mbi_header = NULL;
- printk(BIOS_DEBUG, "|- MBI_GetObjectHeader\n");
- printk(BIOS_DEBUG, "| |- objnum = %d\n", obj_header->objnum);
-
- int i, count=0;
- obj_header->banner.retsts = MSH_IF_NOT_FOUND;
-
- for (i=0; i<mbi_len;) {
- int len;
-
- if (!(mbi[i] == 0xf0 && mbi [i+1] == 0xf6)) {
- i+=16;
- continue;
- }
-
- mbi_header = (mbi_header_t *)&mbi[i];
- len = ALIGN((mbi_header->size * 16) + sizeof(mbi_header) + ALIGN(mbi_header->name_len, 16), 16);
-
- if (obj_header->objnum == count) {
-#ifdef DEBUG_SMI_I82830
- if (mbi_header->name_len == 0xff) {
- printk(BIOS_DEBUG, "| |- corrupt.\n");
- break;
- }
-#endif
- int headerlen = ALIGN(sizeof(mbi_header) + ALIGN(mbi_header->name_len, 16), 16);
-#ifdef DEBUG_SMI_I82830
- printk(BIOS_DEBUG, "| |- headerlen = %d\n", headerlen);
-#endif
- memcpy(&obj_header->header, mbi_header, headerlen);
- obj_header->banner.retsts = MSH_OK;
- printk(BIOS_DEBUG, "| |- MBI module '");
- int j;
- for (j=0; j < mbi_header->name_len && mbi_header->name[j]; j++)
- printk(BIOS_DEBUG, "%c", mbi_header->name[j]);
- printk(BIOS_DEBUG, "' found.\n");
-#ifdef DEBUG_SMI_I82830
- dump((u8 *)banner_id, sizeof(obj_header_t) + ALIGN(mbi_header->name_len, 16));
-#endif
- break;
- }
- i += len;
- count++;
- }
- if (obj_header->banner.retsts == MSH_IF_NOT_FOUND)
- printk(BIOS_DEBUG, "| |- MBI object #%d not found.\n", obj_header->objnum);
- break;
- }
- case 0x0203: {
- get_object_t *getobj = (get_object_t *)banner_id;
- mbi_header_t *mbi_header = NULL;
- printk(BIOS_DEBUG, "|- MBI_GetObject\n");
-#ifdef DEBUG_SMI_I82830
- printk(BIOS_DEBUG, "| |- handle = %016Lx\n", getobj->handle);
-#endif
- printk(BIOS_DEBUG, "| |- objnum = %d\n", getobj->objnum);
- printk(BIOS_DEBUG, "| |- start = %x\n", getobj->start);
- printk(BIOS_DEBUG, "| |- numbytes = %x\n", getobj->numbytes);
- printk(BIOS_DEBUG, "| |- buflen = %x\n", getobj->buflen);
- printk(BIOS_DEBUG, "| |- buffer = %x\n", getobj->buffer);
-
- int i, count=0;
- getobj->banner.retsts = MSH_IF_NOT_FOUND;
-
- for (i=0; i< mbi_len;) {
- int headerlen, objectlen;
-
- if (!(mbi[i] == 0xf0 && mbi [i+1] == 0xf6)) {
- i+=16;
- continue;
- }
-
- mbi_header = (mbi_header_t *)&mbi[i];
- headerlen = ALIGN(sizeof(mbi_header) + ALIGN(mbi_header->name_len, 16), 16);
- objectlen = ALIGN((mbi_header->size * 16), 16);
-
- if (getobj->objnum == count) {
- printk(BIOS_DEBUG, "| |- len = %x\n", headerlen + objectlen);
-
- memcpy((void *)(getobj->buffer + OBJ_OFFSET),
- ((char *)mbi_header) + headerlen, (objectlen > getobj->buflen) ? getobj->buflen : objectlen);
-
- getobj->banner.retsts = MSH_OK;
-#ifdef DEBUG_SMI_I82830
- dump((u8 *)banner_id, sizeof(*getobj));
- dump((u8 *)getobj->buffer + OBJ_OFFSET, objectlen);
-#endif
- break;
- }
- i += (headerlen + objectlen);
- count++;
- }
- if (getobj->banner.retsts == MSH_IF_NOT_FOUND)
- printk(BIOS_DEBUG, "MBI module %d not found.\n", getobj->objnum);
- break;
- }
- default:
- printk(BIOS_DEBUG, "|- function %x\n", banner_id->function);
- printk(BIOS_DEBUG, "| |- Unknown Function!\n");
- break;
- }
- printk(BIOS_DEBUG, "\n");
- //dump(banner_id, 0x20);
-}
-
-#define SMI_IFC_SUCCESS 1
-#define SMI_IFC_FAILURE_GENERIC 0
-#define SMI_IFC_FAILURE_INVALID 2
-#define SMI_IFC_FAILURE_CRITICAL 4
-#define SMI_IFC_FAILURE_NONCRITICAL 6
-
-#define PC10 0x10
-#define PC11 0x11
-#define PC12 0x12
-#define PC13 0x13
-
-static void smi_interface_call(void)
-{
- u32 mmio = pci_read_config32(PCI_DEV(0, 0x02, 0), 0x14);
- // mmio &= 0xfff80000;
- // printk(BIOS_DEBUG, "mmio=%x\n", mmio);
- u16 swsmi = pci_read_config16(PCI_DEV(0, 0x02, 0), 0xe0);
-
- if (!(swsmi & 1))
- return;
-
- swsmi &= ~(1 << 0); // clear SMI toggle
-
- switch ((swsmi>>1) & 0xf) {
- case 0:
- printk(BIOS_DEBUG, "Interface Function Presence Test.\n");
- swsmi = 0;
- swsmi &= ~(7 << 5); // Exit: Result
- swsmi |= (SMI_IFC_SUCCESS << 5);
- swsmi &= 0xff;
- swsmi |= (PC13 << 8);
- pci_write_config16(PCI_DEV(0, 0x02, 0), 0xe0, swsmi);
- // write magic
- write32(mmio + 0x71428, 0x494e5443);
- return;
- case 4:
- printk(BIOS_DEBUG, "Get BIOS Data.\n");
- printk(BIOS_DEBUG, "swsmi=%04x\n", swsmi);
- break;
- case 5:
- printk(BIOS_DEBUG, "Call MBI Functions.\n");
- mbi_call(swsmi >> 8, (banner_id_t *)((read32(mmio + 0x71428) & 0x000fffff) + OBJ_OFFSET) );
- // swsmi = 0x0000;
- swsmi &= ~(7 << 5); // Exit: Result
- swsmi |= (SMI_IFC_SUCCESS << 5);
- pci_write_config16(PCI_DEV(0, 0x02, 0), 0xe0, swsmi);
- return;
- case 6:
- printk(BIOS_DEBUG, "System BIOS Callbacks.\n");
- printk(BIOS_DEBUG, "swsmi=%04x\n", swsmi);
- break;
- default:
- printk(BIOS_DEBUG, "Unknown SMI interface call %04x\n", swsmi);
- break;
- }
-
- swsmi &= ~(7 << 5); // Exit: Result
- swsmi |= (SMI_IFC_FAILURE_CRITICAL << 7);
- pci_write_config16(PCI_DEV(0, 0x02, 0), 0xe0, swsmi);
-}
-
-/**
- * @brief read and clear ERRSTS
- * @return ERRSTS register
- */
-static u16 reset_err_status(void)
-{
- u16 reg16;
-
- reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), ERRSTS);
- /* set status bits are cleared by writing 1 to them */
- pci_write_config16(PCI_DEV(0, 0x00, 0), ERRSTS, reg16);
-
- return reg16;
-}
-
-static void dump_err_status(u32 errsts)
-{
- printk(BIOS_DEBUG, "ERRSTS: ");
- if (errsts & (1 << 12)) printk(BIOS_DEBUG, "MBI ");
- if (errsts & (1 << 9)) printk(BIOS_DEBUG, "LCKF ");
- if (errsts & (1 << 8)) printk(BIOS_DEBUG, "DTF ");
- if (errsts & (1 << 5)) printk(BIOS_DEBUG, "UNSC ");
- if (errsts & (1 << 4)) printk(BIOS_DEBUG, "OOGF ");
- if (errsts & (1 << 3)) printk(BIOS_DEBUG, "IAAF ");
- if (errsts & (1 << 2)) printk(BIOS_DEBUG, "ITTEF ");
- printk(BIOS_DEBUG, "\n");
-}
-
-void northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)
-{
- u16 errsts;
-
- /* We need to clear the SMI status registers, or we won't see what's
- * happening in the following calls.
- */
- errsts = reset_err_status();
- if (errsts & (1 << 12)) {
- smi_interface_call();
- } else {
- if (errsts)
- dump_err_status(errsts);
- }
-
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/smm.h>
+#include <device/pci_def.h>
+#include "i82830.h"
+
+extern unsigned char *mbi;
+extern u32 mbi_len;
+
+// #define DEBUG_SMI_I82830
+
+/* If YABEL is enabled and it's not running at 0x00000000, we have to add some
+ * offset to all our mbi object memory accesses
+ */
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL && !CONFIG_YABEL_DIRECTHW
+#define OBJ_OFFSET CONFIG_YABEL_VIRTMEM_LOCATION
+#else
+#define OBJ_OFFSET 0x00000
+#endif
+
+/* I830M */
+#define SMRAM 0x90
+#define D_OPEN (1 << 6)
+#define D_CLS (1 << 5)
+#define D_LCK (1 << 4)
+#define G_SMRANE (1 << 3)
+#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
+
+
+typedef struct {
+ u32 mhid;
+ u32 function;
+ u32 retsts;
+ u32 rfu;
+} __attribute__((packed)) banner_id_t;
+
+#define MSH_OK 0x0000
+#define MSH_OK_RESTART 0x0001
+#define MSH_FWH_ERR 0x00ff
+#define MSH_IF_BAD_ID 0x0100
+#define MSH_IF_BAD_FUNC 0x0101
+#define MSH_IF_MBI_CORRUPT 0x0102
+#define MSH_IF_BAD_HANDLE 0x0103
+#define MSH_ALRDY_ATCHED 0x0104
+#define MSH_NOT_ATCHED 0x0105
+#define MSH_IF 0x0106
+#define MSH_IF_INVADDR 0x0107
+#define MSH_IF_UKN_TYPE 0x0108
+#define MSH_IF_NOT_FOUND 0x0109
+#define MSH_IF_NO_KEY 0x010a
+#define MSH_IF_BUF_SIZE 0x010b
+#define MSH_IF_NOT_PENDING 0x010c
+
+#ifdef DEBUG_SMI_I82830
+static void
+dump(u8 * addr, u32 len)
+{
+ printk(BIOS_DEBUG, "\n%s(%p, %x):\n", __func__, addr, len);
+ while (len) {
+ unsigned int tmpCnt = len;
+ unsigned char x;
+ if (tmpCnt > 8)
+ tmpCnt = 8;
+ printk(BIOS_DEBUG, "\n%p: ", addr);
+ // print hex
+ while (tmpCnt--) {
+ x = *addr++;
+ printk(BIOS_DEBUG, "%02x ", x);
+ }
+ tmpCnt = len;
+ if (tmpCnt > 8)
+ tmpCnt = 8;
+ len -= tmpCnt;
+ //reset addr ptr to print ascii
+ addr = addr - tmpCnt;
+ // print ascii
+ while (tmpCnt--) {
+ x = *addr++;
+ if ((x < 32) || (x >= 127)) {
+ //non-printable char
+ x = '.';
+ }
+ printk(BIOS_DEBUG, "%c", x);
+ }
+ }
+ printk(BIOS_DEBUG, "\n");
+}
+#endif
+
+typedef struct {
+ banner_id_t banner;
+ u16 versionmajor;
+ u16 versionminor;
+ u32 smicombuffersize;
+} __attribute__((packed)) version_t;
+
+typedef struct {
+ u16 header_id;
+ u16 attributes;
+ u16 size;
+ u8 name_len;
+ u8 reserved;
+ u32 type;
+ u32 header_ext;
+ u8 name[0];
+} __attribute__((packed)) mbi_header_t;
+
+typedef struct {
+ banner_id_t banner;
+ u64 handle;
+ u32 objnum;
+ mbi_header_t header;
+} __attribute__((packed)) obj_header_t;
+
+typedef struct {
+ banner_id_t banner;
+ u64 handle;
+ u32 objnum;
+ u32 start;
+ u32 numbytes;
+ u32 buflen;
+ u32 buffer;
+} __attribute__((packed)) get_object_t;
+
+static void mbi_call(u8 subf, banner_id_t *banner_id)
+{
+#ifdef DEBUG_SMI_I82830
+ printk(BIOS_DEBUG, "MBI\n");
+ printk(BIOS_DEBUG, "|- sub function %x\n", subf);
+ printk(BIOS_DEBUG, "|- banner id @ %x\n", (u32)banner_id);
+ printk(BIOS_DEBUG, "| |- mhid %x\n", banner_id->mhid);
+ printk(BIOS_DEBUG, "| |- function %x\n", banner_id->function);
+ printk(BIOS_DEBUG, "| |- return status %x\n", banner_id->retsts);
+ printk(BIOS_DEBUG, "| |- rfu %x\n", banner_id->rfu);
+#endif
+
+ switch(banner_id->function) {
+ case 0x0001: {
+ version_t *version;
+ printk(BIOS_DEBUG, "|- MBI_QueryInterface\n");
+ version = (version_t *)banner_id;
+ version->banner.retsts = MSH_OK;
+ version->versionmajor=1;
+ version->versionminor=3;
+ version->smicombuffersize=0x1000;
+ break;
+ }
+ case 0x0002:
+ printk(BIOS_DEBUG, "|- MBI_Attach\n");
+ printk(BIOS_DEBUG, "|Â |- Not Implemented!\n");
+ break;
+ case 0x0003:
+ printk(BIOS_DEBUG, "|- MBI_Detach\n");
+ printk(BIOS_DEBUG, "|Â |- Not Implemented!\n");
+ break;
+ case 0x0201: {
+ obj_header_t *obj_header = (obj_header_t *)banner_id;
+ mbi_header_t *mbi_header = NULL;
+ printk(BIOS_DEBUG, "|- MBI_GetObjectHeader\n");
+ printk(BIOS_DEBUG, "| |- objnum = %d\n", obj_header->objnum);
+
+ int i, count=0;
+ obj_header->banner.retsts = MSH_IF_NOT_FOUND;
+
+ for (i=0; i<mbi_len;) {
+ int len;
+
+ if (!(mbi[i] == 0xf0 && mbi [i+1] == 0xf6)) {
+ i+=16;
+ continue;
+ }
+
+ mbi_header = (mbi_header_t *)&mbi[i];
+ len = ALIGN((mbi_header->size * 16) + sizeof(mbi_header) + ALIGN(mbi_header->name_len, 16), 16);
+
+ if (obj_header->objnum == count) {
+#ifdef DEBUG_SMI_I82830
+ if (mbi_header->name_len == 0xff) {
+ printk(BIOS_DEBUG, "| |- corrupt.\n");
+ break;
+ }
+#endif
+ int headerlen = ALIGN(sizeof(mbi_header) + ALIGN(mbi_header->name_len, 16), 16);
+#ifdef DEBUG_SMI_I82830
+ printk(BIOS_DEBUG, "| |- headerlen = %d\n", headerlen);
+#endif
+ memcpy(&obj_header->header, mbi_header, headerlen);
+ obj_header->banner.retsts = MSH_OK;
+ printk(BIOS_DEBUG, "| |- MBI module '");
+ int j;
+ for (j=0; j < mbi_header->name_len && mbi_header->name[j]; j++)
+ printk(BIOS_DEBUG, "%c", mbi_header->name[j]);
+ printk(BIOS_DEBUG, "' found.\n");
+#ifdef DEBUG_SMI_I82830
+ dump((u8 *)banner_id, sizeof(obj_header_t) + ALIGN(mbi_header->name_len, 16));
+#endif
+ break;
+ }
+ i += len;
+ count++;
+ }
+ if (obj_header->banner.retsts == MSH_IF_NOT_FOUND)
+ printk(BIOS_DEBUG, "| |- MBI object #%d not found.\n", obj_header->objnum);
+ break;
+ }
+ case 0x0203: {
+ get_object_t *getobj = (get_object_t *)banner_id;
+ mbi_header_t *mbi_header = NULL;
+ printk(BIOS_DEBUG, "|- MBI_GetObject\n");
+#ifdef DEBUG_SMI_I82830
+ printk(BIOS_DEBUG, "| |- handle = %016Lx\n", getobj->handle);
+#endif
+ printk(BIOS_DEBUG, "| |- objnum = %d\n", getobj->objnum);
+ printk(BIOS_DEBUG, "| |- start = %x\n", getobj->start);
+ printk(BIOS_DEBUG, "| |- numbytes = %x\n", getobj->numbytes);
+ printk(BIOS_DEBUG, "| |- buflen = %x\n", getobj->buflen);
+ printk(BIOS_DEBUG, "| |- buffer = %x\n", getobj->buffer);
+
+ int i, count=0;
+ getobj->banner.retsts = MSH_IF_NOT_FOUND;
+
+ for (i=0; i< mbi_len;) {
+ int headerlen, objectlen;
+
+ if (!(mbi[i] == 0xf0 && mbi [i+1] == 0xf6)) {
+ i+=16;
+ continue;
+ }
+
+ mbi_header = (mbi_header_t *)&mbi[i];
+ headerlen = ALIGN(sizeof(mbi_header) + ALIGN(mbi_header->name_len, 16), 16);
+ objectlen = ALIGN((mbi_header->size * 16), 16);
+
+ if (getobj->objnum == count) {
+ printk(BIOS_DEBUG, "| |- len = %x\n", headerlen + objectlen);
+
+ memcpy((void *)(getobj->buffer + OBJ_OFFSET),
+ ((char *)mbi_header) + headerlen, (objectlen > getobj->buflen) ? getobj->buflen : objectlen);
+
+ getobj->banner.retsts = MSH_OK;
+#ifdef DEBUG_SMI_I82830
+ dump((u8 *)banner_id, sizeof(*getobj));
+ dump((u8 *)getobj->buffer + OBJ_OFFSET, objectlen);
+#endif
+ break;
+ }
+ i += (headerlen + objectlen);
+ count++;
+ }
+ if (getobj->banner.retsts == MSH_IF_NOT_FOUND)
+ printk(BIOS_DEBUG, "MBI module %d not found.\n", getobj->objnum);
+ break;
+ }
+ default:
+ printk(BIOS_DEBUG, "|- function %x\n", banner_id->function);
+ printk(BIOS_DEBUG, "| |- Unknown Function!\n");
+ break;
+ }
+ printk(BIOS_DEBUG, "\n");
+ //dump(banner_id, 0x20);
+}
+
+#define SMI_IFC_SUCCESS 1
+#define SMI_IFC_FAILURE_GENERIC 0
+#define SMI_IFC_FAILURE_INVALID 2
+#define SMI_IFC_FAILURE_CRITICAL 4
+#define SMI_IFC_FAILURE_NONCRITICAL 6
+
+#define PC10 0x10
+#define PC11 0x11
+#define PC12 0x12
+#define PC13 0x13
+
+static void smi_interface_call(void)
+{
+ u32 mmio = pci_read_config32(PCI_DEV(0, 0x02, 0), 0x14);
+ // mmio &= 0xfff80000;
+ // printk(BIOS_DEBUG, "mmio=%x\n", mmio);
+ u16 swsmi = pci_read_config16(PCI_DEV(0, 0x02, 0), 0xe0);
+
+ if (!(swsmi & 1))
+ return;
+
+ swsmi &= ~(1 << 0); // clear SMI toggle
+
+ switch ((swsmi>>1) & 0xf) {
+ case 0:
+ printk(BIOS_DEBUG, "Interface Function Presence Test.\n");
+ swsmi = 0;
+ swsmi &= ~(7 << 5); // Exit: Result
+ swsmi |= (SMI_IFC_SUCCESS << 5);
+ swsmi &= 0xff;
+ swsmi |= (PC13 << 8);
+ pci_write_config16(PCI_DEV(0, 0x02, 0), 0xe0, swsmi);
+ // write magic
+ write32(mmio + 0x71428, 0x494e5443);
+ return;
+ case 4:
+ printk(BIOS_DEBUG, "Get BIOS Data.\n");
+ printk(BIOS_DEBUG, "swsmi=%04x\n", swsmi);
+ break;
+ case 5:
+ printk(BIOS_DEBUG, "Call MBI Functions.\n");
+ mbi_call(swsmi >> 8, (banner_id_t *)((read32(mmio + 0x71428) & 0x000fffff) + OBJ_OFFSET) );
+ // swsmi = 0x0000;
+ swsmi &= ~(7 << 5); // Exit: Result
+ swsmi |= (SMI_IFC_SUCCESS << 5);
+ pci_write_config16(PCI_DEV(0, 0x02, 0), 0xe0, swsmi);
+ return;
+ case 6:
+ printk(BIOS_DEBUG, "System BIOS Callbacks.\n");
+ printk(BIOS_DEBUG, "swsmi=%04x\n", swsmi);
+ break;
+ default:
+ printk(BIOS_DEBUG, "Unknown SMI interface call %04x\n", swsmi);
+ break;
+ }
+
+ swsmi &= ~(7 << 5); // Exit: Result
+ swsmi |= (SMI_IFC_FAILURE_CRITICAL << 7);
+ pci_write_config16(PCI_DEV(0, 0x02, 0), 0xe0, swsmi);
+}
+
+/**
+ * @brief read and clear ERRSTS
+ * @return ERRSTS register
+ */
+static u16 reset_err_status(void)
+{
+ u16 reg16;
+
+ reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), ERRSTS);
+ /* set status bits are cleared by writing 1 to them */
+ pci_write_config16(PCI_DEV(0, 0x00, 0), ERRSTS, reg16);
+
+ return reg16;
+}
+
+static void dump_err_status(u32 errsts)
+{
+ printk(BIOS_DEBUG, "ERRSTS: ");
+ if (errsts & (1 << 12)) printk(BIOS_DEBUG, "MBI ");
+ if (errsts & (1 << 9)) printk(BIOS_DEBUG, "LCKF ");
+ if (errsts & (1 << 8)) printk(BIOS_DEBUG, "DTF ");
+ if (errsts & (1 << 5)) printk(BIOS_DEBUG, "UNSC ");
+ if (errsts & (1 << 4)) printk(BIOS_DEBUG, "OOGF ");
+ if (errsts & (1 << 3)) printk(BIOS_DEBUG, "IAAF ");
+ if (errsts & (1 << 2)) printk(BIOS_DEBUG, "ITTEF ");
+ printk(BIOS_DEBUG, "\n");
+}
+
+void northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)
+{
+ u16 errsts;
+
+ /* We need to clear the SMI status registers, or we won't see what's
+ * happening in the following calls.
+ */
+ errsts = reset_err_status();
+ if (errsts & (1 << 12)) {
+ smi_interface_call();
+ } else {
+ if (errsts)
+ dump_err_status(errsts);
+ }
+
+}
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-ramstage-y += cx700_reset.c
+ramstage-y += reset.c
ramstage-y += northbridge.c
-driver-y += cx700_agp.c
-driver-y += cx700_lpc.c
-driver-y += cx700_sata.c
-driver-y += cx700_vga.c
+driver-y += agp.c
+driver-y += lpc.c
+driver-y += sata.c
+driver-y += vga.c
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+/* This is the AGP 3.0 "bridge" @ Bus 0 Device 1 Func 0 */
+
+static void agp_bridge_init(device_t dev)
+{
+
+ device_t north_dev;
+ u8 reg8;
+ north_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3324, 0);
+
+ pci_write_config8(north_dev, 0xa0, 0x1); // Enable CPU Direct Access Frame Buffer
+
+ pci_write_config8(north_dev, 0xa2, 0x4a);
+
+ reg8 = pci_read_config8(north_dev, 0xc0);
+ reg8 |= 0x1;
+ pci_write_config8(north_dev, 0xc0, reg8);
+
+ /*
+ * Since Internal Graphic already set to AGP3.0 compatible in its Capability Pointer
+ * We must set RAGP8X=1 B0D0F0 Rx84[3]=1 from backdoor register B0D0F0 RxB5[1:0]=11b
+ */
+ north_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x0324, 0);
+ reg8 = pci_read_config8(north_dev, 0xb5);
+ reg8 |= 0x3;
+ pci_write_config8(north_dev, 0xb5, reg8);
+ pci_write_config8(north_dev, 0x94, 0x20);
+ pci_write_config8(north_dev, 0x13, 0xd0);
+
+ pci_write_config16(dev, 0x4, 0x0007);
+
+ pci_write_config8(dev, 0x19, 0x01);
+ pci_write_config8(dev, 0x1a, 0x01);
+ pci_write_config8(dev, 0x1c, 0xe0);
+ pci_write_config8(dev, 0x1d, 0xe0);
+ pci_write_config16(dev, 0x1e, 0xa220);
+
+ pci_write_config16(dev, 0x20, 0xdd00);
+ pci_write_config16(dev, 0x22, 0xdef0);
+ pci_write_config16(dev, 0x24, 0xa000);
+ pci_write_config16(dev, 0x26, 0xbff0);
+
+ pci_write_config8(dev, 0x3e, 0x0c);
+ pci_write_config8(dev, 0x40, 0x8b);
+ pci_write_config8(dev, 0x41, 0x43);
+ pci_write_config8(dev, 0x42, 0x62);
+ pci_write_config8(dev, 0x43, 0x44);
+ pci_write_config8(dev, 0x44, 0x34);
+}
+
+static void cx700_noop(device_t dev)
+{
+}
+
+static struct device_operations agp_bridge_operations = {
+ .read_resources = cx700_noop,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_bus_enable_resources,
+ .init = agp_bridge_init,
+ .scan_bus = pci_scan_bridge,
+};
+
+static const struct pci_driver agp_bridge_driver __pci_driver = {
+ .ops = &agp_bridge_operations,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = 0xb198,
+};
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <arch/io.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-
-/* This is the AGP 3.0 "bridge" @ Bus 0 Device 1 Func 0 */
-
-static void agp_bridge_init(device_t dev)
-{
-
- device_t north_dev;
- u8 reg8;
- north_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3324, 0);
-
- pci_write_config8(north_dev, 0xa0, 0x1); // Enable CPU Direct Access Frame Buffer
-
- pci_write_config8(north_dev, 0xa2, 0x4a);
-
- reg8 = pci_read_config8(north_dev, 0xc0);
- reg8 |= 0x1;
- pci_write_config8(north_dev, 0xc0, reg8);
-
- /*
- * Since Internal Graphic already set to AGP3.0 compatible in its Capability Pointer
- * We must set RAGP8X=1 B0D0F0 Rx84[3]=1 from backdoor register B0D0F0 RxB5[1:0]=11b
- */
- north_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x0324, 0);
- reg8 = pci_read_config8(north_dev, 0xb5);
- reg8 |= 0x3;
- pci_write_config8(north_dev, 0xb5, reg8);
- pci_write_config8(north_dev, 0x94, 0x20);
- pci_write_config8(north_dev, 0x13, 0xd0);
-
- pci_write_config16(dev, 0x4, 0x0007);
-
- pci_write_config8(dev, 0x19, 0x01);
- pci_write_config8(dev, 0x1a, 0x01);
- pci_write_config8(dev, 0x1c, 0xe0);
- pci_write_config8(dev, 0x1d, 0xe0);
- pci_write_config16(dev, 0x1e, 0xa220);
-
- pci_write_config16(dev, 0x20, 0xdd00);
- pci_write_config16(dev, 0x22, 0xdef0);
- pci_write_config16(dev, 0x24, 0xa000);
- pci_write_config16(dev, 0x26, 0xbff0);
-
- pci_write_config8(dev, 0x3e, 0x0c);
- pci_write_config8(dev, 0x40, 0x8b);
- pci_write_config8(dev, 0x41, 0x43);
- pci_write_config8(dev, 0x42, 0x62);
- pci_write_config8(dev, 0x43, 0x44);
- pci_write_config8(dev, 0x44, 0x34);
-}
-
-static void cx700_noop(device_t dev)
-{
-}
-
-static struct device_operations agp_bridge_operations = {
- .read_resources = cx700_noop,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_bus_enable_resources,
- .init = agp_bridge_init,
- .scan_bus = pci_scan_bridge,
-};
-
-static const struct pci_driver agp_bridge_driver __pci_driver = {
- .ops = &agp_bridge_operations,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = 0xb198,
-};
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/*
- * Enable the serial devices on the VIA CX700
- */
-
-#include <arch/romcc_io.h>
-
-static void cx700_writepnpaddr(u8 val)
-{
- outb(val, 0x2e);
- outb(val, 0xeb);
-}
-
-static void cx700_writepnpdata(u8 val)
-{
- outb(val, 0x2f);
- outb(val, 0xeb);
-}
-
-static void cx700_writesiobyte(u16 reg, u8 val)
-{
- outb(val, reg);
-}
-
-static void cx700_writesioword(u16 reg, u16 val)
-{
- outw(val, reg);
-}
-
-static void enable_cx700_serial(void)
-{
- outb(6, 0x80);
-
- // WTH?
- outb(0x03, 0x22);
-
- // Set UART1 I/O Base Address
- pci_write_config8(PCI_DEV(0, 17, 0), 0xb4, 0x7e);
-
- // UART1 Enable
- pci_write_config8(PCI_DEV(0, 17, 0), 0xb0, 0x10);
-
- // turn on pnp
- cx700_writepnpaddr(0x87);
- cx700_writepnpaddr(0x87);
- // now go ahead and set up com1.
- // set address
- cx700_writepnpaddr(0x7);
- cx700_writepnpdata(0x2);
- // enable serial out
- cx700_writepnpaddr(0x30);
- cx700_writepnpdata(0x1);
- // serial port 1 base address (FEh)
- cx700_writepnpaddr(0x60);
- cx700_writepnpdata(0xfe);
- // serial port 1 IRQ (04h)
- cx700_writepnpaddr(0x70);
- cx700_writepnpdata(0x4);
- // serial port 1 control
- cx700_writepnpaddr(0xf0);
- cx700_writepnpdata(0x2);
- // turn of pnp
- cx700_writepnpaddr(0xaa);
-
- // XXX This part should be fully taken care of by
- // src/pc80/serial.c:uart_init
-
- // set up reg to set baud rate.
- cx700_writesiobyte(0x3fb, 0x80);
- // Set 115 kb
- cx700_writesioword(0x3f8, 1);
- // Set 9.6 kb
- // cx700_writesioword(0x3f8, 12)
- // now set no parity, one stop, 8 bits
- cx700_writesiobyte(0x3fb, 3);
- // now turn on RTS, DRT
- cx700_writesiobyte(0x3fc, 3);
- // Enable interrupts
- cx700_writesiobyte(0x3f9, 0xf);
- // should be done. Dump a char for fun.
- cx700_writesiobyte(0x3f8, 48);
-
- outb(7, 0x80);
-}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-// other bioses use this, too:
-#define SMBUS_IO_BASE 0x0500
-
-#define SMBHSTSTAT SMBUS_IO_BASE + 0x0
-#define SMBSLVSTAT SMBUS_IO_BASE + 0x1
-#define SMBHSTCTL SMBUS_IO_BASE + 0x2
-#define SMBHSTCMD SMBUS_IO_BASE + 0x3
-#define SMBXMITADD SMBUS_IO_BASE + 0x4
-#define SMBHSTDAT0 SMBUS_IO_BASE + 0x5
-#define SMBHSTDAT1 SMBUS_IO_BASE + 0x6
-
-#define SMBBLKDAT SMBUS_IO_BASE + 0x7
-#define SMBSLVCTL SMBUS_IO_BASE + 0x8
-#define SMBTRNSADD SMBUS_IO_BASE + 0x9
-#define SMBSLVDATA SMBUS_IO_BASE + 0xa
-#define SMLINK_PIN_CTL SMBUS_IO_BASE + 0xe
-#define SMBUS_PIN_CTL SMBUS_IO_BASE + 0xf
-
-/* Define register settings */
-#define HOST_RESET 0xff
-#define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ
-
-#define SMBUS_TIMEOUT (100*1000*10)
-
-#define I2C_TRANS_CMD 0x40
-#define CLOCK_SLAVE_ADDRESS 0x69
-
-#define SMBUS_DELAY() outb(0x80, 0x80)
-
-/* Debugging macros. */
-#if CONFIG_DEBUG_SMBUS
-#define PRINT_DEBUG(x) print_debug(x)
-#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x)
-#else
-#define PRINT_DEBUG(x)
-#define PRINT_DEBUG_HEX16(x)
-#endif
-
-/* Internal functions */
-#if CONFIG_DEBUG_SMBUS
-static void smbus_print_error(unsigned char host_status_register, int loops)
-{
- /* Check if there actually was an error */
- if (host_status_register == 0x00 || host_status_register == 0x40 ||
- host_status_register == 0x42)
- return;
- print_err("SMBus Error: ");
- print_err_hex8(host_status_register);
-
- print_err("\n");
- if (loops >= SMBUS_TIMEOUT) {
- print_err("SMBus Timout\n");
- }
- if (host_status_register & (1 << 4)) {
- print_err("Interrup/SMI# was Failed Bus Transaction\n");
- }
- if (host_status_register & (1 << 3)) {
- print_err("Bus Error\n");
- }
- if (host_status_register & (1 << 2)) {
- print_err("Device Error\n");
- }
- if (host_status_register & (1 << 1)) {
- /* This isn't a real error... */
- print_debug("Interrupt/SMI# was Successful Completion\n");
- }
- if (host_status_register & (1 << 0)) {
- print_err("Host Busy\n");
- }
-}
-#endif
-
-static void smbus_wait_until_ready(void)
-{
- int loops;
-
- loops = 0;
-
- /* Yes, this is a mess, but it's the easiest way to do it */
- while (((inb(SMBHSTSTAT) & 1) == 1) && (loops <= SMBUS_TIMEOUT)) {
- SMBUS_DELAY();
- ++loops;
- }
-#if CONFIG_DEBUG_SMBUS
- /* Some systems seem to have a flakey SMBus. No need to spew a lot of
- * errors on those, once we know that SMBus access is principally
- * working.
- */
- smbus_print_error(inb(SMBHSTSTAT), loops);
-#endif
-}
-
-static void smbus_reset(void)
-{
- outb(HOST_RESET, SMBHSTSTAT);
-}
-
-/* Public functions */
-static void set_ics_data(unsigned char dev, int data, char len)
-{
- //int i;
- smbus_reset();
- /* clear host data port */
- outb(0x00, SMBHSTDAT0);
- SMBUS_DELAY();
- smbus_wait_until_ready();
-
- /* read to reset block transfer counter */
- inb(SMBHSTCTL);
-
- /* fill blocktransfer array */
- if (dev == 0xd2) {
- //char d2_data[] = {0x0d,0x00,0x3f,0xcd,0x7f,0xbf,0x1a,0x2a,0x01,0x0f,0x0b,0x00,0x8d,0x9b};
- outb(0x0d, SMBBLKDAT);
- outb(0x00, SMBBLKDAT);
- outb(0x3f, SMBBLKDAT);
- outb(0xcd, SMBBLKDAT);
- outb(0x7f, SMBBLKDAT);
- outb(0xbf, SMBBLKDAT);
- outb(0x1a, SMBBLKDAT);
- outb(0x2a, SMBBLKDAT);
- outb(0x01, SMBBLKDAT);
- outb(0x0f, SMBBLKDAT);
- outb(0x0b, SMBBLKDAT);
- outb(0x80, SMBBLKDAT);
- outb(0x8d, SMBBLKDAT);
- outb(0x9b, SMBBLKDAT);
- } else {
- //char d4_data[] = {0x08,0xff,0x3f,0x00,0x00,0xff,0xff,0xff,0xff};
- outb(0x08, SMBBLKDAT);
- outb(0xff, SMBBLKDAT);
- outb(0x3f, SMBBLKDAT);
- outb(0x00, SMBBLKDAT);
- outb(0x00, SMBBLKDAT);
- outb(0xff, SMBBLKDAT);
- outb(0xff, SMBBLKDAT);
- outb(0xff, SMBBLKDAT);
- outb(0xff, SMBBLKDAT);
- }
-
- //for (i=0; i < len; i++)
- // outb(data[i],SMBBLKDAT);
-
- outb(dev, SMBXMITADD);
- outb(0, SMBHSTCMD);
- outb(len, SMBHSTDAT0);
- outb(0x74, SMBHSTCTL);
-
- SMBUS_DELAY();
-
- smbus_wait_until_ready();
-
- smbus_reset();
-
-}
-
-static unsigned int get_spd_data(const struct mem_controller *ctrl, unsigned int dimm,
- unsigned int offset)
-{
- unsigned int val, addr;
-
- smbus_reset();
-
- /* clear host data port */
- outb(0x00, SMBHSTDAT0);
- SMBUS_DELAY();
- smbus_wait_until_ready();
-
- /* Fetch the SMBus address of the SPD ROM from
- * the ctrl struct in romstage.c in case they are at
- * non-standard positions.
- * SMBus Address shifted by 1
- */
- addr = (ctrl->channel0[dimm]) << 1;
-
- outb(addr | 0x1, SMBXMITADD);
- outb(offset, SMBHSTCMD);
- outb(0x48, SMBHSTCTL);
-
- SMBUS_DELAY();
-
- smbus_wait_until_ready();
-
- val = inb(SMBHSTDAT0);
- smbus_reset();
- return val;
-}
-
-static void enable_smbus(void)
-{
- device_t dev;
-
- /* The CX700 ISA Bridge (0x1106, 0x8324) is hardcoded to this location,
- * no need to probe.
- */
- dev = PCI_DEV(0, 17, 0);
-
- /* SMBus Clock Select: Divider fof 14.318MHz */
- pci_write_config8(dev, 0x94, 0x20);
-
- /* SMBus I/O Base, enable SMBus */
- pci_write_config16(dev, 0xd0, SMBUS_IO_BASE | 1);
-
- /* SMBus Clock from 128K Source, Enable SMBus Host Controller */
- pci_write_config8(dev, 0xd2, 0x05);
-
- /* Enable I/O decoding */
- pci_write_config16(dev, 0x04, 0x0003);
-
- /* Setup clock chips */
- set_ics_data(0xd2, 0, 14);
- set_ics_data(0xd4, 0, 9);
-}
-
-/* Debugging Function */
-#if CONFIG_DEBUG_SMBUS
-static void dump_spd_data(const struct mem_controller *ctrl)
-{
- int dimm, offset, regs;
- unsigned int val;
-
- for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) {
- print_debug("SPD Data for DIMM ");
- print_debug_hex8(dimm);
- print_debug("\n");
-
- val = get_spd_data(ctrl, dimm, 0);
- if (val == 0xff) {
- regs = 256;
- } else if (val == 0x80) {
- regs = 128;
- } else {
- print_debug("No DIMM present\n");
- regs = 0;
- }
- for (offset = 0; offset < regs; offset++) {
- print_debug(" Offset ");
- print_debug_hex8(offset);
- print_debug(" = 0x");
- print_debug_hex8(get_spd_data(ctrl, dimm, offset));
- print_debug("\n");
- }
- }
-}
-#else
-#define dump_spd_data(ctrl)
-#endif
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <device/pci_ids.h>
-#include <pc80/mc146818rtc.h>
-#include <pc80/i8259.h>
-#include <pc80/keyboard.h>
-#include <pc80/isa-dma.h>
-#include <cpu/x86/lapic.h>
-#include <arch/ioapic.h>
-#include <stdlib.h>
-
-#define ACPI_IO_BASE 0x400
-#define HPET_ADDR 0xfe800000UL
-
-static const unsigned char pci_irqs[4] = { 11, 11, 10, 10 };
-
-static const unsigned char usb_pins[4] = { 'A', 'B', 'C', 'D' };
-static const unsigned char vga_pins[4] = { 'A', 'B', 'C', 'D' };
-static const unsigned char slot_pins[4] = { 'B', 'C', 'D', 'A' };
-static const unsigned char ac97_pins[4] = { 'B', 'C', 'D', 'A' };
-
-static unsigned char *pin_to_irq(const unsigned char *pin)
-{
- static unsigned char irqs[4];
- int i;
- for (i = 0; i < 4; i++)
- irqs[i] = pci_irqs[pin[i] - 'A'];
-
- return irqs;
-}
-
-static void pci_routing_fixup(struct device *dev)
-{
- printk(BIOS_DEBUG, "%s: device is %p\n", __FUNCTION__, dev);
-
- /* set up PCI IRQ routing */
- pci_write_config8(dev, 0x55, pci_irqs[0] << 4);
- pci_write_config8(dev, 0x56, pci_irqs[1] | (pci_irqs[2] << 4));
- pci_write_config8(dev, 0x57, pci_irqs[3] << 4);
-
- /* Assigning IRQs */
- printk(BIOS_DEBUG, "Setting up USB interrupts.\n");
- pci_assign_irqs(0, 0x10, pin_to_irq(usb_pins));
-
- printk(BIOS_DEBUG, "Setting up VGA interrupts.\n");
- pci_assign_irqs(1, 0x00, pin_to_irq(vga_pins));
-
- printk(BIOS_DEBUG, "Setting up PCI slot interrupts.\n");
- pci_assign_irqs(2, 0x04, pin_to_irq(slot_pins));
- // more?
-
- printk(BIOS_DEBUG, "Setting up AC97 interrupts.\n");
- pci_assign_irqs(0x80, 0x1, pin_to_irq(ac97_pins));
-}
-
-/*
- * Set up the power management capabilities directly into ACPI mode. This
- * avoids having to handle any System Management Interrupts (SMI's) which I
- * can't figure out how to do !!!!
- */
-
-static void setup_pm(device_t dev)
-{
- /* Debounce LID and PWRBTN# Inputs for 16ms. */
- pci_write_config8(dev, 0x80, 0x20);
-
- /* Set ACPI base address to IO ACPI_IO_BASE */
- pci_write_config16(dev, 0x88, ACPI_IO_BASE | 1);
-
- /* set ACPI irq to 9 */
- pci_write_config8(dev, 0x82, 0x49);
-
- /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */
- pci_write_config16(dev, 0x84, 0x609a);
-
- /* SMI output level to low, 7.5us throttle clock */
- pci_write_config8(dev, 0x8d, 0x18);
-
- /* GP Timer Control 1s */
- pci_write_config8(dev, 0x93, 0x88);
-
- /* Power Well */
- pci_write_config8(dev, 0x94, 0x20); // 0x20??
-
- /* 7 = stp to sust delay 1msec
- * 6 = SUSST# Deasserted Before PWRGD for STD
- */
- pci_write_config8(dev, 0x95, 0xc0); // 0xc1??
-
- /* Disable GP2 & GP3 Timer */
- pci_write_config8(dev, 0x98, 0);
-
- /* GP2 Timer Counter */
- pci_write_config8(dev, 0x99, 0xfb);
- /* GP3 Timer Counter */
- //pci_write_config8(dev, 0x9a, 0x20);
-
- /* Multi Function Select 1 */
- pci_write_config8(dev, 0xe4, 0x00);
-
- /* Multi Function Select 2 */
- pci_write_config8(dev, 0xe5, 0x41); //??
-
- /* Enable ACPI access (and setup like award) */
- pci_write_config8(dev, 0x81, 0x84);
-
- /* Clear status events. */
- outw(0xffff, ACPI_IO_BASE + 0x00);
- outw(0xffff, ACPI_IO_BASE + 0x20);
- outw(0xffff, ACPI_IO_BASE + 0x28);
- outl(0xffffffff, ACPI_IO_BASE + 0x30);
-
- /* Disable SCI on GPIO. */
- outw(0x0, ACPI_IO_BASE + 0x22);
-
- /* Disable SMI on GPIO. */
- outw(0x0, ACPI_IO_BASE + 0x24);
-
- /* Disable all global enable SMIs. */
- outw(0x0, ACPI_IO_BASE + 0x2a);
-
- /* All SMI off, both IDE buses ON, PSON rising edge. */
- outw(0x0, ACPI_IO_BASE + 0x2c);
-
- /* Primary activity SMI disable. */
- outl(0x0, ACPI_IO_BASE + 0x34);
-
- /* GP timer reload on none. */
- outl(0x0, ACPI_IO_BASE + 0x38);
-
- /* Disable extended IO traps. */
- outb(0x0, ACPI_IO_BASE + 0x42);
-
- /* SCI is generated for RTC/pwrBtn/slpBtn. */
- outw(0x0001, ACPI_IO_BASE + 0x04);
-
- /* Allow SLP# signal to assert LDTSTOP_L.
- * Will work for C3 and for FID/VID change.
- */
- outb(0x1, ACPI_IO_BASE + 0x11);
-}
-
-static void cx700_set_lpc_registers(struct device *dev)
-{
- unsigned char enables;
-
- printk(BIOS_DEBUG, "VIA CX700 LPC bridge init\n");
-
- // enable the internal I/O decode
- enables = pci_read_config8(dev, 0x6C);
- enables |= 0x80;
- pci_write_config8(dev, 0x6C, enables);
-
- // Map 4MB of FLASH into the address space
-// pci_write_config8(dev, 0x41, 0x7f);
-
- // Set bit 6 of 0x40, because Award does it (IO recovery time)
- // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
- // interrupts can be properly marked as level triggered.
- enables = pci_read_config8(dev, 0x40);
- enables |= 0x44;
- pci_write_config8(dev, 0x40, enables);
-
- /* DMA Line buffer control */
- enables = pci_read_config8(dev, 0x42);
- enables |= 0xf0;
- pci_write_config8(dev, 0x42, enables);
-
- /* I/O recovery time */
- pci_write_config8(dev, 0x4c, 0x44);
-
- /* ROM memory cycles go to LPC. */
- pci_write_config8(dev, 0x59, 0x80);
-
- /* Enable SM dynamic clock gating */
- pci_write_config8(dev, 0x5b, 0x01);
-
- /* Set Read Pass Write Control Enable */
- pci_write_config8(dev, 0x48, 0x0c);
-
- /* Set SM Misc Control: Enable Internal APIC . */
- enables = pci_read_config8(dev, 0x58);
- enables |= 1 << 6;
- pci_write_config8(dev, 0x58, enables);
- enables = pci_read_config8(dev, 0x4d);
- enables |= 1 << 3;
- pci_write_config8(dev, 0x4d, enables);
-
- /* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */
- enables = pci_read_config8(dev, 0x4f);
- enables |= 0x08;
- pci_write_config8(dev, 0x4f, enables);
-
- /* enable KBC configuration */
- pci_write_config8(dev, 0x51, 0x1f);
-
- /* enable serial irq */
- pci_write_config8(dev, 0x52, 0x9);
-
- /* dma */
- pci_write_config8(dev, 0x53, 0x00);
-
- // Power management setup
- setup_pm(dev);
-
- /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
- pci_write_config8(dev, 0x40, 0x54);
-
- /* Enable HPET timer */
- pci_write_config32(dev, 0x68, (1 << 31) | (HPET_ADDR >> 8));
-
-}
-
-static void cx700_read_resources(device_t dev)
-{
- struct resource *res;
-
- /* Make sure we call our childrens set/enable functions - these
- * are not called unless this device has a resource to set.
- */
-
- pci_dev_read_resources(dev);
-
- res = new_resource(dev, 1);
- res->base = 0x0UL;
- res->size = 0x400UL;
- res->limit = 0xffffUL;
- res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
- res = new_resource(dev, 3); /* IOAPIC */
- res->base = IO_APIC_ADDR;
- res->size = 0x00001000;
- res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-}
-
-static void cx700_set_resources(device_t dev)
-{
- struct resource *resource;
- resource = find_resource(dev, 1);
- resource->flags |= IORESOURCE_STORED;
- pci_dev_set_resources(dev);
-}
-
-static void cx700_enable_resources(device_t dev)
-{
- /* Enable SuperIO decoding */
- pci_dev_enable_resources(dev);
-}
-
-static void cx700_lpc_init(struct device *dev)
-{
- cx700_set_lpc_registers(dev);
-
-#if CONFIG_IOAPIC
-#define IO_APIC_ID 2
- setup_ioapic(IO_APIC_ADDR, IO_APIC_ID);
-#endif
-
- /* Initialize interrupts */
- pci_routing_fixup(dev);
- /* make sure interupt controller is configured before keyboard init */
- setup_i8259();
-
- /* Start the Real Time Clock */
- rtc_init(0);
-
- /* Initialize isa dma */
- isa_dma_init();
-
- /* Initialize keyboard controller */
- pc_keyboard_init(0);
-}
-
-static struct device_operations cx700_lpc_ops = {
- .read_resources = cx700_read_resources,
- .set_resources = cx700_set_resources,
- .enable_resources = cx700_enable_resources,
- .init = &cx700_lpc_init,
- .scan_bus = scan_static_bus,
-};
-
-static const struct pci_driver lpc_driver __pci_driver = {
- .ops = &cx700_lpc_ops,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = 0x8324,
-};
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* CX700 has 48 bytes of scratch registers in D0F4 starting at Reg. 0xd0 */
-#define SCRATCH_REG_BASE 0xd0
-#define SCRATCH_RANK_0 0xd0
-#define SCRATCH_RANK_1 0xd1
-#define SCRATCH_RANK_2 0xd2
-#define SCRATCH_RANK_3 0xd3
-#define SCRATCH_DIMM_NUM 0xd4
-#define SCRATCH_RANK_NUM 0xd5
-#define SCRATCH_RANK_MAP 0xd6
-#define SCRATCH_DRAM_FREQ 0xd7
-#define SCRATCH_DRAM_NB_ODT 0xd8
-#define SCRATCH_RANK0_SIZE_REG 0xe0 /* RxE0~RxE3 */
-#define SCRATCH_RANK0_MA_REG 0xe4 /* RxE4~RxE7 */
-#define SCRATCH_CHA_DQSI_LOW_REG 0xe8
-#define SCRATCH_CHA_DQSI_HIGH_REG 0xe9
-#define SCRATCH_ChA_DQSI_REG 0xea
-#define SCRATCH_DRAM_256M_BIT 0xee
-#define SCRATCH_FLAGS 0xef
-
-#define DDRII_666 0x5
-#define DDRII_533 0x4
-#define DDRII_400 0x3
-#define DDRII_333 0x2
-#define DDRII_266 0x1
-#define DDRII_200 0x0
-
-
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <reset.h>
-
-void hard_reset(void)
-{
- outb((1 << 2) | (1 << 1), 0xcf9);
-}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-
-/* IDE specific bits */
-#define IDE_MODE_REG 0x09
-#define IDE0_NATIVE_MODE (1 << 0)
-#define IDE1_NATIVE_MODE (1 << 2)
-
-/* These are default addresses */
-#define IDE0_DATA_ADDR 0x1f0
-#define IDE0_CONTROL_ADDR 0x3f4
-#define IDE1_DATA_ADDR 0x170
-#define IDE1_CONTROL_ADDR 0x370
-
-#define BUS_MASTER_ADDR 0xfc00
-
-#define CHANNEL_ENABLE_REG 0x40
-#define ENABLE_IDE0 (1 << 0)
-#define ENABLE_IDE1 (1 << 1)
-
-/* TODO: better user configuration */
-#define DISABLE_SATA 0
-
-static void sata_init(struct device *dev)
-{
- u8 reg8;
-
- printk(BIOS_DEBUG, "Configuring VIA SATA & EIDE Controller\n");
-
- /* Class IDE Disk, instead of RAID controller */
- reg8 = pci_read_config8(dev, 0x45);
- reg8 &= 0x7f; /* Sub Class Write Protect off */
- pci_write_config8(dev, 0x45, reg8);
- pci_write_config8(dev, 0x0a, 0x01);
- reg8 |= 0x80; /* Sub Class Write Protect on */
- pci_write_config8(dev, 0x45, reg8);
-
-#if defined(DISABLE_SATA) && (DISABLE_SATA == 1)
- printk(BIOS_INFO, "Disabling SATA (Primary Channel)\n");
- /* Disable SATA channels */
- pci_write_config8(dev, 0x40, 0x00);
-#else
- pci_write_config8(dev, 0x40, 0x43);
-#endif
-
- reg8 = pci_read_config8(dev, 0x6a);
- reg8 |= 0x8; /* Mode Select set to Manual Mode */
- reg8 &= ~7;
- reg8 |= 0x2; /* Manual setting to 50 ohm */
-
- pci_write_config8(dev, 0x6a, reg8);
-
- reg8 = pci_read_config8(dev, 0x6b);
- reg8 &= ~7;
- reg8 |= 0x01; /* Autocomp of Termination */
- pci_write_config8(dev, 0x6b, reg8);
-
- /* Enable EIDE (secondary channel) even if SATA disabled */
- reg8 = pci_read_config8(dev, 0xc0);
- reg8 |= 0x1;
- pci_write_config8(dev, 0xc0, reg8);
-
- // Enable bus mastering, memory space acces, io space access
- pci_write_config16(dev, 0x04, 0x0007);
-
- /* Set SATA base ports. */
- pci_write_config32(dev, 0x10, 0x01f1);
- pci_write_config32(dev, 0x14, 0x03f5);
- /* Set EIDE base ports. */
- pci_write_config32(dev, 0x18, 0x0171);
- pci_write_config32(dev, 0x1c, 0x0375);
-
- /* SATA/EIDE Bus Master mode base address */
- pci_write_config32(dev, 0x20, BUS_MASTER_ADDR | 1);
-
- /* Enable read/write prefetch buffers */
- reg8 = pci_read_config8(dev, 0xc1);
- reg8 |= 0x30;
- pci_write_config8(dev, 0xc1, reg8);
-
- /* Set FIFO thresholds like */
- pci_write_config8(dev, 0xc3, 0x1); /* FIFO flushed when 1/2 full */
-
- /* EIDE Sector Size */
- pci_write_config16(dev, 0xe8, 0x200);
-
- /* Some Miscellaneous Control */
- pci_write_config8(dev, 0x44, 0x7);
- pci_write_config8(dev, 0x45, 0xaf);
- pci_write_config8(dev, 0x46, 0x8);
-
- /* EIDE Configuration */
- reg8 = pci_read_config8(dev, 0xc4);
- reg8 |= 0x10;
- pci_write_config8(dev, 0xc4, reg8);
-
- pci_write_config8(dev, 0xc5, 0xc);
-
- /* Interrupt Line */
- reg8 = pci_read_config8(dev, 0x45);
- reg8 &= ~(1 << 4); /* Interrupt Line Write Protect off */
- pci_write_config8(dev, 0x45, reg8);
-
- pci_write_config8(dev, 0x3c, 0x0e); /* Interrupt */
-
- /* Set the drive timing control */
- pci_write_config16(dev, 0x48, 0x5d5d);
-
- /* Enable only compatibility mode. */
- reg8 = pci_read_config8(dev, 0x42);
- reg8 &= ~0xa0;
- pci_write_config8(dev, 0x42, reg8);
- reg8 = pci_read_config8(dev, 0x42);
- printk(BIOS_DEBUG, "Reg 0x42 read back as 0x%x\n", reg8);
-
- /* Support Staggered Spin-Up */
- reg8 = pci_read_config8(dev, 0xb9);
- if ((reg8 & 0x8) == 0) {
- printk(BIOS_DEBUG, "start OOB sequence on both drives\n");
- reg8 |= 0x30;
- pci_write_config8(dev, 0xb9, reg8);
- }
-}
-
-static struct device_operations sata_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = sata_init,
- .enable = 0,
- .ops_pci = 0,
-};
-
-/* When the SATA controller is in IDE mode, the Device ID is 0x5324 */
-static const struct pci_driver northbridge_driver __pci_driver = {
- .ops = &sata_ops,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = 0x5324,
-};
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-
-static void usb_init(struct device *dev)
-{
- u32 reg32;
- u8 reg8;
-
- /* USB Specification says the device must be Bus Master */
- printk(BIOS_DEBUG, "UHCI: Setting up controller.. ");
-
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
-
- reg8 = pci_read_config8(dev, 0xca);
- reg8 |= (1 << 0);
- pci_write_config8(dev, 0xca, reg8);
-
- printk(BIOS_DEBUG, "done.\n");
-}
-
-static struct device_operations usb_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = usb_init,
- .enable = 0,
- .ops_pci = 0,
-};
-
-static const struct pci_driver via_usb_driver __pci_driver = {
- .ops = &usb_ops,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = 0x3038,
-};
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <arch/io.h>
-#include <stdint.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <stdlib.h>
-#include <string.h>
-#include <bitops.h>
-#include <cpu/cpu.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/msr.h>
-#include <arch/interrupt.h>
-#include "cx700_registers.h"
-#include "chip.h"
-#include "northbridge.h"
-
-/* PCI Domain 1 Device 0 Function 0 */
-
-#define SR_INDEX 0x3c4
-#define SR_DATA 0x3c5
-#define CRTM_INDEX 0x3b4
-#define CRTM_DATA 0x3b5
-#define CRTC_INDEX 0x3d4
-#define CRTC_DATA 0x3d5
-
-static int via_cx700_int15_handler(struct eregs *regs)
-{
- int res=-1;
- u8 mem_speed;
-
-#define MEMORY_SPEED_66MHZ (0 << 4)
-#define MEMORY_SPEED_100MHZ (1 << 4)
-#define MEMORY_SPEED_133MHZ (1 << 4)
-#define MEMORY_SPEED_200MHZ (3 << 4) // DDR200
-#define MEMORY_SPEED_266MHZ (4 << 4) // DDR266
-#define MEMORY_SPEED_333MHZ (5 << 4) // DDR333
-#define MEMORY_SPEED_400MHZ (6 << 4) // DDR400
-#define MEMORY_SPEED_533MHZ (7 << 4) // DDR533
-#define MEMORY_SPEED_667MHZ (8 << 4) // DDR667
-
- const u8 memory_mapping[6] = {
- MEMORY_SPEED_200MHZ, MEMORY_SPEED_266MHZ,
- MEMORY_SPEED_333MHZ, MEMORY_SPEED_400MHZ,
- MEMORY_SPEED_533MHZ, MEMORY_SPEED_667MHZ
- };
-
- printk(BIOS_DEBUG, "via_cx700_int15_handler\n");
-
- switch(regs->eax & 0xffff) {
- case 0x5f00: /* VGA POST Initialization Signal */
- regs->eax = (regs->eax & 0xffff0000 ) | 0x5f;
- res = 0;
- break;
-
- case 0x5f01: /* Software Panel Type Configuration */
- regs->eax = (regs->eax & 0xffff0000 ) | 0x5f;
- // panel type = 2 = 1024 * 768
- regs->ecx = (regs->ecx & 0xffffff00 ) | 2;
- res = 0;
- break;
-
- case 0x5f27: /* Boot Device Selection */
- regs->eax = (regs->eax & 0xffff0000 ) | 0x5f;
-
- regs->ebx = 0x00000000; // 0 -> default
- regs->ecx = 0x00000000; // 0 -> default
- // TV Layout - default
- regs->edx = (regs->edx & 0xffffff00) | 0;
- res=0;
- break;
-
- case 0x5f0b: /* Get Expansion Setting */
- regs->eax = (regs->eax & 0xffff0000 ) | 0x5f;
-
- regs->ecx = regs->ecx & 0xffffff00; // non-expansion
- // regs->ecx = regs->ecx & 0xffffff00 | 1; // expansion
- res=0;
- break;
-
- case 0x5f0f: /* VGA Post Completion */
- regs->eax = (regs->eax & 0xffff0000 ) | 0x5f;
- res=0;
- break;
-
- case 0x5f18:
- regs->eax = (regs->eax & 0xffff0000 ) | 0x5f;
-#define UMA_SIZE_8MB (3 << 0)
-#define UMA_SIZE_16MB (4 << 0)
-#define UMA_SIZE_32MB (5 << 0)
-
- regs->ebx = (regs->ebx & 0xffff0000 ) | MEMORY_SPEED_533MHZ | UMA_SIZE_32MB;
-
- mem_speed = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 4)), SCRATCH_DRAM_FREQ);
- if (mem_speed > 5)
- mem_speed = 5;
-
- regs->ebx |= memory_mapping[mem_speed];
-
- res=0;
- break;
-
- default:
- printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
- regs->eax & 0xffff);
- break;
- }
- return res;
-}
-
-#ifdef UNUSED_CODE
-static void write_protect_vgabios(void)
-{
- device_t dev;
-
- printk(BIOS_DEBUG, "write_protect_vgabios\n");
-
- dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3324, 0);
- if (dev)
- pci_write_config8(dev, 0x80, 0xff);
-
- dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x7324, 0);
- if (dev)
- pci_write_config8(dev, 0x61, 0xff);
-}
-#endif
-
-static void vga_enable_console(void)
-{
- /* Call VGA BIOS int10 function 0x4f14 to enable main console
- * Epia-M does not always autosense the main console so forcing
- * it on is good.
- */
-
- /* int#, EAX, EBX, ECX, EDX, ESI, EDI */
- realmode_interrupt(0x10, 0x4f14, 0x8003, 0x0001, 0x0000, 0x0000, 0x0000);
-}
-
-static void vga_init(device_t dev)
-{
- u8 reg8;
-
- mainboard_interrupt_handlers(0x15, &via_cx700_int15_handler);
-
- //*
- pci_write_config8(dev, 0x04, 0x07);
- pci_write_config8(dev, 0x3e, 0x02);
- pci_write_config8(dev, 0x0d, 0x40);
- pci_write_config32(dev, 0x10, 0xa0000008);
- pci_write_config32(dev, 0x14, 0xdd000000);
- pci_write_config8(dev, 0x3c, 0x0b);
- //*/
-
- printk(BIOS_DEBUG, "Initializing VGA...\n");
-
- pci_dev_init(dev);
-
- if (pci_read_config32(dev, PCI_ROM_ADDRESS) != 0xc0000) return;
-
- printk(BIOS_DEBUG, "Enable VGA console\n");
- vga_enable_console();
-
- /* It's not clear if these need to be programmed before or after
- * the VGA bios runs. Try both, clean up later */
- /* Set memory rate to 200MHz */
- outb(0x3d, CRTM_INDEX);
- reg8 = inb(CRTM_DATA);
- reg8 &= 0x0f;
- reg8 |= (0x3 << 4);
- outb(0x3d, CRTM_INDEX);
- outb(reg8, CRTM_DATA);
-
- /* Set framebuffer size to 32mb */
- reg8 = (32 / 4);
- outb(0x39, SR_INDEX);
- outb(reg8, SR_DATA);
-}
-
-static struct device_operations vga_operations = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = vga_init,
- .ops_pci = 0,
-};
-
-static const struct pci_driver vga_driver __pci_driver = {
- .ops = &vga_operations,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = 0x3157,
-};
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * Enable the serial devices on the VIA CX700
+ */
+
+#include <arch/romcc_io.h>
+
+static void cx700_writepnpaddr(u8 val)
+{
+ outb(val, 0x2e);
+ outb(val, 0xeb);
+}
+
+static void cx700_writepnpdata(u8 val)
+{
+ outb(val, 0x2f);
+ outb(val, 0xeb);
+}
+
+static void cx700_writesiobyte(u16 reg, u8 val)
+{
+ outb(val, reg);
+}
+
+static void cx700_writesioword(u16 reg, u16 val)
+{
+ outw(val, reg);
+}
+
+static void enable_cx700_serial(void)
+{
+ outb(6, 0x80);
+
+ // WTH?
+ outb(0x03, 0x22);
+
+ // Set UART1 I/O Base Address
+ pci_write_config8(PCI_DEV(0, 17, 0), 0xb4, 0x7e);
+
+ // UART1 Enable
+ pci_write_config8(PCI_DEV(0, 17, 0), 0xb0, 0x10);
+
+ // turn on pnp
+ cx700_writepnpaddr(0x87);
+ cx700_writepnpaddr(0x87);
+ // now go ahead and set up com1.
+ // set address
+ cx700_writepnpaddr(0x7);
+ cx700_writepnpdata(0x2);
+ // enable serial out
+ cx700_writepnpaddr(0x30);
+ cx700_writepnpdata(0x1);
+ // serial port 1 base address (FEh)
+ cx700_writepnpaddr(0x60);
+ cx700_writepnpdata(0xfe);
+ // serial port 1 IRQ (04h)
+ cx700_writepnpaddr(0x70);
+ cx700_writepnpdata(0x4);
+ // serial port 1 control
+ cx700_writepnpaddr(0xf0);
+ cx700_writepnpdata(0x2);
+ // turn of pnp
+ cx700_writepnpaddr(0xaa);
+
+ // XXX This part should be fully taken care of by
+ // src/pc80/serial.c:uart_init
+
+ // set up reg to set baud rate.
+ cx700_writesiobyte(0x3fb, 0x80);
+ // Set 115 kb
+ cx700_writesioword(0x3f8, 1);
+ // Set 9.6 kb
+ // cx700_writesioword(0x3f8, 12)
+ // now set no parity, one stop, 8 bits
+ cx700_writesiobyte(0x3fb, 3);
+ // now turn on RTS, DRT
+ cx700_writesiobyte(0x3fc, 3);
+ // Enable interrupts
+ cx700_writesiobyte(0x3f9, 0xf);
+ // should be done. Dump a char for fun.
+ cx700_writesiobyte(0x3f8, 48);
+
+ outb(7, 0x80);
+}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// other bioses use this, too:
+#define SMBUS_IO_BASE 0x0500
+
+#define SMBHSTSTAT SMBUS_IO_BASE + 0x0
+#define SMBSLVSTAT SMBUS_IO_BASE + 0x1
+#define SMBHSTCTL SMBUS_IO_BASE + 0x2
+#define SMBHSTCMD SMBUS_IO_BASE + 0x3
+#define SMBXMITADD SMBUS_IO_BASE + 0x4
+#define SMBHSTDAT0 SMBUS_IO_BASE + 0x5
+#define SMBHSTDAT1 SMBUS_IO_BASE + 0x6
+
+#define SMBBLKDAT SMBUS_IO_BASE + 0x7
+#define SMBSLVCTL SMBUS_IO_BASE + 0x8
+#define SMBTRNSADD SMBUS_IO_BASE + 0x9
+#define SMBSLVDATA SMBUS_IO_BASE + 0xa
+#define SMLINK_PIN_CTL SMBUS_IO_BASE + 0xe
+#define SMBUS_PIN_CTL SMBUS_IO_BASE + 0xf
+
+/* Define register settings */
+#define HOST_RESET 0xff
+#define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ
+
+#define SMBUS_TIMEOUT (100*1000*10)
+
+#define I2C_TRANS_CMD 0x40
+#define CLOCK_SLAVE_ADDRESS 0x69
+
+#define SMBUS_DELAY() outb(0x80, 0x80)
+
+/* Debugging macros. */
+#if CONFIG_DEBUG_SMBUS
+#define PRINT_DEBUG(x) print_debug(x)
+#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x)
+#else
+#define PRINT_DEBUG(x)
+#define PRINT_DEBUG_HEX16(x)
+#endif
+
+/* Internal functions */
+#if CONFIG_DEBUG_SMBUS
+static void smbus_print_error(unsigned char host_status_register, int loops)
+{
+ /* Check if there actually was an error */
+ if (host_status_register == 0x00 || host_status_register == 0x40 ||
+ host_status_register == 0x42)
+ return;
+ print_err("SMBus Error: ");
+ print_err_hex8(host_status_register);
+
+ print_err("\n");
+ if (loops >= SMBUS_TIMEOUT) {
+ print_err("SMBus Timout\n");
+ }
+ if (host_status_register & (1 << 4)) {
+ print_err("Interrup/SMI# was Failed Bus Transaction\n");
+ }
+ if (host_status_register & (1 << 3)) {
+ print_err("Bus Error\n");
+ }
+ if (host_status_register & (1 << 2)) {
+ print_err("Device Error\n");
+ }
+ if (host_status_register & (1 << 1)) {
+ /* This isn't a real error... */
+ print_debug("Interrupt/SMI# was Successful Completion\n");
+ }
+ if (host_status_register & (1 << 0)) {
+ print_err("Host Busy\n");
+ }
+}
+#endif
+
+static void smbus_wait_until_ready(void)
+{
+ int loops;
+
+ loops = 0;
+
+ /* Yes, this is a mess, but it's the easiest way to do it */
+ while (((inb(SMBHSTSTAT) & 1) == 1) && (loops <= SMBUS_TIMEOUT)) {
+ SMBUS_DELAY();
+ ++loops;
+ }
+#if CONFIG_DEBUG_SMBUS
+ /* Some systems seem to have a flakey SMBus. No need to spew a lot of
+ * errors on those, once we know that SMBus access is principally
+ * working.
+ */
+ smbus_print_error(inb(SMBHSTSTAT), loops);
+#endif
+}
+
+static void smbus_reset(void)
+{
+ outb(HOST_RESET, SMBHSTSTAT);
+}
+
+/* Public functions */
+static void set_ics_data(unsigned char dev, int data, char len)
+{
+ //int i;
+ smbus_reset();
+ /* clear host data port */
+ outb(0x00, SMBHSTDAT0);
+ SMBUS_DELAY();
+ smbus_wait_until_ready();
+
+ /* read to reset block transfer counter */
+ inb(SMBHSTCTL);
+
+ /* fill blocktransfer array */
+ if (dev == 0xd2) {
+ //char d2_data[] = {0x0d,0x00,0x3f,0xcd,0x7f,0xbf,0x1a,0x2a,0x01,0x0f,0x0b,0x00,0x8d,0x9b};
+ outb(0x0d, SMBBLKDAT);
+ outb(0x00, SMBBLKDAT);
+ outb(0x3f, SMBBLKDAT);
+ outb(0xcd, SMBBLKDAT);
+ outb(0x7f, SMBBLKDAT);
+ outb(0xbf, SMBBLKDAT);
+ outb(0x1a, SMBBLKDAT);
+ outb(0x2a, SMBBLKDAT);
+ outb(0x01, SMBBLKDAT);
+ outb(0x0f, SMBBLKDAT);
+ outb(0x0b, SMBBLKDAT);
+ outb(0x80, SMBBLKDAT);
+ outb(0x8d, SMBBLKDAT);
+ outb(0x9b, SMBBLKDAT);
+ } else {
+ //char d4_data[] = {0x08,0xff,0x3f,0x00,0x00,0xff,0xff,0xff,0xff};
+ outb(0x08, SMBBLKDAT);
+ outb(0xff, SMBBLKDAT);
+ outb(0x3f, SMBBLKDAT);
+ outb(0x00, SMBBLKDAT);
+ outb(0x00, SMBBLKDAT);
+ outb(0xff, SMBBLKDAT);
+ outb(0xff, SMBBLKDAT);
+ outb(0xff, SMBBLKDAT);
+ outb(0xff, SMBBLKDAT);
+ }
+
+ //for (i=0; i < len; i++)
+ // outb(data[i],SMBBLKDAT);
+
+ outb(dev, SMBXMITADD);
+ outb(0, SMBHSTCMD);
+ outb(len, SMBHSTDAT0);
+ outb(0x74, SMBHSTCTL);
+
+ SMBUS_DELAY();
+
+ smbus_wait_until_ready();
+
+ smbus_reset();
+
+}
+
+static unsigned int get_spd_data(const struct mem_controller *ctrl, unsigned int dimm,
+ unsigned int offset)
+{
+ unsigned int val, addr;
+
+ smbus_reset();
+
+ /* clear host data port */
+ outb(0x00, SMBHSTDAT0);
+ SMBUS_DELAY();
+ smbus_wait_until_ready();
+
+ /* Fetch the SMBus address of the SPD ROM from
+ * the ctrl struct in romstage.c in case they are at
+ * non-standard positions.
+ * SMBus Address shifted by 1
+ */
+ addr = (ctrl->channel0[dimm]) << 1;
+
+ outb(addr | 0x1, SMBXMITADD);
+ outb(offset, SMBHSTCMD);
+ outb(0x48, SMBHSTCTL);
+
+ SMBUS_DELAY();
+
+ smbus_wait_until_ready();
+
+ val = inb(SMBHSTDAT0);
+ smbus_reset();
+ return val;
+}
+
+static void enable_smbus(void)
+{
+ device_t dev;
+
+ /* The CX700 ISA Bridge (0x1106, 0x8324) is hardcoded to this location,
+ * no need to probe.
+ */
+ dev = PCI_DEV(0, 17, 0);
+
+ /* SMBus Clock Select: Divider fof 14.318MHz */
+ pci_write_config8(dev, 0x94, 0x20);
+
+ /* SMBus I/O Base, enable SMBus */
+ pci_write_config16(dev, 0xd0, SMBUS_IO_BASE | 1);
+
+ /* SMBus Clock from 128K Source, Enable SMBus Host Controller */
+ pci_write_config8(dev, 0xd2, 0x05);
+
+ /* Enable I/O decoding */
+ pci_write_config16(dev, 0x04, 0x0003);
+
+ /* Setup clock chips */
+ set_ics_data(0xd2, 0, 14);
+ set_ics_data(0xd4, 0, 9);
+}
+
+/* Debugging Function */
+#if CONFIG_DEBUG_SMBUS
+static void dump_spd_data(const struct mem_controller *ctrl)
+{
+ int dimm, offset, regs;
+ unsigned int val;
+
+ for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) {
+ print_debug("SPD Data for DIMM ");
+ print_debug_hex8(dimm);
+ print_debug("\n");
+
+ val = get_spd_data(ctrl, dimm, 0);
+ if (val == 0xff) {
+ regs = 256;
+ } else if (val == 0x80) {
+ regs = 128;
+ } else {
+ print_debug("No DIMM present\n");
+ regs = 0;
+ }
+ for (offset = 0; offset < regs; offset++) {
+ print_debug(" Offset ");
+ print_debug_hex8(offset);
+ print_debug(" = 0x");
+ print_debug_hex8(get_spd_data(ctrl, dimm, offset));
+ print_debug("\n");
+ }
+ }
+}
+#else
+#define dump_spd_data(ctrl)
+#endif
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include <pc80/mc146818rtc.h>
+#include <pc80/i8259.h>
+#include <pc80/keyboard.h>
+#include <pc80/isa-dma.h>
+#include <cpu/x86/lapic.h>
+#include <arch/ioapic.h>
+#include <stdlib.h>
+
+#define ACPI_IO_BASE 0x400
+#define HPET_ADDR 0xfe800000UL
+
+static const unsigned char pci_irqs[4] = { 11, 11, 10, 10 };
+
+static const unsigned char usb_pins[4] = { 'A', 'B', 'C', 'D' };
+static const unsigned char vga_pins[4] = { 'A', 'B', 'C', 'D' };
+static const unsigned char slot_pins[4] = { 'B', 'C', 'D', 'A' };
+static const unsigned char ac97_pins[4] = { 'B', 'C', 'D', 'A' };
+
+static unsigned char *pin_to_irq(const unsigned char *pin)
+{
+ static unsigned char irqs[4];
+ int i;
+ for (i = 0; i < 4; i++)
+ irqs[i] = pci_irqs[pin[i] - 'A'];
+
+ return irqs;
+}
+
+static void pci_routing_fixup(struct device *dev)
+{
+ printk(BIOS_DEBUG, "%s: device is %p\n", __FUNCTION__, dev);
+
+ /* set up PCI IRQ routing */
+ pci_write_config8(dev, 0x55, pci_irqs[0] << 4);
+ pci_write_config8(dev, 0x56, pci_irqs[1] | (pci_irqs[2] << 4));
+ pci_write_config8(dev, 0x57, pci_irqs[3] << 4);
+
+ /* Assigning IRQs */
+ printk(BIOS_DEBUG, "Setting up USB interrupts.\n");
+ pci_assign_irqs(0, 0x10, pin_to_irq(usb_pins));
+
+ printk(BIOS_DEBUG, "Setting up VGA interrupts.\n");
+ pci_assign_irqs(1, 0x00, pin_to_irq(vga_pins));
+
+ printk(BIOS_DEBUG, "Setting up PCI slot interrupts.\n");
+ pci_assign_irqs(2, 0x04, pin_to_irq(slot_pins));
+ // more?
+
+ printk(BIOS_DEBUG, "Setting up AC97 interrupts.\n");
+ pci_assign_irqs(0x80, 0x1, pin_to_irq(ac97_pins));
+}
+
+/*
+ * Set up the power management capabilities directly into ACPI mode. This
+ * avoids having to handle any System Management Interrupts (SMI's) which I
+ * can't figure out how to do !!!!
+ */
+
+static void setup_pm(device_t dev)
+{
+ /* Debounce LID and PWRBTN# Inputs for 16ms. */
+ pci_write_config8(dev, 0x80, 0x20);
+
+ /* Set ACPI base address to IO ACPI_IO_BASE */
+ pci_write_config16(dev, 0x88, ACPI_IO_BASE | 1);
+
+ /* set ACPI irq to 9 */
+ pci_write_config8(dev, 0x82, 0x49);
+
+ /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */
+ pci_write_config16(dev, 0x84, 0x609a);
+
+ /* SMI output level to low, 7.5us throttle clock */
+ pci_write_config8(dev, 0x8d, 0x18);
+
+ /* GP Timer Control 1s */
+ pci_write_config8(dev, 0x93, 0x88);
+
+ /* Power Well */
+ pci_write_config8(dev, 0x94, 0x20); // 0x20??
+
+ /* 7 = stp to sust delay 1msec
+ * 6 = SUSST# Deasserted Before PWRGD for STD
+ */
+ pci_write_config8(dev, 0x95, 0xc0); // 0xc1??
+
+ /* Disable GP2 & GP3 Timer */
+ pci_write_config8(dev, 0x98, 0);
+
+ /* GP2 Timer Counter */
+ pci_write_config8(dev, 0x99, 0xfb);
+ /* GP3 Timer Counter */
+ //pci_write_config8(dev, 0x9a, 0x20);
+
+ /* Multi Function Select 1 */
+ pci_write_config8(dev, 0xe4, 0x00);
+
+ /* Multi Function Select 2 */
+ pci_write_config8(dev, 0xe5, 0x41); //??
+
+ /* Enable ACPI access (and setup like award) */
+ pci_write_config8(dev, 0x81, 0x84);
+
+ /* Clear status events. */
+ outw(0xffff, ACPI_IO_BASE + 0x00);
+ outw(0xffff, ACPI_IO_BASE + 0x20);
+ outw(0xffff, ACPI_IO_BASE + 0x28);
+ outl(0xffffffff, ACPI_IO_BASE + 0x30);
+
+ /* Disable SCI on GPIO. */
+ outw(0x0, ACPI_IO_BASE + 0x22);
+
+ /* Disable SMI on GPIO. */
+ outw(0x0, ACPI_IO_BASE + 0x24);
+
+ /* Disable all global enable SMIs. */
+ outw(0x0, ACPI_IO_BASE + 0x2a);
+
+ /* All SMI off, both IDE buses ON, PSON rising edge. */
+ outw(0x0, ACPI_IO_BASE + 0x2c);
+
+ /* Primary activity SMI disable. */
+ outl(0x0, ACPI_IO_BASE + 0x34);
+
+ /* GP timer reload on none. */
+ outl(0x0, ACPI_IO_BASE + 0x38);
+
+ /* Disable extended IO traps. */
+ outb(0x0, ACPI_IO_BASE + 0x42);
+
+ /* SCI is generated for RTC/pwrBtn/slpBtn. */
+ outw(0x0001, ACPI_IO_BASE + 0x04);
+
+ /* Allow SLP# signal to assert LDTSTOP_L.
+ * Will work for C3 and for FID/VID change.
+ */
+ outb(0x1, ACPI_IO_BASE + 0x11);
+}
+
+static void cx700_set_lpc_registers(struct device *dev)
+{
+ unsigned char enables;
+
+ printk(BIOS_DEBUG, "VIA CX700 LPC bridge init\n");
+
+ // enable the internal I/O decode
+ enables = pci_read_config8(dev, 0x6C);
+ enables |= 0x80;
+ pci_write_config8(dev, 0x6C, enables);
+
+ // Map 4MB of FLASH into the address space
+// pci_write_config8(dev, 0x41, 0x7f);
+
+ // Set bit 6 of 0x40, because Award does it (IO recovery time)
+ // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
+ // interrupts can be properly marked as level triggered.
+ enables = pci_read_config8(dev, 0x40);
+ enables |= 0x44;
+ pci_write_config8(dev, 0x40, enables);
+
+ /* DMA Line buffer control */
+ enables = pci_read_config8(dev, 0x42);
+ enables |= 0xf0;
+ pci_write_config8(dev, 0x42, enables);
+
+ /* I/O recovery time */
+ pci_write_config8(dev, 0x4c, 0x44);
+
+ /* ROM memory cycles go to LPC. */
+ pci_write_config8(dev, 0x59, 0x80);
+
+ /* Enable SM dynamic clock gating */
+ pci_write_config8(dev, 0x5b, 0x01);
+
+ /* Set Read Pass Write Control Enable */
+ pci_write_config8(dev, 0x48, 0x0c);
+
+ /* Set SM Misc Control: Enable Internal APIC . */
+ enables = pci_read_config8(dev, 0x58);
+ enables |= 1 << 6;
+ pci_write_config8(dev, 0x58, enables);
+ enables = pci_read_config8(dev, 0x4d);
+ enables |= 1 << 3;
+ pci_write_config8(dev, 0x4d, enables);
+
+ /* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */
+ enables = pci_read_config8(dev, 0x4f);
+ enables |= 0x08;
+ pci_write_config8(dev, 0x4f, enables);
+
+ /* enable KBC configuration */
+ pci_write_config8(dev, 0x51, 0x1f);
+
+ /* enable serial irq */
+ pci_write_config8(dev, 0x52, 0x9);
+
+ /* dma */
+ pci_write_config8(dev, 0x53, 0x00);
+
+ // Power management setup
+ setup_pm(dev);
+
+ /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
+ pci_write_config8(dev, 0x40, 0x54);
+
+ /* Enable HPET timer */
+ pci_write_config32(dev, 0x68, (1 << 31) | (HPET_ADDR >> 8));
+
+}
+
+static void cx700_read_resources(device_t dev)
+{
+ struct resource *res;
+
+ /* Make sure we call our childrens set/enable functions - these
+ * are not called unless this device has a resource to set.
+ */
+
+ pci_dev_read_resources(dev);
+
+ res = new_resource(dev, 1);
+ res->base = 0x0UL;
+ res->size = 0x400UL;
+ res->limit = 0xffffUL;
+ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+ res = new_resource(dev, 3); /* IOAPIC */
+ res->base = IO_APIC_ADDR;
+ res->size = 0x00001000;
+ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+static void cx700_set_resources(device_t dev)
+{
+ struct resource *resource;
+ resource = find_resource(dev, 1);
+ resource->flags |= IORESOURCE_STORED;
+ pci_dev_set_resources(dev);
+}
+
+static void cx700_enable_resources(device_t dev)
+{
+ /* Enable SuperIO decoding */
+ pci_dev_enable_resources(dev);
+}
+
+static void cx700_lpc_init(struct device *dev)
+{
+ cx700_set_lpc_registers(dev);
+
+#if CONFIG_IOAPIC
+#define IO_APIC_ID 2
+ setup_ioapic(IO_APIC_ADDR, IO_APIC_ID);
+#endif
+
+ /* Initialize interrupts */
+ pci_routing_fixup(dev);
+ /* make sure interupt controller is configured before keyboard init */
+ setup_i8259();
+
+ /* Start the Real Time Clock */
+ rtc_init(0);
+
+ /* Initialize isa dma */
+ isa_dma_init();
+
+ /* Initialize keyboard controller */
+ pc_keyboard_init(0);
+}
+
+static struct device_operations cx700_lpc_ops = {
+ .read_resources = cx700_read_resources,
+ .set_resources = cx700_set_resources,
+ .enable_resources = cx700_enable_resources,
+ .init = &cx700_lpc_init,
+ .scan_bus = scan_static_bus,
+};
+
+static const struct pci_driver lpc_driver __pci_driver = {
+ .ops = &cx700_lpc_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = 0x8324,
+};
#include <spd.h>
#include <spd_ddr2.h>
#include <delay.h>
-#include "cx700_registers.h"
+#include "registers.h"
/* Debugging macros. */
#if CONFIG_DEBUG_RAM_SETUP
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* CX700 has 48 bytes of scratch registers in D0F4 starting at Reg. 0xd0 */
+#define SCRATCH_REG_BASE 0xd0
+#define SCRATCH_RANK_0 0xd0
+#define SCRATCH_RANK_1 0xd1
+#define SCRATCH_RANK_2 0xd2
+#define SCRATCH_RANK_3 0xd3
+#define SCRATCH_DIMM_NUM 0xd4
+#define SCRATCH_RANK_NUM 0xd5
+#define SCRATCH_RANK_MAP 0xd6
+#define SCRATCH_DRAM_FREQ 0xd7
+#define SCRATCH_DRAM_NB_ODT 0xd8
+#define SCRATCH_RANK0_SIZE_REG 0xe0 /* RxE0~RxE3 */
+#define SCRATCH_RANK0_MA_REG 0xe4 /* RxE4~RxE7 */
+#define SCRATCH_CHA_DQSI_LOW_REG 0xe8
+#define SCRATCH_CHA_DQSI_HIGH_REG 0xe9
+#define SCRATCH_ChA_DQSI_REG 0xea
+#define SCRATCH_DRAM_256M_BIT 0xee
+#define SCRATCH_FLAGS 0xef
+
+#define DDRII_666 0x5
+#define DDRII_533 0x4
+#define DDRII_400 0x3
+#define DDRII_333 0x2
+#define DDRII_266 0x1
+#define DDRII_200 0x0
+
+
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <reset.h>
+
+void hard_reset(void)
+{
+ outb((1 << 2) | (1 << 1), 0xcf9);
+}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+/* IDE specific bits */
+#define IDE_MODE_REG 0x09
+#define IDE0_NATIVE_MODE (1 << 0)
+#define IDE1_NATIVE_MODE (1 << 2)
+
+/* These are default addresses */
+#define IDE0_DATA_ADDR 0x1f0
+#define IDE0_CONTROL_ADDR 0x3f4
+#define IDE1_DATA_ADDR 0x170
+#define IDE1_CONTROL_ADDR 0x370
+
+#define BUS_MASTER_ADDR 0xfc00
+
+#define CHANNEL_ENABLE_REG 0x40
+#define ENABLE_IDE0 (1 << 0)
+#define ENABLE_IDE1 (1 << 1)
+
+/* TODO: better user configuration */
+#define DISABLE_SATA 0
+
+static void sata_init(struct device *dev)
+{
+ u8 reg8;
+
+ printk(BIOS_DEBUG, "Configuring VIA SATA & EIDE Controller\n");
+
+ /* Class IDE Disk, instead of RAID controller */
+ reg8 = pci_read_config8(dev, 0x45);
+ reg8 &= 0x7f; /* Sub Class Write Protect off */
+ pci_write_config8(dev, 0x45, reg8);
+ pci_write_config8(dev, 0x0a, 0x01);
+ reg8 |= 0x80; /* Sub Class Write Protect on */
+ pci_write_config8(dev, 0x45, reg8);
+
+#if defined(DISABLE_SATA) && (DISABLE_SATA == 1)
+ printk(BIOS_INFO, "Disabling SATA (Primary Channel)\n");
+ /* Disable SATA channels */
+ pci_write_config8(dev, 0x40, 0x00);
+#else
+ pci_write_config8(dev, 0x40, 0x43);
+#endif
+
+ reg8 = pci_read_config8(dev, 0x6a);
+ reg8 |= 0x8; /* Mode Select set to Manual Mode */
+ reg8 &= ~7;
+ reg8 |= 0x2; /* Manual setting to 50 ohm */
+
+ pci_write_config8(dev, 0x6a, reg8);
+
+ reg8 = pci_read_config8(dev, 0x6b);
+ reg8 &= ~7;
+ reg8 |= 0x01; /* Autocomp of Termination */
+ pci_write_config8(dev, 0x6b, reg8);
+
+ /* Enable EIDE (secondary channel) even if SATA disabled */
+ reg8 = pci_read_config8(dev, 0xc0);
+ reg8 |= 0x1;
+ pci_write_config8(dev, 0xc0, reg8);
+
+ // Enable bus mastering, memory space acces, io space access
+ pci_write_config16(dev, 0x04, 0x0007);
+
+ /* Set SATA base ports. */
+ pci_write_config32(dev, 0x10, 0x01f1);
+ pci_write_config32(dev, 0x14, 0x03f5);
+ /* Set EIDE base ports. */
+ pci_write_config32(dev, 0x18, 0x0171);
+ pci_write_config32(dev, 0x1c, 0x0375);
+
+ /* SATA/EIDE Bus Master mode base address */
+ pci_write_config32(dev, 0x20, BUS_MASTER_ADDR | 1);
+
+ /* Enable read/write prefetch buffers */
+ reg8 = pci_read_config8(dev, 0xc1);
+ reg8 |= 0x30;
+ pci_write_config8(dev, 0xc1, reg8);
+
+ /* Set FIFO thresholds like */
+ pci_write_config8(dev, 0xc3, 0x1); /* FIFO flushed when 1/2 full */
+
+ /* EIDE Sector Size */
+ pci_write_config16(dev, 0xe8, 0x200);
+
+ /* Some Miscellaneous Control */
+ pci_write_config8(dev, 0x44, 0x7);
+ pci_write_config8(dev, 0x45, 0xaf);
+ pci_write_config8(dev, 0x46, 0x8);
+
+ /* EIDE Configuration */
+ reg8 = pci_read_config8(dev, 0xc4);
+ reg8 |= 0x10;
+ pci_write_config8(dev, 0xc4, reg8);
+
+ pci_write_config8(dev, 0xc5, 0xc);
+
+ /* Interrupt Line */
+ reg8 = pci_read_config8(dev, 0x45);
+ reg8 &= ~(1 << 4); /* Interrupt Line Write Protect off */
+ pci_write_config8(dev, 0x45, reg8);
+
+ pci_write_config8(dev, 0x3c, 0x0e); /* Interrupt */
+
+ /* Set the drive timing control */
+ pci_write_config16(dev, 0x48, 0x5d5d);
+
+ /* Enable only compatibility mode. */
+ reg8 = pci_read_config8(dev, 0x42);
+ reg8 &= ~0xa0;
+ pci_write_config8(dev, 0x42, reg8);
+ reg8 = pci_read_config8(dev, 0x42);
+ printk(BIOS_DEBUG, "Reg 0x42 read back as 0x%x\n", reg8);
+
+ /* Support Staggered Spin-Up */
+ reg8 = pci_read_config8(dev, 0xb9);
+ if ((reg8 & 0x8) == 0) {
+ printk(BIOS_DEBUG, "start OOB sequence on both drives\n");
+ reg8 |= 0x30;
+ pci_write_config8(dev, 0xb9, reg8);
+ }
+}
+
+static struct device_operations sata_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = sata_init,
+ .enable = 0,
+ .ops_pci = 0,
+};
+
+/* When the SATA controller is in IDE mode, the Device ID is 0x5324 */
+static const struct pci_driver northbridge_driver __pci_driver = {
+ .ops = &sata_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = 0x5324,
+};
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+static void usb_init(struct device *dev)
+{
+ u32 reg32;
+ u8 reg8;
+
+ /* USB Specification says the device must be Bus Master */
+ printk(BIOS_DEBUG, "UHCI: Setting up controller.. ");
+
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
+
+ reg8 = pci_read_config8(dev, 0xca);
+ reg8 |= (1 << 0);
+ pci_write_config8(dev, 0xca, reg8);
+
+ printk(BIOS_DEBUG, "done.\n");
+}
+
+static struct device_operations usb_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = usb_init,
+ .enable = 0,
+ .ops_pci = 0,
+};
+
+static const struct pci_driver via_usb_driver __pci_driver = {
+ .ops = &usb_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = 0x3038,
+};
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <stdlib.h>
+#include <string.h>
+#include <bitops.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <arch/interrupt.h>
+#include "registers.h"
+#include "chip.h"
+#include "northbridge.h"
+
+/* PCI Domain 1 Device 0 Function 0 */
+
+#define SR_INDEX 0x3c4
+#define SR_DATA 0x3c5
+#define CRTM_INDEX 0x3b4
+#define CRTM_DATA 0x3b5
+#define CRTC_INDEX 0x3d4
+#define CRTC_DATA 0x3d5
+
+static int via_cx700_int15_handler(struct eregs *regs)
+{
+ int res=-1;
+ u8 mem_speed;
+
+#define MEMORY_SPEED_66MHZ (0 << 4)
+#define MEMORY_SPEED_100MHZ (1 << 4)
+#define MEMORY_SPEED_133MHZ (1 << 4)
+#define MEMORY_SPEED_200MHZ (3 << 4) // DDR200
+#define MEMORY_SPEED_266MHZ (4 << 4) // DDR266
+#define MEMORY_SPEED_333MHZ (5 << 4) // DDR333
+#define MEMORY_SPEED_400MHZ (6 << 4) // DDR400
+#define MEMORY_SPEED_533MHZ (7 << 4) // DDR533
+#define MEMORY_SPEED_667MHZ (8 << 4) // DDR667
+
+ const u8 memory_mapping[6] = {
+ MEMORY_SPEED_200MHZ, MEMORY_SPEED_266MHZ,
+ MEMORY_SPEED_333MHZ, MEMORY_SPEED_400MHZ,
+ MEMORY_SPEED_533MHZ, MEMORY_SPEED_667MHZ
+ };
+
+ printk(BIOS_DEBUG, "via_cx700_int15_handler\n");
+
+ switch(regs->eax & 0xffff) {
+ case 0x5f00: /* VGA POST Initialization Signal */
+ regs->eax = (regs->eax & 0xffff0000 ) | 0x5f;
+ res = 0;
+ break;
+
+ case 0x5f01: /* Software Panel Type Configuration */
+ regs->eax = (regs->eax & 0xffff0000 ) | 0x5f;
+ // panel type = 2 = 1024 * 768
+ regs->ecx = (regs->ecx & 0xffffff00 ) | 2;
+ res = 0;
+ break;
+
+ case 0x5f27: /* Boot Device Selection */
+ regs->eax = (regs->eax & 0xffff0000 ) | 0x5f;
+
+ regs->ebx = 0x00000000; // 0 -> default
+ regs->ecx = 0x00000000; // 0 -> default
+ // TV Layout - default
+ regs->edx = (regs->edx & 0xffffff00) | 0;
+ res=0;
+ break;
+
+ case 0x5f0b: /* Get Expansion Setting */
+ regs->eax = (regs->eax & 0xffff0000 ) | 0x5f;
+
+ regs->ecx = regs->ecx & 0xffffff00; // non-expansion
+ // regs->ecx = regs->ecx & 0xffffff00 | 1; // expansion
+ res=0;
+ break;
+
+ case 0x5f0f: /* VGA Post Completion */
+ regs->eax = (regs->eax & 0xffff0000 ) | 0x5f;
+ res=0;
+ break;
+
+ case 0x5f18:
+ regs->eax = (regs->eax & 0xffff0000 ) | 0x5f;
+#define UMA_SIZE_8MB (3 << 0)
+#define UMA_SIZE_16MB (4 << 0)
+#define UMA_SIZE_32MB (5 << 0)
+
+ regs->ebx = (regs->ebx & 0xffff0000 ) | MEMORY_SPEED_533MHZ | UMA_SIZE_32MB;
+
+ mem_speed = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 4)), SCRATCH_DRAM_FREQ);
+ if (mem_speed > 5)
+ mem_speed = 5;
+
+ regs->ebx |= memory_mapping[mem_speed];
+
+ res=0;
+ break;
+
+ default:
+ printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
+ regs->eax & 0xffff);
+ break;
+ }
+ return res;
+}
+
+#ifdef UNUSED_CODE
+static void write_protect_vgabios(void)
+{
+ device_t dev;
+
+ printk(BIOS_DEBUG, "write_protect_vgabios\n");
+
+ dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3324, 0);
+ if (dev)
+ pci_write_config8(dev, 0x80, 0xff);
+
+ dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x7324, 0);
+ if (dev)
+ pci_write_config8(dev, 0x61, 0xff);
+}
+#endif
+
+static void vga_enable_console(void)
+{
+ /* Call VGA BIOS int10 function 0x4f14 to enable main console
+ * Epia-M does not always autosense the main console so forcing
+ * it on is good.
+ */
+
+ /* int#, EAX, EBX, ECX, EDX, ESI, EDI */
+ realmode_interrupt(0x10, 0x4f14, 0x8003, 0x0001, 0x0000, 0x0000, 0x0000);
+}
+
+static void vga_init(device_t dev)
+{
+ u8 reg8;
+
+ mainboard_interrupt_handlers(0x15, &via_cx700_int15_handler);
+
+ //*
+ pci_write_config8(dev, 0x04, 0x07);
+ pci_write_config8(dev, 0x3e, 0x02);
+ pci_write_config8(dev, 0x0d, 0x40);
+ pci_write_config32(dev, 0x10, 0xa0000008);
+ pci_write_config32(dev, 0x14, 0xdd000000);
+ pci_write_config8(dev, 0x3c, 0x0b);
+ //*/
+
+ printk(BIOS_DEBUG, "Initializing VGA...\n");
+
+ pci_dev_init(dev);
+
+ if (pci_read_config32(dev, PCI_ROM_ADDRESS) != 0xc0000) return;
+
+ printk(BIOS_DEBUG, "Enable VGA console\n");
+ vga_enable_console();
+
+ /* It's not clear if these need to be programmed before or after
+ * the VGA bios runs. Try both, clean up later */
+ /* Set memory rate to 200MHz */
+ outb(0x3d, CRTM_INDEX);
+ reg8 = inb(CRTM_DATA);
+ reg8 &= 0x0f;
+ reg8 |= (0x3 << 4);
+ outb(0x3d, CRTM_INDEX);
+ outb(reg8, CRTM_DATA);
+
+ /* Set framebuffer size to 32mb */
+ reg8 = (32 / 4);
+ outb(0x39, SR_INDEX);
+ outb(reg8, SR_DATA);
+}
+
+static struct device_operations vga_operations = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = vga_init,
+ .ops_pci = 0,
+};
+
+static const struct pci_driver vga_driver __pci_driver = {
+ .ops = &vga_operations,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = 0x3157,
+};
driver-y += northbridge.c
driver-y += vga.c
-driver-y += vx800_lpc.c
-driver-y += vx800_ide.c
+driver-y += lpc.c
+driver-y += ide.c
chipset_bootblock_inc += $(src)/northbridge/via/vx800/romstrap.inc
chipset_bootblock_lds += $(src)/northbridge/via/vx800/romstrap.lds
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 One Laptop per Child, Association, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+/*
+ * Enable the serial devices on the VIA
+ */
+#include <arch/romcc_io.h>
+
+/* The base address is 0x15c, 0x2e, depending on config bytes */
+
+#define SIO_BASE 0x3f0
+#define SIO_DATA SIO_BASE+1
+
+static void vx800_writepnpaddr(uint8_t val)
+{
+ outb(val, 0x2e);
+ outb(val, 0xeb);
+}
+
+static void vx800_writepnpdata(uint8_t val)
+{
+ outb(val, 0x2f);
+ outb(val, 0xeb);
+}
+
+static void vx800_writesiobyte(uint16_t reg, uint8_t val)
+{
+ outb(val, reg);
+}
+
+static void vx800_writesioword(uint16_t reg, uint16_t val)
+{
+ outw(val, reg);
+}
+
+/* regs we use: 85, and the southbridge devfn is defined by the
+ mainboard
+ */
+
+void enable_vx800_serial(void)
+{
+ outb(6, 0x80);
+ outb(0x03, 0x22);
+
+ //pci_write_config8(PCI_DEV(0,17,0),0xb4,0x7e);
+ //pci_write_config8(PCI_DEV(0,17,0),0xb0,0x10);
+
+ // turn on pnp
+ vx800_writepnpaddr(0x87);
+ vx800_writepnpaddr(0x87);
+ // now go ahead and set up com1.
+ // set address
+ vx800_writepnpaddr(0x7);
+ vx800_writepnpdata(0x2);
+ // enable serial out
+ vx800_writepnpaddr(0x30);
+ vx800_writepnpdata(0x1);
+ // serial port 1 base address (FEh)
+ vx800_writepnpaddr(0x60);
+ vx800_writepnpdata(0xfe);
+ // serial port 1 IRQ (04h)
+ vx800_writepnpaddr(0x70);
+ vx800_writepnpdata(0x4);
+ // serial port 1 control
+ vx800_writepnpaddr(0xf0);
+ vx800_writepnpdata(0x2);
+ // turn of pnp
+ vx800_writepnpaddr(0xaa);
+
+ // set up reg to set baud rate.
+ vx800_writesiobyte(0x3fb, 0x80);
+ // Set 115 kb
+ vx800_writesioword(0x3f8, 1);
+ // Set 9.6 kb
+ // WRITESIOWORD(0x3f8, 12)
+ // now set no parity, one stop, 8 bits
+ vx800_writesiobyte(0x3fb, 3);
+ // now turn on RTS, DRT
+ vx800_writesiobyte(0x3fc, 3);
+ // Enable interrupts
+ vx800_writesiobyte(0x3f9, 0xf);
+ // should be done. Dump a char for fun.
+ vx800_writesiobyte(0x3f8, 48);
+ outb(7, 0x80);
+}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 One Laptop per Child, Association, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/pci_ids.h>
+#include "vx800.h"
+
+#define SMBUS_IO_BASE 0x0500 //from award bios
+#define PMIO_BASE VX800_ACPI_IO_BASE //might as well set this while we're here
+
+#define SMBHSTSTAT SMBUS_IO_BASE + 0x0
+#define SMBSLVSTAT SMBUS_IO_BASE + 0x1
+#define SMBHSTCTL SMBUS_IO_BASE + 0x2
+#define SMBHSTCMD SMBUS_IO_BASE + 0x3
+#define SMBXMITADD SMBUS_IO_BASE + 0x4
+#define SMBHSTDAT0 SMBUS_IO_BASE + 0x5
+#define SMBHSTDAT1 SMBUS_IO_BASE + 0x6
+/* Rest of these aren't currently used... */
+#define SMBBLKDAT SMBUS_IO_BASE + 0x7
+#define SMBSLVCTL SMBUS_IO_BASE + 0x8
+#define SMBTRNSADD SMBUS_IO_BASE + 0x9
+#define SMBSLVDATA SMBUS_IO_BASE + 0xa
+#define SMLINK_PIN_CTL SMBUS_IO_BASE + 0xe
+#define SMBUS_PIN_CTL SMBUS_IO_BASE + 0xf
+
+/* Define register settings */
+#define HOST_RESET 0xff
+#define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ
+
+#define SMBUS_TIMEOUT (100*1000*10)
+
+#define I2C_TRANS_CMD 0x40
+#define CLOCK_SLAVE_ADDRESS 0x69
+
+#define SMBUS_DELAY() outb(0x80, 0x80)
+
+#ifdef CONFIG_DEBUG_SMBUS
+#define PRINT_DEBUG(x) print_debug(x)
+#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x)
+#else
+#define PRINT_DEBUG(x)
+#define PRINT_DEBUG_HEX16(x)
+#endif
+
+/* Internal functions */
+static void smbus_print_error(unsigned char host_status_register, int loops)
+{
+// print_err("some i2c error\n");
+ /* Check if there actually was an error */
+ if (host_status_register == 0x00 || host_status_register == 0x40 ||
+ host_status_register == 0x42)
+ return;
+ print_err("smbus_error: ");
+ print_err_hex8(host_status_register);
+ print_err("\n");
+ if (loops >= SMBUS_TIMEOUT) {
+ print_err("SMBus Timout\n");
+ }
+ if (host_status_register & (1 << 4)) {
+ print_err("Interrup/SMI# was Failed Bus Transaction\n");
+ }
+ if (host_status_register & (1 << 3)) {
+ print_err("Bus Error\n");
+ }
+ if (host_status_register & (1 << 2)) {
+ print_err("Device Error\n");
+ }
+ if (host_status_register & (1 << 1)) {
+ /* This isn't a real error... */
+ print_debug("Interrupt/SMI# was Successful Completion\n");
+ }
+ if (host_status_register & (1 << 0)) {
+ print_err("Host Busy\n");
+ }
+}
+
+static void smbus_wait_until_ready(void)
+{
+ int loops;
+
+ loops = 0;
+ /* Yes, this is a mess, but it's the easiest way to do it */
+ while (((inb(SMBHSTSTAT) & 1) == 1) && (loops <= SMBUS_TIMEOUT)) {
+ SMBUS_DELAY();
+ ++loops;
+ }
+ smbus_print_error(inb(SMBHSTSTAT), loops);
+}
+
+static void smbus_reset(void)
+{
+ outb(HOST_RESET, SMBHSTSTAT);
+}
+
+/* Public functions */
+
+static unsigned int get_spd_data(unsigned int dimm, unsigned int offset)
+{
+ unsigned int val;
+
+ smbus_reset();
+ /* clear host data port */
+ outb(0x00, SMBHSTDAT0);
+ SMBUS_DELAY();
+ smbus_wait_until_ready();
+
+ /* Do some mathmatic magic */
+ dimm = (DIMM0 + dimm) << 1;
+
+ outb(dimm | 0x1, SMBXMITADD);
+ outb(offset, SMBHSTCMD);
+ outb(0x48, SMBHSTCTL);
+
+ SMBUS_DELAY();
+
+ smbus_wait_until_ready();
+
+ val = inb(SMBHSTDAT0);
+ smbus_reset();
+ return val;
+}
+
+void enable_smbus(void)
+{
+ device_t dev;
+
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_LPC), 0);
+
+ if (dev == PCI_DEV_INVALID) {
+ /* This won't display text if enable_smbus() is before serial init */
+ die("Power Managment Controller not found\n");
+ }
+
+ /* Set clock source */
+ pci_write_config8(dev, 0x94, 0x20);
+
+ /* Write SMBus IO base to 0xd0, and enable SMBus */
+ pci_write_config16(dev, 0xd0, SMBUS_IO_BASE | 1);
+
+ /* Set to Award value */
+ pci_write_config8(dev, 0xd2, 0x05);
+
+ /* Make it work for I/O ... */
+ pci_write_config16(dev, 0x04, 0x0003);
+
+ smbus_reset();
+ /* clear host data port */
+ outb(0x00, SMBHSTDAT0);
+ SMBUS_DELAY();
+ smbus_wait_until_ready();
+}
+
+/**
+ * A fixup for some systems that need time for the SMBus to "warm up". This is
+ * needed on some VT823x based systems, where the SMBus spurts out bad data for
+ * a short time after power on. This has been seen on the VIA Epia series and
+ * Jetway J7F2-series. It reads the ID byte from SMBus, looking for
+ * known-good data from a slot/address. Exits on either good data or a timeout.
+ *
+ * TODO: This should probably go into some global file, but one would need to
+ * be created just for it. If some other chip needs/wants it, we can
+ * worry about it then.
+ *
+ * @param mem_ctrl The memory controller and SMBus addresses.
+ */
+void smbus_fixup(const struct mem_controller *mem_ctrl)
+{
+ int i, ram_slots, current_slot = 0;
+ u8 result = 0;
+
+ ram_slots = ARRAY_SIZE(mem_ctrl->channel0);
+ if (!ram_slots) {
+ print_err("smbus_fixup() thinks there are no RAM slots!\n");
+ return;
+ }
+
+ PRINT_DEBUG("Waiting for SMBus to warm up");
+
+ /*
+ * Bad SPD data should be either 0 or 0xff, but YMMV. So we look for
+ * the ID bytes of SDRAM, DDR, DDR2, and DDR3 (and anything in between).
+ * VT8237R has only been seen on DDR and DDR2 based systems, so far.
+ */
+ for (i = 0; (i < SMBUS_TIMEOUT && ((result < SPD_MEMORY_TYPE_SDRAM) ||
+ (result >
+ SPD_MEMORY_TYPE_SDRAM_DDR3)));
+ i++) {
+
+ if (current_slot > ram_slots)
+ current_slot = 0;
+
+ result = get_spd_data(mem_ctrl->channel0[current_slot],
+ SPD_MEMORY_TYPE);
+ current_slot++;
+ PRINT_DEBUG(".");
+ }
+
+ if (i >= SMBUS_TIMEOUT)
+ print_err("SMBus timed out while warming up\n");
+ else
+ PRINT_DEBUG("Done\n");
+}
+
+/* Debugging Function */
+#if CONFIG_DEBUG_SMBUS
+static void dump_spd_data(void)
+{
+ int dimm, offset, regs;
+ unsigned int val;
+
+ for (dimm = 0; dimm < 8; dimm++) {
+ print_debug("SPD Data for DIMM ");
+ print_debug_hex8(dimm);
+ print_debug("\n");
+
+ val = get_spd_data(dimm, 0);
+ if (val == 0xff) {
+ regs = 256;
+ } else if (val == 0x80) {
+ regs = 128;
+ } else {
+ print_debug("No DIMM present\n");
+ regs = 0;
+ }
+ for (offset = 0; offset < regs; offset++) {
+ print_debug(" Offset ");
+ print_debug_hex8(offset);
+ print_debug(" = 0x");
+ print_debug_hex8(get_spd_data(dimm, offset));
+ print_debug("\n");
+ }
+ }
+}
+#else
+#define dump_spd_data()
+#endif
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 One Laptop per Child, Association, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+#include "chip.h"
+#include <arch/io.h>
+#include "vx800.h"
+
+static const u8 idedevicepcitable[16 * 12] = {
+ /*
+ 0x02, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00,
+ 0x00, 0x00, 0xA8, 0xA8, 0xF0, 0x00, 0x00, 0xB6,
+ 0x00, 0x00, 0x01, 0x21, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4,
+ 0x00, 0xC2, 0xF9, 0x01, 0x10, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ */
+
+ 0x02, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00,
+ 0x00, 0x00, 0x99, 0x20, 0xf0, 0x00, 0x00, 0x20,
+ 0x00, 0x00, 0x17, 0xF1, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4,
+ 0x00, 0xc2, 0x09, 0x01, 0x10, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+ /* Legacy BIOS XP PCI value */
+ /*
+ 0x02, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00,
+ 0x00, 0x00, 0xa8, 0x20, 0x00, 0x00, 0x00, 0xb6,
+ 0x00, 0x00, 0x16, 0xF1, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4,
+ 0x00, 0x02, 0x09, 0x00, 0x18, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ */
+
+ /* ROM legacy BIOS on cn_8562b */
+ /*
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00,
+ 0x00, 0x00, 0x99, 0x20, 0x60, 0x00, 0x00, 0x20,
+ 0x00, 0x00, 0x1E, 0xF1, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4,
+ 0x00, 0x02, 0x09, 0x01, 0x18, 0x0C, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ */
+
+ /* From legacy BIOS on c7_8562b */
+ /*
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00,
+ 0x00, 0x00, 0x5E, 0x20, 0x60, 0x00, 0x00, 0xB6,
+ 0x00, 0x00, 0x1E, 0xF1, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4,
+ 0x00, 0x02, 0x09, 0x01, 0x18, 0x0C, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ */
+};
+
+static void ide_init(struct device *dev)
+{
+ u8 i, data;
+ printk(BIOS_INFO, "ide_init\n");
+
+ /* these 3 lines help to keep interl back door for DID VID SUBID untouched */
+ u16 data16_1, data16_2;
+ data16_1 = pci_read_config16(dev, 0xba);
+ data16_2 = pci_read_config16(dev, 0xbe);
+
+ for (i = 0; i < (16 * 12); i++) {
+ pci_write_config8(dev, 0x40 + i, idedevicepcitable[i]);
+ }
+ //pci_write_config8(dev, 0x0d, 0x20);
+ data = pci_read_config8(dev, 0x0d);
+ data &= 0x0f;
+ data |= 0x40;
+ pci_write_config8(dev, 0x0d, data);
+
+ //these 2 lines help to keep interl back door for DID VID SUBID untouched
+ pci_write_config16(dev, 0xba, data16_1);
+ pci_write_config16(dev, 0xbe, data16_2);
+
+ /* Force interrupts to use compat mode. */
+ pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0);
+ pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff);
+#if 0
+
+ struct southbridge_via_vt8237r_config *sb =
+ (struct southbridge_via_vt8237r_config *)dev->chip_info;
+
+ u8 enables;
+ u32 cablesel;
+
+ pci_write_config16(dev, 0x04, 0x0007);
+
+ enables = pci_read_config8(dev, IDE_CS) & ~0x3;
+ enables |= 0x02;
+ pci_write_config8(dev, IDE_CS, enables);
+ enables = pci_read_config8(dev, IDE_CS);
+ printk(BIOS_DEBUG, "Enables in reg 0x40 read back as 0x%x\n", enables);
+
+ /* Enable only compatibility mode. */
+ enables = pci_read_config8(dev, IDE_CONF_II);
+ enables &= ~0xc0;
+ pci_write_config8(dev, IDE_CONF_II, enables);
+ enables = pci_read_config8(dev, IDE_CONF_II);
+ printk(BIOS_DEBUG, "Enables in reg 0x42 read back as 0x%x\n", enables);
+
+ /* Enable prefetch buffers. */
+ enables = pci_read_config8(dev, IDE_CONF_I);
+ enables |= 0xf0;
+ pci_write_config8(dev, IDE_CONF_I, enables);
+
+ /* Flush FIFOs at half. */
+ enables = pci_read_config8(dev, IDE_CONF_FIFO);
+ enables &= 0xf0;
+ enables |= (1 << 2) | (1 << 0);
+ pci_write_config8(dev, IDE_CONF_FIFO, enables);
+
+ /* PIO read prefetch counter, Bus Master IDE Status Reg. Read Retry. */
+ enables = pci_read_config8(dev, IDE_MISC_I);
+ enables &= 0xe2;
+ enables |= (1 << 4) | (1 << 3);
+ pci_write_config8(dev, IDE_MISC_I, enables);
+
+ /* Use memory read multiple, Memory-Write-and-Invalidate. */
+ enables = pci_read_config8(dev, IDE_MISC_II);
+ enables |= (1 << 2) | (1 << 3);
+ pci_write_config8(dev, IDE_MISC_II, enables);
+
+ /* Force interrupts to use compat mode. */
+ pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0);
+ pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff);
+
+ /* Cable guy... */
+ cablesel = pci_read_config32(dev, IDE_UDMA);
+ cablesel &= ~((1 << 28) | (1 << 20) | (1 << 12) | (1 << 4));
+ cablesel |= (sb->ide0_80pin_cable << 28) |
+ (sb->ide0_80pin_cable << 20) |
+ (sb->ide1_80pin_cable << 12) | (sb->ide1_80pin_cable << 4);
+ pci_write_config32(dev, IDE_UDMA, cablesel);
+#endif
+}
+
+static struct device_operations ide_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = ide_init,
+ .enable = 0,
+ .ops_pci = 0,
+};
+
+static const struct pci_driver via_ide_driver __pci_driver = {
+ .ops = &ide_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_VX855_IDE,
+};
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 One Laptop per Child, Association, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+
+#include <pc80/mc146818rtc.h>
+#include <pc80/keyboard.h>
+#include <pc80/i8259.h>
+#include "vx800.h"
+#include "chip.h"
+
+static const unsigned char pciIrqs[4] = { 0xa, 0x9, 0xb, 0xa };
+
+static const unsigned char vgaPins[4] = { 'A', 'B', 'C', 'D' }; //only INTA
+
+static const unsigned char slotPins[4] = { 'A', 'A', 'A', 'A' }; //all 4
+
+static const unsigned char usbdevicePins[4] = { 'A', 'B', 'C', 'D' }; //only INTA
+static const unsigned char sdioPins[4] = { 'A', 'B', 'C', 'D' }; //only INTA
+static const unsigned char sd_ms_ctrl_Pins[4] = { 'B', 'C', 'D', 'A' }; //only INTA
+static const unsigned char ce_ata_nf_ctrl_Pins[4] = { 'C', 'C', 'D', 'A' }; //only INTA
+static const unsigned char idePins[4] = { 'B', 'C', 'D', 'A' }; //only INTA
+
+static const unsigned char usbPins[4] = { 'A', 'B', 'C', 'D' }; //all 4
+
+static const unsigned char hdacaudioPins[4] = { 'B', 'C', 'D', 'A' }; //only INTA
+
+static unsigned char *pin_to_irq(const unsigned char *pin)
+{
+ static unsigned char Irqs[4];
+ int i;
+ for (i = 0; i < 4; i++)
+ Irqs[i] = pciIrqs[pin[i] - 'A'];
+
+ return Irqs;
+}
+
+static void pci_routing_fixup(struct device *dev)
+{
+ printk(BIOS_INFO, "%s: dev is %p\n", __FUNCTION__, dev);
+
+ /* set up PCI IRQ routing */
+ pci_write_config8(dev, 0x55, pciIrqs[0] << 4);
+ pci_write_config8(dev, 0x56, pciIrqs[1] | (pciIrqs[2] << 4));
+ pci_write_config8(dev, 0x57, pciIrqs[3] << 4);
+
+ /* VGA */
+ printk(BIOS_INFO, "setting vga\n");
+ pci_assign_irqs(0, 0x1, pin_to_irq(vgaPins));
+
+ /* PCI slot */
+ printk(BIOS_INFO, "setting pci slot\n");
+ pci_assign_irqs(0, 0x08, pin_to_irq(slotPins));
+
+ /* PCI slot */
+ printk(BIOS_INFO, "setting USB Device Controller\n");
+ pci_assign_irqs(0, 0x0b, pin_to_irq(usbdevicePins));
+
+ /* PCI slot */
+ printk(BIOS_INFO, "setting SDIO Controller\n");
+ pci_assign_irqs(0, 0x0c, pin_to_irq(sdioPins));
+
+ /* PCI slot */
+ printk(BIOS_INFO, "setting SD $ MS Controller\n");
+ pci_assign_irqs(0, 0x0d, pin_to_irq(sd_ms_ctrl_Pins));
+
+ /* PCI slot */
+ printk(BIOS_INFO, "setting CE-ATA NF Controller(Card Boot)\n");
+ pci_assign_irqs(0, 0x0e, pin_to_irq(ce_ata_nf_ctrl_Pins));
+
+ /* PCI slot */
+ printk(BIOS_INFO, "setting ide\n");
+ //pci_assign_irqs(0, 0x0f, pin_to_irq(idePins));
+
+ /* Standard usb components */
+ printk(BIOS_INFO, "setting usb1-2\n");
+// pci_assign_irqs(0, 0x10, pin_to_irq(usbPins));
+
+ /* sound hardware */
+ printk(BIOS_INFO, "setting hdac audio\n");
+ pci_assign_irqs(0, 0x14, pin_to_irq(hdacaudioPins));
+
+ printk(BIOS_SPEW, "%s: DONE\n", __FUNCTION__);
+}
+
+static void setup_pm(device_t dev)
+{
+ u16 tmp;
+ /* Debounce LID and PWRBTN# Inputs for 16ms. */
+ pci_write_config8(dev, 0x80, 0x20);
+
+ /* Set ACPI base address to IO VX800_ACPI_IO_BASE */
+ pci_write_config16(dev, 0x88, VX800_ACPI_IO_BASE | 1);
+
+ /* set ACPI irq to 9 */
+ pci_write_config8(dev, 0x82, 0x49);
+
+ /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */
+// pci_write_config16(dev, 0x84, 0x30f2);
+ pci_write_config16(dev, 0x84, 0x609a); // 0x609a??
+
+ /* SMI output level to low, 7.5us throttle clock */
+ pci_write_config8(dev, 0x8d, 0x18);
+
+ /* GP Timer Control 1s */
+ pci_write_config8(dev, 0x93, 0x88);
+
+ /* Power Well */
+ pci_write_config8(dev, 0x94, 0x20); // 0x20??
+
+ /* 7 = stp to sust delay 1msec
+ * 6 = SUSST# Deasserted Before PWRGD for STD
+ */
+ pci_write_config8(dev, 0x95, 0xc0); // 0xc1??
+
+ /* Disable GP2 & GP3 Timer */
+ pci_write_config8(dev, 0x98, 0);
+
+ /* GP2 Timer Counter */
+ pci_write_config8(dev, 0x99, 0xfb);
+ /* GP3 Timer Counter */
+ //pci_write_config8(dev, 0x9a, 0x20);
+
+ /* Multi Function Select 1 */
+ pci_write_config8(dev, 0xe4, 0x00);
+ /* Multi Function Select 2 */
+ pci_write_config8(dev, 0xe5, 0x41); //??
+
+ /* Enable ACPI access (and setup like award) */
+ pci_write_config8(dev, 0x81, 0x84);
+
+ /* Clear status events. */
+ outw(0xffff, VX800_ACPI_IO_BASE + 0x00);
+ outw(0xffff, VX800_ACPI_IO_BASE + 0x20);
+ outw(0xffff, VX800_ACPI_IO_BASE + 0x28);
+ outl(0xffffffff, VX800_ACPI_IO_BASE + 0x30);
+
+ /* Disable SCI on GPIO. */
+ outw(0x0, VX800_ACPI_IO_BASE + 0x22);
+
+ /* Disable SMI on GPIO. */
+ outw(0x0, VX800_ACPI_IO_BASE + 0x24);
+
+ /* Disable all global enable SMIs. */
+ outw(0x0, VX800_ACPI_IO_BASE + 0x2a);
+
+ /* All SMI off, both IDE buses ON, PSON rising edge. */
+ outw(0x0, VX800_ACPI_IO_BASE + 0x2c);
+
+ /* Primary activity SMI disable. */
+ outl(0x0, VX800_ACPI_IO_BASE + 0x34);
+
+ /* GP timer reload on none. */
+ outl(0x0, VX800_ACPI_IO_BASE + 0x38);
+
+ /* Disable extended IO traps. */
+ outb(0x0, VX800_ACPI_IO_BASE + 0x42);
+
+ tmp = inw(VX800_ACPI_IO_BASE + 0x04);
+ /* SCI is generated for RTC/pwrBtn/slpBtn. */
+ tmp |= 1;
+ outw(tmp, VX800_ACPI_IO_BASE + 0x04);
+
+ /* Allow SLP# signal to assert LDTSTOP_L.
+ * Will work for C3 and for FID/VID change.
+ */
+ outb(0x1, VX800_ACPI_IO_BASE + 0x11);
+/*
+ outw(0x0, 0x424);
+ outw(0x0, 0x42a);
+ outw(0x1, 0x42c);
+ outl(0x0, 0x434);
+ outl(0x01, 0x438);
+ outb(0x0, 0x442);
+ outl(0xffff7fff, 0x448);
+ outw(0x001, 0x404);
+*/
+}
+
+static void S3_ps2_kb_ms_wakeup(struct device *dev)
+{
+ u8 enables;
+ enables = pci_read_config8(dev, 0x51);
+ enables |= 2;
+ pci_write_config8(dev, 0x51, enables);
+
+ outb(0xe0, 0x2e);
+ outb(0x0b, 0x2f); //if 09,then only support kb wakeup
+
+ outb(0xe1, 0x2e); //set any key scan code can wakeup
+ outb(0x00, 0x2f);
+
+ outb(0xe9, 0x2e); //set any mouse scan code can wakeup
+ outb(0x00, 0x2f);
+
+ enables &= 0xd;
+ pci_write_config8(dev, 0x51, enables);
+
+ outb(inb(VX800_ACPI_IO_BASE + 0x02) | 0x20, VX800_ACPI_IO_BASE + 0x02); //ACPI golabe enable for sci smi trigger
+ outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x204, VX800_ACPI_IO_BASE + 0x22); //ACPI SCI on Internal KBC PME and mouse PME
+
+}
+
+static void S3_usb_wakeup(struct device *dev)
+{
+ outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x4000, VX800_ACPI_IO_BASE + 0x22); //SCI on USB PME
+}
+
+static void S3_lid_wakeup(struct device *dev)
+{
+ outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x800, VX800_ACPI_IO_BASE + 0x22); //SCI on LID PME
+}
+
+/* This looks good enough to work, maybe */
+static void vx800_sb_init(struct device *dev)
+{
+ unsigned char enables;
+
+ // enable the internal I/O decode
+ enables = pci_read_config8(dev, 0x6C);
+ enables |= 0x80;
+ pci_write_config8(dev, 0x6C, enables);
+
+ // Map 4MB of FLASH into the address space
+// pci_write_config8(dev, 0x41, 0x7f);
+
+ // Set bit 6 of 0x40, because Award does it (IO recovery time)
+ // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
+ // interrupts can be properly marked as level triggered.
+ enables = pci_read_config8(dev, 0x40);
+ enables |= 0x44;
+ pci_write_config8(dev, 0x40, enables);
+
+ /* DMA Line buffer control */
+ enables = pci_read_config8(dev, 0x42);
+ enables |= 0xf0;
+ pci_write_config8(dev, 0x42, enables);
+
+ /* I/O recovery time */
+ pci_write_config8(dev, 0x4c, 0x44);
+
+ /* ROM memory cycles go to LPC. */
+ pci_write_config8(dev, 0x59, 0x80);
+
+ /* Set 0x5b to 0x01 to match Award */
+ //pci_write_config8(dev, 0x5b, 0x01);
+ enables = pci_read_config8(dev, 0x5b);
+ enables |= 0x01;
+ pci_write_config8(dev, 0x5b, enables);
+
+ /* Set Read Pass Write Control Enable */
+ pci_write_config8(dev, 0x48, 0x0c);
+
+ /* Set 0x58 to 0x42 APIC and RTC. */
+ //pci_write_config8(dev, 0x58, 0x42); this cmd cause the irq0 can not be triggerd,since bit 5 was set to 0.
+ enables = pci_read_config8(dev, 0x58);
+ enables |= 0x41; //
+ pci_write_config8(dev, 0x58, enables);
+
+ /* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */
+ enables = pci_read_config8(dev, 0x4f);
+ enables |= 0x08;
+ pci_write_config8(dev, 0x4f, enables);
+
+ /* enable serial irq */
+ pci_write_config8(dev, 0x52, 0x9);
+
+ /* dma */
+ pci_write_config8(dev, 0x53, 0x00);
+
+ // Power management setup
+ setup_pm(dev);
+
+ /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
+ pci_write_config8(dev, 0x40, 0x54);
+
+ // Start the rtc
+ rtc_init(0);
+}
+
+/* total kludge to get lxb to call our childrens set/enable functions - these are
+ not called unless this device has a resource to set - so set a dummy one */
+static void vx800_read_resources(device_t dev)
+{
+
+ struct resource *resource;
+ pci_dev_read_resources(dev);
+ resource = new_resource(dev, 1);
+ resource->flags |=
+ IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO |
+ IORESOURCE_STORED;
+ resource->size = 2;
+ resource->base = 0x2e;
+}
+
+static void vx800_set_resources(device_t dev)
+{
+ struct resource *resource;
+ resource = find_resource(dev, 1);
+ resource->flags |= IORESOURCE_STORED;
+ pci_dev_set_resources(dev);
+}
+
+static void southbridge_init(struct device *dev)
+{
+ printk(BIOS_DEBUG, "vx800 sb init\n");
+ vx800_sb_init(dev);
+ pci_routing_fixup(dev);
+
+ setup_i8259(); // make sure interupt controller is configured before keyboard init
+
+ /* turn on keyboard and RTC, no need to visit this reg twice */
+ pc_keyboard_init(0);
+
+ printk(BIOS_DEBUG, "ps2 usb lid, you set who can wakeup system from s3 sleep\n");
+ S3_ps2_kb_ms_wakeup(dev);
+ S3_usb_wakeup(dev);
+ S3_lid_wakeup(dev);
+
+/* enable acpi cpu c3 state. (c2 state need not do anything.)
+ #1
+ fadt->pm2_cnt_blk = 0x22;//to support cpu-c3
+ fadt->p_lvl2_lat = 0x50; //this is the coreboot source
+ fadt->p_lvl3_lat = 0x320;//
+ fadt->pm2_cnt_len = 1;//to support cpu-c3
+ #2
+ ssdt? ->every cpu has a P_BLK address. set it to 0x10 (so that "Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state"---VIA vx800 P SPEC )
+ #3 write 0x17 in to PMIO=VX800_ACPI_IO_BASE + 0x26, following the describtion in the P-spec.
+ 1 enable SLP# asserts in C3 state PMIORx26<1> =1
+ 2 enable CPUSTP# asserts in C3 state; PMIORx26<2> =1
+ 3 CLKRUN# is always asserted PMIORx26<3> =0
+ 4 Disable PCISTP# When CLKRUN# is asserted
+ 1: PCISTP# will not assert When CLKRUN# is asserted
+ PMIORx26<4> =1
+ 5 This bit controls whether the CPU voltage is lowered when in C3/S1 state.
+ VRDSLP will be active in either this bit set in C3 or LVL4 register read
+ PMIORx26<0> =0
+ 6 Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state PMIORx15
+ */
+ outb(0x17, VX800_ACPI_IO_BASE + 0x26);
+
+}
+
+static struct device_operations vx800_lpc_ops = {
+ .read_resources = vx800_read_resources,
+ .set_resources = vx800_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = southbridge_init,
+ .scan_bus = scan_static_bus,
+};
+
+static const struct pci_driver lpc_driver __pci_driver = {
+ .ops = &vx800_lpc_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_VX855_LPC,
+};
#endif
#include "northbridge/via/vx800/translator_ddr2_init.c"
#include "northbridge/via/vx800/dram_init.h"
-#include "northbridge/via/vx800/vx800_early_smbus.c"
-#include "northbridge/via/vx800/vx800_early_serial.c"
+#include "northbridge/via/vx800/early_smbus.c"
+#include "northbridge/via/vx800/early_serial.c"
#include "northbridge/via/vx800/dram_util.h"
#include "northbridge/via/vx800/dram_util.c"
#include "northbridge/via/vx800/detection.c"
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 One Laptop per Child, Association, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-*/
-
-/*
- * Enable the serial devices on the VIA
- */
-#include <arch/romcc_io.h>
-
-/* The base address is 0x15c, 0x2e, depending on config bytes */
-
-#define SIO_BASE 0x3f0
-#define SIO_DATA SIO_BASE+1
-
-static void vx800_writepnpaddr(uint8_t val)
-{
- outb(val, 0x2e);
- outb(val, 0xeb);
-}
-
-static void vx800_writepnpdata(uint8_t val)
-{
- outb(val, 0x2f);
- outb(val, 0xeb);
-}
-
-static void vx800_writesiobyte(uint16_t reg, uint8_t val)
-{
- outb(val, reg);
-}
-
-static void vx800_writesioword(uint16_t reg, uint16_t val)
-{
- outw(val, reg);
-}
-
-/* regs we use: 85, and the southbridge devfn is defined by the
- mainboard
- */
-
-void enable_vx800_serial(void)
-{
- outb(6, 0x80);
- outb(0x03, 0x22);
-
- //pci_write_config8(PCI_DEV(0,17,0),0xb4,0x7e);
- //pci_write_config8(PCI_DEV(0,17,0),0xb0,0x10);
-
- // turn on pnp
- vx800_writepnpaddr(0x87);
- vx800_writepnpaddr(0x87);
- // now go ahead and set up com1.
- // set address
- vx800_writepnpaddr(0x7);
- vx800_writepnpdata(0x2);
- // enable serial out
- vx800_writepnpaddr(0x30);
- vx800_writepnpdata(0x1);
- // serial port 1 base address (FEh)
- vx800_writepnpaddr(0x60);
- vx800_writepnpdata(0xfe);
- // serial port 1 IRQ (04h)
- vx800_writepnpaddr(0x70);
- vx800_writepnpdata(0x4);
- // serial port 1 control
- vx800_writepnpaddr(0xf0);
- vx800_writepnpdata(0x2);
- // turn of pnp
- vx800_writepnpaddr(0xaa);
-
- // set up reg to set baud rate.
- vx800_writesiobyte(0x3fb, 0x80);
- // Set 115 kb
- vx800_writesioword(0x3f8, 1);
- // Set 9.6 kb
- // WRITESIOWORD(0x3f8, 12)
- // now set no parity, one stop, 8 bits
- vx800_writesiobyte(0x3fb, 3);
- // now turn on RTS, DRT
- vx800_writesiobyte(0x3fc, 3);
- // Enable interrupts
- vx800_writesiobyte(0x3f9, 0xf);
- // should be done. Dump a char for fun.
- vx800_writesiobyte(0x3f8, 48);
- outb(7, 0x80);
-}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 One Laptop per Child, Association, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/pci_ids.h>
-#include "vx800.h"
-
-#define SMBUS_IO_BASE 0x0500 //from award bios
-#define PMIO_BASE VX800_ACPI_IO_BASE //might as well set this while we're here
-
-#define SMBHSTSTAT SMBUS_IO_BASE + 0x0
-#define SMBSLVSTAT SMBUS_IO_BASE + 0x1
-#define SMBHSTCTL SMBUS_IO_BASE + 0x2
-#define SMBHSTCMD SMBUS_IO_BASE + 0x3
-#define SMBXMITADD SMBUS_IO_BASE + 0x4
-#define SMBHSTDAT0 SMBUS_IO_BASE + 0x5
-#define SMBHSTDAT1 SMBUS_IO_BASE + 0x6
-/* Rest of these aren't currently used... */
-#define SMBBLKDAT SMBUS_IO_BASE + 0x7
-#define SMBSLVCTL SMBUS_IO_BASE + 0x8
-#define SMBTRNSADD SMBUS_IO_BASE + 0x9
-#define SMBSLVDATA SMBUS_IO_BASE + 0xa
-#define SMLINK_PIN_CTL SMBUS_IO_BASE + 0xe
-#define SMBUS_PIN_CTL SMBUS_IO_BASE + 0xf
-
-/* Define register settings */
-#define HOST_RESET 0xff
-#define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ
-
-#define SMBUS_TIMEOUT (100*1000*10)
-
-#define I2C_TRANS_CMD 0x40
-#define CLOCK_SLAVE_ADDRESS 0x69
-
-#define SMBUS_DELAY() outb(0x80, 0x80)
-
-#ifdef CONFIG_DEBUG_SMBUS
-#define PRINT_DEBUG(x) print_debug(x)
-#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x)
-#else
-#define PRINT_DEBUG(x)
-#define PRINT_DEBUG_HEX16(x)
-#endif
-
-/* Internal functions */
-static void smbus_print_error(unsigned char host_status_register, int loops)
-{
-// print_err("some i2c error\n");
- /* Check if there actually was an error */
- if (host_status_register == 0x00 || host_status_register == 0x40 ||
- host_status_register == 0x42)
- return;
- print_err("smbus_error: ");
- print_err_hex8(host_status_register);
- print_err("\n");
- if (loops >= SMBUS_TIMEOUT) {
- print_err("SMBus Timout\n");
- }
- if (host_status_register & (1 << 4)) {
- print_err("Interrup/SMI# was Failed Bus Transaction\n");
- }
- if (host_status_register & (1 << 3)) {
- print_err("Bus Error\n");
- }
- if (host_status_register & (1 << 2)) {
- print_err("Device Error\n");
- }
- if (host_status_register & (1 << 1)) {
- /* This isn't a real error... */
- print_debug("Interrupt/SMI# was Successful Completion\n");
- }
- if (host_status_register & (1 << 0)) {
- print_err("Host Busy\n");
- }
-}
-
-static void smbus_wait_until_ready(void)
-{
- int loops;
-
- loops = 0;
- /* Yes, this is a mess, but it's the easiest way to do it */
- while (((inb(SMBHSTSTAT) & 1) == 1) && (loops <= SMBUS_TIMEOUT)) {
- SMBUS_DELAY();
- ++loops;
- }
- smbus_print_error(inb(SMBHSTSTAT), loops);
-}
-
-static void smbus_reset(void)
-{
- outb(HOST_RESET, SMBHSTSTAT);
-}
-
-/* Public functions */
-
-static unsigned int get_spd_data(unsigned int dimm, unsigned int offset)
-{
- unsigned int val;
-
- smbus_reset();
- /* clear host data port */
- outb(0x00, SMBHSTDAT0);
- SMBUS_DELAY();
- smbus_wait_until_ready();
-
- /* Do some mathmatic magic */
- dimm = (DIMM0 + dimm) << 1;
-
- outb(dimm | 0x1, SMBXMITADD);
- outb(offset, SMBHSTCMD);
- outb(0x48, SMBHSTCTL);
-
- SMBUS_DELAY();
-
- smbus_wait_until_ready();
-
- val = inb(SMBHSTDAT0);
- smbus_reset();
- return val;
-}
-
-void enable_smbus(void)
-{
- device_t dev;
-
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_LPC), 0);
-
- if (dev == PCI_DEV_INVALID) {
- /* This won't display text if enable_smbus() is before serial init */
- die("Power Managment Controller not found\n");
- }
-
- /* Set clock source */
- pci_write_config8(dev, 0x94, 0x20);
-
- /* Write SMBus IO base to 0xd0, and enable SMBus */
- pci_write_config16(dev, 0xd0, SMBUS_IO_BASE | 1);
-
- /* Set to Award value */
- pci_write_config8(dev, 0xd2, 0x05);
-
- /* Make it work for I/O ... */
- pci_write_config16(dev, 0x04, 0x0003);
-
- smbus_reset();
- /* clear host data port */
- outb(0x00, SMBHSTDAT0);
- SMBUS_DELAY();
- smbus_wait_until_ready();
-}
-
-/**
- * A fixup for some systems that need time for the SMBus to "warm up". This is
- * needed on some VT823x based systems, where the SMBus spurts out bad data for
- * a short time after power on. This has been seen on the VIA Epia series and
- * Jetway J7F2-series. It reads the ID byte from SMBus, looking for
- * known-good data from a slot/address. Exits on either good data or a timeout.
- *
- * TODO: This should probably go into some global file, but one would need to
- * be created just for it. If some other chip needs/wants it, we can
- * worry about it then.
- *
- * @param mem_ctrl The memory controller and SMBus addresses.
- */
-void smbus_fixup(const struct mem_controller *mem_ctrl)
-{
- int i, ram_slots, current_slot = 0;
- u8 result = 0;
-
- ram_slots = ARRAY_SIZE(mem_ctrl->channel0);
- if (!ram_slots) {
- print_err("smbus_fixup() thinks there are no RAM slots!\n");
- return;
- }
-
- PRINT_DEBUG("Waiting for SMBus to warm up");
-
- /*
- * Bad SPD data should be either 0 or 0xff, but YMMV. So we look for
- * the ID bytes of SDRAM, DDR, DDR2, and DDR3 (and anything in between).
- * VT8237R has only been seen on DDR and DDR2 based systems, so far.
- */
- for (i = 0; (i < SMBUS_TIMEOUT && ((result < SPD_MEMORY_TYPE_SDRAM) ||
- (result >
- SPD_MEMORY_TYPE_SDRAM_DDR3)));
- i++) {
-
- if (current_slot > ram_slots)
- current_slot = 0;
-
- result = get_spd_data(mem_ctrl->channel0[current_slot],
- SPD_MEMORY_TYPE);
- current_slot++;
- PRINT_DEBUG(".");
- }
-
- if (i >= SMBUS_TIMEOUT)
- print_err("SMBus timed out while warming up\n");
- else
- PRINT_DEBUG("Done\n");
-}
-
-/* Debugging Function */
-#if CONFIG_DEBUG_SMBUS
-static void dump_spd_data(void)
-{
- int dimm, offset, regs;
- unsigned int val;
-
- for (dimm = 0; dimm < 8; dimm++) {
- print_debug("SPD Data for DIMM ");
- print_debug_hex8(dimm);
- print_debug("\n");
-
- val = get_spd_data(dimm, 0);
- if (val == 0xff) {
- regs = 256;
- } else if (val == 0x80) {
- regs = 128;
- } else {
- print_debug("No DIMM present\n");
- regs = 0;
- }
- for (offset = 0; offset < regs; offset++) {
- print_debug(" Offset ");
- print_debug_hex8(offset);
- print_debug(" = 0x");
- print_debug_hex8(get_spd_data(dimm, offset));
- print_debug("\n");
- }
- }
-}
-#else
-#define dump_spd_data()
-#endif
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 One Laptop per Child, Association, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <device/pci_ids.h>
-#include <console/console.h>
-#include "chip.h"
-#include <arch/io.h>
-#include "vx800.h"
-
-static const u8 idedevicepcitable[16 * 12] = {
- /*
- 0x02, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00,
- 0x00, 0x00, 0xA8, 0xA8, 0xF0, 0x00, 0x00, 0xB6,
- 0x00, 0x00, 0x01, 0x21, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4,
- 0x00, 0xC2, 0xF9, 0x01, 0x10, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- */
-
- 0x02, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00,
- 0x00, 0x00, 0x99, 0x20, 0xf0, 0x00, 0x00, 0x20,
- 0x00, 0x00, 0x17, 0xF1, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4,
- 0x00, 0xc2, 0x09, 0x01, 0x10, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-
- /* Legacy BIOS XP PCI value */
- /*
- 0x02, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00,
- 0x00, 0x00, 0xa8, 0x20, 0x00, 0x00, 0x00, 0xb6,
- 0x00, 0x00, 0x16, 0xF1, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4,
- 0x00, 0x02, 0x09, 0x00, 0x18, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- */
-
- /* ROM legacy BIOS on cn_8562b */
- /*
- 0x03, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00,
- 0x00, 0x00, 0x99, 0x20, 0x60, 0x00, 0x00, 0x20,
- 0x00, 0x00, 0x1E, 0xF1, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4,
- 0x00, 0x02, 0x09, 0x01, 0x18, 0x0C, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- */
-
- /* From legacy BIOS on c7_8562b */
- /*
- 0x03, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00,
- 0x00, 0x00, 0x5E, 0x20, 0x60, 0x00, 0x00, 0xB6,
- 0x00, 0x00, 0x1E, 0xF1, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4,
- 0x00, 0x02, 0x09, 0x01, 0x18, 0x0C, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- */
-};
-
-static void ide_init(struct device *dev)
-{
- u8 i, data;
- printk(BIOS_INFO, "ide_init\n");
-
- /* these 3 lines help to keep interl back door for DID VID SUBID untouched */
- u16 data16_1, data16_2;
- data16_1 = pci_read_config16(dev, 0xba);
- data16_2 = pci_read_config16(dev, 0xbe);
-
- for (i = 0; i < (16 * 12); i++) {
- pci_write_config8(dev, 0x40 + i, idedevicepcitable[i]);
- }
- //pci_write_config8(dev, 0x0d, 0x20);
- data = pci_read_config8(dev, 0x0d);
- data &= 0x0f;
- data |= 0x40;
- pci_write_config8(dev, 0x0d, data);
-
- //these 2 lines help to keep interl back door for DID VID SUBID untouched
- pci_write_config16(dev, 0xba, data16_1);
- pci_write_config16(dev, 0xbe, data16_2);
-
- /* Force interrupts to use compat mode. */
- pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0);
- pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff);
-#if 0
-
- struct southbridge_via_vt8237r_config *sb =
- (struct southbridge_via_vt8237r_config *)dev->chip_info;
-
- u8 enables;
- u32 cablesel;
-
- pci_write_config16(dev, 0x04, 0x0007);
-
- enables = pci_read_config8(dev, IDE_CS) & ~0x3;
- enables |= 0x02;
- pci_write_config8(dev, IDE_CS, enables);
- enables = pci_read_config8(dev, IDE_CS);
- printk(BIOS_DEBUG, "Enables in reg 0x40 read back as 0x%x\n", enables);
-
- /* Enable only compatibility mode. */
- enables = pci_read_config8(dev, IDE_CONF_II);
- enables &= ~0xc0;
- pci_write_config8(dev, IDE_CONF_II, enables);
- enables = pci_read_config8(dev, IDE_CONF_II);
- printk(BIOS_DEBUG, "Enables in reg 0x42 read back as 0x%x\n", enables);
-
- /* Enable prefetch buffers. */
- enables = pci_read_config8(dev, IDE_CONF_I);
- enables |= 0xf0;
- pci_write_config8(dev, IDE_CONF_I, enables);
-
- /* Flush FIFOs at half. */
- enables = pci_read_config8(dev, IDE_CONF_FIFO);
- enables &= 0xf0;
- enables |= (1 << 2) | (1 << 0);
- pci_write_config8(dev, IDE_CONF_FIFO, enables);
-
- /* PIO read prefetch counter, Bus Master IDE Status Reg. Read Retry. */
- enables = pci_read_config8(dev, IDE_MISC_I);
- enables &= 0xe2;
- enables |= (1 << 4) | (1 << 3);
- pci_write_config8(dev, IDE_MISC_I, enables);
-
- /* Use memory read multiple, Memory-Write-and-Invalidate. */
- enables = pci_read_config8(dev, IDE_MISC_II);
- enables |= (1 << 2) | (1 << 3);
- pci_write_config8(dev, IDE_MISC_II, enables);
-
- /* Force interrupts to use compat mode. */
- pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0);
- pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff);
-
- /* Cable guy... */
- cablesel = pci_read_config32(dev, IDE_UDMA);
- cablesel &= ~((1 << 28) | (1 << 20) | (1 << 12) | (1 << 4));
- cablesel |= (sb->ide0_80pin_cable << 28) |
- (sb->ide0_80pin_cable << 20) |
- (sb->ide1_80pin_cable << 12) | (sb->ide1_80pin_cable << 4);
- pci_write_config32(dev, IDE_UDMA, cablesel);
-#endif
-}
-
-static struct device_operations ide_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = ide_init,
- .enable = 0,
- .ops_pci = 0,
-};
-
-static const struct pci_driver via_ide_driver __pci_driver = {
- .ops = &ide_ops,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_VX855_IDE,
-};
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 One Laptop per Child, Association, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <device/pci_ids.h>
-
-#include <pc80/mc146818rtc.h>
-#include <pc80/keyboard.h>
-#include <pc80/i8259.h>
-#include "vx800.h"
-#include "chip.h"
-
-static const unsigned char pciIrqs[4] = { 0xa, 0x9, 0xb, 0xa };
-
-static const unsigned char vgaPins[4] = { 'A', 'B', 'C', 'D' }; //only INTA
-
-static const unsigned char slotPins[4] = { 'A', 'A', 'A', 'A' }; //all 4
-
-static const unsigned char usbdevicePins[4] = { 'A', 'B', 'C', 'D' }; //only INTA
-static const unsigned char sdioPins[4] = { 'A', 'B', 'C', 'D' }; //only INTA
-static const unsigned char sd_ms_ctrl_Pins[4] = { 'B', 'C', 'D', 'A' }; //only INTA
-static const unsigned char ce_ata_nf_ctrl_Pins[4] = { 'C', 'C', 'D', 'A' }; //only INTA
-static const unsigned char idePins[4] = { 'B', 'C', 'D', 'A' }; //only INTA
-
-static const unsigned char usbPins[4] = { 'A', 'B', 'C', 'D' }; //all 4
-
-static const unsigned char hdacaudioPins[4] = { 'B', 'C', 'D', 'A' }; //only INTA
-
-static unsigned char *pin_to_irq(const unsigned char *pin)
-{
- static unsigned char Irqs[4];
- int i;
- for (i = 0; i < 4; i++)
- Irqs[i] = pciIrqs[pin[i] - 'A'];
-
- return Irqs;
-}
-
-static void pci_routing_fixup(struct device *dev)
-{
- printk(BIOS_INFO, "%s: dev is %p\n", __FUNCTION__, dev);
-
- /* set up PCI IRQ routing */
- pci_write_config8(dev, 0x55, pciIrqs[0] << 4);
- pci_write_config8(dev, 0x56, pciIrqs[1] | (pciIrqs[2] << 4));
- pci_write_config8(dev, 0x57, pciIrqs[3] << 4);
-
- /* VGA */
- printk(BIOS_INFO, "setting vga\n");
- pci_assign_irqs(0, 0x1, pin_to_irq(vgaPins));
-
- /* PCI slot */
- printk(BIOS_INFO, "setting pci slot\n");
- pci_assign_irqs(0, 0x08, pin_to_irq(slotPins));
-
- /* PCI slot */
- printk(BIOS_INFO, "setting USB Device Controller\n");
- pci_assign_irqs(0, 0x0b, pin_to_irq(usbdevicePins));
-
- /* PCI slot */
- printk(BIOS_INFO, "setting SDIO Controller\n");
- pci_assign_irqs(0, 0x0c, pin_to_irq(sdioPins));
-
- /* PCI slot */
- printk(BIOS_INFO, "setting SD $ MS Controller\n");
- pci_assign_irqs(0, 0x0d, pin_to_irq(sd_ms_ctrl_Pins));
-
- /* PCI slot */
- printk(BIOS_INFO, "setting CE-ATA NF Controller(Card Boot)\n");
- pci_assign_irqs(0, 0x0e, pin_to_irq(ce_ata_nf_ctrl_Pins));
-
- /* PCI slot */
- printk(BIOS_INFO, "setting ide\n");
- //pci_assign_irqs(0, 0x0f, pin_to_irq(idePins));
-
- /* Standard usb components */
- printk(BIOS_INFO, "setting usb1-2\n");
-// pci_assign_irqs(0, 0x10, pin_to_irq(usbPins));
-
- /* sound hardware */
- printk(BIOS_INFO, "setting hdac audio\n");
- pci_assign_irqs(0, 0x14, pin_to_irq(hdacaudioPins));
-
- printk(BIOS_SPEW, "%s: DONE\n", __FUNCTION__);
-}
-
-static void setup_pm(device_t dev)
-{
- u16 tmp;
- /* Debounce LID and PWRBTN# Inputs for 16ms. */
- pci_write_config8(dev, 0x80, 0x20);
-
- /* Set ACPI base address to IO VX800_ACPI_IO_BASE */
- pci_write_config16(dev, 0x88, VX800_ACPI_IO_BASE | 1);
-
- /* set ACPI irq to 9 */
- pci_write_config8(dev, 0x82, 0x49);
-
- /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */
-// pci_write_config16(dev, 0x84, 0x30f2);
- pci_write_config16(dev, 0x84, 0x609a); // 0x609a??
-
- /* SMI output level to low, 7.5us throttle clock */
- pci_write_config8(dev, 0x8d, 0x18);
-
- /* GP Timer Control 1s */
- pci_write_config8(dev, 0x93, 0x88);
-
- /* Power Well */
- pci_write_config8(dev, 0x94, 0x20); // 0x20??
-
- /* 7 = stp to sust delay 1msec
- * 6 = SUSST# Deasserted Before PWRGD for STD
- */
- pci_write_config8(dev, 0x95, 0xc0); // 0xc1??
-
- /* Disable GP2 & GP3 Timer */
- pci_write_config8(dev, 0x98, 0);
-
- /* GP2 Timer Counter */
- pci_write_config8(dev, 0x99, 0xfb);
- /* GP3 Timer Counter */
- //pci_write_config8(dev, 0x9a, 0x20);
-
- /* Multi Function Select 1 */
- pci_write_config8(dev, 0xe4, 0x00);
- /* Multi Function Select 2 */
- pci_write_config8(dev, 0xe5, 0x41); //??
-
- /* Enable ACPI access (and setup like award) */
- pci_write_config8(dev, 0x81, 0x84);
-
- /* Clear status events. */
- outw(0xffff, VX800_ACPI_IO_BASE + 0x00);
- outw(0xffff, VX800_ACPI_IO_BASE + 0x20);
- outw(0xffff, VX800_ACPI_IO_BASE + 0x28);
- outl(0xffffffff, VX800_ACPI_IO_BASE + 0x30);
-
- /* Disable SCI on GPIO. */
- outw(0x0, VX800_ACPI_IO_BASE + 0x22);
-
- /* Disable SMI on GPIO. */
- outw(0x0, VX800_ACPI_IO_BASE + 0x24);
-
- /* Disable all global enable SMIs. */
- outw(0x0, VX800_ACPI_IO_BASE + 0x2a);
-
- /* All SMI off, both IDE buses ON, PSON rising edge. */
- outw(0x0, VX800_ACPI_IO_BASE + 0x2c);
-
- /* Primary activity SMI disable. */
- outl(0x0, VX800_ACPI_IO_BASE + 0x34);
-
- /* GP timer reload on none. */
- outl(0x0, VX800_ACPI_IO_BASE + 0x38);
-
- /* Disable extended IO traps. */
- outb(0x0, VX800_ACPI_IO_BASE + 0x42);
-
- tmp = inw(VX800_ACPI_IO_BASE + 0x04);
- /* SCI is generated for RTC/pwrBtn/slpBtn. */
- tmp |= 1;
- outw(tmp, VX800_ACPI_IO_BASE + 0x04);
-
- /* Allow SLP# signal to assert LDTSTOP_L.
- * Will work for C3 and for FID/VID change.
- */
- outb(0x1, VX800_ACPI_IO_BASE + 0x11);
-/*
- outw(0x0, 0x424);
- outw(0x0, 0x42a);
- outw(0x1, 0x42c);
- outl(0x0, 0x434);
- outl(0x01, 0x438);
- outb(0x0, 0x442);
- outl(0xffff7fff, 0x448);
- outw(0x001, 0x404);
-*/
-}
-
-static void S3_ps2_kb_ms_wakeup(struct device *dev)
-{
- u8 enables;
- enables = pci_read_config8(dev, 0x51);
- enables |= 2;
- pci_write_config8(dev, 0x51, enables);
-
- outb(0xe0, 0x2e);
- outb(0x0b, 0x2f); //if 09,then only support kb wakeup
-
- outb(0xe1, 0x2e); //set any key scan code can wakeup
- outb(0x00, 0x2f);
-
- outb(0xe9, 0x2e); //set any mouse scan code can wakeup
- outb(0x00, 0x2f);
-
- enables &= 0xd;
- pci_write_config8(dev, 0x51, enables);
-
- outb(inb(VX800_ACPI_IO_BASE + 0x02) | 0x20, VX800_ACPI_IO_BASE + 0x02); //ACPI golabe enable for sci smi trigger
- outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x204, VX800_ACPI_IO_BASE + 0x22); //ACPI SCI on Internal KBC PME and mouse PME
-
-}
-
-static void S3_usb_wakeup(struct device *dev)
-{
- outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x4000, VX800_ACPI_IO_BASE + 0x22); //SCI on USB PME
-}
-
-static void S3_lid_wakeup(struct device *dev)
-{
- outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x800, VX800_ACPI_IO_BASE + 0x22); //SCI on LID PME
-}
-
-/* This looks good enough to work, maybe */
-static void vx800_sb_init(struct device *dev)
-{
- unsigned char enables;
-
- // enable the internal I/O decode
- enables = pci_read_config8(dev, 0x6C);
- enables |= 0x80;
- pci_write_config8(dev, 0x6C, enables);
-
- // Map 4MB of FLASH into the address space
-// pci_write_config8(dev, 0x41, 0x7f);
-
- // Set bit 6 of 0x40, because Award does it (IO recovery time)
- // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
- // interrupts can be properly marked as level triggered.
- enables = pci_read_config8(dev, 0x40);
- enables |= 0x44;
- pci_write_config8(dev, 0x40, enables);
-
- /* DMA Line buffer control */
- enables = pci_read_config8(dev, 0x42);
- enables |= 0xf0;
- pci_write_config8(dev, 0x42, enables);
-
- /* I/O recovery time */
- pci_write_config8(dev, 0x4c, 0x44);
-
- /* ROM memory cycles go to LPC. */
- pci_write_config8(dev, 0x59, 0x80);
-
- /* Set 0x5b to 0x01 to match Award */
- //pci_write_config8(dev, 0x5b, 0x01);
- enables = pci_read_config8(dev, 0x5b);
- enables |= 0x01;
- pci_write_config8(dev, 0x5b, enables);
-
- /* Set Read Pass Write Control Enable */
- pci_write_config8(dev, 0x48, 0x0c);
-
- /* Set 0x58 to 0x42 APIC and RTC. */
- //pci_write_config8(dev, 0x58, 0x42); this cmd cause the irq0 can not be triggerd,since bit 5 was set to 0.
- enables = pci_read_config8(dev, 0x58);
- enables |= 0x41; //
- pci_write_config8(dev, 0x58, enables);
-
- /* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */
- enables = pci_read_config8(dev, 0x4f);
- enables |= 0x08;
- pci_write_config8(dev, 0x4f, enables);
-
- /* enable serial irq */
- pci_write_config8(dev, 0x52, 0x9);
-
- /* dma */
- pci_write_config8(dev, 0x53, 0x00);
-
- // Power management setup
- setup_pm(dev);
-
- /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
- pci_write_config8(dev, 0x40, 0x54);
-
- // Start the rtc
- rtc_init(0);
-}
-
-/* total kludge to get lxb to call our childrens set/enable functions - these are
- not called unless this device has a resource to set - so set a dummy one */
-static void vx800_read_resources(device_t dev)
-{
-
- struct resource *resource;
- pci_dev_read_resources(dev);
- resource = new_resource(dev, 1);
- resource->flags |=
- IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO |
- IORESOURCE_STORED;
- resource->size = 2;
- resource->base = 0x2e;
-}
-
-static void vx800_set_resources(device_t dev)
-{
- struct resource *resource;
- resource = find_resource(dev, 1);
- resource->flags |= IORESOURCE_STORED;
- pci_dev_set_resources(dev);
-}
-
-static void southbridge_init(struct device *dev)
-{
- printk(BIOS_DEBUG, "vx800 sb init\n");
- vx800_sb_init(dev);
- pci_routing_fixup(dev);
-
- setup_i8259(); // make sure interupt controller is configured before keyboard init
-
- /* turn on keyboard and RTC, no need to visit this reg twice */
- pc_keyboard_init(0);
-
- printk(BIOS_DEBUG, "ps2 usb lid, you set who can wakeup system from s3 sleep\n");
- S3_ps2_kb_ms_wakeup(dev);
- S3_usb_wakeup(dev);
- S3_lid_wakeup(dev);
-
-/* enable acpi cpu c3 state. (c2 state need not do anything.)
- #1
- fadt->pm2_cnt_blk = 0x22;//to support cpu-c3
- fadt->p_lvl2_lat = 0x50; //this is the coreboot source
- fadt->p_lvl3_lat = 0x320;//
- fadt->pm2_cnt_len = 1;//to support cpu-c3
- #2
- ssdt? ->every cpu has a P_BLK address. set it to 0x10 (so that "Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state"---VIA vx800 P SPEC )
- #3 write 0x17 in to PMIO=VX800_ACPI_IO_BASE + 0x26, following the describtion in the P-spec.
- 1 enable SLP# asserts in C3 state PMIORx26<1> =1
- 2 enable CPUSTP# asserts in C3 state; PMIORx26<2> =1
- 3 CLKRUN# is always asserted PMIORx26<3> =0
- 4 Disable PCISTP# When CLKRUN# is asserted
- 1: PCISTP# will not assert When CLKRUN# is asserted
- PMIORx26<4> =1
- 5 This bit controls whether the CPU voltage is lowered when in C3/S1 state.
- VRDSLP will be active in either this bit set in C3 or LVL4 register read
- PMIORx26<0> =0
- 6 Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state PMIORx15
- */
- outb(0x17, VX800_ACPI_IO_BASE + 0x26);
-
-}
-
-static struct device_operations vx800_lpc_ops = {
- .read_resources = vx800_read_resources,
- .set_resources = vx800_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = southbridge_init,
- .scan_bus = scan_static_bus,
-};
-
-static const struct pci_driver lpc_driver __pci_driver = {
- .ops = &vx800_lpc_ops,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_VX855_LPC,
-};
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey@slightlyhackish.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Pre-RAM driver for the Fintek F71805F/FG Super I/O chip. */
+
+#include <arch/romcc_io.h>
+#include "f71805f.h"
+
+static void pnp_enter_conf_state(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0x87, port);
+ outb(0x87, port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0xaa, port);
+}
+
+static void f71805f_enable_serial(device_t dev, u16 iobase)
+{
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_conf_state(dev);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Corey Osgood <corey@slightlyhackish.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* Pre-RAM driver for the Fintek F71805F/FG Super I/O chip. */
-
-#include <arch/romcc_io.h>
-#include "f71805f.h"
-
-static void pnp_enter_conf_state(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0x87, port);
- outb(0x87, port);
-}
-
-static void pnp_exit_conf_state(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0xaa, port);
-}
-
-static void f71805f_enable_serial(device_t dev, u16 iobase)
-{
- pnp_enter_conf_state(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
- pnp_exit_conf_state(dev);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Marc Jones <marcj303@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Pre-RAM driver for the Fintek F71859 Super I/O chip. */
+
+#include <arch/romcc_io.h>
+#include "f71859.h"
+
+static void pnp_enter_conf_state(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0x87, port);
+ outb(0x87, port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0xaa, port);
+}
+
+static void f71859_enable_serial(device_t dev, u16 iobase)
+{
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_conf_state(dev);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Marc Jones <marcj303@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* Pre-RAM driver for the Fintek F71859 Super I/O chip. */
-
-#include <arch/romcc_io.h>
-#include "f71859.h"
-
-static void pnp_enter_conf_state(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0x87, port);
- outb(0x87, port);
-}
-
-static void pnp_exit_conf_state(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0xaa, port);
-}
-
-static void f71859_enable_serial(device_t dev, u16 iobase)
-{
- pnp_enter_conf_state(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
- pnp_exit_conf_state(dev);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey@slightlyhackish.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Pre-RAM driver for the Fintek F71863FG Super I/O chip. */
+
+#include <arch/romcc_io.h>
+#include "f71863fg.h"
+
+static void pnp_enter_conf_state(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0x87, port);
+ outb(0x87, port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0xaa, port);
+}
+
+static void f71863fg_enable_serial(device_t dev, u16 iobase)
+{
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_conf_state(dev);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Corey Osgood <corey@slightlyhackish.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* Pre-RAM driver for the Fintek F71863FG Super I/O chip. */
-
-#include <arch/romcc_io.h>
-#include "f71863fg.h"
-
-static void pnp_enter_conf_state(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0x87, port);
- outb(0x87, port);
-}
-
-static void pnp_exit_conf_state(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0xaa, port);
-}
-
-static void f71863fg_enable_serial(device_t dev, u16 iobase)
-{
- pnp_enter_conf_state(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
- pnp_exit_conf_state(dev);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey@slightlyhackish.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Pre-RAM driver for the Fintek F71872F/FG Super I/O chip. */
+
+#include <arch/romcc_io.h>
+#include "f71872.h"
+
+static void pnp_enter_conf_state(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0x87, port);
+ outb(0x87, port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0xaa, port);
+}
+
+static void f71872_enable_serial(device_t dev, u16 iobase)
+{
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_conf_state(dev);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Corey Osgood <corey@slightlyhackish.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* Pre-RAM driver for the Fintek F71872F/FG Super I/O chip. */
-
-#include <arch/romcc_io.h>
-#include "f71872.h"
-
-static void pnp_enter_conf_state(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0x87, port);
- outb(0x87, port);
-}
-
-static void pnp_exit_conf_state(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0xaa, port);
-}
-
-static void f71872_enable_serial(device_t dev, u16 iobase)
-{
- pnp_enter_conf_state(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
- pnp_exit_conf_state(dev);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Alec Ari <neotheuser@ymail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/romcc_io.h>
+#include "f71889.h"
+
+static void pnp_enter_conf_state(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0x87, port);
+ outb(0x87, port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0xaa, port);
+}
+
+static void f71889_enable_serial(device_t dev, u16 iobase)
+{
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_conf_state(dev);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Alec Ari <neotheuser@ymail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdint.h>
-#include <arch/romcc_io.h>
-#include "f71889.h"
-
-static void pnp_enter_conf_state(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0x87, port);
- outb(0x87, port);
-}
-
-static void pnp_exit_conf_state(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0xaa, port);
-}
-
-static void f71889_enable_serial(device_t dev, u16 iobase)
-{
- pnp_enter_conf_state(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
- pnp_exit_conf_state(dev);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "i3100.h"
+
+static void pnp_enter_ext_func_mode(device_t dev)
+{
+ u16 port = dev >> 8;
+
+ outb(0x80, port);
+ outb(0x86, port);
+}
+
+static void pnp_exit_ext_func_mode(device_t dev)
+{
+ u16 port = dev >> 8;
+
+ outb(0x68, port);
+ outb(0x08, port);
+}
+
+/* Enable device interrupts, set UART_CLK predivide. */
+static void i3100_configure_uart_clk(device_t dev, u8 predivide)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_write_config(dev, I3100_SIW_CONFIGURATION, (predivide << 2) | 1);
+ pnp_exit_ext_func_mode(dev);
+}
+
+static void i3100_enable_serial(device_t dev, u16 iobase)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_ext_func_mode(dev);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Arastra, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/romcc_io.h>
-#include "i3100.h"
-
-static void pnp_enter_ext_func_mode(device_t dev)
-{
- u16 port = dev >> 8;
-
- outb(0x80, port);
- outb(0x86, port);
-}
-
-static void pnp_exit_ext_func_mode(device_t dev)
-{
- u16 port = dev >> 8;
-
- outb(0x68, port);
- outb(0x08, port);
-}
-
-/* Enable device interrupts, set UART_CLK predivide. */
-static void i3100_configure_uart_clk(device_t dev, u8 predivide)
-{
- pnp_enter_ext_func_mode(dev);
- pnp_write_config(dev, I3100_SIW_CONFIGURATION, (predivide << 2) | 1);
- pnp_exit_ext_func_mode(dev);
-}
-
-static void i3100_enable_serial(device_t dev, u16 iobase)
-{
- pnp_enter_ext_func_mode(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
- pnp_exit_ext_func_mode(dev);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "it8661f.h"
+
+/* Perform MB PnP setup to put the SIO chip at 0x3f0. */
+/* Base address 0x3f0: 0x86 0x80 0x55 0x55. */
+/* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */
+/* Base address 0x370: 0x86 0x80 0xaa 0x55. */
+static void pnp_enter_ext_func_mode(device_t dev)
+{
+ int i;
+ u16 port = dev >> 8;
+
+ /* TODO: Don't hardcode Super I/O config port to 0x3f0. */
+ outb(0x86, IT8661F_ISA_PNP_PORT);
+ outb(0x80, IT8661F_ISA_PNP_PORT);
+ outb(0x55, IT8661F_ISA_PNP_PORT);
+ outb(0x55, IT8661F_ISA_PNP_PORT);
+
+ /* Sequentially write the 32 special values. */
+ for (i = 0; i < 32; i++)
+ outb(init_values[i], port);
+}
+
+static void pnp_exit_ext_func_mode(device_t dev)
+{
+ pnp_write_config(dev, IT8661F_REG_CC, (1 << 1));
+}
+
+/*
+ * The logical devices will only be involved in the ISA PnP sequence if their
+ * respective enable bits in IT8661F_REG_LDE are set.
+ *
+ * TODO: Find out if we actually need this (we use MB PnP mode).
+ *
+ * Bits: FDC (0), Com1 (1), Com2 (2), PP (3), IR (4). Bits 5-7 are reserved.
+ */
+static void it8661f_enable_logical_devices(device_t dev)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_write_config(dev, IT8661F_REG_LDE, 0x1f);
+ pnp_exit_ext_func_mode(dev);
+}
+
+static void it8661f_set_clkin(device_t dev, u8 clkin)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_write_config(dev, IT8661F_REG_SWSUSP, (clkin << 1));
+ pnp_exit_ext_func_mode(dev);
+}
+
+static void it8661f_enable_serial(device_t dev, u16 iobase)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_ext_func_mode(dev);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/romcc_io.h>
-#include "it8661f.h"
-
-/* Perform MB PnP setup to put the SIO chip at 0x3f0. */
-/* Base address 0x3f0: 0x86 0x80 0x55 0x55. */
-/* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */
-/* Base address 0x370: 0x86 0x80 0xaa 0x55. */
-static void pnp_enter_ext_func_mode(device_t dev)
-{
- int i;
- u16 port = dev >> 8;
-
- /* TODO: Don't hardcode Super I/O config port to 0x3f0. */
- outb(0x86, IT8661F_ISA_PNP_PORT);
- outb(0x80, IT8661F_ISA_PNP_PORT);
- outb(0x55, IT8661F_ISA_PNP_PORT);
- outb(0x55, IT8661F_ISA_PNP_PORT);
-
- /* Sequentially write the 32 special values. */
- for (i = 0; i < 32; i++)
- outb(init_values[i], port);
-}
-
-static void pnp_exit_ext_func_mode(device_t dev)
-{
- pnp_write_config(dev, IT8661F_REG_CC, (1 << 1));
-}
-
-/*
- * The logical devices will only be involved in the ISA PnP sequence if their
- * respective enable bits in IT8661F_REG_LDE are set.
- *
- * TODO: Find out if we actually need this (we use MB PnP mode).
- *
- * Bits: FDC (0), Com1 (1), Com2 (2), PP (3), IR (4). Bits 5-7 are reserved.
- */
-static void it8661f_enable_logical_devices(device_t dev)
-{
- pnp_enter_ext_func_mode(dev);
- pnp_write_config(dev, IT8661F_REG_LDE, 0x1f);
- pnp_exit_ext_func_mode(dev);
-}
-
-static void it8661f_set_clkin(device_t dev, u8 clkin)
-{
- pnp_enter_ext_func_mode(dev);
- pnp_write_config(dev, IT8661F_REG_SWSUSP, (clkin << 1));
- pnp_exit_ext_func_mode(dev);
-}
-
-static void it8661f_enable_serial(device_t dev, u16 iobase)
-{
- pnp_enter_ext_func_mode(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
- pnp_exit_ext_func_mode(dev);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "it8671f.h"
+
+/* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */
+#define SIO_BASE 0x3f0
+#define SIO_INDEX SIO_BASE
+#define SIO_DATA (SIO_BASE + 1)
+
+/* Global configuration registers. */
+#define IT8671F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
+#define IT8671F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
+#define IT8671F_CONFIG_REG_LDE 0x23 /* PnP Logical Device Enable. */
+#define IT8671F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend. */
+
+#define IT8671F_CONFIGURATION_PORT 0x0279 /* Write-only. */
+
+/*
+ * Special values used for entering MB PnP mode. The first four bytes of
+ * each line determine the address port, the last four are data.
+ */
+static const u8 init_values[] = {
+ 0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe,
+ 0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61,
+ 0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1,
+ 0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39,
+};
+
+static void it8671f_sio_write(u8 ldn, u8 index, u8 value)
+{
+ outb(IT8671F_CONFIG_REG_LDN, SIO_BASE);
+ outb(ldn, SIO_DATA);
+ outb(index, SIO_BASE);
+ outb(value, SIO_DATA);
+}
+
+/* Enter the configuration state (MB PnP mode). */
+static void it8671f_enter_conf(void)
+{
+ int i;
+
+ /* Perform MB PnP setup to put the SIO chip at 0x3f0. */
+ /* Base address 0x3f0: 0x86 0x80 0x55 0x55. */
+ /* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */
+ /* Base address 0x370: 0x86 0x80 0xaa 0x55. */
+ outb(0x86, IT8671F_CONFIGURATION_PORT);
+ outb(0x80, IT8671F_CONFIGURATION_PORT);
+ outb(0x55, IT8671F_CONFIGURATION_PORT);
+ outb(0x55, IT8671F_CONFIGURATION_PORT);
+
+ /* Sequentially write the 32 special values. */
+ for (i = 0; i < 32; i++)
+ outb(init_values[i], SIO_BASE);
+}
+
+/* Exit the configuration state (MB PnP mode). */
+static void it8671f_exit_conf(void)
+{
+ it8671f_sio_write(0x00, IT8671F_CONFIG_REG_CC, 0x02);
+}
+
+/* Select 48MHz CLKIN (24MHz is the default). */
+void it8671f_48mhz_clkin(void)
+{
+ it8671f_enter_conf();
+ it8671f_sio_write(0x00, IT8671F_CONFIG_REG_SWSUSP, (1 << 6));
+ it8671f_exit_conf();
+}
+
+/* Enable the serial port(s). */
+static void it8671f_enable_serial(device_t dev, u16 iobase)
+{
+ it8671f_enter_conf();
+
+ /*
+ * Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2),
+ * PP (3), Reserved (4), KBCK (5), KBCM (6), Reserved (7).
+ */
+ it8671f_sio_write(0x00, IT8671F_CONFIG_REG_LDE, 0x6f);
+
+ /* Enable serial port(s). */
+ it8671f_sio_write(IT8671F_SP1, 0x30, 0x01); /* Serial port 1 */
+ it8671f_sio_write(IT8671F_SP2, 0x30, 0x01); /* Serial port 2 */
+
+ it8671f_exit_conf();
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/romcc_io.h>
-#include "it8671f.h"
-
-/* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */
-#define SIO_BASE 0x3f0
-#define SIO_INDEX SIO_BASE
-#define SIO_DATA (SIO_BASE + 1)
-
-/* Global configuration registers. */
-#define IT8671F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
-#define IT8671F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
-#define IT8671F_CONFIG_REG_LDE 0x23 /* PnP Logical Device Enable. */
-#define IT8671F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend. */
-
-#define IT8671F_CONFIGURATION_PORT 0x0279 /* Write-only. */
-
-/*
- * Special values used for entering MB PnP mode. The first four bytes of
- * each line determine the address port, the last four are data.
- */
-static const u8 init_values[] = {
- 0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe,
- 0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61,
- 0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1,
- 0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39,
-};
-
-static void it8671f_sio_write(u8 ldn, u8 index, u8 value)
-{
- outb(IT8671F_CONFIG_REG_LDN, SIO_BASE);
- outb(ldn, SIO_DATA);
- outb(index, SIO_BASE);
- outb(value, SIO_DATA);
-}
-
-/* Enter the configuration state (MB PnP mode). */
-static void it8671f_enter_conf(void)
-{
- int i;
-
- /* Perform MB PnP setup to put the SIO chip at 0x3f0. */
- /* Base address 0x3f0: 0x86 0x80 0x55 0x55. */
- /* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */
- /* Base address 0x370: 0x86 0x80 0xaa 0x55. */
- outb(0x86, IT8671F_CONFIGURATION_PORT);
- outb(0x80, IT8671F_CONFIGURATION_PORT);
- outb(0x55, IT8671F_CONFIGURATION_PORT);
- outb(0x55, IT8671F_CONFIGURATION_PORT);
-
- /* Sequentially write the 32 special values. */
- for (i = 0; i < 32; i++)
- outb(init_values[i], SIO_BASE);
-}
-
-/* Exit the configuration state (MB PnP mode). */
-static void it8671f_exit_conf(void)
-{
- it8671f_sio_write(0x00, IT8671F_CONFIG_REG_CC, 0x02);
-}
-
-/* Select 48MHz CLKIN (24MHz is the default). */
-void it8671f_48mhz_clkin(void)
-{
- it8671f_enter_conf();
- it8671f_sio_write(0x00, IT8671F_CONFIG_REG_SWSUSP, (1 << 6));
- it8671f_exit_conf();
-}
-
-/* Enable the serial port(s). */
-static void it8671f_enable_serial(device_t dev, u16 iobase)
-{
- it8671f_enter_conf();
-
- /*
- * Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2),
- * PP (3), Reserved (4), KBCK (5), KBCM (6), Reserved (7).
- */
- it8671f_sio_write(0x00, IT8671F_CONFIG_REG_LDE, 0x6f);
-
- /* Enable serial port(s). */
- it8671f_sio_write(IT8671F_SP1, 0x30, 0x01); /* Serial port 1 */
- it8671f_sio_write(IT8671F_SP2, 0x30, 0x01); /* Serial port 2 */
-
- it8671f_exit_conf();
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "it8673f.h"
+
+/* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */
+#define SIO_BASE 0x3f0
+#define SIO_INDEX SIO_BASE
+#define SIO_DATA (SIO_BASE + 1)
+
+/* Global configuration registers. */
+#define IT8673F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
+#define IT8673F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
+#define IT8673F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
+#define IT8673F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend. */
+
+#define IT8673F_CONFIGURATION_PORT 0x0279 /* Write-only. */
+
+/*
+ * Special values used for entering MB PnP mode. The first four bytes of
+ * each line determine the address port, the last four are data.
+ */
+static const u8 init_values[] = {
+ 0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe,
+ 0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61,
+ 0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1,
+ 0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39,
+};
+
+static void it8673f_sio_write(u8 ldn, u8 index, u8 value)
+{
+ outb(IT8673F_CONFIG_REG_LDN, SIO_BASE);
+ outb(ldn, SIO_DATA);
+ outb(index, SIO_BASE);
+ outb(value, SIO_DATA);
+}
+
+/* Enable the serial port(s). */
+static void it8673f_enable_serial(device_t dev, u16 iobase)
+{
+ int i;
+
+ /* (1) Enter the configuration state (MB PnP mode). */
+
+ /* Perform MB PnP setup to put the SIO chip at 0x3f0. */
+ /* Base address 0x3f0: 0x86 0x80 0x55 0x55. */
+ /* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */
+ /* Base address 0x370: 0x86 0x80 0xaa 0x55. */
+ outb(0x86, IT8673F_CONFIGURATION_PORT);
+ outb(0x80, IT8673F_CONFIGURATION_PORT);
+ outb(0x55, IT8673F_CONFIGURATION_PORT);
+ outb(0x55, IT8673F_CONFIGURATION_PORT);
+
+ /* Sequentially write the 32 special values. */
+ for (i = 0; i < 32; i++)
+ outb(init_values[i], SIO_BASE);
+
+ /* (2) Modify the data of configuration registers. */
+
+ /* Enable all devices. */
+ it8673f_sio_write(IT8673F_SP1, 0x30, 0x1); /* Serial port 1 */
+ it8673f_sio_write(IT8673F_SP2, 0x30, 0x1); /* Serial port 2 */
+
+ /* Select 24MHz CLKIN (clear bit 0). */
+ it8673f_sio_write(0x00, IT8673F_CONFIG_REG_CLOCKSEL, 0x00);
+
+ /* Clear software suspend mode (clear bit 0). */
+ it8673f_sio_write(0x00, IT8673F_CONFIG_REG_SWSUSP, 0x00);
+
+ /* (3) Exit the configuration state (MB PnP mode). */
+ it8673f_sio_write(0x00, IT8673F_CONFIG_REG_CC, 0x02);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/romcc_io.h>
-#include "it8673f.h"
-
-/* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */
-#define SIO_BASE 0x3f0
-#define SIO_INDEX SIO_BASE
-#define SIO_DATA (SIO_BASE + 1)
-
-/* Global configuration registers. */
-#define IT8673F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
-#define IT8673F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
-#define IT8673F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
-#define IT8673F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend. */
-
-#define IT8673F_CONFIGURATION_PORT 0x0279 /* Write-only. */
-
-/*
- * Special values used for entering MB PnP mode. The first four bytes of
- * each line determine the address port, the last four are data.
- */
-static const u8 init_values[] = {
- 0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe,
- 0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61,
- 0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1,
- 0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39,
-};
-
-static void it8673f_sio_write(u8 ldn, u8 index, u8 value)
-{
- outb(IT8673F_CONFIG_REG_LDN, SIO_BASE);
- outb(ldn, SIO_DATA);
- outb(index, SIO_BASE);
- outb(value, SIO_DATA);
-}
-
-/* Enable the serial port(s). */
-static void it8673f_enable_serial(device_t dev, u16 iobase)
-{
- int i;
-
- /* (1) Enter the configuration state (MB PnP mode). */
-
- /* Perform MB PnP setup to put the SIO chip at 0x3f0. */
- /* Base address 0x3f0: 0x86 0x80 0x55 0x55. */
- /* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */
- /* Base address 0x370: 0x86 0x80 0xaa 0x55. */
- outb(0x86, IT8673F_CONFIGURATION_PORT);
- outb(0x80, IT8673F_CONFIGURATION_PORT);
- outb(0x55, IT8673F_CONFIGURATION_PORT);
- outb(0x55, IT8673F_CONFIGURATION_PORT);
-
- /* Sequentially write the 32 special values. */
- for (i = 0; i < 32; i++)
- outb(init_values[i], SIO_BASE);
-
- /* (2) Modify the data of configuration registers. */
-
- /* Enable all devices. */
- it8673f_sio_write(IT8673F_SP1, 0x30, 0x1); /* Serial port 1 */
- it8673f_sio_write(IT8673F_SP2, 0x30, 0x1); /* Serial port 2 */
-
- /* Select 24MHz CLKIN (clear bit 0). */
- it8673f_sio_write(0x00, IT8673F_CONFIG_REG_CLOCKSEL, 0x00);
-
- /* Clear software suspend mode (clear bit 0). */
- it8673f_sio_write(0x00, IT8673F_CONFIG_REG_SWSUSP, 0x00);
-
- /* (3) Exit the configuration state (MB PnP mode). */
- it8673f_sio_write(0x00, IT8673F_CONFIG_REG_CC, 0x02);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "it8705f.h"
+
+/* The base address is 0x2e or 0x4e, depending on config bytes. */
+#define SIO_BASE 0x2e
+#define SIO_INDEX SIO_BASE
+#define SIO_DATA (SIO_BASE + 1)
+
+/* Global configuration registers. */
+#define IT8705F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
+#define IT8705F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
+#define IT8705F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
+
+/* WTF? 0x23 and 0x24 are swapped here (when compared to other IT87xx). */
+#define IT8705F_CONFIG_REG_CLOCKSEL 0x24 /* Clock Selection, Flash I/F. */
+#define IT8705F_CONFIG_REG_SWSUSP 0x23 /* Software Suspend. */
+
+#define IT8705F_CONFIGURATION_PORT 0x2e /* Write-only. */
+
+static void it8705f_sio_write(u8 ldn, u8 index, u8 value)
+{
+ outb(IT8705F_CONFIG_REG_LDN, SIO_BASE);
+ outb(ldn, SIO_DATA);
+ outb(index, SIO_BASE);
+ outb(value, SIO_DATA);
+}
+
+/* Enable the serial port(s). */
+static void it8705f_enable_serial(device_t dev, u16 iobase)
+{
+ /* (1) Enter the configuration state (MB PnP mode). */
+
+ /* Perform MB PnP setup to put the SIO chip at 0x2e. */
+ /* Base address 0x2e: 0x87 0x01 0x55 0x55. */
+ /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */
+ outb(0x87, IT8705F_CONFIGURATION_PORT);
+ outb(0x01, IT8705F_CONFIGURATION_PORT);
+ outb(0x55, IT8705F_CONFIGURATION_PORT);
+ outb(0x55, IT8705F_CONFIGURATION_PORT);
+
+ /* (2) Modify the data of configuration registers. */
+
+ /*
+ * Select the chip to configure (if there's more than one).
+ * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
+ * If this register is not written, both chips are configured.
+ */
+ /* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CONFIGSEL, 0x00); */
+
+ /* Enable serial port(s). */
+ it8705f_sio_write(IT8705F_SP1, 0x30, 0x1); /* Serial port 1 */
+ it8705f_sio_write(IT8705F_SP2, 0x30, 0x1); /* Serial port 2 */
+
+ /* Select 24MHz CLKIN (set bit 0). */
+ it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CLOCKSEL, 0x01);
+
+ /* Clear software suspend mode (clear bit 0). TODO: Needed? */
+ /* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_SWSUSP, 0x00); */
+
+ /* (3) Exit the configuration state (MB PnP mode). */
+ it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CC, 0x02);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/romcc_io.h>
-#include "it8705f.h"
-
-/* The base address is 0x2e or 0x4e, depending on config bytes. */
-#define SIO_BASE 0x2e
-#define SIO_INDEX SIO_BASE
-#define SIO_DATA (SIO_BASE + 1)
-
-/* Global configuration registers. */
-#define IT8705F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
-#define IT8705F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
-#define IT8705F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
-
-/* WTF? 0x23 and 0x24 are swapped here (when compared to other IT87xx). */
-#define IT8705F_CONFIG_REG_CLOCKSEL 0x24 /* Clock Selection, Flash I/F. */
-#define IT8705F_CONFIG_REG_SWSUSP 0x23 /* Software Suspend. */
-
-#define IT8705F_CONFIGURATION_PORT 0x2e /* Write-only. */
-
-static void it8705f_sio_write(u8 ldn, u8 index, u8 value)
-{
- outb(IT8705F_CONFIG_REG_LDN, SIO_BASE);
- outb(ldn, SIO_DATA);
- outb(index, SIO_BASE);
- outb(value, SIO_DATA);
-}
-
-/* Enable the serial port(s). */
-static void it8705f_enable_serial(device_t dev, u16 iobase)
-{
- /* (1) Enter the configuration state (MB PnP mode). */
-
- /* Perform MB PnP setup to put the SIO chip at 0x2e. */
- /* Base address 0x2e: 0x87 0x01 0x55 0x55. */
- /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */
- outb(0x87, IT8705F_CONFIGURATION_PORT);
- outb(0x01, IT8705F_CONFIGURATION_PORT);
- outb(0x55, IT8705F_CONFIGURATION_PORT);
- outb(0x55, IT8705F_CONFIGURATION_PORT);
-
- /* (2) Modify the data of configuration registers. */
-
- /*
- * Select the chip to configure (if there's more than one).
- * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
- * If this register is not written, both chips are configured.
- */
- /* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CONFIGSEL, 0x00); */
-
- /* Enable serial port(s). */
- it8705f_sio_write(IT8705F_SP1, 0x30, 0x1); /* Serial port 1 */
- it8705f_sio_write(IT8705F_SP2, 0x30, 0x1); /* Serial port 2 */
-
- /* Select 24MHz CLKIN (set bit 0). */
- it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CLOCKSEL, 0x01);
-
- /* Clear software suspend mode (clear bit 0). TODO: Needed? */
- /* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_SWSUSP, 0x00); */
-
- /* (3) Exit the configuration state (MB PnP mode). */
- it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CC, 0x02);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "it8712f.h"
+
+/* The base address is 0x2e or 0x4e, depending on config bytes. */
+#define SIO_BASE 0x2e
+#define SIO_INDEX SIO_BASE
+#define SIO_DATA (SIO_BASE + 1)
+
+/* Global configuration registers. */
+#define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
+#define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
+#define IT8712F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
+#define IT8712F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
+#define IT8712F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
+#define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */
+#define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */
+
+static void it8712f_sio_write(u8 ldn, u8 index, u8 value)
+{
+ outb(IT8712F_CONFIG_REG_LDN, SIO_BASE);
+ outb(ldn, SIO_DATA);
+ outb(index, SIO_BASE);
+ outb(value, SIO_DATA);
+}
+
+static void it8712f_enter_conf(void)
+{
+ u16 port = 0x2e; /* TODO: Don't hardcode! */
+
+ outb(0x87, port);
+ outb(0x01, port);
+ outb(0x55, port);
+ outb((port == 0x4e) ? 0xaa : 0x55, port);
+}
+
+static void it8712f_exit_conf(void)
+{
+ it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02);
+}
+
+/* Select 24MHz CLKIN (48MHz is the default). */
+void it8712f_24mhz_clkin(void)
+{
+ it8712f_enter_conf();
+ it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x1);
+ it8712f_exit_conf();
+}
+
+/*
+ * We need to set enable 3VSBSW#, this was documented only in IT8712F_V0.9.2!
+ *
+ * LDN 7, reg 0x2a - needed for S3, or memory power will be cut off.
+ *
+ * Enable 3VSBSW#. (For System Suspend-to-RAM)
+ * 0: 3VSBSW# will be always inactive.
+ * 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#.
+ */
+void it8712f_enable_3vsbsw(void)
+{
+ it8712f_enter_conf();
+ it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_MFC, 0x80);
+ it8712f_exit_conf();
+}
+
+void it8712f_kill_watchdog(void)
+{
+ it8712f_enter_conf();
+ it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_WATCHDOG, 0x00);
+ it8712f_exit_conf();
+}
+
+/* Enable the serial port(s). */
+void it8712f_enable_serial(device_t dev, u16 iobase)
+{
+ /* (1) Enter the configuration state (MB PnP mode). */
+ it8712f_enter_conf();
+
+ /* (2) Modify the data of configuration registers. */
+
+ /*
+ * Select the chip to configure (if there's more than one).
+ * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
+ * If this register is not written, both chips are configured.
+ */
+
+ /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CONFIGSEL, 0x00); */
+
+ /* Enable serial port(s). */
+ it8712f_sio_write(IT8712F_SP1, 0x30, 0x1); /* Serial port 1 */
+ it8712f_sio_write(IT8712F_SP2, 0x30, 0x1); /* Serial port 2 */
+
+ /* Clear software suspend mode (clear bit 0). TODO: Needed? */
+ /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_SWSUSP, 0x00); */
+
+ /* (3) Exit the configuration state (MB PnP mode). */
+ it8712f_exit_conf();
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/romcc_io.h>
-#include "it8712f.h"
-
-/* The base address is 0x2e or 0x4e, depending on config bytes. */
-#define SIO_BASE 0x2e
-#define SIO_INDEX SIO_BASE
-#define SIO_DATA (SIO_BASE + 1)
-
-/* Global configuration registers. */
-#define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
-#define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
-#define IT8712F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
-#define IT8712F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
-#define IT8712F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
-#define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */
-#define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */
-
-static void it8712f_sio_write(u8 ldn, u8 index, u8 value)
-{
- outb(IT8712F_CONFIG_REG_LDN, SIO_BASE);
- outb(ldn, SIO_DATA);
- outb(index, SIO_BASE);
- outb(value, SIO_DATA);
-}
-
-static void it8712f_enter_conf(void)
-{
- u16 port = 0x2e; /* TODO: Don't hardcode! */
-
- outb(0x87, port);
- outb(0x01, port);
- outb(0x55, port);
- outb((port == 0x4e) ? 0xaa : 0x55, port);
-}
-
-static void it8712f_exit_conf(void)
-{
- it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02);
-}
-
-/* Select 24MHz CLKIN (48MHz is the default). */
-void it8712f_24mhz_clkin(void)
-{
- it8712f_enter_conf();
- it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x1);
- it8712f_exit_conf();
-}
-
-/*
- * We need to set enable 3VSBSW#, this was documented only in IT8712F_V0.9.2!
- *
- * LDN 7, reg 0x2a - needed for S3, or memory power will be cut off.
- *
- * Enable 3VSBSW#. (For System Suspend-to-RAM)
- * 0: 3VSBSW# will be always inactive.
- * 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#.
- */
-void it8712f_enable_3vsbsw(void)
-{
- it8712f_enter_conf();
- it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_MFC, 0x80);
- it8712f_exit_conf();
-}
-
-void it8712f_kill_watchdog(void)
-{
- it8712f_enter_conf();
- it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_WATCHDOG, 0x00);
- it8712f_exit_conf();
-}
-
-/* Enable the serial port(s). */
-void it8712f_enable_serial(device_t dev, u16 iobase)
-{
- /* (1) Enter the configuration state (MB PnP mode). */
- it8712f_enter_conf();
-
- /* (2) Modify the data of configuration registers. */
-
- /*
- * Select the chip to configure (if there's more than one).
- * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
- * If this register is not written, both chips are configured.
- */
-
- /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CONFIGSEL, 0x00); */
-
- /* Enable serial port(s). */
- it8712f_sio_write(IT8712F_SP1, 0x30, 0x1); /* Serial port 1 */
- it8712f_sio_write(IT8712F_SP2, 0x30, 0x1); /* Serial port 2 */
-
- /* Clear software suspend mode (clear bit 0). TODO: Needed? */
- /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_SWSUSP, 0x00); */
-
- /* (3) Exit the configuration state (MB PnP mode). */
- it8712f_exit_conf();
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "it8716f.h"
+
+void it8716f_disable_dev(device_t dev)
+{
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+}
+
+void it8716f_enable_dev(device_t dev, u16 iobase)
+{
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "it8716f.h"
+
+/* The base address is 0x2e or 0x4e, depending on config bytes. */
+#define SIO_BASE 0x2e
+#define SIO_INDEX SIO_BASE
+#define SIO_DATA (SIO_BASE + 1)
+
+/* Global configuration registers. */
+#define IT8716F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
+#define IT8716F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
+#define IT8716F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
+#define IT8716F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
+#define IT8716F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
+
+static void pnp_enter_ext_func_mode(device_t dev)
+{
+ u16 port = dev >> 8;
+
+ outb(0x87, port);
+ outb(0x01, port);
+ outb(0x55, port);
+ outb((port == 0x4e) ? 0xaa : 0x55, port);
+}
+
+static void pnp_exit_ext_func_mode(device_t dev)
+{
+ pnp_write_config(dev, IT8716F_CONFIG_REG_CC, 0x02);
+}
+
+void it8716f_enable_serial(device_t dev, u16 iobase)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_ext_func_mode(dev);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/romcc_io.h>
-#include "it8716f.h"
-
-void it8716f_disable_dev(device_t dev)
-{
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
-}
-
-void it8716f_enable_dev(device_t dev, u16 iobase)
-{
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
-}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/romcc_io.h>
-#include "it8716f.h"
-
-/* The base address is 0x2e or 0x4e, depending on config bytes. */
-#define SIO_BASE 0x2e
-#define SIO_INDEX SIO_BASE
-#define SIO_DATA (SIO_BASE + 1)
-
-/* Global configuration registers. */
-#define IT8716F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
-#define IT8716F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
-#define IT8716F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
-#define IT8716F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
-#define IT8716F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
-
-static void pnp_enter_ext_func_mode(device_t dev)
-{
- u16 port = dev >> 8;
-
- outb(0x87, port);
- outb(0x01, port);
- outb(0x55, port);
- outb((port == 0x4e) ? 0xaa : 0x55, port);
-}
-
-static void pnp_exit_ext_func_mode(device_t dev)
-{
- pnp_write_config(dev, IT8716F_CONFIG_REG_CC, 0x02);
-}
-
-void it8716f_enable_serial(device_t dev, u16 iobase)
-{
- pnp_enter_ext_func_mode(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
- pnp_exit_ext_func_mode(dev);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "it8718f.h"
+
+/* The base address is 0x2e or 0x4e, depending on config bytes. */
+#define SIO_BASE 0x2e
+#define SIO_INDEX SIO_BASE
+#define SIO_DATA (SIO_BASE + 1)
+
+/* Global configuration registers. */
+#define IT8718F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
+#define IT8718F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
+#define IT8718F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
+#define IT8718F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
+#define IT8718F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
+
+static void it8718f_sio_write(u8 ldn, u8 index, u8 value)
+{
+ outb(IT8718F_CONFIG_REG_LDN, SIO_BASE);
+ outb(ldn, SIO_DATA);
+ outb(index, SIO_BASE);
+ outb(value, SIO_DATA);
+}
+
+static void it8718f_enter_conf(void)
+{
+ u16 port = 0x2e; /* TODO: Don't hardcode! */
+
+ outb(0x87, port);
+ outb(0x01, port);
+ outb(0x55, port);
+ outb((port == 0x4e) ? 0xaa : 0x55, port);
+}
+
+static void it8718f_exit_conf(void)
+{
+ it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02);
+}
+
+/* Select 24MHz CLKIN (48MHz default). */
+void it8718f_24mhz_clkin(void)
+{
+ it8718f_enter_conf();
+ it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x1);
+ it8718f_exit_conf();
+}
+
+/*
+ * GIGABYTE uses a special Super I/O register to protect its Dual BIOS
+ * mechanism. It lives in the GPIO LDN. However, register 0xEF is not
+ * mentioned in the IT8718F datasheet so just hardcode it to 0x7E for now.
+ */
+void it8718f_disable_reboot(void)
+{
+ it8718f_enter_conf();
+ it8718f_sio_write(IT8718F_GPIO, 0xEF, 0x7E);
+ it8718f_exit_conf();
+}
+
+/* Enable the serial port(s). */
+void it8718f_enable_serial(device_t dev, u16 iobase)
+{
+ /* (1) Enter the configuration state (MB PnP mode). */
+ it8718f_enter_conf();
+
+ /* (2) Modify the data of configuration registers. */
+
+ /*
+ * Select the chip to configure (if there's more than one).
+ * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
+ * If this register is not written, both chips are configured.
+ */
+
+ /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */
+
+ /* Enable serial port(s). */
+ it8718f_sio_write(IT8718F_SP1, 0x30, 0x1); /* Serial port 1 */
+ it8718f_sio_write(IT8718F_SP2, 0x30, 0x1); /* Serial port 2 */
+
+ /* Clear software suspend mode (clear bit 0). TODO: Needed? */
+ /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_SWSUSP, 0x00); */
+
+ /* (3) Exit the configuration state (MB PnP mode). */
+ it8718f_exit_conf();
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/romcc_io.h>
-#include "it8718f.h"
-
-/* The base address is 0x2e or 0x4e, depending on config bytes. */
-#define SIO_BASE 0x2e
-#define SIO_INDEX SIO_BASE
-#define SIO_DATA (SIO_BASE + 1)
-
-/* Global configuration registers. */
-#define IT8718F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
-#define IT8718F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
-#define IT8718F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
-#define IT8718F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
-#define IT8718F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
-
-static void it8718f_sio_write(u8 ldn, u8 index, u8 value)
-{
- outb(IT8718F_CONFIG_REG_LDN, SIO_BASE);
- outb(ldn, SIO_DATA);
- outb(index, SIO_BASE);
- outb(value, SIO_DATA);
-}
-
-static void it8718f_enter_conf(void)
-{
- u16 port = 0x2e; /* TODO: Don't hardcode! */
-
- outb(0x87, port);
- outb(0x01, port);
- outb(0x55, port);
- outb((port == 0x4e) ? 0xaa : 0x55, port);
-}
-
-static void it8718f_exit_conf(void)
-{
- it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02);
-}
-
-/* Select 24MHz CLKIN (48MHz default). */
-void it8718f_24mhz_clkin(void)
-{
- it8718f_enter_conf();
- it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x1);
- it8718f_exit_conf();
-}
-
-/*
- * GIGABYTE uses a special Super I/O register to protect its Dual BIOS
- * mechanism. It lives in the GPIO LDN. However, register 0xEF is not
- * mentioned in the IT8718F datasheet so just hardcode it to 0x7E for now.
- */
-void it8718f_disable_reboot(void)
-{
- it8718f_enter_conf();
- it8718f_sio_write(IT8718F_GPIO, 0xEF, 0x7E);
- it8718f_exit_conf();
-}
-
-/* Enable the serial port(s). */
-void it8718f_enable_serial(device_t dev, u16 iobase)
-{
- /* (1) Enter the configuration state (MB PnP mode). */
- it8718f_enter_conf();
-
- /* (2) Modify the data of configuration registers. */
-
- /*
- * Select the chip to configure (if there's more than one).
- * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
- * If this register is not written, both chips are configured.
- */
-
- /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */
-
- /* Enable serial port(s). */
- it8718f_sio_write(IT8718F_SP1, 0x30, 0x1); /* Serial port 1 */
- it8718f_sio_write(IT8718F_SP2, 0x30, 0x1); /* Serial port 2 */
-
- /* Clear software suspend mode (clear bit 0). TODO: Needed? */
- /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_SWSUSP, 0x00); */
-
- /* (3) Exit the configuration state (MB PnP mode). */
- it8718f_exit_conf();
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000 AG Electronics Ltd.
+ * Copyright (C) 2003-2004 Linux Networx
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "pc8374.h"
+
+static void pc8374_enable(u16 iobase, u8 *init)
+{
+ u8 val, count;
+
+ outb(0x29, iobase);
+ val = inb(iobase + 1);
+ val |= 0x91;
+ outb(val, iobase + 1);
+
+ for (count = 0; count < 255; count++)
+ if (inb(iobase + 1) == 0x91)
+ break;
+
+ for (; *init; init++) {
+ outb(*init, iobase);
+ val = inb(iobase + 1);
+ init++;
+ val &= *init;
+ init++;
+ val |= *init;
+ outb(val, iobase + 1);
+ }
+}
+
+static void pc8374_enable_dev(device_t dev, u16 iobase)
+{
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ if (iobase)
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/romcc_io.h>
-#include "pc8374.h"
-
-static void pc8374_enable(u16 iobase, u8 *init)
-{
- u8 val, count;
-
- outb(0x29, iobase);
- val = inb(iobase + 1);
- val |= 0x91;
- outb(val, iobase + 1);
-
- for (count = 0; count < 255; count++)
- if (inb(iobase + 1) == 0x91)
- break;
-
- for (; *init; init++) {
- outb(*init, iobase);
- val = inb(iobase + 1);
- init++;
- val &= *init;
- init++;
- val |= *init;
- outb(val, iobase + 1);
- }
-}
-
-static void pc8374_enable_dev(device_t dev, u16 iobase)
-{
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- if (iobase)
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "pc87309.h"
+
+static void pc87309_enable_serial(device_t dev, u16 iobase)
+{
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/romcc_io.h>
-#include "pc87309.h"
-
-static void pc87309_enable_serial(device_t dev, u16 iobase)
-{
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000 AG Electronics Ltd.
+ * Copyright (C) 2003-2004 Linux Networx
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "pc87351.h"
+
+static void pc87351_enable_serial(device_t dev, u16 iobase)
+{
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/romcc_io.h>
-#include "pc87351.h"
-
-static void pc87351_enable_serial(device_t dev, u16 iobase)
-{
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000 AG Electronics Ltd.
+ * Copyright (C) 2003-2004 Linux Networx
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "pc87360.h"
+
+static void pc87360_enable_serial(device_t dev, u16 iobase)
+{
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/romcc_io.h>
-#include "pc87360.h"
-
-static void pc87360_enable_serial(device_t dev, u16 iobase)
-{
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000 AG Electronics Ltd.
+ * Copyright (C) 2003-2004 Linux Networx
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "pc87366.h"
+
+static void pc87366_enable_serial(device_t dev, u16 iobase)
+{
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/romcc_io.h>
-#include "pc87366.h"
-
-static void pc87366_enable_serial(device_t dev, u16 iobase)
-{
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000 AG Electronics Ltd.
+ * Copyright (C) 2003-2004 Linux Networx
+ * Copyright (C) 2004 Tyan
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "pc87417.h"
+
+static void pc87417_disable_dev(device_t dev)
+{
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+}
+
+static void pc87417_enable_dev(device_t dev, u16 iobase)
+{
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+}
+
+static void xbus_cfg(device_t dev)
+{
+ u8 i, data;
+ u16 xbus_index;
+
+ pnp_set_logical_device(dev);
+ /* Select proper BIOS size (4MB). */
+ pnp_write_config(dev, PC87417_XMEMCNF2,
+ (pnp_read_config(dev, PC87417_XMEMCNF2)) | 0x04);
+ xbus_index = pnp_read_iobase(dev, 0x60);
+
+ /* Enable writes to devices attached to XCS0 (XBUS Chip Select 0). */
+ for (i = 0; i <= 0xf; i++)
+ outb((i << 4), xbus_index + PC87417_HAP0);
+}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000 AG Electronics Ltd.
+ * Copyright (C) 2003-2004 Linux Networx
+ * Copyright (C) 2004 Tyan
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "pc87417.h"
+
+void pc87417_enable_serial(device_t dev, u16 iobase)
+{
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+}
+
+void pc87417_enable_dev(device_t dev)
+{
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 1);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- * Copyright (C) 2004 Tyan
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/romcc_io.h>
-#include "pc87417.h"
-
-static void pc87417_disable_dev(device_t dev)
-{
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
-}
-
-static void pc87417_enable_dev(device_t dev, u16 iobase)
-{
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
-}
-
-static void xbus_cfg(device_t dev)
-{
- u8 i, data;
- u16 xbus_index;
-
- pnp_set_logical_device(dev);
- /* Select proper BIOS size (4MB). */
- pnp_write_config(dev, PC87417_XMEMCNF2,
- (pnp_read_config(dev, PC87417_XMEMCNF2)) | 0x04);
- xbus_index = pnp_read_iobase(dev, 0x60);
-
- /* Enable writes to devices attached to XCS0 (XBUS Chip Select 0). */
- for (i = 0; i <= 0xf; i++)
- outb((i << 4), xbus_index + PC87417_HAP0);
-}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- * Copyright (C) 2004 Tyan
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/romcc_io.h>
-#include "pc87417.h"
-
-void pc87417_enable_serial(device_t dev, u16 iobase)
-{
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
-}
-
-void pc87417_enable_dev(device_t dev)
-{
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 1);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000 AG Electronics Ltd.
+ * Copyright (C) 2003-2004 Linux Networx
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "pc87427.h"
+
+static void pc87427_disable_dev(device_t dev)
+{
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+}
+
+static void pc87427_enable_dev(device_t dev, u16 iobase)
+{
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+}
+
+static void xbus_cfg(device_t dev)
+{
+ u8 i, data;
+ u16 xbus_index;
+
+ pnp_set_logical_device(dev);
+
+ /* Select proper BIOS size (4MB). */
+ pnp_write_config(dev, PC87427_XMEMCNF2,
+ (pnp_read_config(dev, PC87427_XMEMCNF2)) | 0x04);
+ xbus_index = pnp_read_iobase(dev, 0x60);
+
+ /* Enable writes to devices attached to XCS0 (XBUS Chip Select 0). */
+ for (i = 0; i <= 0xf; i++)
+ outb((i << 4), xbus_index + PC87427_HAP0);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/romcc_io.h>
-#include "pc87427.h"
-
-static void pc87427_disable_dev(device_t dev)
-{
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
-}
-
-static void pc87427_enable_dev(device_t dev, u16 iobase)
-{
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
-}
-
-static void xbus_cfg(device_t dev)
-{
- u8 i, data;
- u16 xbus_index;
-
- pnp_set_logical_device(dev);
-
- /* Select proper BIOS size (4MB). */
- pnp_write_config(dev, PC87427_XMEMCNF2,
- (pnp_read_config(dev, PC87427_XMEMCNF2)) | 0x04);
- xbus_index = pnp_read_iobase(dev, 0x60);
-
- /* Enable writes to devices attached to XCS0 (XBUS Chip Select 0). */
- for (i = 0; i <= 0xf; i++)
- outb((i << 4), xbus_index + PC87427_HAP0);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000 AG Electronics Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "pc97317.h"
+
+#define PM_DEV PNP_DEV(0x2e, PC97317_PM)
+#define PM_BASE 0xe8
+
+/* The PC97317 needs clocks to be set up before the serial port will operate. */
+static void pc97317_enable_serial(device_t dev, u16 iobase)
+{
+ /* Set base address of power management unit. */
+ pnp_set_logical_device(PM_DEV);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, PM_BASE);
+ pnp_set_enable(dev, 1);
+
+ /* Use on-chip clock multiplier. */
+ outb(0x03, PM_BASE);
+ outb(inb(PM_BASE + 1) | 0x07, PM_BASE + 1);
+
+ /* Wait for the clock to stabilise. */
+ while(!(inb(PM_BASE + 1) & 0x80))
+ ;
+
+ /* Set the base address of the port. */
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/romcc_io.h>
-#include "pc97317.h"
-
-#define PM_DEV PNP_DEV(0x2e, PC97317_PM)
-#define PM_BASE 0xe8
-
-/* The PC97317 needs clocks to be set up before the serial port will operate. */
-static void pc97317_enable_serial(device_t dev, u16 iobase)
-{
- /* Set base address of power management unit. */
- pnp_set_logical_device(PM_DEV);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, PM_BASE);
- pnp_set_enable(dev, 1);
-
- /* Use on-chip clock multiplier. */
- outb(0x03, PM_BASE);
- outb(inb(PM_BASE + 1) | 0x07, PM_BASE + 1);
-
- /* Wait for the clock to stabilise. */
- while(!(inb(PM_BASE + 1) & 0x80))
- ;
-
- /* Set the base address of the port. */
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 University of Heidelberg
+ * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for Univ. Heidelberg
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* PILOT Super I/O is only based on LPC observation done on factory system. */
+
+#define BLUBB_DEV PNP_DEV(port, 0x04)
+
+/*
+ * Logical device 4, 5 and 7 are being deactivated. Logical Device 1 seems to
+ * be another serial (?), it is also deactivated on the HP machine.
+ */
+static void pilot_early_init(device_t dev)
+{
+ u16 port = dev >> 8;
+
+ print_debug("Using port: ");
+ print_debug_hex16(port);
+ print_debug("\n");
+ pilot_disable_serial(PNP_DEV(port, 0x1));
+ print_debug("disable serial 1\n");
+
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(PNP_DEV(port, 0x3));
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, 0x60, 0x0b00);
+ pnp_set_iobase(dev, 0x62, 0x0b80);
+ pnp_set_iobase(dev, 0x64, 0x0b84);
+ pnp_set_iobase(dev, 0x66, 0x0b86);
+ pnp_set_enable(dev, 1);
+ pnp_exit_ext_func_mode(dev);
+
+/*
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(PNP_DEV(port, 0x3));
+ pnp_exit_ext_func_mode(dev);
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_enable(PNP_DEV(port, 0x3), 0);
+ pnp_exit_ext_func_mode(dev);
+*/
+
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(PNP_DEV(port, 0x4));
+ pnp_exit_ext_func_mode(dev);
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_enable( PNP_DEV(port, 0x4), 0);
+ pnp_exit_ext_func_mode(dev);
+
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(PNP_DEV(port, 0x5));
+ pnp_exit_ext_func_mode(dev);
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_enable(PNP_DEV(port, 0x5), 0);
+ pnp_exit_ext_func_mode(dev);
+
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(PNP_DEV(port, 0x6));
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
+ pnp_set_iobase(dev, PNP_IDX_IO1, 0x64);
+ pnp_set_irq(dev, PNP_IDX_IRQ0, 1);
+ pnp_set_drq(dev, 0x71, 3);
+ pnp_set_enable(dev, 0);
+ pnp_exit_ext_func_mode(dev);
+
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(PNP_DEV(port, 0xe));
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, 0x70);
+ pnp_set_iobase(dev, PNP_IDX_IO1, 0x72);
+ pnp_set_irq(dev, PNP_IDX_IRQ0, 8);
+ pnp_set_drq(dev, 0x71, 3);
+ pnp_set_enable(dev, 0);
+ pnp_exit_ext_func_mode(dev);
+
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(PNP_DEV(port, 0x7));
+ pnp_exit_ext_func_mode(dev);
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_enable(PNP_DEV(port, 0x7), 0);
+ pnp_exit_ext_func_mode(dev);
+
+/*
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(PNP_DEV(port, 0x8));
+ pnp_exit_ext_func_mode(dev);
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_enable(PNP_DEV(port, 0x8), 0);
+ pnp_exit_ext_func_mode(dev);
+
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(PNP_DEV(port, 0x9));
+ pnp_exit_ext_func_mode(dev);
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_enable(PNP_DEV(port, 0x9), 0);
+ pnp_exit_ext_func_mode(dev);
+
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(PNP_DEV(port, 0x10));
+ pnp_exit_ext_func_mode(dev);
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_enable(PNP_DEV(port, 0x10), 0);
+ pnp_exit_ext_func_mode(dev);
+*/
+}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 University of Heidelberg
+ * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for Univ. Heidelberg
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* PILOT Super I/O is only based on LPC observation done on factory system. */
+
+#include <arch/romcc_io.h>
+#include "pilot.h"
+
+/* Pilot uses 0x5A/0xA5 pattern to actiavte deactivate config access. */
+static void pnp_enter_ext_func_mode(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0x5A, port);
+}
+
+static void pnp_exit_ext_func_mode(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0xA5, port);
+}
+
+/* Serial config is a fairly standard procedure. */
+static void pilot_enable_serial(device_t dev, u16 iobase)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_ext_func_mode(dev);
+}
+
+static void pilot_disable_serial(device_t dev)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_iobase(dev, PNP_IDX_IO0, 0x0000);
+ pnp_set_enable(dev, 0);
+ pnp_exit_ext_func_mode(dev);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 University of Heidelberg
- * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for Univ. Heidelberg
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* PILOT Super I/O is only based on LPC observation done on factory system. */
-
-#define BLUBB_DEV PNP_DEV(port, 0x04)
-
-/*
- * Logical device 4, 5 and 7 are being deactivated. Logical Device 1 seems to
- * be another serial (?), it is also deactivated on the HP machine.
- */
-static void pilot_early_init(device_t dev)
-{
- u16 port = dev >> 8;
-
- print_debug("Using port: ");
- print_debug_hex16(port);
- print_debug("\n");
- pilot_disable_serial(PNP_DEV(port, 0x1));
- print_debug("disable serial 1\n");
-
- pnp_enter_ext_func_mode(dev);
- pnp_set_logical_device(PNP_DEV(port, 0x3));
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, 0x60, 0x0b00);
- pnp_set_iobase(dev, 0x62, 0x0b80);
- pnp_set_iobase(dev, 0x64, 0x0b84);
- pnp_set_iobase(dev, 0x66, 0x0b86);
- pnp_set_enable(dev, 1);
- pnp_exit_ext_func_mode(dev);
-
-/*
- pnp_enter_ext_func_mode(dev);
- pnp_set_logical_device(PNP_DEV(port, 0x3));
- pnp_exit_ext_func_mode(dev);
- pnp_enter_ext_func_mode(dev);
- pnp_set_enable(PNP_DEV(port, 0x3), 0);
- pnp_exit_ext_func_mode(dev);
-*/
-
- pnp_enter_ext_func_mode(dev);
- pnp_set_logical_device(PNP_DEV(port, 0x4));
- pnp_exit_ext_func_mode(dev);
- pnp_enter_ext_func_mode(dev);
- pnp_set_enable( PNP_DEV(port, 0x4), 0);
- pnp_exit_ext_func_mode(dev);
-
- pnp_enter_ext_func_mode(dev);
- pnp_set_logical_device(PNP_DEV(port, 0x5));
- pnp_exit_ext_func_mode(dev);
- pnp_enter_ext_func_mode(dev);
- pnp_set_enable(PNP_DEV(port, 0x5), 0);
- pnp_exit_ext_func_mode(dev);
-
- pnp_enter_ext_func_mode(dev);
- pnp_set_logical_device(PNP_DEV(port, 0x6));
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
- pnp_set_iobase(dev, PNP_IDX_IO1, 0x64);
- pnp_set_irq(dev, PNP_IDX_IRQ0, 1);
- pnp_set_drq(dev, 0x71, 3);
- pnp_set_enable(dev, 0);
- pnp_exit_ext_func_mode(dev);
-
- pnp_enter_ext_func_mode(dev);
- pnp_set_logical_device(PNP_DEV(port, 0xe));
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, 0x70);
- pnp_set_iobase(dev, PNP_IDX_IO1, 0x72);
- pnp_set_irq(dev, PNP_IDX_IRQ0, 8);
- pnp_set_drq(dev, 0x71, 3);
- pnp_set_enable(dev, 0);
- pnp_exit_ext_func_mode(dev);
-
- pnp_enter_ext_func_mode(dev);
- pnp_set_logical_device(PNP_DEV(port, 0x7));
- pnp_exit_ext_func_mode(dev);
- pnp_enter_ext_func_mode(dev);
- pnp_set_enable(PNP_DEV(port, 0x7), 0);
- pnp_exit_ext_func_mode(dev);
-
-/*
- pnp_enter_ext_func_mode(dev);
- pnp_set_logical_device(PNP_DEV(port, 0x8));
- pnp_exit_ext_func_mode(dev);
- pnp_enter_ext_func_mode(dev);
- pnp_set_enable(PNP_DEV(port, 0x8), 0);
- pnp_exit_ext_func_mode(dev);
-
- pnp_enter_ext_func_mode(dev);
- pnp_set_logical_device(PNP_DEV(port, 0x9));
- pnp_exit_ext_func_mode(dev);
- pnp_enter_ext_func_mode(dev);
- pnp_set_enable(PNP_DEV(port, 0x9), 0);
- pnp_exit_ext_func_mode(dev);
-
- pnp_enter_ext_func_mode(dev);
- pnp_set_logical_device(PNP_DEV(port, 0x10));
- pnp_exit_ext_func_mode(dev);
- pnp_enter_ext_func_mode(dev);
- pnp_set_enable(PNP_DEV(port, 0x10), 0);
- pnp_exit_ext_func_mode(dev);
-*/
-}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 University of Heidelberg
- * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for Univ. Heidelberg
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* PILOT Super I/O is only based on LPC observation done on factory system. */
-
-#include <arch/romcc_io.h>
-#include "pilot.h"
-
-/* Pilot uses 0x5A/0xA5 pattern to actiavte deactivate config access. */
-static void pnp_enter_ext_func_mode(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0x5A, port);
-}
-
-static void pnp_exit_ext_func_mode(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0xA5, port);
-}
-
-/* Serial config is a fairly standard procedure. */
-static void pilot_enable_serial(device_t dev, u16 iobase)
-{
- pnp_enter_ext_func_mode(dev);
- pnp_set_logical_device(dev);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
- pnp_exit_ext_func_mode(dev);
-}
-
-static void pilot_disable_serial(device_t dev)
-{
- pnp_enter_ext_func_mode(dev);
- pnp_set_logical_device(dev);
- pnp_set_iobase(dev, PNP_IDX_IO0, 0x0000);
- pnp_set_enable(dev, 0);
- pnp_exit_ext_func_mode(dev);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "fdc37m60x.h"
+
+/* The base address is 0x3f0 or 0x370, depending on the SYSOPT pin. */
+#define SIO_BASE 0x3f0
+#define SIO_INDEX SIO_BASE
+#define SIO_DATA (SIO_BASE + 1)
+
+/* Global configuration registers. */
+#define FDC37M60X_CONFIG_REG_CC 0x02 /* Configure Control. */
+#define FDC37M60X_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
+#define FDC37M60X_CONFIG_POWER_CONTROL 0x22 /* Power Control. */
+#define FDC37M60X_CONFIG_POWER_MGMT 0x23 /* Intelligent Power Mgmt. */
+#define FDC37M60X_CONFIG_OSC 0x24 /* OSC. */
+
+#define FDC37M60X_CONFIGURATION_PORT 0x3f0 /* Write-only. */
+
+/* The content of FDC37M60X_CONFIG_REG_LDN (index 0x07) must be set to the
+ LDN the register belongs to, before you can access the register. */
+static void fdc37m60x_sio_write(uint8_t ldn, u8 index, u8 value)
+{
+ outb(FDC37M60X_CONFIG_REG_LDN, SIO_BASE);
+ outb(ldn, SIO_DATA);
+ outb(index, SIO_BASE);
+ outb(value, SIO_DATA);
+}
+
+/* Enable the peripheral devices on the FDC37M60X Super I/O chip. */
+static void fdc37m60x_enable_serial(device_t dev, u16 iobase)
+{
+ /* (1) Enter the configuration state. */
+ outb(0x55, FDC37M60X_CONFIGURATION_PORT);
+
+ /* (2) Modify the data of configuration registers. */
+
+ /* Power on all devices by setting the respective bit.
+ Bits: 0 (FDC), 3 (PP), 4 (Com1), 5 (Com2). The rest is reserved. */
+ fdc37m60x_sio_write(0x00, FDC37M60X_CONFIG_POWER_CONTROL, 0x39);
+
+ /* Disable intelligent power management. */
+ fdc37m60x_sio_write(0x00, FDC37M60X_CONFIG_POWER_MGMT, 0x00);
+
+ /* Turn on OSC, turn on BRG clock. */
+ fdc37m60x_sio_write(0x00, FDC37M60X_CONFIG_OSC, 0x04);
+
+ /* Configure serial port 1. */
+ fdc37m60x_sio_write(FDC37M60X_SP1, 0x60, 0x03);
+ fdc37m60x_sio_write(FDC37M60X_SP1, 0x61, 0xf8); /* I/O 0x3f8 */
+ fdc37m60x_sio_write(FDC37M60X_SP1, 0x70, 0x04); /* IRQ 4 */
+ fdc37m60x_sio_write(FDC37M60X_SP1, 0xf0, 0x00); /* Normal */
+
+ /* Enable serial port 1. */
+ fdc37m60x_sio_write(FDC37M60X_SP1, 0x30, 0x01);
+
+ /* (3) Exit the configuration state. */
+ outb(0xaa, FDC37M60X_CONFIGURATION_PORT);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/romcc_io.h>
-#include "fdc37m60x.h"
-
-/* The base address is 0x3f0 or 0x370, depending on the SYSOPT pin. */
-#define SIO_BASE 0x3f0
-#define SIO_INDEX SIO_BASE
-#define SIO_DATA (SIO_BASE + 1)
-
-/* Global configuration registers. */
-#define FDC37M60X_CONFIG_REG_CC 0x02 /* Configure Control. */
-#define FDC37M60X_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
-#define FDC37M60X_CONFIG_POWER_CONTROL 0x22 /* Power Control. */
-#define FDC37M60X_CONFIG_POWER_MGMT 0x23 /* Intelligent Power Mgmt. */
-#define FDC37M60X_CONFIG_OSC 0x24 /* OSC. */
-
-#define FDC37M60X_CONFIGURATION_PORT 0x3f0 /* Write-only. */
-
-/* The content of FDC37M60X_CONFIG_REG_LDN (index 0x07) must be set to the
- LDN the register belongs to, before you can access the register. */
-static void fdc37m60x_sio_write(uint8_t ldn, u8 index, u8 value)
-{
- outb(FDC37M60X_CONFIG_REG_LDN, SIO_BASE);
- outb(ldn, SIO_DATA);
- outb(index, SIO_BASE);
- outb(value, SIO_DATA);
-}
-
-/* Enable the peripheral devices on the FDC37M60X Super I/O chip. */
-static void fdc37m60x_enable_serial(device_t dev, u16 iobase)
-{
- /* (1) Enter the configuration state. */
- outb(0x55, FDC37M60X_CONFIGURATION_PORT);
-
- /* (2) Modify the data of configuration registers. */
-
- /* Power on all devices by setting the respective bit.
- Bits: 0 (FDC), 3 (PP), 4 (Com1), 5 (Com2). The rest is reserved. */
- fdc37m60x_sio_write(0x00, FDC37M60X_CONFIG_POWER_CONTROL, 0x39);
-
- /* Disable intelligent power management. */
- fdc37m60x_sio_write(0x00, FDC37M60X_CONFIG_POWER_MGMT, 0x00);
-
- /* Turn on OSC, turn on BRG clock. */
- fdc37m60x_sio_write(0x00, FDC37M60X_CONFIG_OSC, 0x04);
-
- /* Configure serial port 1. */
- fdc37m60x_sio_write(FDC37M60X_SP1, 0x60, 0x03);
- fdc37m60x_sio_write(FDC37M60X_SP1, 0x61, 0xf8); /* I/O 0x3f8 */
- fdc37m60x_sio_write(FDC37M60X_SP1, 0x70, 0x04); /* IRQ 4 */
- fdc37m60x_sio_write(FDC37M60X_SP1, 0xf0, 0x00); /* Normal */
-
- /* Enable serial port 1. */
- fdc37m60x_sio_write(FDC37M60X_SP1, 0x30, 0x01);
-
- /* (3) Exit the configuration state. */
- outb(0xaa, FDC37M60X_CONFIGURATION_PORT);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Pre-RAM driver for SMSC LPC47B272 Super I/O chip. */
+
+#include <arch/romcc_io.h>
+#include "lpc47b272.h"
+
+static void pnp_enter_conf_state(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0x55, port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0xaa, port);
+}
+
+/**
+ * Configure the base I/O port of the specified serial device and enable the
+ * serial device.
+ *
+ * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
+ * @param iobase Processor I/O port address to assign to this serial device.
+ */
+static void lpc47b272_enable_serial(device_t dev, u16 iobase)
+{
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_conf_state(dev);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* Pre-RAM driver for SMSC LPC47B272 Super I/O chip. */
-
-#include <arch/romcc_io.h>
-#include "lpc47b272.h"
-
-static void pnp_enter_conf_state(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0x55, port);
-}
-
-static void pnp_exit_conf_state(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0xaa, port);
-}
-
-/**
- * Configure the base I/O port of the specified serial device and enable the
- * serial device.
- *
- * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
- * @param iobase Processor I/O port address to assign to this serial device.
- */
-static void lpc47b272_enable_serial(device_t dev, u16 iobase)
-{
- pnp_enter_conf_state(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
- pnp_exit_conf_state(dev);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000 AG Electronics Ltd.
+ * Copyright (C) 2003-2004 Linux Networx
+ * Copyright (C) 2004 Tyan
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+static void lpc47b397_gpio_offset_out(u16 iobase, u16 offset, u8 value)
+{
+ outb(value, iobase + offset);
+}
+
+static u8 lpc47b397_gpio_offset_in(u16 iobase, u16 offset)
+{
+ return inb(iobase+offset);
+}
+
+#if 0
+/* For GP60-GP64, GP66-GP85. */
+#define LPC47B397_GPIO_CNTL_INDEX 0x70
+#define LPC47B397_GPIO_CNTL_DATA 0x71
+
+static void lpc47b397_gpio_index_out(u16 iobase, u8 index, u8 value)
+{
+ outb(index, iobase + LPC47B397_GPIO_CNTL_INDEX);
+ outb(value, iobase + LPC47B397_GPIO_CNTL_DATA);
+}
+
+static u8 lpc47b397_gpio_index_in(u16 iobase, u8 index)
+{
+ outb(index, iobase + LPC47B397_GPIO_CNTL_INDEX);
+ return inb(iobase + LPC47B397_GPIO_CNTL_DATA);
+}
+#endif
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000 AG Electronics Ltd.
+ * Copyright (C) 2003-2004 Linux Networx
+ * Copyright (C) 2004 Tyan
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "lpc47b397.h"
+
+static void pnp_enter_conf_state(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0x55, port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0xaa, port);
+}
+
+static void lpc47b397_enable_serial(device_t dev, u16 iobase)
+{
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_conf_state(dev);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- * Copyright (C) 2004 Tyan
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-static void lpc47b397_gpio_offset_out(u16 iobase, u16 offset, u8 value)
-{
- outb(value, iobase + offset);
-}
-
-static u8 lpc47b397_gpio_offset_in(u16 iobase, u16 offset)
-{
- return inb(iobase+offset);
-}
-
-#if 0
-/* For GP60-GP64, GP66-GP85. */
-#define LPC47B397_GPIO_CNTL_INDEX 0x70
-#define LPC47B397_GPIO_CNTL_DATA 0x71
-
-static void lpc47b397_gpio_index_out(u16 iobase, u8 index, u8 value)
-{
- outb(index, iobase + LPC47B397_GPIO_CNTL_INDEX);
- outb(value, iobase + LPC47B397_GPIO_CNTL_DATA);
-}
-
-static u8 lpc47b397_gpio_index_in(u16 iobase, u8 index)
-{
- outb(index, iobase + LPC47B397_GPIO_CNTL_INDEX);
- return inb(iobase + LPC47B397_GPIO_CNTL_DATA);
-}
-#endif
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- * Copyright (C) 2004 Tyan
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/romcc_io.h>
-#include "lpc47b397.h"
-
-static void pnp_enter_conf_state(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0x55, port);
-}
-
-static void pnp_exit_conf_state(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0xaa, port);
-}
-
-static void lpc47b397_enable_serial(device_t dev, u16 iobase)
-{
- pnp_enter_conf_state(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
- pnp_exit_conf_state(dev);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "lpc47m10x.h"
+
+static void pnp_enter_conf_state(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0x55, port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0xaa, port);
+}
+
+/**
+ * Configure the base I/O port of the specified serial device and enable the
+ * serial device.
+ *
+ * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
+ * @param iobase Processor I/O port address to assign to this serial device.
+ */
+static void lpc47m10x_enable_serial(device_t dev, u16 iobase)
+{
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_conf_state(dev);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/romcc_io.h>
-#include "lpc47m10x.h"
-
-static void pnp_enter_conf_state(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0x55, port);
-}
-
-static void pnp_exit_conf_state(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0xaa, port);
-}
-
-/**
- * Configure the base I/O port of the specified serial device and enable the
- * serial device.
- *
- * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
- * @param iobase Processor I/O port address to assign to this serial device.
- */
-static void lpc47m10x_enable_serial(device_t dev, u16 iobase)
-{
- pnp_enter_conf_state(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
- pnp_exit_conf_state(dev);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Pre-RAM driver for the SMSC LPC47M15X Super I/O chip */
+
+#include <arch/romcc_io.h>
+#include "lpc47m15x.h"
+
+static void pnp_enter_conf_state(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0x55, port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0xaa, port);
+}
+
+static inline void lpc47m15x_enable_serial(device_t dev, u16 iobase)
+{
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_conf_state(dev);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* Pre-RAM driver for the SMSC LPC47M15X Super I/O chip */
-
-#include <arch/romcc_io.h>
-#include "lpc47m15x.h"
-
-static void pnp_enter_conf_state(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0x55, port);
-}
-
-static void pnp_exit_conf_state(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0xaa, port);
-}
-
-static inline void lpc47m15x_enable_serial(device_t dev, u16 iobase)
-{
- pnp_enter_conf_state(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
- pnp_exit_conf_state(dev);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Pre-RAM driver for SMSC LPC47N217 Super I/O chip. */
+
+#include <arch/romcc_io.h>
+#include <assert.h>
+#include "lpc47n217.h"
+
+static void pnp_enter_conf_state(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0x55, port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0xaa, port);
+}
+
+/**
+ * Program the base I/O port for the specified logical device.
+ *
+ * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
+ * @param iobase Base I/O port for the logical device.
+ */
+void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase)
+{
+ /* LPC47N217 requires base ports to be a multiple of 4. */
+ ASSERT(!(iobase & 0x3));
+
+ switch(dev & 0xFF) {
+ case LPC47N217_PP:
+ pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
+ break;
+ case LPC47N217_SP1:
+ pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
+ break;
+ case LPC47N217_SP2:
+ pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * Enable or disable the specified logical device.
+ *
+ * Technically, a full disable requires setting the device's base I/O port
+ * below 0x100. We don't do that here, because we don't have access to a data
+ * structure that specifies what the 'real' base port is (when asked to enable
+ * the device). Also the function is used only to disable the device while its
+ * true base port is programmed (see lpc47n217_enable_serial() below).
+ *
+ * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
+ * @param enable 0 to disable, anythig else to enable.
+ */
+void lpc47n217_pnp_set_enable(device_t dev, int enable)
+{
+ u8 power_register = 0, power_mask = 0, current_power, new_power;
+
+ switch(dev & 0xFF) {
+ case LPC47N217_PP:
+ power_register = 0x01;
+ power_mask = 0x04;
+ break;
+ case LPC47N217_SP1:
+ power_register = 0x02;
+ power_mask = 0x08;
+ break;
+ case LPC47N217_SP2:
+ power_register = 0x02;
+ power_mask = 0x80;
+ break;
+ default:
+ return;
+ }
+
+ current_power = pnp_read_config(dev, power_register);
+ new_power = current_power & ~power_mask; /* Disable by default. */
+ if (enable)
+ new_power |= power_mask; /* Enable. */
+ pnp_write_config(dev, power_register, new_power);
+}
+
+/**
+ * Configure the base I/O port of the specified serial device and enable the
+ * serial device.
+ *
+ * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
+ * @param iobase Processor I/O port address to assign to this serial device.
+ */
+static void lpc47n217_enable_serial(device_t dev, u16 iobase)
+{
+ /*
+ * NOTE: Cannot use pnp_set_XXX() here because they assume chip
+ * support for logical devices, which the LPC47N217 doesn't have.
+ */
+ pnp_enter_conf_state(dev);
+ lpc47n217_pnp_set_enable(dev, 0);
+ lpc47n217_pnp_set_iobase(dev, iobase);
+ lpc47n217_pnp_set_enable(dev, 1);
+ pnp_exit_conf_state(dev);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* Pre-RAM driver for SMSC LPC47N217 Super I/O chip. */
-
-#include <arch/romcc_io.h>
-#include <assert.h>
-#include "lpc47n217.h"
-
-static void pnp_enter_conf_state(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0x55, port);
-}
-
-static void pnp_exit_conf_state(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0xaa, port);
-}
-
-/**
- * Program the base I/O port for the specified logical device.
- *
- * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
- * @param iobase Base I/O port for the logical device.
- */
-void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase)
-{
- /* LPC47N217 requires base ports to be a multiple of 4. */
- ASSERT(!(iobase & 0x3));
-
- switch(dev & 0xFF) {
- case LPC47N217_PP:
- pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
- break;
- case LPC47N217_SP1:
- pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
- break;
- case LPC47N217_SP2:
- pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
- break;
- default:
- break;
- }
-}
-
-/**
- * Enable or disable the specified logical device.
- *
- * Technically, a full disable requires setting the device's base I/O port
- * below 0x100. We don't do that here, because we don't have access to a data
- * structure that specifies what the 'real' base port is (when asked to enable
- * the device). Also the function is used only to disable the device while its
- * true base port is programmed (see lpc47n217_enable_serial() below).
- *
- * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
- * @param enable 0 to disable, anythig else to enable.
- */
-void lpc47n217_pnp_set_enable(device_t dev, int enable)
-{
- u8 power_register = 0, power_mask = 0, current_power, new_power;
-
- switch(dev & 0xFF) {
- case LPC47N217_PP:
- power_register = 0x01;
- power_mask = 0x04;
- break;
- case LPC47N217_SP1:
- power_register = 0x02;
- power_mask = 0x08;
- break;
- case LPC47N217_SP2:
- power_register = 0x02;
- power_mask = 0x80;
- break;
- default:
- return;
- }
-
- current_power = pnp_read_config(dev, power_register);
- new_power = current_power & ~power_mask; /* Disable by default. */
- if (enable)
- new_power |= power_mask; /* Enable. */
- pnp_write_config(dev, power_register, new_power);
-}
-
-/**
- * Configure the base I/O port of the specified serial device and enable the
- * serial device.
- *
- * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
- * @param iobase Processor I/O port address to assign to this serial device.
- */
-static void lpc47n217_enable_serial(device_t dev, u16 iobase)
-{
- /*
- * NOTE: Cannot use pnp_set_XXX() here because they assume chip
- * support for logical devices, which the LPC47N217 doesn't have.
- */
- pnp_enter_conf_state(dev);
- lpc47n217_pnp_set_enable(dev, 0);
- lpc47n217_pnp_set_iobase(dev, iobase);
- lpc47n217_pnp_set_enable(dev, 1);
- pnp_exit_conf_state(dev);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Pre-RAM driver for SMSC LPC47N227 Super I/O chip. */
+
+#include <arch/romcc_io.h>
+#include "lpc47n227.h"
+
+static void pnp_enter_conf_state(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0x55, port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0xaa, port);
+}
+
+/**
+ * Program the base I/O port for the specified logical device.
+ *
+ * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
+ * @param iobase Base I/O port for the logical device.
+ */
+void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase)
+{
+ /* LPC47N227 requires base ports to be a multiple of 4. */
+ ASSERT(!(iobase & 0x3));
+
+ switch (dev & 0xFF) {
+ case LPC47N227_PP:
+ pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
+ break;
+ case LPC47N227_SP1:
+ pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
+ break;
+ case LPC47N227_SP2:
+ pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * Enable or disable the specified logical device.
+ *
+ * Technically, a full disable requires setting the device's base I/O port
+ * below 0x100. We don't do that here, because we don't have access to a data
+ * structure that specifies what the 'real' base port is (when asked to enable
+ * the device). Also the function is used only to disable the device while its
+ * true base port is programmed (see lpc47n227_enable_serial() below).
+ *
+ * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
+ * @param enable 0 to disable, anythig else to enable.
+ */
+void lpc47n227_pnp_set_enable(device_t dev, int enable)
+{
+ u8 power_register = 0, power_mask = 0, current_power, new_power;
+
+ switch (dev & 0xFF) {
+ case LPC47N227_PP:
+ power_register = 0x01;
+ power_mask = 0x04;
+ break;
+ case LPC47N227_SP1:
+ power_register = 0x02;
+ power_mask = 0x08;
+ break;
+ case LPC47N227_SP2:
+ power_register = 0x02;
+ power_mask = 0x80;
+ break;
+ default:
+ return;
+ }
+
+ current_power = pnp_read_config(dev, power_register);
+ new_power = current_power & ~power_mask; /* Disable by default. */
+ if (enable)
+ new_power |= power_mask; /* Enable. */
+ pnp_write_config(dev, power_register, new_power);
+}
+
+/**
+ * Configure the base I/O port of the specified serial device and enable the
+ * serial device.
+ *
+ * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
+ * @param iobase Processor I/O port address to assign to this serial device.
+ */
+static void lpc47n227_enable_serial(device_t dev, u16 iobase)
+{
+ /*
+ * NOTE: Cannot use pnp_set_XXX() here because they assume chip
+ * support for logical devices, which the LPC47N227 doesn't have.
+ */
+ pnp_enter_conf_state(dev);
+ lpc47n227_pnp_set_enable(dev, 0);
+ lpc47n227_pnp_set_iobase(dev, iobase);
+ lpc47n227_pnp_set_enable(dev, 1);
+ pnp_exit_conf_state(dev);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 Digital Design Corporation
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* Pre-RAM driver for SMSC LPC47N227 Super I/O chip. */
-
-#include <arch/romcc_io.h>
-#include "lpc47n227.h"
-
-static void pnp_enter_conf_state(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0x55, port);
-}
-
-static void pnp_exit_conf_state(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0xaa, port);
-}
-
-/**
- * Program the base I/O port for the specified logical device.
- *
- * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
- * @param iobase Base I/O port for the logical device.
- */
-void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase)
-{
- /* LPC47N227 requires base ports to be a multiple of 4. */
- ASSERT(!(iobase & 0x3));
-
- switch (dev & 0xFF) {
- case LPC47N227_PP:
- pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
- break;
- case LPC47N227_SP1:
- pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
- break;
- case LPC47N227_SP2:
- pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
- break;
- default:
- break;
- }
-}
-
-/**
- * Enable or disable the specified logical device.
- *
- * Technically, a full disable requires setting the device's base I/O port
- * below 0x100. We don't do that here, because we don't have access to a data
- * structure that specifies what the 'real' base port is (when asked to enable
- * the device). Also the function is used only to disable the device while its
- * true base port is programmed (see lpc47n227_enable_serial() below).
- *
- * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
- * @param enable 0 to disable, anythig else to enable.
- */
-void lpc47n227_pnp_set_enable(device_t dev, int enable)
-{
- u8 power_register = 0, power_mask = 0, current_power, new_power;
-
- switch (dev & 0xFF) {
- case LPC47N227_PP:
- power_register = 0x01;
- power_mask = 0x04;
- break;
- case LPC47N227_SP1:
- power_register = 0x02;
- power_mask = 0x08;
- break;
- case LPC47N227_SP2:
- power_register = 0x02;
- power_mask = 0x80;
- break;
- default:
- return;
- }
-
- current_power = pnp_read_config(dev, power_register);
- new_power = current_power & ~power_mask; /* Disable by default. */
- if (enable)
- new_power |= power_mask; /* Enable. */
- pnp_write_config(dev, power_register, new_power);
-}
-
-/**
- * Configure the base I/O port of the specified serial device and enable the
- * serial device.
- *
- * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
- * @param iobase Processor I/O port address to assign to this serial device.
- */
-static void lpc47n227_enable_serial(device_t dev, u16 iobase)
-{
- /*
- * NOTE: Cannot use pnp_set_XXX() here because they assume chip
- * support for logical devices, which the LPC47N227 doesn't have.
- */
- pnp_enter_conf_state(dev);
- lpc47n227_pnp_set_enable(dev, 0);
- lpc47n227_pnp_set_iobase(dev, iobase);
- lpc47n227_pnp_set_enable(dev, 1);
- pnp_exit_conf_state(dev);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include <device/pnp_def.h>
+
+/* All known/supported SMSC Super I/Os have the same logical device IDs
+ * for the serial ports (COM1, COM2).
+ */
+#define SMSCSUPERIO_SP1 4 /* Com1 */
+#define SMSCSUPERIO_SP2 5 /* Com2 */
+
+/**
+ * Enable the specified serial port.
+ *
+ * @param dev The device to use.
+ * @param iobase The I/O base of the serial port (usually 0x3f8/0x2f8).
+ */
+static inline void smscsuperio_enable_serial(device_t dev, u16 iobase)
+{
+ u16 port = dev >> 8;
+
+ outb(0x55, port); /* Enter the configuration state. */
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ outb(0xaa, port); /* Exit the configuration state. */
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/romcc_io.h>
-#include <device/pnp_def.h>
-
-/* All known/supported SMSC Super I/Os have the same logical device IDs
- * for the serial ports (COM1, COM2).
- */
-#define SMSCSUPERIO_SP1 4 /* Com1 */
-#define SMSCSUPERIO_SP2 5 /* Com2 */
-
-/**
- * Enable the specified serial port.
- *
- * @param dev The device to use.
- * @param iobase The I/O base of the serial port (usually 0x3f8/0x2f8).
- */
-static inline void smscsuperio_enable_serial(device_t dev, u16 iobase)
-{
- u16 port = dev >> 8;
-
- outb(0x55, port); /* Enter the configuration state. */
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
- outb(0xaa, port); /* Exit the configuration state. */
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include <stdint.h>
+#include "w83627dhg.h"
+
+static void pnp_enter_ext_func_mode(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0x87, port);
+ outb(0x87, port);
+}
+
+static void pnp_exit_ext_func_mode(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0xaa, port);
+}
+
+static void w83627dhg_enable_serial(device_t dev, u16 iobase)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_ext_func_mode(dev);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/romcc_io.h>
-#include <stdint.h>
-#include "w83627dhg.h"
-
-static void pnp_enter_ext_func_mode(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0x87, port);
- outb(0x87, port);
-}
-
-static void pnp_exit_ext_func_mode(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0xaa, port);
-}
-
-static void w83627dhg_enable_serial(device_t dev, u16 iobase)
-{
- pnp_enter_ext_func_mode(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
- pnp_exit_ext_func_mode(dev);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/romcc_io.h>
+#include "w83627ehg.h"
+
+void w83627ehg_disable_dev(device_t dev)
+{
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+}
+
+void w83627ehg_enable_dev(device_t dev, u16 iobase)
+{
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "w83627ehg.h"
+
+static void pnp_enter_ext_func_mode(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0x87, port);
+ outb(0x87, port);
+}
+
+static void pnp_exit_ext_func_mode(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0xaa, port);
+}
+
+void w83627ehg_enable_serial(device_t dev, u16 iobase)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_ext_func_mode(dev);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdint.h>
-#include <arch/romcc_io.h>
-#include "w83627ehg.h"
-
-void w83627ehg_disable_dev(device_t dev)
-{
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
-}
-
-void w83627ehg_enable_dev(device_t dev, u16 iobase)
-{
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
-}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/romcc_io.h>
-#include "w83627ehg.h"
-
-static void pnp_enter_ext_func_mode(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0x87, port);
- outb(0x87, port);
-}
-
-static void pnp_exit_ext_func_mode(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0xaa, port);
-}
-
-void w83627ehg_enable_serial(device_t dev, u16 iobase)
-{
- pnp_enter_ext_func_mode(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
- pnp_exit_ext_func_mode(dev);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000 AG Electronics Ltd.
+ * Copyright 2003-2004 Linux Networx
+ * Copyright 2004 Tyan
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "w83627hf.h"
+
+void w83627hf_disable_dev(device_t dev)
+{
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+}
+
+void w83627hf_enable_dev(device_t dev, u16 iobase)
+{
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000 AG Electronics Ltd.
+ * Copyright (C) 2003-2004 Linux Networx
+ * Copyright (C) 2004 Tyan
+ * Copyright (C) 2010 Win Enterprises (anishp@win-ent.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "w83627hf.h"
+
+static void pnp_enter_ext_func_mode(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0x87, port);
+ outb(0x87, port);
+}
+
+static void pnp_exit_ext_func_mode(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0xaa, port);
+}
+
+void w83627hf_enable_serial(device_t dev, u16 iobase)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_ext_func_mode(dev);
+}
+
+void w83627hf_set_clksel_48(device_t dev)
+{
+ u8 reg8;
+
+ pnp_enter_ext_func_mode(dev);
+ reg8 = pnp_read_config(dev, 0x24);
+ reg8 |= (1 << 6); /* Set CLKSEL (clock input on pin 1) to 48MHz. */
+ pnp_write_config(dev, 0x24, reg8);
+ pnp_exit_ext_func_mode(dev);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright 2003-2004 Linux Networx
- * Copyright 2004 Tyan
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/romcc_io.h>
-#include "w83627hf.h"
-
-void w83627hf_disable_dev(device_t dev)
-{
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
-}
-
-void w83627hf_enable_dev(device_t dev, u16 iobase)
-{
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
-}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- * Copyright (C) 2004 Tyan
- * Copyright (C) 2010 Win Enterprises (anishp@win-ent.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/romcc_io.h>
-#include "w83627hf.h"
-
-static void pnp_enter_ext_func_mode(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0x87, port);
- outb(0x87, port);
-}
-
-static void pnp_exit_ext_func_mode(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0xaa, port);
-}
-
-void w83627hf_enable_serial(device_t dev, u16 iobase)
-{
- pnp_enter_ext_func_mode(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
- pnp_exit_ext_func_mode(dev);
-}
-
-void w83627hf_set_clksel_48(device_t dev)
-{
- u8 reg8;
-
- pnp_enter_ext_func_mode(dev);
- reg8 = pnp_read_config(dev, 0x24);
- reg8 |= (1 << 6); /* Set CLKSEL (clock input on pin 1) to 48MHz. */
- pnp_write_config(dev, 0x24, reg8);
- pnp_exit_ext_func_mode(dev);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000 AG Electronics Ltd.
+ * Copyright (C) 2003-2004 Linux Networx
+ * Copyright (C) 2004 Tyan
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "w83627thg.h"
+
+static void pnp_enter_ext_func_mode(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0x87, port);
+ outb(0x87, port);
+}
+
+static void pnp_exit_ext_func_mode(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0xaa, port);
+}
+
+static void inline w83627thg_enable_serial(device_t dev, u16 iobase)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_ext_func_mode(dev);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- * Copyright (C) 2004 Tyan
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/romcc_io.h>
-#include "w83627thg.h"
-
-static void pnp_enter_ext_func_mode(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0x87, port);
- outb(0x87, port);
-}
-
-static void pnp_exit_ext_func_mode(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0xaa, port);
-}
-
-static void inline w83627thg_enable_serial(device_t dev, u16 iobase)
-{
- pnp_enter_ext_func_mode(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
- pnp_exit_ext_func_mode(dev);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Dynon Avionics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include <stdint.h>
+#include "w83627uhg.h"
+
+static void pnp_enter_ext_func_mode(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0x87, port);
+ outb(0x87, port);
+}
+
+static void pnp_exit_ext_func_mode(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0xaa, port);
+}
+
+/** Set the input clock to 24 or 48 MHz. */
+static void w83627uhg_set_input_clk_sel(device_t dev, u8 speed_24mhz)
+{
+ u8 value;
+
+ value = pnp_read_config(dev, 0x24);
+ value &= ~(1 << 6);
+ if (!speed_24mhz)
+ value |= (1 << 6);
+ pnp_write_config(dev, 0x24, value);
+}
+
+static void w83627uhg_enable_serial(device_t dev, u16 iobase)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_ext_func_mode(dev);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 Dynon Avionics
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/romcc_io.h>
-#include <stdint.h>
-#include "w83627uhg.h"
-
-static void pnp_enter_ext_func_mode(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0x87, port);
- outb(0x87, port);
-}
-
-static void pnp_exit_ext_func_mode(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0xaa, port);
-}
-
-/** Set the input clock to 24 or 48 MHz. */
-static void w83627uhg_set_input_clk_sel(device_t dev, u8 speed_24mhz)
-{
- u8 value;
-
- value = pnp_read_config(dev, 0x24);
- value &= ~(1 << 6);
- if (!speed_24mhz)
- value |= (1 << 6);
- pnp_write_config(dev, 0x24, value);
-}
-
-static void w83627uhg_enable_serial(device_t dev, u16 iobase)
-{
- pnp_enter_ext_func_mode(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
- pnp_exit_ext_func_mode(dev);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Sean Nelson <snelson@nmt.edu>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/romcc_io.h>
+#include "w83697hf.h"
+
+static void pnp_enter_ext_func_mode(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0x87, port);
+ outb(0x87, port);
+}
+
+static void pnp_exit_ext_func_mode(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0xaa, port);
+}
+
+static void w83697hf_set_clksel_48(device_t dev)
+{
+ u8 reg8;
+
+ pnp_enter_ext_func_mode(dev);
+ reg8 = pnp_read_config(dev, 0x24);
+ reg8 |= (1 << 6); /* Set the clock input to 48MHz. */
+ pnp_write_config(dev, 0x24, reg8);
+ pnp_exit_ext_func_mode(dev);
+}
+
+static void w83697hf_enable_serial(device_t dev, u16 iobase)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_ext_func_mode(dev);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Sean Nelson <snelson@nmt.edu>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdint.h>
-#include <arch/romcc_io.h>
-#include "w83697hf.h"
-
-static void pnp_enter_ext_func_mode(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0x87, port);
- outb(0x87, port);
-}
-
-static void pnp_exit_ext_func_mode(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0xaa, port);
-}
-
-static void w83697hf_set_clksel_48(device_t dev)
-{
- u8 reg8;
-
- pnp_enter_ext_func_mode(dev);
- reg8 = pnp_read_config(dev, 0x24);
- reg8 |= (1 << 6); /* Set the clock input to 48MHz. */
- pnp_write_config(dev, 0x24, reg8);
- pnp_exit_ext_func_mode(dev);
-}
-
-static void w83697hf_enable_serial(device_t dev, u16 iobase)
-{
- pnp_enter_ext_func_mode(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
- pnp_exit_ext_func_mode(dev);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "w83977f.h"
+
+static void pnp_enter_ext_func_mode(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0x87, port);
+ outb(0x87, port);
+}
+
+static void pnp_exit_ext_func_mode(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0xaa, port);
+}
+
+static void w83977f_enable_serial(device_t dev, u16 iobase)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_ext_func_mode(dev);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/romcc_io.h>
-#include "w83977f.h"
-
-static void pnp_enter_ext_func_mode(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0x87, port);
- outb(0x87, port);
-}
-
-static void pnp_exit_ext_func_mode(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0xaa, port);
-}
-
-static void w83977f_enable_serial(device_t dev, u16 iobase)
-{
- pnp_enter_ext_func_mode(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
- pnp_exit_ext_func_mode(dev);
-}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000 AG Electronics Ltd.
+ * Copyright (C) 2003-2004 Linux Networx
+ * Copyright (C) 2004 Tyan
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "w83977tf.h"
+
+static void pnp_enter_ext_func_mode(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0x87, port);
+ outb(0x87, port);
+}
+
+static void pnp_exit_ext_func_mode(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0xaa, port);
+}
+
+static void w83977tf_enable_serial(device_t dev, u16 iobase)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_ext_func_mode(dev);
+}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- * Copyright (C) 2004 Tyan
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/romcc_io.h>
-#include "w83977tf.h"
-
-static void pnp_enter_ext_func_mode(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0x87, port);
- outb(0x87, port);
-}
-
-static void pnp_exit_ext_func_mode(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0xaa, port);
-}
-
-static void w83977tf_enable_serial(device_t dev, u16 iobase)
-{
- pnp_enter_ext_func_mode(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
- pnp_exit_ext_func_mode(dev);
-}
projects / coreboot.git / commitdiff