Report GSE chipset and warn if the code has been compiled for the wrong chipset.

It would be nicer to unify the code so that it does all detection at runtime
instead of compile time (but that would also significantly increase code size)
so if someone else wants to give it a shot...

Change-Id: Idc67bdf7a6ff2b78dc8fc67a0da5ae7a4c0a3bf0
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/184
Tested-by: build bot (Jenkins)

diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 21efc37a53929be4b90cd4cbb5abf3c4f342ebfa..197c58fce5e7fa63c864b1fb12ee7ec03406182c 100644 (file)
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -42,7 +42,7 @@ static void i945m_detect_chipset(void)
                printk(BIOS_INFO, "Mobile Intel(R) 82945GM/GME Express");
                break;
        case 2:
-               printk(BIOS_INFO, "Mobile Intel(R) 82945GMS/GU Express");
+               printk(BIOS_INFO, "Mobile Intel(R) 82945GMS/GU/GSE Express");
                break;
        case 3:
                printk(BIOS_INFO, "Mobile Intel(R) 82945PM Express");
@@ -91,6 +91,9 @@ static void i945m_detect_chipset(void)
                printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8);      /* Others reserved. */
        }
        printk(BIOS_DEBUG, "\n");
+#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
+       printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n");
+#endif
 }
 
 static void i945_detect_chipset(void)
@@ -137,6 +140,9 @@ static void i945_detect_chipset(void)
                printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8);      /* Others reserved. */
        }
        printk(BIOS_DEBUG, "\n");
+#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
+       printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n");
+#endif
 }
 
 static void i945_setup_bars(void)