In the bootblock, 4MB of ROM are mapped instead of the
default 1MB
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5580
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
config SOUTHBRIDGE_BROADCOM_BCM5785
bool
+ select HAVE_HARD_RESET
+
+config BOOTBLOCK_SOUTHBRIDGE_INIT
+ string
+ default "southbridge/broadcom/bcm5785/bootblock.c"
+ depends on SOUTHBRIDGE_BROADCOM_BCM5785
*/
#include <reset.h>
-static void bcm5785_enable_rom(void)
-{
- unsigned char byte;
- device_t addr;
-
- /* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */
- /* Locate the BCM 5785 SB PCI Main */
- addr = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); // 0x0201?
-
- /* Set the 4MB enable bit bit */
- byte = pci_read_config8(addr, 0x41);
- byte |= 0x0e;
- pci_write_config8(addr, 0x41, byte);
-}
+#include "bcm5785_enable_rom.c"
static void bcm5785_enable_lpc(void)
{
--- /dev/null
+static void bcm5785_enable_rom(void)
+{
+ unsigned char byte;
+ device_t addr;
+
+ /* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */
+ /* Locate the BCM 5785 SB PCI Main */
+ addr = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); // 0x0201?
+
+ /* Set the 4MB enable bit bit */
+ byte = pci_read_config8(addr, 0x41);
+ byte |= 0x0e;
+ pci_write_config8(addr, 0x41, byte);
+}
--- /dev/null
+#include "bcm5785_enable_rom.c"
+
+static void bootblock_southbridge_init(void) {
+ bcm5785_enable_rom();
+}