Move several i945 config #defines from romstage.c to Kconfig.
authorPatrick Georgi <patrick.georgi@coresystems.de>
Fri, 1 Oct 2010 08:02:45 +0000 (08:02 +0000)
committerPatrick Georgi <patrick.georgi@coresystems.de>
Fri, 1 Oct 2010 08:02:45 +0000 (08:02 +0000)
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

12 files changed:
src/mainboard/getac/p470/Kconfig
src/mainboard/getac/p470/romstage.c
src/mainboard/ibase/mb899/Kconfig
src/mainboard/ibase/mb899/romstage.c
src/mainboard/intel/d945gclf/Kconfig
src/mainboard/intel/d945gclf/romstage.c
src/mainboard/kontron/986lcd-m/Kconfig
src/mainboard/kontron/986lcd-m/romstage.c
src/mainboard/roda/rk886ex/Kconfig
src/mainboard/roda/rk886ex/romstage.c
src/northbridge/intel/i945/Kconfig
src/northbridge/intel/i945/raminit.c

index 8085fd62419dee9509cf50303e8e29e577fb5ab8..f3a80cf8d2f54e1cb065681186221fe46da1105a 100644 (file)
@@ -43,6 +43,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select CACHE_AS_RAM
        select GFXUMA
        select TINY_BOOTBLOCK
+       select I945GM
+       select CHANNEL_XOR_RANDOMIZATION
 
 config MAINBOARD_DIR
        string
index 0809926c704ecaf28cbd43f27c74e34f34c5e643..8a39d997fa2599aeee08319d97fa30d98b5ec659 100644 (file)
  * MA 02110-1301 USA
  */
 
-/* Configuration of the i945 driver */
-#define CHIPSET_I945GM 1
-#define CHANNEL_XOR_RANDOMIZATION 1
-
 #include <stdint.h>
 #include <string.h>
 #include <arch/io.h>
index e340d52ee41395c1d1362f451bdf69da553ad112..26bd6c0b8fe5441529e7d25509c6beb0ce76f225 100644 (file)
@@ -20,6 +20,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select CACHE_AS_RAM
        select GFXUMA
        select TINY_BOOTBLOCK
+       select I945GM
+       select CHANNEL_XOR_RANDOMIZATION
 
 config MAINBOARD_DIR
        string
index 4c953d7ab12c75319c350c472840bbba017e9191..53750dfc080a2ff1efb8204b8b7daba22c27ddbe 100644 (file)
 
 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
 
-/* Configuration of the i945 driver */
-#define CHIPSET_I945GM 1
-//#define OVERRIDE_CLOCK_DISABLE 1
-#define CHANNEL_XOR_RANDOMIZATION 1
-
 #include <stdint.h>
 #include <string.h>
 #include <arch/io.h>
index 6db43590171043fb92d8c2d5f840b1ca475b55f2..f4f22a8b6ec5fcc8f4742f4f112bd8eb29fb16bc 100644 (file)
@@ -40,6 +40,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select BOARD_ROMSIZE_KB_512
        select GFXUMA
        select TINY_BOOTBLOCK
+       select I945GC
+       select CHANNEL_XOR_RANDOMIZATION
 
 config MAINBOARD_DIR
        string
index 337d8567586704aa206823899fd72ea80db4792d..dd6f3836b8cadc5f37cea8921a092755cf85ea5c 100644 (file)
 
 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
 
-/* Configuration of the i945 driver */
-#define CHIPSET_I945GC 1
-#define CHANNEL_XOR_RANDOMIZATION 1
-
 #include <stdint.h>
 #include <string.h>
 #include <arch/io.h>
index 5f745ebe9ec8c71955ec80a714d0ae6ef653cc72..e3ca6a5265e6e3a29a544525a433d552ccc57910 100644 (file)
@@ -20,6 +20,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select CACHE_AS_RAM
        select GFXUMA
        select TINY_BOOTBLOCK
+       select CHANNEL_XOR_RANDOMIZATION
+       select I945GM
+       select OVERRIDE_CLOCK_DISABLE
 
 config MAINBOARD_DIR
        string
index e400feea472280b603c46d7e09ec5a4a96626ab2..c6ea1b10d6945878f61293180bd12bbb7b04a566 100644 (file)
 
 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
 
-/* Configuration of the i945 driver */
-#define CHIPSET_I945GM 1
-/* Usually system firmware turns off system memory clock signals to
- * unused SO-DIMM slots to reduce EMI and power consumption.
- * However, the Kontron 986LCD-M does not like unused clock signals to
- * be disabled. If other similar mainboard occur, it would make sense
- * to make this an entry in the sysinfo structure, and pre-initialize that
- * structure in the mainboard's romstage.c main() function. For now a
- * #define will do.
- */
-#define OVERRIDE_CLOCK_DISABLE 1
-#define CHANNEL_XOR_RANDOMIZATION 1
-
 #include <stdint.h>
 #include <string.h>
 #include <arch/io.h>
index 29ae5d036db3e6e6fd38b89758fcc78dd11d8895..8c951ead9f5828c2cf9c2758deafc091dd4403d4 100644 (file)
@@ -19,6 +19,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select HAVE_ACPI_TABLES
        select HAVE_ACPI_RESUME
        select BOARD_ROMSIZE_KB_1024
+       select I945GM
+       select CHANNEL_XOR_RANDOMIZATION
 
 config MAINBOARD_DIR
        string
@@ -56,4 +58,8 @@ config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
        hex
        default 0x6886
 
+config MAXIMUM_SUPPORTED_FREQUENCY
+       int
+       default 400
+
 endif # BOARD_RODA_RK886EX
index 1fdcd0b7bac9b03e915cf21dc63f1b623c2ac08e..98ebadbc22bcc80ac6d34602de5f4ca5782c684d 100644 (file)
 
 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
 
-/* Configuration of the i945 driver */
-#define CHIPSET_I945GM 1
-#define CHANNEL_XOR_RANDOMIZATION 1
-// Rocky freezing temperature settings:
-#define MAXIMUM_SUPPORTED_FREQUENCY 400
-
 #include <stdint.h>
 #include <string.h>
 #include <arch/io.h>
index 952bd9ed6855fdf770551551feb579c59ad85fe2..cee1a8745de3bfc5dabeaa3dbfd47767a3577538 100644 (file)
@@ -26,3 +26,41 @@ config FALLBACK_VGA_BIOS_ID
        default "8086,27a2"
        depends on NORTHBRIDGE_INTEL_I945
 
+choice
+       default I945GM
+       depends on NORTHBRIDGE_INTEL_I945
+       help
+         Different i945 variants require slightly different setup.
+
+config I945GM
+       bool "i945GM (Mobile) chipset"
+
+config I945GC
+       bool "i945GC chipset"
+
+endchoice
+
+config CHANNEL_XOR_RANDOMIZATION
+       bool
+       default n
+       depends on NORTHBRIDGE_INTEL_I945
+
+config OVERRIDE_CLOCK_DISABLE
+       bool
+       default n
+       depends on NORTHBRIDGE_INTEL_I945
+       help
+         Usually system firmware turns off system memory clock
+         signals to unused SO-DIMM slots to reduce EMI and power
+         consumption.
+         However, some boards do not like unused clock signals to
+         be disabled.
+
+config MAXIMUM_SUPPORTED_FREQUENCY
+       int
+       default 0
+       depends on NORTHBRIDGE_INTEL_I945
+       help
+         If non-zero, this designates the maximum DDR frequency
+         the board supports, despite what the chipset should be
+         capable of.
index 424fd2b6e9f97e9a1ed9fb6bbd0053714b140729..50cab4929db1cf767aff596eff57fb980efc073e 100644 (file)
@@ -90,7 +90,7 @@ static void sdram_dump_mchbar_registers(void)
 static int memclk(void)
 {
        int offset = 0;
-#ifdef CHIPSET_I945GM
+#if CONFIG_I945GM
        offset++;
 #endif
        switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) {
@@ -102,7 +102,7 @@ static int memclk(void)
        return -1;
 }
 
-#ifdef CHIPSET_I945GM
+#if CONFIG_I945GM
 static int fsbclk(void)
 {
        switch (MCHBAR32(CLKCFG) & 7) {
@@ -114,7 +114,7 @@ static int fsbclk(void)
        return -1;
 }
 #endif
-#ifdef CHIPSET_I945GC
+#if CONFIG_I945GC
 static int fsbclk(void)
 {
        switch (MCHBAR32(CLKCFG) & 7) {
@@ -131,8 +131,8 @@ static int sdram_capabilities_max_supported_memory_frequency(void)
 {
        u32 reg32;
 
-#ifdef MAXIMUM_SUPPORTED_FREQUENCY
-       return MAXIMUM_SUPPORTED_FREQUENCY;
+#if CONFIG_MAXIMUM_SUPPORTED_FREQUENCY
+       return CONFIG_MAXIMUM_SUPPORTED_FREQUENCY;
 #endif
 
        reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4); /* CAPID0 + 4 */
@@ -1045,7 +1045,7 @@ static const u32 *slew_group_lookup(int dual_channel, int index)
        return nc;
 }
 
-#ifdef CHIPSET_I945GM
+#if CONFIG_I945GM
 /* Strength multiplier tables */
 static const u8 dual_channel_strength_multiplier[] = {
        0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
@@ -1101,7 +1101,7 @@ static const u8 single_channel_strength_multiplier[] = {
        0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11
 };
 #endif
-#ifdef CHIPSET_I945GC
+#if CONFIG_I945GC
 static const u8 dual_channel_strength_multiplier[] = {
        0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
        0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
@@ -2155,7 +2155,7 @@ static void sdram_program_clock_crossing(void)
        /**
         * We add the indices according to our clocks from CLKCFG.
         */
-#ifdef CHIPSET_I945GM
+#if CONFIG_I945GM
        static const u32 data_clock_crossing[] = {
                0x00100401, 0x00000000, /* DDR400 FSB400 */
                0xffffffff, 0xffffffff, /*  nonexistant  */
@@ -2201,7 +2201,7 @@ static void sdram_program_clock_crossing(void)
        };
 
 #endif
-#ifdef CHIPSET_I945GC
+#if CONFIG_I945GC
        /* i945 G/P */
        static const u32 data_clock_crossing[] = {
                0xffffffff, 0xffffffff, /*  nonexistant  */
@@ -2420,7 +2420,7 @@ static void sdram_post_jedec_initialization(struct sys_info *sysinfo)
        if (sysinfo->interleaved) {
 
                reg32 = MCHBAR32(DCC);
-#if CHANNEL_XOR_RANDOMIZATION
+#if CONFIG_CHANNEL_XOR_RANDOMIZATION
                reg32 &= ~(1 << 10);
                reg32 |= (1 << 9);
 #else
@@ -2792,10 +2792,10 @@ static void sdram_enable_memory_clocks(struct sys_info *sysinfo)
 {
        u8 clocks[2] = { 0, 0 };
 
-#ifdef CHIPSET_I945GM
+#if CONFIG_I945GM
 #define CLOCKS_WIDTH 2
 #endif
-#ifdef CHIPSET_I945GC
+#if CONFIG_I945GC
 #define CLOCKS_WIDTH 3
 #endif
        if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED)
@@ -2810,15 +2810,11 @@ static void sdram_enable_memory_clocks(struct sys_info *sysinfo)
        if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
                clocks[1] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH;
 
-#ifdef OVERRIDE_CLOCK_DISABLE
+#if CONFIG_OVERRIDE_CLOCK_DISABLE
        /* Usually system firmware turns off system memory clock signals
         * to unused SO-DIMM slots to reduce EMI and power consumption.
         * However, the Kontron 986LCD-M does not like unused clock
         * signals to be disabled.
-        * If other similar mainboard occur, it would make sense to make
-        * this an entry in the sysinfo structure, and pre-initialize that
-        * structure in the mainboard's romstage.c main() function.
-        * For now an #ifdef will do.
         */
 
        clocks[0] = 0xf; /* force all clock gate pairs to enable */