object pnp_device.o
object hypertransport.o
object pci_ops.o
+object smbus_ops.o
--- /dev/null
+#include <console/console.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/path.h>
+#include <device/smbus.h>
+
+struct bus *get_pbus_smbus(device_t dev)
+{
+ struct bus *pbus = dev->bus;
+ while(pbus && pbus->dev && !ops_smbus_bus(pbus)) {
+ pbus = pbus->dev->bus;
+ }
+ if (!pbus || !pbus->dev || !pbus->dev->ops || !pbus->dev->ops->ops_smbus_bus) {
+ printk_alert("%s Cannot find smbus bus operations", dev_path(dev));
+ die("");
+ for(;;);
+ }
+ return pbus;
+}
+
+ /*multi level i2c MUX??? may need to find the first i2c device and then set link down to current dev
+ 1 store get_pbus_smbus list link
+ 2 reverse the link and call set link */
+
+int smbus_set_link(device_t dev)
+{
+ struct bus *pbus_a[4]; // 4 level mux only. Enough?
+ struct bus *pbus = dev->bus;
+ int pbus_num=0;
+ int i;
+ while(pbus && pbus->dev && (pbus->dev->path.type==DEVICE_PATH_I2C)) {
+ pbus_a[pbus_num++] = pbus;
+ pbus = pbus->dev->bus;
+ }
+// printk_info("smbus_set_link: ");
+ for(i=pbus_num-1; i>=0; i--) {
+// printk_info(" %s[%d] -> ", dev_path(pbus_a[i]->dev), pbus_a[i]->link);
+ if(ops_smbus_bus(get_pbus_smbus(pbus_a[i]->dev))) {
+ if(pbus_a[i]->dev->ops && pbus_a[i]->dev->ops->set_link)
+ pbus_a[i]->dev->ops->set_link(pbus_a[i]->dev, pbus_a[i]->link);
+ }
+ }
+// printk_info(" %s\n", dev_path(dev));
+
+ return pbus_num;
+}
+
+int smbus_quick_read(device_t dev)
+{
+ return ops_smbus_bus(get_pbus_smbus(dev))->quick_read(dev);
+}
+int smbus_quick_write(device_t dev)
+{
+ return ops_smbus_bus(get_pbus_smbus(dev))->quick_write(dev);
+}
+int smbus_recv_byte(device_t dev)
+{
+ return ops_smbus_bus(get_pbus_smbus(dev))->recv_byte(dev);
+}
+int smbus_send_byte(device_t dev, uint8_t byte)
+{
+ return ops_smbus_bus(get_pbus_smbus(dev))->send_byte(dev, byte);
+}
+int smbus_read_byte(device_t dev, uint8_t addr)
+{
+ return ops_smbus_bus(get_pbus_smbus(dev))->read_byte(dev, addr);
+}
+int smbus_write_byte(device_t dev, uint8_t addr, uint8_t val)
+{
+ return ops_smbus_bus(get_pbus_smbus(dev))->write_byte(dev, addr, val);
+}
+int smbus_read_word(device_t dev, uint8_t addr)
+{
+ return ops_smbus_bus(get_pbus_smbus(dev))->read_word(dev, addr);
+}
+int smbus_write_word(device_t dev, uint8_t addr, uint16_t val)
+{
+ return ops_smbus_bus(get_pbus_smbus(dev))->write_word(dev, addr, val);
+}
+int smbus_process_call(device_t dev, uint8_t cmd, uint16_t data)
+{
+ return ops_smbus_bus(get_pbus_smbus(dev))->process_call(dev, cmd, data);
+}
+int smbus_block_read(device_t dev, uint8_t cmd, uint8_t bytes, uint8_t *buffer)
+{
+ return ops_smbus_bus(get_pbus_smbus(dev))->block_read(dev, cmd, bytes, buffer);
+}
+int smbus_block_write(device_t dev, uint8_t cmd, uint8_t bytes, const uint8_t *buffer)
+{
+ return ops_smbus_bus(get_pbus_smbus(dev))->block_write(dev, cmd, bytes, buffer);
+}
+
+
#include <console/console.h>
#include <device/device.h>
+#include <device/smbus.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
if(!dev->enabled) {
continue;
}
- printk_debug("\n%02x:%02x:%02x aka %s",i,j,k, dev_path(dev));
+ printk_debug("\n%02x:%02x:%02x aka %s",i,j,k, dev_path(dev));
print_pci_regs(dev);
}
}
static void print_msr()
{
- msr_t msr;
- unsigned index;
- unsigned eax, ebx, ecx, edx;
- index = 0x80000007;
- printk_debug("calling cpuid 0x%08x\n", index);
- asm volatile(
- "cpuid"
- : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
- : "a" (index)
- );
- printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
- index, eax, ebx, ecx, edx);
- if (edx & (3 << 1)) {
- index = 0xC0010042;
- printk_debug("Reading msr: 0x%08x\n", index);
- msr = rdmsr(index);
- printk_debug("msr[0x%08x]: 0x%08x%08x\n",
- index, msr.hi, msr.hi);
- }
+ msr_t msr;
+ unsigned index;
+ unsigned eax, ebx, ecx, edx;
+ index = 0x80000007;
+ printk_debug("calling cpuid 0x%08x\n", index);
+ asm volatile(
+ "cpuid"
+ : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
+ : "a" (index)
+ );
+ printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
+ index, eax, ebx, ecx, edx);
+ if (edx & (3 << 1)) {
+ index = 0xC0010042;
+ printk_debug("Reading msr: 0x%08x\n", index);
+ msr = rdmsr(index);
+ printk_debug("msr[0x%08x]: 0x%08x%08x\n",
+ index, msr.hi, msr.hi);
+ }
}
-
+static void print_smbus_regs(struct device *dev)
+{
+ int j;
+ printk_debug("smbus: %s[%d]->", dev_path(dev->bus->dev), dev->bus->link );
+ printk_debug("%s", dev_path(dev));
+ for(j = 0; j < 256; j++) {
+ int status;
+ unsigned char byte;
+ if ((j & 0xf) == 0) {
+ printk_debug("\r\n%02x: ", j);
+ }
+ status = smbus_read_byte(dev, j);
+ if (status < 0) {
+ printk_debug("bad device status= %08x\r\n", status);
+ break;
+ }
+ byte = status & 0xff;
+ printk_debug("%02x ", byte);
+ }
+ printk_debug("\r\n");
+}
+
+static void print_smbus_regs_all(struct device *dev)
+{
+ struct device *child;
+ int i;
+ if (dev->enabled && dev->path.type == DEVICE_PATH_I2C)
+ {
+ // Here don't need to call smbus_set_link, because we scan it from top to down
+ if( dev->bus->dev->path.type == DEVICE_PATH_I2C) { // it's under i2c MUX so set mux at first
+ if(ops_smbus_bus(get_pbus_smbus(dev->bus->dev))) {
+ if(dev->bus->dev->ops && dev->bus->dev->ops->set_link)
+ dev->bus->dev->ops->set_link(dev->bus->dev, dev->bus->link);
+ }
+ }
+
+ if(ops_smbus_bus(get_pbus_smbus(dev))) print_smbus_regs(dev);
+ }
+
+ for(i=0; i< dev->links; i++) {
+ for (child = dev->link[i].children; child; child = child->sibling) {
+ print_smbus_regs_all(child);
+ }
+ }
+}
static void debug_init(device_t dev)
{
device_t parent;
case 3:
print_msr();
break;
+ case 4:
+ print_smbus_regs_all(&dev_root);
+ break;
}
}
--- /dev/null
+config chip.h
+object adm1026.o
--- /dev/null
+#include <console/console.h>
+#include <device/device.h>
+#include <device/smbus.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <part/hard_reset.h>
+#include <cpu/x86/msr.h>
+#include "chip.h"
+
+#define ADM1026_DEVICE 0x2c /* 0x2e or 0x2d */
+#define ADM1026_REG_CONFIG1 0x00
+#define CFG1_MONITOR 0x01
+#define CFG1_INT_ENABLE 0x02
+#define CFG1_INT_CLEAR 0x04
+#define CFG1_AIN8_9 0x08
+#define CFG1_THERM_HOT 0x10
+#define CFT1_DAC_AFC 0x20
+#define CFG1_PWM_AFC 0x40
+#define CFG1_RESET 0x80
+#define ADM1026_REG_CONFIG2 0x01
+#define ADM1026_REG_CONFIG3 0x07
+
+static void adm1026_init(device_t dev)
+{
+ if (dev->enabled && dev->path.type == DEVICE_PATH_I2C)
+ {
+ if(ops_smbus_bus(get_pbus_smbus(dev))) {
+ if( dev->bus->dev->path.type == DEVICE_PATH_I2C) smbus_set_link(dev); // it is under mux
+ adm1026_enable_monitoring(dev);
+ }
+
+ }
+
+}
+static void adm1026_enable_monitoring(device_t dev)
+{
+ int result;
+ result = smbus_read_byte(dev, ADM1026_REG_CONFIG1);
+
+ result = (result | CFG1_MONITOR) & ~(CFG1_INT_CLEAR | CFG1_RESET);
+ result = smbus_write_byte(dev, ADM1026_REG_CONFIG1, result);
+
+ result = smbus_read_byte(dev, ADM1026_REG_CONFIG1);
+ if (!(result & CFG1_MONITOR)) {
+ printk_debug("ADM1026: monitoring would not enable");
+ }
+}
+static void adm1026_noop(device_t dummy)
+{
+}
+
+static struct device_operations adm1026_operations = {
+ .read_resources = adm1026_noop,
+ .set_resources = adm1026_noop,
+ .enable_resources = adm1026_noop,
+ .init = adm1026_init,
+};
+
+static void enable_dev(struct device *dev)
+{
+ dev->ops = &adm1026_operations;
+}
+
+struct chip_operations drivers_i2c_adm1026_ops = {
+ CHIP_NAME("adm1026")
+ .enable_dev = enable_dev,
+};
--- /dev/null
+extern struct chip_operations drivers_i2c_adm1026_ops;
+
+struct drivers_i2c_adm1026_config {
+};
--- /dev/null
+config chip.h
+object adm1027.o
--- /dev/null
+#include <console/console.h>
+#include <device/device.h>
+#include <device/smbus.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <part/hard_reset.h>
+#include <cpu/x86/msr.h>
+#include "chip.h"
+
+#define ADM1027_REG_CONFIG1 0x40
+#define CFG1_STRT 0x01
+#define CFG1_LOCK 0x02
+#define CFG1_RDY 0x04
+#define CFG1_FSPD 0x08
+#define CFG1_VXI 0x10
+#define CFT1_FSPDIS 0x20
+#define CFG1_TODIS 0x40
+#define CFG1_VCC 0x80
+#define ADM1027_REG_CONFIG2 0x73
+#define ADM1027_REG_CONFIG3 0x78
+
+static void adm1027_enable_monitoring(device_t dev)
+{
+ int result;
+ result = smbus_read_byte(dev, ADM1027_REG_CONFIG1);
+
+ if(!(result & CFG1_RDY) ) {
+ printk_debug("ADM1027: monitoring not ready");
+ return;
+ }
+ result = (result | CFG1_STRT);
+ result = smbus_write_byte(dev, ADM1027_REG_CONFIG1, result);
+
+ result = smbus_read_byte(dev, ADM1027_REG_CONFIG1);
+ if (!(result & CFG1_STRT)) {
+ printk_debug("ADM1027: monitoring would not enable");
+ }
+}
+
+static void adm1027_init(device_t dev)
+{
+ if (dev->enabled && dev->path.type == DEVICE_PATH_I2C)
+ {
+ if(ops_smbus_bus(get_pbus_smbus(dev))) {
+ if( dev->bus->dev->path.type == DEVICE_PATH_I2C) smbus_set_link(dev); // it is under mux
+ adm1027_enable_monitoring(dev);
+ }
+
+ }
+
+}
+static void adm1027_noop(device_t dummy)
+{
+}
+
+static struct device_operations adm1027_operations = {
+ .read_resources = adm1027_noop,
+ .set_resources = adm1027_noop,
+ .enable_resources = adm1027_noop,
+ .init = adm1027_init,
+};
+
+static void enable_dev(struct device *dev)
+{
+ dev->ops = &adm1027_operations;
+}
+
+struct chip_operations drivers_i2c_adm1027_ops = {
+ CHIP_NAME("adm1027")
+ .enable_dev = enable_dev,
+};
--- /dev/null
+extern struct chip_operations drivers_i2c_adm1027_ops;
+
+struct drivers_i2c_adm1027_config {
+};
--- /dev/null
+config chip.h
+object i2cmux.o
--- /dev/null
+extern struct chip_operations drivers_i2c_i2cmux_ops;
+
+struct drivers_i2c_i2cmux_config {
+};
--- /dev/null
+#include <console/console.h>
+#include <device/device.h>
+#include <device/smbus.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <cpu/x86/msr.h>
+#include "chip.h"
+
+static void i2cmux_set_link(device_t dev, unsigned int link)
+{
+ if (dev->enabled && dev->path.type == DEVICE_PATH_I2C)
+ {
+ if(ops_smbus_bus(get_pbus_smbus(dev))) {
+ smbus_write_byte(dev, 0x01, 1<<link); // output value
+ smbus_write_byte(dev, 0x03, 0); // all output
+ }
+
+ }
+
+}
+static void i2cmux_noop(device_t dummy)
+{
+}
+
+static struct device_operations i2cmux_operations = {
+ .read_resources = i2cmux_noop,
+ .set_resources = i2cmux_noop,
+ .enable_resources = i2cmux_noop,
+ .init = i2cmux_noop,
+ .scan_bus = scan_static_bus,
+ .set_link = i2cmux_set_link,
+};
+
+static void enable_dev(struct device *dev)
+{
+ if(dev->links>0)
+ dev->ops = &i2cmux_operations;
+}
+
+struct chip_operations drivers_i2c_i2cmux_ops = {
+ CHIP_NAME("i2cmux")
+ .enable_dev = enable_dev,
+};
--- /dev/null
+config chip.h
+object lm63.o
--- /dev/null
+extern struct chip_operations drivers_i2c_lm63_ops;
+
+struct drivers_i2c_lm63_config {
+};
--- /dev/null
+#include <console/console.h>
+#include <device/device.h>
+#include <device/smbus.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <cpu/x86/msr.h>
+#include "chip.h"
+
+
+static void lm63_init(device_t dev)
+{
+ int result;
+ if (dev->enabled && dev->path.type == DEVICE_PATH_I2C)
+ {
+ if(ops_smbus_bus(get_pbus_smbus(dev))) {
+ if( dev->bus->dev->path.type == DEVICE_PATH_I2C) smbus_set_link(dev); // it is under mux
+ result = smbus_read_byte(dev, 0x03);
+// result &= ~0x04;
+ result |= 0x04;
+ smbus_write_byte(dev, 0x03, result & 0xff); // config lm63
+ }
+
+ }
+
+}
+static void lm63_noop(device_t dummy)
+{
+}
+
+static struct device_operations lm63_operations = {
+ .read_resources = lm63_noop,
+ .set_resources = lm63_noop,
+ .enable_resources = lm63_noop,
+ .init = lm63_init,
+};
+
+static void enable_dev(struct device *dev)
+{
+ dev->ops = &lm63_operations;
+}
+
+struct chip_operations drivers_i2c_lm63_ops = {
+ CHIP_NAME("lm63")
+ .enable_dev = enable_dev,
+};
void (*init)(device_t dev);
unsigned int (*scan_bus)(device_t bus, unsigned int max);
void (*enable)(device_t dev);
+ void (*set_link)(device_t dev, unsigned int link);
const struct pci_operations *ops_pci;
const struct smbus_bus_operations *ops_smbus_bus;
const struct pci_bus_operations *ops_pci_bus;
};
#define MAX_RESOURCES 12
-#define MAX_LINKS 4
+#define MAX_LINKS 8
/*
* There is one device structure for each slot-number/function-number
* combination:
int (*block_write) (device_t dev, uint8_t cmd, uint8_t bytes, const uint8_t *buffer);
};
-static inline int smbus_quick_read(device_t dev)
+static inline const struct smbus_bus_operations *ops_smbus_bus(struct bus *bus)
{
- return dev->bus->dev->ops->ops_smbus_bus->quick_read(dev);
-}
-static inline int smbus_quick_write(device_t dev)
-{
- return dev->bus->dev->ops->ops_smbus_bus->quick_write(dev);
-}
-static inline int smbus_recv_byte(device_t dev)
-{
- return dev->bus->dev->ops->ops_smbus_bus->recv_byte(dev);
-}
-static inline int smbus_send_byte(device_t dev, uint8_t byte)
-{
- return dev->bus->dev->ops->ops_smbus_bus->send_byte(dev, byte);
-}
-static inline int smbus_read_byte(device_t dev, uint8_t addr)
-{
- return dev->bus->dev->ops->ops_smbus_bus->read_byte(dev, addr);
-}
-static inline int smbus_write_byte(device_t dev, uint8_t addr, uint8_t val)
-{
- return dev->bus->dev->ops->ops_smbus_bus->write_byte(dev, addr, val);
-}
-static inline int smbus_read_word(device_t dev, uint8_t addr)
-{
- return dev->bus->dev->ops->ops_smbus_bus->read_word(dev, addr);
-}
-static inline int smbus_write_word(device_t dev, uint8_t addr, uint16_t val)
-{
- return dev->bus->dev->ops->ops_smbus_bus->write_word(dev, addr, val);
-}
-static inline int smbus_process_call(device_t dev, uint8_t cmd, uint16_t data)
-{
- return dev->bus->dev->ops->ops_smbus_bus->process_call(dev, cmd, data);
-}
-static inline int smbus_block_read(device_t dev, uint8_t cmd, uint8_t bytes, uint8_t *buffer)
-{
- return dev->bus->dev->ops->ops_smbus_bus->block_read(dev, cmd, bytes, buffer);
-}
-static inline int smbus_block_write(device_t dev, uint8_t cmd, uint8_t bytes, const uint8_t *buffer)
-{
- return dev->bus->dev->ops->ops_smbus_bus->block_write(dev, cmd, bytes, buffer);
+ const struct smbus_bus_operations *bops;
+ bops = 0;
+ if (bus && bus->dev && bus->dev->ops) {
+ bops = bus->dev->ops->ops_smbus_bus;
+ }
+ return bops;
}
+struct bus *get_pbus_smbus(device_t dev);
+int smbus_set_link(device_t dev);
+
+int smbus_quick_read(device_t dev);
+int smbus_quick_write(device_t dev);
+int smbus_recv_byte(device_t dev);
+int smbus_send_byte(device_t dev, uint8_t byte);
+int smbus_read_byte(device_t dev, uint8_t addr);
+int smbus_write_byte(device_t dev, uint8_t addr, uint8_t val);
+int smbus_read_word(device_t dev, uint8_t addr);
+int smbus_write_word(device_t dev, uint8_t addr, uint16_t val);
+int smbus_process_call(device_t dev, uint8_t cmd, uint16_t data);
+int smbus_block_read(device_t dev, uint8_t cmd, uint8_t bytes, uint8_t *buffer);
+int smbus_block_write(device_t dev, uint8_t cmd, uint8_t bytes, const uint8_t *buffer);
#endif /* DEVICE_SMBUS_H */
io 0x60 = 0x3f8
irq 0x70 = 4
end
- device pnp 2e.3 off # Com2
+ device pnp 2e.3 on # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
io 0x60 = 0x100
end
device pnp 2e.7 off # GAME_MIDI_GIPO1
- io 0x60 = 0x201
- io 0x62 = 0x330
+ io 0x60 = 0x220
+ io 0x62 = 0x300
irq 0x70 = 9
end
device pnp 2e.8 off end # GPIO2
end
device pci 1.1 on end
device pci 1.2 on end
- device pci 1.3 on end
+ device pci 1.3 on
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 53 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-0
+ device i2c 54 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-1
+ device i2c 55 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-0
+ device i2c 56 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-1
+ device i2c 57 on end
+ end
+ end # acpi
device pci 1.5 on end
device pci 1.6 off end
register "ide0_enable" = "1"
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on
-# chip drivers/generic/debug
-# device pnp 1.0 on end
-# device pnp 1.1 off end
-# device pnp 1.2 off end
-# device pnp 1.3 on end
-# end
+# chip drivers/generic/debug
+# device pnp 1.0 on end
+# device pnp 1.1 off end
+# device pnp 1.2 off end
+# device pnp 1.3 on end
+# end
end
end
end
end
- chip drivers/generic/debug
- device pnp 0.0 on end
- device pnp 0.1 off end
- device pnp 0.2 off end
- device pnp 0.3 on end
- end
+# chip drivers/generic/debug
+# device pnp 0.0 on end
+# device pnp 0.1 off end
+# device pnp 0.2 off end
+# device pnp 0.3 on end
+# end
end
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
static void main(unsigned long bist)
{
- static const struct mem_controller cpu[] = {
+ static const struct mem_controller cpu[] = {
#if FIRST_CPU
- {
- .node_id = 0,
- .f0 = PCI_DEV(0, 0x18, 0),
- .f1 = PCI_DEV(0, 0x18, 1),
- .f2 = PCI_DEV(0, 0x18, 2),
- .f3 = PCI_DEV(0, 0x18, 3),
- .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
- .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
- },
+ {
+ .node_id = 0,
+ .f0 = PCI_DEV(0, 0x18, 0),
+ .f1 = PCI_DEV(0, 0x18, 1),
+ .f2 = PCI_DEV(0, 0x18, 2),
+ .f3 = PCI_DEV(0, 0x18, 3),
+ .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
+ .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
+ },
#endif
#if SECOND_CPU
- {
- .node_id = 1,
- .f0 = PCI_DEV(0, 0x19, 0),
- .f1 = PCI_DEV(0, 0x19, 1),
- .f2 = PCI_DEV(0, 0x19, 2),
- .f3 = PCI_DEV(0, 0x19, 3),
- .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
- .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
- },
+ {
+ .node_id = 1,
+ .f0 = PCI_DEV(0, 0x19, 0),
+ .f1 = PCI_DEV(0, 0x19, 1),
+ .f2 = PCI_DEV(0, 0x19, 2),
+ .f3 = PCI_DEV(0, 0x19, 3),
+ .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
+ .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
+ },
#endif
- };
+ };
#if 1
static const struct ht_chain ht_c[] = {
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
#if 0
- dump_pci_devices();
+ dump_pci_devices();
#endif
+
+ /* Check all of memory */
#if 0
- dump_pci_device(PCI_DEV(0, 0x18, 1));
+ msr_t msr;
+ msr = rdmsr(TOP_MEM2);
+ print_debug("TOP_MEM2: ");
+ print_debug_hex32(msr.hi);
+ print_debug_hex32(msr.lo);
+ print_debug("\r\n");
#endif
- /* Check all of memory */
-#if 0
- msr_t msr;
- msr = rdmsr(TOP_MEM2);
- print_debug("TOP_MEM2: ");
- print_debug_hex32(msr.hi);
- print_debug_hex32(msr.lo);
- print_debug("\r\n");
-
- ram_check(0x00000000, msr.lo+(msr.hi<<32));
+#if 0
+ ram_check(0x00000000, msr.lo+(msr.hi<<32));
#endif
-#if 0
-
-//#if TOTAL_CPUS < 2
- // Check 16MB of memory @ 0
- ram_check(0x00000000, 0x00100000);
-//#else
- // Check 16MB of memory @ 2GB
-// ram_check(0x80000000, 0x80100000);
-//#endif
+#if 0
+ // Check 16MB of memory @ 0
+ ram_check(0x00000000, 0x00100000);
+ // Check 16MB of memory @ 2GB
+ ram_check(0x80000000, 0x80100000);
#endif
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
- 32+16*11, /* there can be total 11 devices on the bus */
- 3, /* Where the interrupt router lies (bus) */
+ 32+16*22, /* there can be total 22 devices on the bus */
+ 1, /* Where the interrupt router lies (bus) */
(4<<3)|3, /* Where the interrupt router lies (dev) */
0, /* IRQs devoted exclusively to PCI usage */
0x1022, /* Vendor */
- 0x746b, /* Device */
+ 0x7400, /* Device */
0, /* Crap (miniport) */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0xd8, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+ 0x5b, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
{
- {3,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
- {0x6,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0},
- {0x1,0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0x0, 0},
- {0x5,(3<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
- {0x5,(6<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0},
- {0x4,(8<<3)|0, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
- {0x4,(7<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
- {0x6,(0x0a<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0},
- {0x4,(9<<3)|0, {{0x1, 0xdef8}, {2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
- {0x6,(0x0b<<3)|0, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
- {0x6,(0x0c<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
+ {0,0xc0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
+ {1,(3<<3)|0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
+ {0x4,0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
+ {0x4,0x8, {{0x1, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
+ {0x4,0x20, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
+ {0x4,0x18, {{0x2, 0xdef8}, {0x1, 0xdef8}, {0x3, 0xdef8}, {0, 0xdef8}}, 0, 0},
+ {0x4,0x28, {{0x4, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
+ {0x4,0x30, {{0x3, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
+ {1,(4<<3)|0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
+ {1,(1<<3)|0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
+ {0x2,0x18, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x2, 0},
+ {0x2,0x10, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x3, 0},
+ {0x2,0x48, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
+ {0x2,0x20, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
+ {1,(2<<3)|0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
+ {0x3,0x18, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x4, 0},
+ {0x3,0x8, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x5, 0},
+ {0x3,0x20, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x6, 0},
+ {0x3,0x28, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x7, 0},
+ {0,0xc8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
+ {0,0xd0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
+ {0,0xd8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
}
};
io 0x60 = 0x3f8
irq 0x70 = 4
end
- device pnp 2e.3 off # Com2
+ device pnp 2e.3 on # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
io 0x60 = 0x100
end
device pnp 2e.7 off # GAME_MIDI_GIPO1
- io 0x60 = 0x201
- io 0x62 = 0x330
+ io 0x60 = 0x220
+ io 0x62 = 0x300
irq 0x70 = 9
end
device pnp 2e.8 off end # GPIO2
end
device pci 1.1 on end
device pci 1.2 on end
- device pci 1.3 on end
+ device pci 1.3 on
+ chip drivers/i2c/i2cmux # pca9556 smbus mux
+ device i2c 18 on #0 pca9516 2, 1
+ chip drivers/i2c/lm63 #cpu0 temp
+ device i2c 4c on end
+ end
+ end
+ device i2c 18 on #1 pca9516 1, 1
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 53 on end
+ end
+ end
+ device i2c 18 on #2 pca9516 1, 2
+ chip drivers/generic/generic #dimm 1-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-1
+ device i2c 53 on end
+ end
+ end
+ device i2c 18 on #3 pca9516 1, 3
+ chip drivers/generic/generic #dimm 2-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 2-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 2-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 2-1-1
+ device i2c 53 on end
+ end
+ end
+ device i2c 18 on #4 pca9516 1, 4
+ chip drivers/generic/generic #dimm 3-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 3-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 3-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 3-1-1
+ device i2c 53 on end
+ end
+ end
+ device i2c 18 on #5 pca9516 2, 2
+ chip drivers/i2c/lm63 #cpu1 temp
+ device i2c 4c on end
+ end
+ end
+ device i2c 18 on #6 pca9516 2, 3
+ chip drivers/i2c/lm63 #cpu2 temp
+ device i2c 4c on end
+ end
+ end
+ device i2c 18 on #7 pca9516 2, 4
+ chip drivers/i2c/lm63 #cpu3 temp
+ device i2c 4c on end
+ end
+ end
+ end # i2cmux
+ chip drivers/i2c/adm1027 # ADM1027 CPU1 vid and System FAN...
+ device i2c 2e on end
+ end
+ chip drivers/generic/generic # Winbond HWM 0x54 CPU0 vid
+ device i2c 2a on end
+ end
+ chip drivers/generic/generic # Winbond HWM 0x92
+ device i2c 49 on end
+ end
+ chip drivers/generic/generic # Winbond HWM 0x94
+ device i2c 4a on end
+ end
+ chip drivers/generic/generic # ??
+ device i2c 69 on end
+ end
+ end # acpi
device pci 1.5 off end
device pci 1.6 off end
end
device apic 3 on end
end
end
+ chip drivers/generic/debug
+ device pnp 0.0 off end
+ device pnp 0.1 off end
+ device pnp 0.2 off end
+ device pnp 0.3 off end
+ device pnp 0.4 on end
+ end
end
* generic K8 debug code, used by mainboard specific auto.c
*
*/
-
+#if 1
static void print_debug_pci_dev(unsigned dev)
{
print_debug("PCI: ");
{
device_t dev;
for(dev = PCI_DEV(0, 0, 0);
- dev <= PCI_DEV(0, 0x1f, 0x7);
+ dev <= PCI_DEV(0xff, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
uint32_t id;
id = pci_read_config32(dev, PCI_VENDOR_ID);
{
device_t dev;
for(dev = PCI_DEV(0, 0, 0);
- dev <= PCI_DEV(0, 0x1f, 0x7);
+ dev <= PCI_DEV(0xff, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
uint32_t id;
id = pci_read_config32(dev, PCI_VENDOR_ID);
}
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device status=");
+ print_debug_hex32(status);
+ print_debug("\r\n");
break;
}
byte = status & 0xff;
print_debug("\r\n");
}
}
+
+static void dump_io_resources(unsigned port)
+{
+
+ int i;
+ udelay(2000);
+ print_debug_hex16(port);
+ print_debug(":\r\n");
+ for(i=0;i<256;i++) {
+ uint8_t val;
+ if ((i & 0x0f) == 0) {
+ print_debug_hex8(i);
+ print_debug_char(':');
+ }
+ val = inb(port);
+ print_debug_char(' ');
+ print_debug_hex8(val);
+ if ((i & 0x0f) == 0x0f) {
+ print_debug("\r\n");
+ }
+ port++;
+ }
+}
+#endif
struct resource *res;
device = dev->path.u.i2c.device;
- res = find_resource(dev->bus->dev, 0x20);
+ res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
return do_smbus_recv_byte(res->base, device);
}
struct resource *res;
device = dev->path.u.i2c.device;
- res = find_resource(dev->bus->dev, 0x20);
+ res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
return do_smbus_send_byte(res->base, device, val);
}
struct resource *res;
device = dev->path.u.i2c.device;
- res = find_resource(dev->bus->dev, 0x20);
+ res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
return do_smbus_read_byte(res->base, device, address);
}
struct resource *res;
device = dev->path.u.i2c.device;
- res = find_resource(dev->bus->dev, 0x20);
+ res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
return do_smbus_write_byte(res->base, device, address, val);
}
.read_byte = lsmbus_read_byte,
.write_byte = lsmbus_write_byte,
};
+
static struct pci_operations lops_pci = {
.set_subsystem = lpci_set_subsystem,
};
.enable_resources = acpi_enable_resources,
.init = acpi_init,
.scan_bus = scan_static_bus,
- .enable = amd8111_enable,
+// .enable = amd8111_enable,
.ops_pci = &lops_pci,
.ops_smbus_bus = &lops_smbus_bus,
};
projects / coreboot.git / commitdiff