remove some more warnings

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5348 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/cpu/amd/model_gx2/vsmsetup.c b/src/cpu/amd/model_gx2/vsmsetup.c
index aa25042a61732ee06d9fcf99cdbcaf76257dd764..a284a9c726e690666e5e08067591963b622c5e06 100644 (file)
--- a/src/cpu/amd/model_gx2/vsmsetup.c
+++ b/src/cpu/amd/model_gx2/vsmsetup.c
@@ -35,7 +35,6 @@
 #include <arch/io.h>
 #include <cbfs.h>
 
-u32 VSA_vrRead(u16 classIndex);
 void do_vsmbios(void);
 
 #define VSA2_BUFFER            0x60000
@@ -150,7 +149,7 @@ extern char real_mode_switch_end[];
 
 /* andrei: Some VSA virtual register helpers: raw read and MSR read. */
 
-u32 VSA_vrRead(u16 classIndex)
+static u32 VSA_vrRead(u16 classIndex)
 {
        unsigned eax, ebx, ecx, edx;
        asm volatile (
@@ -166,7 +165,7 @@ u32 VSA_vrRead(u16 classIndex)
        return eax;
 }
 
-u32 VSA_msrRead(u32 msrAddr)
+static u32 VSA_msrRead(u32 msrAddr)
 {
        unsigned eax, ebx, ecx, edx;
        asm volatile (

diff --git a/src/include/console/console.h b/src/include/console/console.h
index f5301ee128c501cfe93a3bfee9221f9c5ee61ae1..50b3a0d7ceab518fe607d5ebd5b455eb3ea51da3 100644 (file)
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -44,6 +44,9 @@ extern int console_loglevel;
 #endif
 
 #ifndef __ROMCC__
+void console_init(void);
+void post_code(u8 value);
+void __attribute__ ((noreturn)) die(const char *msg);
 int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
 
 #undef WE_CLEANED_UP_ALL_SIDE_EFFECTS

diff --git a/src/mainboard/advantech/pcm-5820/irq_tables.c b/src/mainboard/advantech/pcm-5820/irq_tables.c
index d176ecbf262ecb2e70cf845d52d85f655a940809..fa2fe0ff3b1e8a25774a0037b822d263e8e495a2 100644 (file)
--- a/src/mainboard/advantech/pcm-5820/irq_tables.c
+++ b/src/mainboard/advantech/pcm-5820/irq_tables.c
@@ -30,7 +30,7 @@ const struct irq_routing_table intel_irq_routing_table = {
        0x1078,                 /* Vendor */
        0x2,                    /* Device */
        0,                      /* Crap (miniport) */
-       // { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+       { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
        0xde,                   /* Checksum */
        {
                /* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */

diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c
index 33ca9a2210b4ca1abd250b7546c8f2c355cfacbd..210e4e8c10ba445fa9f5a2512345cdde6b2c8d88 100644 (file)
--- a/src/mainboard/amd/db800/romstage.c
+++ b/src/mainboard/amd/db800/romstage.c
@@ -24,6 +24,7 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
+#include <console/console.h>
 #include "console/console.c"
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"

diff --git a/src/northbridge/amd/lx/pll_reset.c b/src/northbridge/amd/lx/pll_reset.c
index 188a96e85c0e10dbfb8de793203ab18a95a9cc6f..576a2239ed1a6f4e417a49b972e8cc8d7111099e 100644 (file)
--- a/src/northbridge/amd/lx/pll_reset.c
+++ b/src/northbridge/amd/lx/pll_reset.c
@@ -72,6 +72,7 @@ static void pll_reset(char manualconf)
        return;
 }
 
+#if 0 // Unused
 static unsigned int CPUSpeed(void)
 {
        unsigned int speed;
@@ -84,6 +85,8 @@ static unsigned int CPUSpeed(void)
        }
        return (speed);
 }
+#endif
+
 static unsigned int GeodeLinkSpeed(void)
 {
        unsigned int speed;
@@ -96,6 +99,8 @@ static unsigned int GeodeLinkSpeed(void)
        }
        return (speed);
 }
+
+#if 0 // Unused
 static unsigned int PCISpeed(void)
 {
        msr_t msr;
@@ -107,3 +112,4 @@ static unsigned int PCISpeed(void)
                return (33);
        }
 }
+#endif

diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c
index 10717add086c625f654028ad7b34bb8e36399c3d..68fd0bfdbe0e9126a2e76d5f712d38c2e4ef5867 100644 (file)
--- a/src/northbridge/amd/lx/raminit.c
+++ b/src/northbridge/amd/lx/raminit.c
@@ -514,6 +514,8 @@ static void set_extended_mode_registers(void)
        wrmsr(MC_CF07_DATA, msr);
 }
 
+#undef TLA_MEMORY_DEBUG
+#ifdef TLA_MEMORY_DEBUG
 static void EnableMTest(void)
 {
        msr_t msr;
@@ -534,6 +536,7 @@ static void EnableMTest(void)
 
        print_info("Enabled MTest for TLA debug\n");
 }
+#endif
 
 static void sdram_set_registers(const struct mem_controller *ctrl)
 {
@@ -642,8 +645,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 ;********************************************************************/
        post_code(POST_MEM_ENABLE);     // post_76h
 
+#ifdef TLA_MEMORY_DEBUG
        /* Only enable MTest for TLA memory debug */
-       /*EnableMTest(); */
+       EnableMTest();
+#endif
 
        /* If both Page Size = "Not Installed" we have a problems and should halt. */
        msr = rdmsr(MC_CF07_DATA);

diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index f068006f75bb1dedfd75908f7c98aa298fa5c92c..2a3662c5179a597389d4246980f3223f34317fb1 100644 (file)
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -77,7 +77,7 @@ struct acpiinit acpi_init_table[] = {
        {PMS_IO_BASE + PM_SIDD, 0x000008C02},
        {PMS_IO_BASE + PM_WKD, 0x0000000A0},
        {PMS_IO_BASE + PM_WKXD, 0x0000000A0},
-       {0, 0, 0}
+       {0, 0}
 };
 
 struct FLASH_DEVICE {
@@ -197,7 +197,7 @@ static void ChipsetFlashSetup(void)
 /*             Run after VSA init to enable the flash PCI device header */
 /* **/
 /* ***************************************************************************/
-static void enable_ide_nand_flash_header()
+static void enable_ide_nand_flash_header(void)
 {
        /* Tell VSA to use FLASH PCI header. Not IDE header. */
        outl(0x80007A40, 0xCF8);

diff --git a/src/southbridge/amd/cs5536/cs5536_early_setup.c b/src/southbridge/amd/cs5536/cs5536_early_setup.c
index cd8bffa8689b1fddc64e44eb5eff1b715a171936..cedc209c56ee49ab9822d342d6cec1c6d094f1ac 100644 (file)
--- a/src/southbridge/amd/cs5536/cs5536_early_setup.c
+++ b/src/southbridge/amd/cs5536/cs5536_early_setup.c
@@ -156,7 +156,7 @@ static void cs5536_setup_cis_mode(void)
  *
  * See page 412 of the AMD Geode CS5536 Companion Device data book.
  */
-void cs5536_setup_onchipuart1(void)
+static void cs5536_setup_onchipuart1(void)
 {
        msr_t msr;
 
@@ -196,7 +196,7 @@ void cs5536_setup_onchipuart1(void)
        wrmsr(MDD_UART1_CONF, msr);
 }
 
-void cs5536_setup_onchipuart2(void)
+static void cs5536_setup_onchipuart2(void)
 {
        msr_t msr;