#endif
//use by raminit
-#define K8_4RANK_DIMM_SUPPORT 1
+#define QRANK_DIMM_SUPPORT 1
//used by incoherent_ht
//#define K8_SCAN_PCI_BUS 1
}
//#include "northbridge/amd/amdk8/setup_resource_map.c"
-#define K8_4RANK_DIMM_SUPPORT 1
+#define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c"
#if 0
return smbus_read_byte(device, address);
}
-#define K8_4RANK_DIMM_SUPPORT 1
+#define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c"
#if 0
//#define K8_SCAN_PCI_BUS 1
-#define K8_4RANK_DIMM_SUPPORT 1
+#define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
return smbus_read_byte(device, address);
}
-#define K8_4RANK_DIMM_SUPPORT 1
-
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/resourcemap.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
return smbus_read_byte(device, address);
}
-#define K8_4RANK_DIMM_SUPPORT 1
+#define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
return smbus_read_byte(device, address);
}
-#define K8_4RANK_DIMM_SUPPORT 1
+#define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/resourcemap.c"
}
//#include "northbridge/amd/amdk8/setup_resource_map.c"
-#define K8_4RANK_DIMM_SUPPORT 1
+#define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
}
#include "northbridge/amd/amdk8/setup_resource_map.c"
-#define K8_4RANK_DIMM_SUPPORT 1
+#define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/resourcemap.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
return smbus_read_byte(device, address);
}
-#define K8_4RANK_DIMM_SUPPORT 1
+#define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/resourcemap.c"
}
//#include "northbridge/amd/amdk8/setup_resource_map.c"
-#define K8_4RANK_DIMM_SUPPORT 1
+#define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c"
#if 0
return smbus_read_byte(device, address);
}
-#define K8_4RANK_DIMM_SUPPORT 1
+#define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
return smbus_read_byte(device, address);
}
-#define K8_4RANK_DIMM_SUPPORT 1
+#define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
return smbus_read_byte(device, address);
}
-#define K8_4RANK_DIMM_SUPPORT 1
+#define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c"
#if 0
return smbus_read_byte(device, address);
}
-#define K8_4RANK_DIMM_SUPPORT 1
+#define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
}
#include "northbridge/amd/amdk8/setup_resource_map.c"
-#define K8_4RANK_DIMM_SUPPORT 1
+#define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c"
#if 0
#define ENABLE_APIC_EXT_ID 1
return smbus_read_byte(device, address);
}
-#define K8_4RANK_DIMM_SUPPORT 1
+#define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
# error "CONFIG_LB_MEM_TOPK must be a power of 2"
#endif
-#ifndef K8_4RANK_DIMM_SUPPORT
-#define K8_4RANK_DIMM_SUPPORT 0
+#ifndef QRANK_DIMM_SUPPORT
+#define QRANK_DIMM_SUPPORT 0
#endif
#if defined (__GNUC__)
unsigned long side2;
unsigned long rows;
unsigned long col;
-#if K8_4RANK_DIMM_SUPPORT == 1
+#if QRANK_DIMM_SUPPORT == 1
unsigned long rank;
#endif
};
sz.side2 = 0;
sz.rows = 0;
sz.col = 0;
-#if K8_4RANK_DIMM_SUPPORT == 1
+#if QRANK_DIMM_SUPPORT == 1
sz.rank = 0;
#endif
if ((value != 2) && (value != 4 )) {
goto val_err;
}
-#if K8_4RANK_DIMM_SUPPORT == 1
+#if QRANK_DIMM_SUPPORT == 1
sz.rank = value;
#endif
sz.side2 = 0;
sz.rows = 0;
sz.col = 0;
-#if K8_4RANK_DIMM_SUPPORT == 1
+#if QRANK_DIMM_SUPPORT == 1
sz.rank = 0;
#endif
out:
/* Set the appropriate DIMM base address register */
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1);
-#if K8_4RANK_DIMM_SUPPORT == 1
+#if QRANK_DIMM_SUPPORT == 1
if(sz.rank == 4) {
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), base0);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), base1);
if (base0) {
dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
dch |= DCH_MEMCLK_EN0 << index;
-#if K8_4RANK_DIMM_SUPPORT == 1
+#if QRANK_DIMM_SUPPORT == 1
if(sz.rank == 4) {
dch |= DCH_MEMCLK_EN0 << (index + 2);
}
map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
map &= ~(0xf << (index * 4));
-#if K8_4RANK_DIMM_SUPPORT == 1
+#if QRANK_DIMM_SUPPORT == 1
if(sz.rank == 4) {
map &= ~(0xf << ( (index + 2) * 4));
}
if (sz.side1 >= (25 +3)) {
if(is_cpu_pre_d0()) {
map |= (sz.side1 - (25 + 3)) << (index *4);
-#if K8_4RANK_DIMM_SUPPORT == 1
+#if QRANK_DIMM_SUPPORT == 1
if(sz.rank == 4) {
map |= (sz.side1 - (25 + 3)) << ( (index + 2) * 4);
}
}
else {
map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << (index*4);
-#if K8_4RANK_DIMM_SUPPORT == 1
+#if QRANK_DIMM_SUPPORT == 1
if(sz.rank == 4) {
map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << ( (index + 2) * 4);
}
}
#if 0
//down speed for full load 4 rank support
-#if K8_4RANK_DIMM_SUPPORT
+#if QRANK_DIMM_SUPPORT
if(dimm_mask == (3|(3<<DIMM_SOCKETS)) ) {
int ranks = 4;
for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
{
uint32_t dcl;
int value;
-#if K8_4RANK_DIMM_SUPPORT == 1
+#if QRANK_DIMM_SUPPORT == 1
int rank;
#endif
int dimm;
return -1;
}
-#if K8_4RANK_DIMM_SUPPORT == 1
+#if QRANK_DIMM_SUPPORT == 1
rank = spd_read_byte(ctrl->channel0[i], 5); /* number of physical banks */
if (rank < 0) {
return -1;
#endif
dimm = 1<<(DCL_x4DIMM_SHIFT+i);
-#if K8_4RANK_DIMM_SUPPORT == 1
+#if QRANK_DIMM_SUPPORT == 1
if(rank==4) {
dimm |= 1<<(DCL_x4DIMM_SHIFT+i+2);
}