Add TINY_BOOTBLOCK support for AMD SB700.

Factor out the ROM decode enable functionality into bootblock.c and
handle it via the usual TINY_BOOTBLOCK mechanism.

Use "select TINY_BOOTBLOCK" in the southbridge, not individual boards.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/mainboard/amd/mahogany_fam10/Kconfig b/src/mainboard/amd/mahogany_fam10/Kconfig
index e4a5971fecd4e230f1a1e8402eb97c50eb2d26ff..106fcfa5de009f532b7f24b2b188e36338f7dd7a 100644 (file)
--- a/src/mainboard/amd/mahogany_fam10/Kconfig
+++ b/src/mainboard/amd/mahogany_fam10/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select BOARD_ROMSIZE_KB_1024
        select RAMINIT_SYSINFO
        select ENABLE_APIC_EXT_ID
-       select TINY_BOOTBLOCK
        select GFXUMA
        select QRANK_DIMM_SUPPORT
 

diff --git a/src/mainboard/amd/tilapia_fam10/Kconfig b/src/mainboard/amd/tilapia_fam10/Kconfig
index 5b61fd32e3c32d909eb12dede8b7c06d62d2f1f8..fd4b7853a78f6721431679e2a7303ad6d585fc8f 100644 (file)
--- a/src/mainboard/amd/tilapia_fam10/Kconfig
+++ b/src/mainboard/amd/tilapia_fam10/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select BOARD_ROMSIZE_KB_1024
        select RAMINIT_SYSINFO
        select ENABLE_APIC_EXT_ID
-       select TINY_BOOTBLOCK
        select GFXUMA
        select QRANK_DIMM_SUPPORT
 

diff --git a/src/mainboard/asus/m4a78-em/Kconfig b/src/mainboard/asus/m4a78-em/Kconfig
index da9f74be8a95762b0b4634ea94b95cc42defe0f2..4bdce66c491f524431b4985a1c675343aae1e7d2 100644 (file)
--- a/src/mainboard/asus/m4a78-em/Kconfig
+++ b/src/mainboard/asus/m4a78-em/Kconfig
@@ -23,7 +23,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select BOARD_ROMSIZE_KB_1024
        select RAMINIT_SYSINFO
        select ENABLE_APIC_EXT_ID
-       select TINY_BOOTBLOCK
        select GFXUMA
        select QRANK_DIMM_SUPPORT
 

diff --git a/src/mainboard/asus/m4a785-m/Kconfig b/src/mainboard/asus/m4a785-m/Kconfig
index c8fc305ea480eece26b0099410b997c3f8668b50..45f0d8d367bc401ae470ba6149afc8a535285f49 100644 (file)
--- a/src/mainboard/asus/m4a785-m/Kconfig
+++ b/src/mainboard/asus/m4a785-m/Kconfig
@@ -24,7 +24,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select BOARD_ROMSIZE_KB_1024
        select RAMINIT_SYSINFO
        select ENABLE_APIC_EXT_ID
-       select TINY_BOOTBLOCK
        select GFXUMA
        select QRANK_DIMM_SUPPORT
 

diff --git a/src/mainboard/gigabyte/ma785gmt/Kconfig b/src/mainboard/gigabyte/ma785gmt/Kconfig
index de5bfe0cf2fefdc8d76eb26777a0c1d7e713386b..2e2aa14cdd2511ebff174c1601ca5722ee25fc61 100644 (file)
--- a/src/mainboard/gigabyte/ma785gmt/Kconfig
+++ b/src/mainboard/gigabyte/ma785gmt/Kconfig
@@ -24,7 +24,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select HAVE_ACPI_TABLES
        select BOARD_ROMSIZE_KB_1024
        select ENABLE_APIC_EXT_ID
-       select TINY_BOOTBLOCK
        select GFXUMA
        select RAMINIT_SYSINFO
        select QRANK_DIMM_SUPPORT

diff --git a/src/mainboard/gigabyte/ma78gm/Kconfig b/src/mainboard/gigabyte/ma78gm/Kconfig
index b1a61de7105ed029be0062e3da6503900e2bb6bc..e29f38c3414f64216a6f4b451eedd5cf02247f18 100644 (file)
--- a/src/mainboard/gigabyte/ma78gm/Kconfig
+++ b/src/mainboard/gigabyte/ma78gm/Kconfig
@@ -24,7 +24,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select HAVE_ACPI_TABLES
        select BOARD_ROMSIZE_KB_1024
        select ENABLE_APIC_EXT_ID
-       select TINY_BOOTBLOCK
        select GFXUMA
        select RAMINIT_SYSINFO
        select QRANK_DIMM_SUPPORT

diff --git a/src/mainboard/iei/kino-780am2-fam10/Kconfig b/src/mainboard/iei/kino-780am2-fam10/Kconfig
index 3b519086ae2f373e5ddb6e554aa1b05898bb6a37..781e93ca438afcf72422d1e6a37cc8f7b7808731 100644 (file)
--- a/src/mainboard/iei/kino-780am2-fam10/Kconfig
+++ b/src/mainboard/iei/kino-780am2-fam10/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select BOARD_ROMSIZE_KB_1024
        select RAMINIT_SYSINFO
        select ENABLE_APIC_EXT_ID
-       select TINY_BOOTBLOCK
        select GFXUMA
        select QRANK_DIMM_SUPPORT
 

diff --git a/src/mainboard/jetway/pa78vm5/Kconfig b/src/mainboard/jetway/pa78vm5/Kconfig
index 0f35db224bc80b79a481edbdea98ac91908538f4..2be43754898107f3a3c582ee17944779919b123b 100644 (file)
--- a/src/mainboard/jetway/pa78vm5/Kconfig
+++ b/src/mainboard/jetway/pa78vm5/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select BOARD_ROMSIZE_KB_1024
        select RAMINIT_SYSINFO
        select ENABLE_APIC_EXT_ID
-       select TINY_BOOTBLOCK
        select GFXUMA
        select QRANK_DIMM_SUPPORT
 

diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig
index 97768d18e5da469025f7efa3ee07a30454b8f9be..2fd98d5295f1cc483c3e95c2505bcac59c76b120 100644 (file)
--- a/src/southbridge/amd/sb700/Kconfig
+++ b/src/southbridge/amd/sb700/Kconfig
@@ -21,6 +21,7 @@ config SOUTHBRIDGE_AMD_SB700
        bool
        select IOAPIC
        select HAVE_USBDEBUG
+       select TINY_BOOTBLOCK
 
 config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
        bool

diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c
new file mode 100644 (file)
index 0000000..ffb5774
--- /dev/null
+++ b/src/southbridge/amd/sb700/bootblock.c
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_ids.h>
+
+/*
+ * Enable 1MB (LPC) ROM access at 0xFFF00000 - 0xFFFFFFFF.
+ *
+ * Hardware should enable LPC ROM by pin straps. This function does not
+ * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations.
+ *
+ * The SB700 power-on default is to map 256K ROM space.
+ *
+ * Details: AMD SB700/710/750 BIOS Developer's Guide (BDG), Rev. 1.00,
+ *          PN 43366_sb7xx_bdg_pub_1.00, June 2009, section 3.1, page 14.
+ */
+static void sb700_enable_rom(void)
+{
+       u8 reg8;
+       device_t dev;
+
+       dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI,
+                               PCI_DEVICE_ID_ATI_SB700_LPC), 0);
+
+       /* Decode variable LPC ROM address ranges 1 and 2. */
+       reg8 = pci_read_config8(dev, 0x48);
+       reg8 |= (1 << 3) | (1 << 4);
+       pci_write_config8(dev, 0x48, reg8);
+
+       /* LPC ROM address range 1: */
+       /* Enable LPC ROM range mirroring start at 0x000e(0000). */
+       pci_write_config16(dev, 0x68, 0x000e);
+       /* Enable LPC ROM range mirroring end at 0x000f(ffff). */
+       pci_write_config16(dev, 0x6a, 0x000f);
+
+       /* LPC ROM address range 2: */
+       /*
+        * Enable LPC ROM range start at:
+        * 0xfff8(0000): 512KB
+        * 0xfff0(0000): 1MB
+        */
+       pci_write_config16(dev, 0x6c, 0xfff0); /* 1 MB */
+       /* Enable LPC ROM range end at 0xffff(ffff). */
+       pci_write_config16(dev, 0x6e, 0xffff);
+}
+
+static void bootblock_southbridge_init(void)
+{
+       sb700_enable_rom();
+}

diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index 81ffc1c7d502b7ea80fcf9cc94793d6ab25c4fc3..f1f0548a792f244316274e8f4d526bc7a1ebbada 100644 (file)
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -92,7 +92,6 @@ static u8 set_sb700_revision(void)
 *      Serial port 0
 *      KBC Port
 *      ACPI Micro-controller port
-*      LPC ROM size
 *      This function does not change port 0x80 decoding.
 *      Console output through any port besides 0x3f8 is unsupported.
 *      If you use FWH ROMs, you have to setup IDSEL.
@@ -134,27 +133,13 @@ static void sb700_lpc_init(void)
        reg8 |= 1 << 0;
        pci_write_config8(dev, 0xbb, reg8);
 
-       /* SuperIO, LPC ROM */
+       /* Super I/O, RTC */
        reg8 = pci_read_config8(dev, 0x48);
        /* Decode ports 0x2e-0x2f, 0x4e-0x4f (SuperI/O configuration) */
        reg8 |= (1 << 1) | (1 << 0);
-       /* Decode variable LPC ROM address ranges 1&2 (see register 0x68-0x6b, 0x6c-0x6f) */
-       reg8 |= (1 << 3) | (1 << 4);
        /* Decode port 0x70-0x73 (RTC) */
-       reg8 |= 1 << 6;
+       reg8 |= (1 << 6);
        pci_write_config8(dev, 0x48, reg8);
-
-       /* hardware should enable LPC ROM by pin straps */
-       /* ROM access at 0xFFF80000/0xFFF00000 - 0xFFFFFFFF */
-       /* See detail in 43366_sb700_bdg_nda_1.01.pdf page 17. */
-       /* enable LPC ROM range mirroring start 0x000e(0000) */
-       pci_write_config16(dev, 0x68, 0x000e);
-       /* enable LPC ROM range mirroring end   0x000f(ffff) */
-       pci_write_config16(dev, 0x6a, 0x000f);
-       /* enable LPC ROM range start, 0xfff8(0000): 512KB, 0xfff0(0000): 1MB */
-       pci_write_config16(dev, 0x6c, 0xfff0);
-       /* enable LPC ROM range end at 0xffff(ffff) */
-       pci_write_config16(dev, 0x6e, 0xffff);
 }
 
 /* what is its usage? */
@@ -403,13 +388,12 @@ static void sb700_devices_por_init(void)
        pci_write_config8(dev, 0x46, 0xC3);
        pci_write_config8(dev, 0x47, 0xFF);
 
+       // TODO: This has already been done(?)
        /* IO/Mem Port Decode Enable, I don't know why CIM disable some ports.
         *  Disable LPC TimeOut counter, enable SuperIO Configuration Port (2e/2f),
-        * Alternate SuperIO Configuration Port (4e/4f), Wide Generic IO Port (64/65).
-        * Enable bits for LPC ROM memory address range 1&2 for 1M ROM setting.*/
+        * Alternate Super I/O Configuration Port (4e/4f), Wide Generic IO Port (64/65). */
        byte = pci_read_config8(dev, 0x48);
        byte |= (1 << 1) | (1 << 0);    /* enable Super IO config port 2e-2h, 4e-4f */
-       byte |= (1 << 3) | (1 << 4);    /* enable for LPC ROM address range1&2, Enable 512KB rom access at 0xFFF80000 - 0xFFFFFFFF */
        byte |= 1 << 6;         /* enable for RTC I/O range */
        pci_write_config8(dev, 0x48, byte);
        pci_write_config8(dev, 0x49, 0xFF);
@@ -418,12 +402,6 @@ static void sb700_devices_por_init(void)
        byte |= ((1 << 1) + (1 << 6));  /*0x42, save the configuraion for port 0x80. */
        pci_write_config8(dev, 0x4A, byte);
 
-       /* Set LPC ROM size, it has been done in sb700_lpc_init().
-        * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB;
-        * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB
-        * pci_write_config16(dev, 0x68, 0x000e)
-        * pci_write_config16(dev, 0x6c, 0xfff0);*/
-
        /* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */
        pci_write_config8(dev, 0x7C, 0x05);