unsigned nodes;
unsigned nodeid;
- if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0) { // disable dual_core
- return;
- }
+ if (HAVE_OPTION_TABLE &&
+ read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0) {
+ return; // disable dual_core
+ }
nodes = get_nodes();
nodes = get_nodes();
disable_siblings = !CONFIG_LOGICAL_CPUS;
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS == 1 && HAVE_OPTION_TABLE == 1
if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0) { // 0 mean dual core
disable_siblings = 1;
}
#if CONFIG_LOGICAL_CPUS==1
unsigned total_cpus;
- if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) == 0) { /* dual_core */
+ if ((!HAVE_OPTION_TABLE) ||
+ read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) == 0) { /* dual_core */
total_cpus = verify_dualcore(nodes);
}
else {
if (nbcap & NBCAP_ECC) {
dcl |= DCL_DimmEccEn;
}
- if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
+ if (HAVE_OPTION_TABLE &&
+ read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
dcl &= ~DCL_DimmEccEn;
}
pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
-
}
static int is_dual_channel(const struct mem_controller *ctrl)
{
unsigned long tom_k, base_k;
- if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) {
+ if ((!HAVE_OPTION_TABLE) ||
+ read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) {
tom_k = interleave_chip_selects(ctrl);
} else {
print_debug("Interleaving disabled\r\n");
min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
bios_cycle_time = min_cycle_times[
read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)];
- if (bios_cycle_time > min_cycle_time) {
+ if (HAVE_OPTION_TABLE && bios_cycle_time > min_cycle_time) {
min_cycle_time = bios_cycle_time;
}
min_latency = 2;