leal _stack, %edi
movl $_estack, %ecx
subl %edi, %ecx
- shrl $2, %ecx /* it is 32 bit align, right? */
+ shrl $2, %ecx /* it is 32 bit aligned, right? */
xorl %eax, %eax
rep
stosl
movl $_ebss, %ecx
subl %edi, %ecx
jz .Lnobss
- shrl $2, %ecx /* it is 32 bit align, right? */
+ shrl $2, %ecx /* it is 32 bit aligned, right? */
xorl %eax, %eax
rep
stosl
* Now we are finished. Memory is up, data is copied and
* bss is cleared. Now we call the main routine and
* let it do the rest.
- */
+ */
post_code(0xfe) /* post fe */
/* Restore the stack location */
movl %ebp, %esp
-
+
/* The boot_complete flag has already been pushed */
call hardwaremain
- /*NOTREACHED*/
+ /* NOTREACHED */
.Lhlt:
post_code(0xee) /* post ee */
hlt
jmp .Lhlt
-
+
vec0:
pushl $0 /* error code */
pushl $0 /* vector */
pushl $0 /* error code */
pushl $1 /* vector */
jmp int_hand
-
+
vec2:
pushl $0 /* error code */
pushl $2 /* vector */
jmp int_hand
-
+
vec3:
pushl $0 /* error code */
pushl $3 /* vector */
jmp int_hand
-
+
vec4:
pushl $0 /* error code */
pushl $4 /* vector */
jmp int_hand
-
+
vec5:
pushl $0 /* error code */
pushl $5 /* vector */
jmp int_hand
-
+
vec6:
pushl $0 /* error code */
pushl $6 /* vector */
jmp int_hand
-
+
vec7:
pushl $0 /* error code */
pushl $7 /* vector */
jmp int_hand
-
+
vec8:
/* error code */
pushl $8 /* vector */
jmp int_hand
.word 0x9090
-
+
vec9:
pushl $0 /* error code */
pushl $9 /* vector */
jmp int_hand
-
+
vec10:
/* error code */
pushl $10 /* vector */
jmp int_hand
.word 0x9090
-
+
vec11:
/* error code */
pushl $11 /* vector */
jmp int_hand
.word 0x9090
-
+
vec12:
/* error code */
pushl $12 /* vector */
jmp int_hand
.word 0x9090
-
+
vec13:
/* error code */
pushl $13 /* vector */
jmp int_hand
.word 0x9090
-
+
vec14:
/* error code */
pushl $14 /* vector */
jmp int_hand
.word 0x9090
-
+
vec15:
pushl $0 /* error code */
pushl $15 /* vector */
jmp int_hand
-
+
vec16:
pushl $0 /* error code */
pushl $16 /* vector */
jmp int_hand
-
+
vec17:
/* error code */
pushl $17 /* vector */
jmp int_hand
.word 0x9090
-
+
vec18:
pushl $0 /* error code */
pushl $18 /* vector */
jmp int_hand
-
+
vec19:
pushl $0 /* error code */
pushl $19 /* vector */
jmp int_hand
+
int_hand:
/* At this point on the stack there is:
* 0(%esp) vector
.globl gdb_stub_breakpoint
gdb_stub_breakpoint:
popl %eax /* Return address */
- pushfl
+ pushfl
pushl %cs
pushl %eax /* Return address */
pushl $0 /* No error code */
*
* When we're executing code from RAM, we want to do more complex
* stuff, like initializing PCI option roms in real mode, or doing
- * a resume from a suspend to ram.
+ * a resume from a suspend to ram.
*/
gdt:
/* selgdt 0, unused */
.word 0x0000, 0x0000 /* dummy */
.byte 0x00, 0x00, 0x00, 0x00
- /* selgdt 0x10, flat code segment */
- .word 0xffff, 0x0000
- .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */
+ /* selgdt 0x10, flat code segment */
+ .word 0xffff, 0x0000
+ .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */
/* selgdt 0x18, flat data segment */
- .word 0xffff, 0x0000
- .byte 0x00, 0x93, 0xcf, 0x00
+ .word 0xffff, 0x0000
+ .byte 0x00, 0x93, 0xcf, 0x00
/* selgdt 0x20, unused */
.word 0x0000, 0x0000 /* dummy */
/* The next two entries are used for executing VGA option ROMs */
- /* selgdt 0x28 16-bit 64k code at 0x00000000 */
+ /* selgdt 0x28 16 bit 64k code at 0x00000000 */
.word 0xffff, 0x0000
.byte 0, 0x9a, 0, 0
- /* selgdt 0x30 16-bit 64k data at 0x00000000 */
+ /* selgdt 0x30 16 bit 64k data at 0x00000000 */
.word 0xffff, 0x0000
.byte 0, 0x92, 0, 0
/* The next two entries are used for ACPI S3 RESUME */
- /* selgdt 0x38, flat data segment 16bit */
+ /* selgdt 0x38, flat data segment 16 bit */
.word 0x0000, 0x0000 /* dummy */
- .byte 0x00, 0x93, 0x8f, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */
+ .byte 0x00, 0x93, 0x8f, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */
- /* selgdt 0x40, flat code segment 16bit */
- .word 0xffff, 0x0000
- .byte 0x00, 0x9b, 0x8f, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */
+ /* selgdt 0x40, flat code segment 16 bit */
+ .word 0xffff, 0x0000
+ .byte 0x00, 0x9b, 0x8f, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */
gdt_end:
idtarg:
.word _idt_end - _idt - 1 /* limit */
.long _idt
- .word 0
+ .word 0
_idt:
- .fill 20, 8, 0 # idt is unitiailzed
+ .fill 20, 8, 0 # idt is uninitialized
_idt_end:
.previous
/* Realmode IDT pointer structure. */
.globl __realmode_idt
__realmode_idt = RELOCATED(.)
- .word 1023 /* 16-bit limit */
- .long 0 /* 24-bit base */
+ .word 1023 /* 16 bit limit */
+ .long 0 /* 24 bit base */
.word 0
/* Preserve old stack */
1:
/* Setup a stack: Put the stack at the end of page zero.
* That way we can easily share it between real and
- * protected, since the 16-bit ESP at segment 0 will
+ * protected, since the 16 bit ESP at segment 0 will
* work for any case. */
mov $0x0, %ax
mov %ax, %ss
movl $0x1000, %eax
movl %eax, %esp
- /* Load our 16 bit idt */
+ /* Load 16 bit IDT */
xor %ax, %ax
mov %ax, %ds
lidt __realmode_idt
mov %ax, %gs
mov $0x40, %ax
mov %ax, %ds
- mov %cx, %ax // restore ax
/* ************************************ */
+ mov %cx, %ax // restore ax
// TODO this will not work for non-VGA option ROMs
/* run VGA BIOS at 0xc000:0003 */
lcall $0xc000, $0x0003
1:
/* Setup a stack: Put the stack at the end of page zero.
* That way we can easily share it between real and
- * protected, since the 16-bit ESP at segment 0 will
+ * protected, since the 16 bit ESP at segment 0 will
* work for any case. */
mov $0x0, %ax
mov %ax, %ss
mov $0x0, %ax
mov %ax, %ss
- /* Restore 16-bit IDT */
+ /* Restore 16 bit IDT */
xor %ax, %ax
mov %ax, %ds
lidt __realmode_idt
- /* Set up our segment registers to segment 0x0000 */
+ /* Set up segment registers to segment 0x0000 */
mov %ax, %es
mov %ax, %fs
mov %ax, %gs
return 0;
}
+#define PCI_CONFIG_SPACE_TYPE1 (1 << 0)
+#define PCI_CONFIG_SPACE_TYPE2 (1 << 1)
+#define PCI_SPECIAL_CYCLE_TYPE1 (1 << 4)
+#define PCI_SPECIAL_CYCLE_TYPE2 (1 << 5)
+
int int1a_handler(struct eregs *regs)
{
unsigned short func = (unsigned short)regs->eax;
switch (func) {
case PCIBIOS_CHECK:
regs->edx = 0x20494350; /* ' ICP' */
+ regs->eax &= 0xffff0000; /* Clear AH / AL */
+ regs->eax |= PCI_CONFIG_SPACE_TYPE1 | PCI_SPECIAL_CYCLE_TYPE1;
+ // last bus in the system. Hard code to 255 for now.
+ // dev_enumerate() does not seem to tell us (publically)
+ regs->ecx = 0xff;
regs->edi = 0x00000000; /* protected mode entry */
retval = 0;
break;
dev = dev_find_slot(bus, devfn);
if (!dev) {
printk(BIOS_DEBUG, "0x%x: BAD DEVICE bus %d devfn 0x%x\n", func, bus, devfn);
- // idiots. the pcibios guys assumed you'd never pass a bad bus/devfn!
+ // Or are we supposed to return PCIBIOS_NODEV?
regs->eax = PCIBIOS_BADREG;
retval = -1;
return retval;
{
int res = -1;
- /* This int15 handler is VIA Tech. specific. Other chipsets need other
+ /* This int15 handler is Intel IGD. specific. Other chipsets need other
* handlers. The right way to do this is to move this handler code into
* the mainboard or northbridge code.
+ * TODO: completely move to mainboards / chipsets.
*/
switch (regs->eax & 0xffff) {
- case 0x5f19:
- break;
- case 0x5f18:
- regs->eax = 0x5f;
- // MCLK = 133, 32M frame buffer, 256 M main memory
- regs->ebx = 0x545;
- regs->ecx = 0x060;
- res = 0;
- break;
- case 0x5f00:
- regs->eax = 0x8600;
- break;
- case 0x5f01:
- regs->eax = 0x5f;
- regs->ecx = (regs->ecx & 0xffffff00 ) | 2; // panel type = 2 = 1024 * 768
- res = 0;
- break;
- case 0x5f02:
- regs->eax = 0x5f;
- regs->ebx = (regs->ebx & 0xffff0000) | 2;
- regs->ecx = (regs->ecx & 0xffff0000) | 0x401; // PAL + crt only
- regs->edx = (regs->edx & 0xffff0000) | 0; // TV Layout - default
- res = 0;
- break;
- case 0x5f0f:
- regs->eax = 0x860f;
- break;
/* And now Intel IGD code */
#define BOOT_DISPLAY_DEFAULT 0
#define BOOT_DISPLAY_CRT (1 << 0)
#define BOOT_DISPLAY_TV2 (1 << 5)
#define BOOT_DISPLAY_EFP2 (1 << 6)
#define BOOT_DISPLAY_LCD2 (1 << 7)
-
case 0x5f35:
regs->eax = 0x5f;
regs->ecx = BOOT_DISPLAY_DEFAULT;
projects / coreboot.git / commitdiff