+++ /dev/null
-#ifndef ASM_H
-#define ASM_H
-
-#define ASSEMBLER 1
-
-#endif /* ASM_H */
uint32_t ecx;
uint32_t edx;
};
+
/*
* Generic CPUID function
*/
return result;
}
-
/*
* CPUID functions returning a single datum
*/
: "ebx", "ecx", "edx");
return eax;
}
+
static inline unsigned int cpuid_ebx(unsigned int op)
{
unsigned int eax, ebx;
: "ecx", "edx" );
return ebx;
}
+
static inline unsigned int cpuid_ecx(unsigned int op)
{
unsigned int eax, ecx;
: "ebx", "edx" );
return ecx;
}
+
static inline unsigned int cpuid_edx(unsigned int op)
{
unsigned int eax, edx;
return edx;
}
-
-
#define X86_VENDOR_INVALID 0
#define X86_VENDOR_INTEL 1
#define X86_VENDOR_CYRIX 2
unsigned vendor;
unsigned device;
};
+
struct cpu_driver {
struct device_operations *ops;
struct cpu_device_id *id_table;
return ci->index;
}
-
struct cpuinfo_x86 {
uint8_t x86; /* CPU family */
uint8_t x86_vendor; /* CPU vendor */
+++ /dev/null
-/*
-This software and ancillary information (herein called SOFTWARE )
-called LinuxBIOS is made available under the terms described
-here. The SOFTWARE has been approved for release with associated
-LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has
-been authored by an employee or employees of the University of
-California, operator of the Los Alamos National Laboratory under
-Contract No. W-7405-ENG-36 with the U.S. Department of Energy. The
-U.S. Government has rights to use, reproduce, and distribute this
-SOFTWARE. The public may copy, distribute, prepare derivative works
-and publicly display this SOFTWARE without charge, provided that this
-Notice and any statement of authorship are reproduced on all copies.
-Neither the Government nor the University makes any warranty, express
-or implied, or assumes any liability or responsibility for the use of
-this SOFTWARE. If SOFTWARE is modified to produce derivative works,
-such modified SOFTWARE should be clearly marked, so as not to confuse
-it with the version available from LANL.
- */
-/* Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL
- * rminnich@lanl.gov
- */
-
-
-#ifndef ROM_INTEL_H
-#define ROM_INTEL_H
-
-/*
- * Bootstrap code for the Intel
- *
- */
-
-#define RET_LABEL(label) \
- jmp label##_done
-
-#define CALL_LABEL(label) \
- jmp label ;\
-label##_done:
-
-#define CALLSP(func) \
- lea 0f, %esp ; \
- jmp func ; \
-0:
-
-#define RETSP \
- jmp *%esp
-
-
-#define post_code(value) \
- movb $value, %al; \
- outb %al, $0x80
-
-#endif /* ROM_INTEL_H */
-/* -*- asm -*-
- * $ $
- *
- */
-
-/*
- * Copyright (C) 1996-2002 Markus Franz Xaver Johannes Oberhumer
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2002 Eric Biederman
*
- * This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
*
- * Originally this code was part of ucl the data compression library
- * for upx the ``Ultimate Packer of eXecutables''.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
*
- * - Converted to gas assembly, and refitted to work with etherboot.
- * Eric Biederman 20 Aug 2002
- * - Merged the nrv2b decompressor into crt0.base of coreboot
- * Eric Biederman 26 Sept 2002
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <cpu/x86/post_code.h>
-#include <arch/asm.h>
-#include <arch/intel.h>
-#include <console/loglevel.h>
-
-/*
- * This is the entry code the code in .reset section
- * jumps to this address.
- *
- */
.section ".rom.data", "a", @progbits
.section ".rom.text", "ax", @progbits
- post_code(0x01) /* delay for chipsets */
+/* This is the entry codde. The code in the .reset section jumps here. */
+
+ post_code(0x01)
-/*
- * Copyright 2002 Eric Biederman
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2002 Eric Biederman
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
*
- * This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the License.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <arch/asm.h>
-#include <arch/intel.h>
-#include <console/loglevel.h>
+#include <cpu/x86/post_code.h>
-/*
- * This is the entry code.
- * The code in the .reset section jumps to this address.
- *
- */
.section ".rom.data", "a", @progbits
.section ".rom.text", "ax", @progbits
- post_code(0x01) /* delay for chipsets */
+/* This is the entry code. The code in the .reset section jumps here. */
+
+ post_code(0x01)
-#include <arch/asm.h>
-#include <arch/intel.h>
+#include <cpu/x86/post_code.h>
.section ".text"
.code32
get_fms(&c, cpu->device);
- printk(BIOS_DEBUG, "CPU: family %02x, model %02x, stepping %02x\n", c.x86, c.x86_model, c.x86_mask);
+ printk(BIOS_DEBUG, "CPU: family %02x, model %02x, stepping %02x\n",
+ c.x86, c.x86_model, c.x86_mask);
/* Lookup the cpu's operations */
set_cpu_ops(cpu);
-// #include <loglevel.h>
jmp console0
+
+#define RET_LABEL(label) \
+ jmp label##_done
+
+#define CALL_LABEL(label) \
+ jmp label ;\
+label##_done:
+
+#define CALLSP(func) \
+ lea 0f, %esp ; \
+ jmp func ; \
+0:
+
+#define RETSP \
+ jmp *%esp
+
+
#include "console.inc"
#include "pci.inc"
#include "ramtest.inc"
-#include <arch/asm.h>
-#include <arch/intel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/lapic_def.h>
+
.text
.globl _secondary_start, _secondary_start_end
.balign 4096
*
*/
-#include <arch/asm.h>
-
#define LAPIC_ID 0xfee00020
/* SMM_HANDLER_OFFSET is the 16bit offset within the ASEG
* MA 02110-1301 USA
*/
-#include <arch/asm.h>
-
// Make sure no stage 2 code is included:
#define __PRE_RAM__
// FIXME: Is this piece of code southbridge specific, or
// can it be cleaned up so this include is not required?
+// It's needed right now because we get our PM_BASE from
+// here.
#include "../../../southbridge/intel/i82801gx/i82801gx.h"
#undef DEBUG_SMM_RELOCATION
--- /dev/null
+
+
+#define post_code(value) \
+ movb $value, %al; \
+ outb %al, $0x80
+
projects / coreboot.git / commitdiff