resource->flags &= ~IORESOURCE_STORED;
base += size;
- printk_spew(
- "%s %02x * [0x%08lx - 0x%08lx] %s\n",
- dev_path(dev),
- resource->index,
- resource->base, resource->base + resource->size -1,
- (resource->flags & IORESOURCE_IO)? "io":
- (resource->flags & IORESOURCE_PREFETCH)? "prefmem": "mem");
+ printk_spew("%s %02x * [0x%08lx - 0x%08lx] %s\n",
+ dev_path(dev),
+ resource->index, resource->base,
+ resource->base + resource->size - 1,
+ (resource->flags & IORESOURCE_IO)? "io":
+ (resource->flags & IORESOURCE_PREFETCH)? "prefmem": "mem");
}
-
}
/* A pci bridge resource does not need to be a power
* of two size, but it does have a minimum granularity.
bridge->size = round(base, 1UL << bridge->gran) - bridge->base;
printk_spew("%s compute_allocate_%s: base: %08lx size: %08lx align: %d gran: %d done\n",
- dev_path(dev),
- (bridge->flags & IORESOURCE_IO)? "io":
- (bridge->flags & IORESOURCE_PREFETCH)? "prefmem" : "mem",
- base, bridge->size, bridge->align, bridge->gran);
+ dev_path(dev),
+ (bridge->flags & IORESOURCE_IO)? "io":
+ (bridge->flags & IORESOURCE_PREFETCH)? "prefmem" : "mem",
+ base, bridge->size, bridge->align, bridge->gran);
}
/** Assign the computed resources to the bridges and devices on the bus.
* Recurse to any bridges found on this bus first. Then do the devices
- * on this bus.
+ * on this bus.
+ *
* @param bus Pointer to the structure for this bus
*/
void assign_resources(struct bus *bus)
printk_debug("ASSIGNED RESOURCES, bus %d\n", bus->secondary);
}
+/**
+ * @brief Enable the resources for a specific device
+ *
+ * @param dev the device whose resources are to be enabled
+ *
+ * Enable resources of the device by calling the device specific
+ * enable_resources() method.
+ *
+ * The parent's resources should be enabled first to avoid having enabling
+ * order problem. This is done by calling the parent's enable_resources()
+ * method and let the method to call it's children's enable_resoruces() via
+ * enable_childrens_resources().
+ */
void enable_resources(struct device *dev)
{
- /* Enable the resources for a specific device.
- * The parents resources should be enabled first to avoid
- * having enabling ordering problems.
- */
if (!dev->ops || !dev->ops->enable_resources) {
- printk_err("%s missing enable_resources\n",
- dev_path(dev));
+ printk_err("%s missing enable_resources\n", dev_path(dev));
return;
}
if (!dev->enable) {
* @brief Determine the existence of dynamic devices and construct dynamic
* device tree.
*
- * Start for the root device 'dev_root', scan the buses in the system, build
- * the dynamic device tree according to the result of the probe.
+ * Start for the root device 'dev_root', scan the buses in the system
+ * recursively, build the dynamic device tree according to the result
+ * of the probe.
*
- * This function have no idea how to scan and probe the buses and devices at
- * all. It depends on the bus/device specific scan_bus() method to do it.
- * The scan_bus() function also have to create the device structure and attach
+ * This function has no idea how to scan and probe buses and devices at all.
+ * It depends on the bus/device specific scan_bus() method to do it. The
+ * scan_bus() function also have to create the device structure and attach
* it to the device tree.
*/
void dev_enumerate(void)
/**
* @brief Configure devices on the devices tree.
*
- * Starting at the root, compute what resources are needed and allocate them.
- * I/O starts at PCI_IO_START. Since the assignment is hierarchical we
- * set the values into the dev_root struct.
+ * Starting at the root of the dynamic device tree, travel recursively,
+ * compute resources needed by each device and allocate them.
+ *
+ * I/O resources start at DEVICE_IO_START and grow upward. MEM resources start
+ * at DEVICE_MEM_START and grow downward.
+ *
+ * Since the assignment is hierarchical we set the values into the dev_root
+ * struct.
*/
void dev_configure(void)
{
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
- }
- else {
+ } else {
printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
bus_8111_1 = 4;
dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
if (dev) {
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
- }
- else {
+ } else {
printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
-
bus_8131_1 = 2;
}
/* 8131-2 */
dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
if (dev) {
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
- }
- else {
+ } else {
printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
bus_8131_2 = 3;
smp_write_bus(mc, bus_isa, "ISA ");
/* IOAPIC handling */
-
smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
{
device_t dev;
uint32_t base;
- /* 8131 apic 3 */
+ /* 8131-1 apic #3 */
dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
if (dev) {
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
base &= PCI_BASE_ADDRESS_MEM_MASK;
smp_write_ioapic(mc, 0x03, 0x11, base);
}
- /* 8131 apic 4 */
+ /* 8131-2 apic #4 */
dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
if (dev) {
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x00, MP_APIC_ALL, 0x01);
+ /* PCI Ints: Type Polarity Trigger Bus ID PCIDEVNUM|IRQ APIC ID PIN# */
+ /* On board nics */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x03<<2)|0, 0x02, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x04<<2)|0, 0x02, 0x13);
/* PCI Slot 1 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (1<<2)|0, 0x02, 0x11);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (1<<2)|1, 0x02, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (1<<2)|2, 0x02, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (1<<2)|3, 0x02, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|0, 0x02, 0x11);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|1, 0x02, 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|2, 0x02, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|3, 0x02, 0x10);
/* PCI Slot 2 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (2<<2)|0, 0x02, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (2<<2)|1, 0x02, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (2<<2)|2, 0x02, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (2<<2)|3, 0x02, 0x11);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|0, 0x02, 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|1, 0x02, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|2, 0x02, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|3, 0x02, 0x11);
/* PCI Slot 3 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (1<<2)|0, 0x02, 0x11);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (1<<2)|1, 0x02, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (1<<2)|2, 0x02, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (1<<2)|3, 0x02, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|0, 0x02, 0x11);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|1, 0x02, 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|2, 0x02, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|3, 0x02, 0x10);
/* PCI Slot 4 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (2<<2)|0, 0x02, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (2<<2)|1, 0x02, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (2<<2)|2, 0x02, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (2<<2)|3, 0x02, 0x11);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (2<<2)|0, 0x02, 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (2<<2)|1, 0x02, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (2<<2)|2, 0x02, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (2<<2)|3, 0x02, 0x11);
/* PCI Slot 5 */
#warning "FIXME get the irqs right, it's just hacked to work for now"
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (4<<2)|3, 0x02, 0x13);
- /* On board nics */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (3<<2)|0, 0x02, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (4<<2)|0, 0x02, 0x13);
-
/* There is no extension information... */
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk_debug("Wrote the mp table end at: %p - %p\n",
- mc, smp_next_mpe_entry(mc));
+ mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
pci 0:18.1
pci 0:18.2
pci 0:18.3
- southbridge amd/amd8131 "amd8131" link 0
+ southbridge amd/amd8131 "amd8131" link 1
pci 0:0.0
pci 0:0.1
pci 0:1.0
pci 0:1.1
end
- southbridge amd/amd8111 "amd8111" link 0
+ southbridge amd/amd8111 "amd8111" link 1
pci 0:0.0
pci 0:1.0 on
pci 0:1.1 on
end
cpu k8 "cpu0"
- register "up" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600 }"
+ register "across" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600 }"
end
cpu k8 "cpu1"
console_init();
setup_ibm_e325_resource_map();
needs_reset = setup_coherent_ht_domain();
- needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
+ needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xA0);
if (needs_reset) {
print_info("ht reset -\r\n");
soft_reset();
}
-#if 0
+#if 1
print_pci_devices();
#endif
enable_smbus();
#if 0
dump_spd_registers(&cpu[0]);
#endif
+
memreset_setup();
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
dump_pci_device(PCI_DEV(0, 0x18, 2));
#endif
-
#if 0
/* Check the first 1M */
ram_check(0x00000000, 0x001000000);
}
struct chip_control mainboard_arima_hdama_control = {
.enumerate = enumerate,
- .name = "Arima HDAMA mainboard ",
+ .name = "IBM E325 mainboard ",
};
-#if 0
-=================== CPU0 ===================
-RAM 0x0(0x3,0x3f0000):
- 0x000:0x3f00(no interleave, bogus), CP0, s: WE
-RAM 0x1(0x400003,0x7f0001):
- 0x4000:0x7f00(no interleave, bogus), CP1, s: WE
-RAM 0x2(0x800000,0x2):
- 0x8000:0x000(no interleave, bogus), CP2, s: NO WE
-RAM 0x3(0x800000,0x3):
- 0x8000:0x000(no interleave, bogus), CP3, s: NO WE
-RAM 0x4(0x800000,0x4):
- 0x8000:0x000(no interleave, bogus), CP4, s: NO WE
-RAM 0x5(0x800000,0x5):
- 0x8000:0x000(no interleave, bogus), CP5, s: NO WE
-RAM 0x6(0x800000,0x6):
- 0x8000:0x000(no interleave, bogus), CP6, s: NO WE
-RAM 0x7(0x800000,0x7):
- 0x8000:0x000(no interleave, bogus), CP7, s: NO WE
-MMIO 0x0(0xfc0003,0xfe2f10):
- 0xfc000000:0xfe2f0000, HT1 CP0, WE:RE
-MMIO 0x1(0x0,0x0):
- 0x00000:0x00000, HT0 CP0, NO WE:NO RE
-MMIO 0x2(0x0,0x0):
- 0x00000:0x00000, HT0 CP0, NO WE:NO RE
-MMIO 0x3(0x0,0x0):
- 0x00000:0x00000, HT0 CP0, NO WE:NO RE
-MMIO 0x4(0xfec003,0xfec010):
- 0xfec00000:0xfec00000, HT1 CP0, WE:RE
-MMIO 0x5(0xa03,0xb10):
- 0xa0000:0xb0000, HT1 CP0, WE:RE
-MMIO 0x6(0xfed003,0xfed010):
- 0xfed00000:0xfed00000, HT1 CP0, WE:RE
-MMIO 0x7(0x0,0x0):
- 0x00000:0x00000, HT0 CP0, NO WE:NO RE
-PCIO 0x0(0x33,0x1fff010):
- 0x00000:0x1fff0000, HT1 CP0, ISA VGA WE:RE
-PCIO 0x1(0x0,0x0):
- 0x00000:0x00000, HT0 CP0, NO WE:NO RE
-PCIO 0x2(0x0,0x0):
- 0x00000:0x00000, HT0 CP0, NO WE:NO RE
-PCIO 0x3(0x0,0x0):
- 0x00000:0x00000, HT0 CP0, NO WE:NO RE
-CONF 0x0(0xff000103):
- 0x00000:0x00000, HT1 CP0, Dev number compare enable WE:RE
-CONF 0x1(0xffff0060):
- 0xff0000:0x00000, HT0 CP6, Dev number compare enable NO WE:NO RE
-CONF 0x2(0xffff0324):
- 0xff0000:0x00000, HT3 CP2, Dev number compare enable NO WE:NO RE
-CONF 0x3(0xffff0204):
- 0xff0000:0x00000, HT2 CP0, Dev number compare enable NO WE:NO RE
-=================== CPU1 ===================
-RAM 0x0(0x3,0x3f0000):
- 0x000:0x3f00(no interleave, bogus), CP0, s: WE
-RAM 0x1(0x400003,0x7f0001):
- 0x4000:0x7f00(no interleave, bogus), CP1, s: WE
-RAM 0x2(0x800000,0x2):
- 0x8000:0x000(no interleave, bogus), CP2, s: NO WE
-RAM 0x3(0x800000,0x3):
- 0x8000:0x000(no interleave, bogus), CP3, s: NO WE
-RAM 0x4(0x800000,0x4):
- 0x8000:0x000(no interleave, bogus), CP4, s: NO WE
-RAM 0x5(0x800000,0x5):
- 0x8000:0x000(no interleave, bogus), CP5, s: NO WE
-RAM 0x6(0x800000,0x6):
- 0x8000:0x000(no interleave, bogus), CP6, s: NO WE
-RAM 0x7(0x800000,0x7):
- 0x8000:0x000(no interleave, bogus), CP7, s: NO WE
-MMIO 0x0(0xfc0003,0xfe2f10):
- 0xfc000000:0xfe2f0000, HT1 CP0, WE:RE
-MMIO 0x1(0x0,0x0):
- 0x00000:0x00000, HT0 CP0, NO WE:NO RE
-MMIO 0x2(0x0,0x0):
- 0x00000:0x00000, HT0 CP0, NO WE:NO RE
-MMIO 0x3(0x0,0x0):
- 0x00000:0x00000, HT0 CP0, NO WE:NO RE
-MMIO 0x4(0xfec003,0xfec010):
- 0xfec00000:0xfec00000, HT1 CP0, WE:RE
-MMIO 0x5(0xa03,0xb10):
- 0xa0000:0xb0000, HT1 CP0, WE:RE
-MMIO 0x6(0xfed003,0xfed010):
- 0xfed00000:0xfed00000, HT1 CP0, WE:RE
-MMIO 0x7(0x0,0x0):
- 0x00000:0x00000, HT0 CP0, NO WE:NO RE
-PCIO 0x0(0x33,0x1fff010):
- 0x00000:0x1fff0000, HT1 CP0, ISA VGA WE:RE
-PCIO 0x1(0x0,0x0):
- 0x00000:0x00000, HT0 CP0, NO WE:NO RE
-PCIO 0x2(0x0,0x0):
- 0x00000:0x00000, HT0 CP0, NO WE:NO RE
-PCIO 0x3(0x0,0x0):
- 0x00000:0x00000, HT0 CP0, NO WE:NO RE
-CONF 0x0(0xff000103):
- 0x00000:0x00000, HT1 CP0, Dev number compare enable WE:RE
-CONF 0x1(0xffff0200):
- 0xff0000:0x00000, HT2 CP0, NO WE:NO RE
-CONF 0x2(0xffff0370):
- 0xff0000:0x00000, HT3 CP7, Dev number compare enable NO WE:NO RE
-CONF 0x3(0xffff0330):
- 0xff0000:0x00000, HT3 CP3, Dev number compare enable NO WE:NO RE
-#endif
/*
* IBM E325 needs a different resource map
*
* This field defines the upper address bits of a 40bit address
* that defines the start of memory-mapped I/O region i
*/
- PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0xfe2f10,
- PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0xfc0003,
- PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0xfec010,
- PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0xfec003,
- PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0xb10,
- PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0xa03,
- PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0xfed010,
- PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0xfed003,
- PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0x0,
- PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0x0,
- PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0x0,
- PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0x0,
- PCI_ADDR(0, 0x18, 1, 0xac), 0x48, 0x0,
- PCI_ADDR(0, 0x18, 1, 0xa8), 0xf0, 0x0,
- PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0x0,
- PCI_ADDR(0, 0x18, 1, 0xa0), 0xf0, 0x0,
+
+ PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0xfe2f10,
+ PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0xfc0003,
+ //PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0x0,
+ // PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0x0,
+
+ PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0xfec010,
+ PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0xfec003,
+ //PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0x0,
+ //PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0x0,
+
+ PCI_ADDR(0, 0x18, 1, 0xac), 0x48, 0xb10,
+ PCI_ADDR(0, 0x18, 1, 0xa8), 0xf0, 0xa03,
+ //PCI_ADDR(0, 0x18, 1, 0xac), 0x48, 0x0,
+ //PCI_ADDR(0, 0x18, 1, 0xa8), 0xf0, 0x0,
+
+ PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0xfed010,
+ PCI_ADDR(0, 0x18, 1, 0xa0), 0xf0, 0xfed003,
+ //PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0x0,
+ //PCI_ADDR(0, 0x18, 1, 0xa0), 0xf0, 0x0,
+
PCI_ADDR(0, 0x18, 1, 0x9c), 0x48, 0x0,
PCI_ADDR(0, 0x18, 1, 0x98), 0xf0, 0x0,
PCI_ADDR(0, 0x18, 1, 0x94), 0x48, 0x0,
* registers on Hammer A0 revision.
*/
-#if 0
+#if 1
print_debug("coherent_ht_finalize\r\n");
#endif
rev_a0 = is_cpu_rev_a0();
pci_write_config32(dev, 0x68, val);
if (rev_a0) {
+ print_debug("shit it is an old cup\n");
pci_write_config32(dev, 0x94, 0);
pci_write_config32(dev, 0xb4, 0);
pci_write_config32(dev, 0xd4, 0);
}
-
-
}
-#if 0
+#if 1
print_debug("done\r\n");
#endif
}
link_type = pci_read_config32(f0_dev, reg);
if (link_type & LinkConnected) {
cmd &= 0xff << (link *8);
- /* FIXME this assumes the device on the other side is an AMD device */
+ /* FIXME this assumes the device on the other
+ * side is an AMD device */
cmd |= 0x25 << (link *8);
}
}
}
if ((mem[idx - 1].basek + mem[idx - 1].sizek) <= 4*1024*1024) {
idx -= 1;
- }
- else {
+ } else {
mem[idx - 1].basek = 4*1024*1024;
mem[idx - 1].sizek -= (4*1024*1024 - mmio_basek);
}
static void debug_f1_devs(void)
{
int i;
- for(i = 0; i < F1_DEVS; i++) {
+ for (i = 0; i < F1_DEVS; i++) {
device_t dev;
dev = __f1_dev[i];
if (dev) {
printk_debug("__f1_dev[%d]: %s bus: %p\n",
- i, dev_path(dev), dev->bus);
+ i, dev_path(dev), dev->bus);
}
}
}
if (__f1_dev[0]) {
return;
}
- for(i = 0; i < F1_DEVS; i++) {
+ for (i = 0; i < F1_DEVS; i++) {
__f1_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 1));
}
if (!__f1_dev[0]) {
{
int i;
get_f1_devs();
- for(i = 0; i < F1_DEVS; i++) {
+ for (i = 0; i < F1_DEVS; i++) {
device_t dev;
dev = __f1_dev[i];
if (dev) {
return (dev->path.u.pci.devfn >> 3) - 0x18;
}
-
static unsigned int amdk8_scan_chains(device_t dev, unsigned int max)
{
unsigned nodeid;
unsigned link;
+
nodeid = amdk8_nodeid(dev);
+
#if 1
printk_debug("amdk8_scan_chains max: %d starting...\n", max);
#endif
- for(link = 0; link < dev->links; link++) {
+
+ for (link = 0; link < dev->links; link++) {
uint32_t link_type;
uint32_t busses, config_busses;
unsigned free_reg, config_reg;
if (!(link_type & NonCoherent)) {
continue;
}
- /* See if there is an available configuration space mapping register in function 1. */
+ /* See if there is an available configuration space mapping register
+ * in function 1. */
free_reg = 0;
for(config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) {
uint32_t config;
if (free_reg && (config_reg > 0xec)) {
config_reg = free_reg;
}
- /* If we can't find an available configuration space mapping register skip this bus */
+ /* If we can't find an available configuration space mapping
+ * register skip this bus */
if (config_reg > 0xec) {
continue;
}
- /* Set up the primary, secondary and subordinate bus numbers. We have
- * no idea how many busses are behind this bridge yet, so we set the subordinate
- * bus number to 0xff for the moment.
+ /* Set up the primary, secondary and subordinate bus numbers.
+ * We have no idea how many busses are behind this bridge yet,
+ * so we set the subordinate bus number to 0xff for the moment.
*/
dev->link[link].secondary = ++max;
dev->link[link].subordinate = 0xff;
config_busses = f1_read_config32(config_reg);
/* Configure the bus numbers for this bridge: the configuration
- * transactions will not be propagates by the bridge if it is not
- * correctly configured
+ * transactions will not be propagates by the bridge if it is
+ * not correctly configured
*/
busses &= 0xff000000;
busses |= (((unsigned int)(dev->bus->secondary) << 0) |
f1_write_config32(config_reg, config_busses);
#if 1
- printk_debug("Hyper transport scan link: %d max: %d\n", link, max);
-#endif
- /* Now we can scan all of the subordinate busses i.e. the chain on the hypertranport link */
+ printk_debug("Hyper transport scan link: %d max: %d\n",
+ link, max);
+#endif
+
+ /* Now we can scan all of the subordinate busses i.e. the
+ * chain on the hypertranport link */
max = hypertransport_scan_chain(&dev->link[link], max);
#if 1
- printk_debug("Hyper transport scan link: %d new max: %d\n", link, max);
+ printk_debug("Hyper transport scan link: %d new max: %d\n",
+ link, max);
#endif
- /* We know the number of busses behind this bridge. Set the subordinate
- * bus number to it's real value
+ /* We know the number of busses behind this bridge. Set the
+ * subordinate bus number to it's real value
*/
dev->link[link].subordinate = max;
busses = (busses & 0xff00ffff) |
((unsigned int) (dev->link[link].subordinate) << 16);
pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
- config_busses = (config_busses & 0x00ffffff) | (dev->link[link].subordinate << 24);
+ config_busses = (config_busses & 0x00ffffff) |
+ (dev->link[link].subordinate << 24);
f1_write_config32(config_reg, config_busses);
#if 1
printk_debug("Hypertransport scan link done\n");
return max;
}
-
static unsigned amdk8_find_iopair(unsigned nodeid, unsigned link)
{
unsigned free_reg, reg;
free_reg = 0;
- for(reg = 0xc0; reg <= 0xd8; reg += 0x8) {
+ for (reg = 0xc0; reg <= 0xd8; reg += 0x8) {
uint32_t base, limit;
base = f1_read_config32(reg);
limit = f1_read_config32(reg + 0x4);
}
/* Do I have a match for this node and link? */
if (((base & 3) == 3) &&
- ((limit & 7) == nodeid) &&
- (((limit >> 4) & 3) == link)) {
+ ((limit & 7) == nodeid) &&
+ (((limit >> 4) & 3) == link)) {
break;
}
}
static unsigned amdk8_find_mempair(unsigned nodeid, unsigned link)
{
unsigned free_reg, reg;
+
free_reg = 0;
- for(reg = 0x80; reg <= 0xb8; reg += 0x8) {
+ for (reg = 0x80; reg <= 0xb8; reg += 0x8) {
uint32_t base, limit;
base = f1_read_config32(reg);
limit = f1_read_config32(reg + 0x4);
dev->resource[reg].flags = IORESOURCE_IO;
dev->resource[reg].index = index | (link & 0x3);
compute_allocate_resource(&dev->link[link], &dev->resource[reg],
- IORESOURCE_IO, IORESOURCE_IO);
+ IORESOURCE_IO, IORESOURCE_IO);
reg++;
}
dev->resource[reg].flags = IORESOURCE_MEM;
dev->resource[reg].index = index | (link & 0x3);
compute_allocate_resource(&dev->link[link], &dev->resource[reg],
- IORESOURCE_MEM, IORESOURCE_MEM);
+ IORESOURCE_MEM, IORESOURCE_MEM);
reg++;
}
dev->resources = reg;
nodeid = amdk8_nodeid(dev);
dev->resources = 0;
memset(&dev->resource, 0, sizeof(dev->resource));
- for(link = 0; link < dev->links; link++) {
+ for (link = 0; link < dev->links; link++) {
if (dev->link[link].children) {
amdk8_link_read_bases(dev, nodeid, link);
}
}
}
-static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned nodeid)
+static void amdk8_set_resource(device_t dev, struct resource *resource,
+ unsigned nodeid)
{
unsigned long rbase, rlimit;
unsigned reg, link;
rbase = resource->base;
/* Get the limit (rounded up) */
- rlimit = rbase + ((resource->size + resource->align - 1UL) & ~(resource->align -1)) - 1UL;
+ rlimit = rbase + ((resource->size + resource->align - 1UL) &
+ ~(resource->align -1)) - 1UL;
/* Get the register and link */
reg = resource->index & ~3;
if (resource->flags & IORESOURCE_IO) {
uint32_t base, limit;
compute_allocate_resource(&dev->link[link], resource,
- IORESOURCE_IO, IORESOURCE_IO);
+ IORESOURCE_IO, IORESOURCE_IO);
base = f1_read_config32(reg);
limit = f1_read_config32(reg + 0x4);
base &= 0xfe000fcc;
f1_write_config32(reg + 0x4, limit);
f1_write_config32(reg, base);
- }
- else if (resource->flags & IORESOURCE_MEM) {
+ } else if (resource->flags & IORESOURCE_MEM) {
uint32_t base, limit;
compute_allocate_resource(&dev->link[link], resource,
- IORESOURCE_MEM, IORESOURCE_MEM);
+ IORESOURCE_MEM, IORESOURCE_MEM);
base = f1_read_config32(reg);
limit = f1_read_config32(reg + 0x4);
base &= 0x000000f0;
f1_write_config32(reg, base);
}
resource->flags |= IORESOURCE_STORED;
- printk_debug(
- "%s %02x <- [0x%08lx - 0x%08lx] node %d link %d %s\n",
- dev_path(dev),
- reg,
- rbase, rlimit,
- nodeid, link,
- (resource->flags & IORESOURCE_IO)? "io": "mem");
+ printk_debug("%s %02x <- [0x%08lx - 0x%08lx] node %d link %d %s\n",
+ dev_path(dev), reg, rbase, rlimit, nodeid, link,
+ (resource->flags & IORESOURCE_IO)? "io": "mem");
}
static void amdk8_set_resources(device_t dev)
nodeid = amdk8_nodeid(dev);
/* Set each resource we have found */
- for(i = 0; i < dev->resources; i++) {
+ for (i = 0; i < dev->resources; i++) {
amdk8_set_resource(dev, &dev->resource[i], nodeid);
}
-
- for(link = 0; link < dev->links; link++) {
+
+ for (link = 0; link < dev->links; link++) {
struct bus *bus;
bus = &dev->link[link];
if (bus->children) {
{
unsigned reg;
/* Unmap all of the HT chains */
- for(reg = 0xe0; reg <= 0xec; reg += 4) {
+ for (reg = 0xe0; reg <= 0xec; reg += 4) {
f1_write_config32(reg, 0);
}
max = pci_scan_bus(&root->link[0], PCI_DEVFN(0x18, 0), 0xff, max);
}
if (vgalink != 1) {
- /* now find the IOPAIR that goes to vgalink and set the vga enable in the base part (0x30) */
- /* now allocate an MMIOPAIR and point it to the CPU0, LINK=vgalink */
- /* now set IORR1 so it has a hole for the 0xa0000-0xcffff region */
+ /* now find the IOPAIR that goes to vgalink and set the vga
+ * enable in the base part (0x30) */
+ /* now allocate an MMIOPAIR and point it to the CPU0,
+ * LINK=vgalink */
+ /* now set IORR1 so it has a hole for the 0xa0000-0xcffff
+ * region */
}
#endif
-
pci_dev_enable_resources(dev);
- //enable_childrens_resources(dev);
}
static struct device_operations northbridge_operations = {
projects / coreboot.git / commitdiff