zero warnings days. Down to under 600 different warnings

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5425 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/cpu/amd/model_lx/vsmsetup.c b/src/cpu/amd/model_lx/vsmsetup.c
index 290fa864df6d770e7a22e5edfe59f5543153dfee..d2a3c58344504f434c2ee7155a01229040ff8613 100644 (file)
--- a/src/cpu/amd/model_lx/vsmsetup.c
+++ b/src/cpu/amd/model_lx/vsmsetup.c
@@ -268,10 +268,7 @@ uint32_t VSA_msrRead(uint32_t msrAddr)
 
 void do_vsmbios(void)
 {
-       device_t dev;
-       unsigned long busdevfn;
        unsigned char *buf;
-       unsigned int size = SMM_SIZE * 1024;
        int i;
 
        printk(BIOS_ERR, "do_vsmbios\n");

diff --git a/src/drivers/ati/ragexl/xlinit.c b/src/drivers/ati/ragexl/xlinit.c
index 6e43bf834fb6390000806e86b0258e5932b9241e..09c9400e444a5605263c26803851fd1a6e88c611 100644 (file)
--- a/src/drivers/ati/ragexl/xlinit.c
+++ b/src/drivers/ati/ragexl/xlinit.c
@@ -489,7 +489,10 @@ static void ati_ragexl_init(device_t dev)
        int j;
        u16 type;
         u8 rev;
-       const char *chipname = NULL, *xtal;
+       const char *chipname = NULL;
+#if CONFIG_CONSOLE_BTEXT
+       const char *xtal;
+#endif
        int pll, mclk, xclk;
 
 #if CONFIG_CONSOLE_BTEXT==1

diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c
index 4bd7a4584433fd42e80dcbf4180598817dbcecd0..05f436e65e605015c73f9234d4bd3ce5af7f1813 100644 (file)
--- a/src/mainboard/bcom/winnetp680/romstage.c
+++ b/src/mainboard/bcom/winnetp680/romstage.c
@@ -39,10 +39,6 @@
 #include "superio/winbond/w83697hf/w83697hf_early_serial.c"
 #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
 
-static void memreset_setup(void)
-{
-}
-
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
        return smbus_read_byte(device, address);
@@ -53,8 +49,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 static void enable_mainboard_devices(void)
 {
        device_t dev;
-       u8 reg;
- 
        dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
        if (dev == PCI_DEV_INVALID)
                die("Southbridge not found!!!\n");
@@ -89,9 +83,6 @@ static const struct mem_controller ctrl = {
 
 void main(unsigned long bist)
 {
-       unsigned long x;
-       device_t dev;
-
        /* Enable multifunction for northbridge. */
        pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
 

diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c
index 1e4ee4c7ebb2709140d763ae4bccef7e056db2fb..be696d97d4cf1bc36aa08fca3ec6260edd8b02fb 100644 (file)
--- a/src/mainboard/digitallogic/msm800sev/romstage.c
+++ b/src/mainboard/digitallogic/msm800sev/romstage.c
@@ -51,7 +51,6 @@ static void msr_init(void)
        msr.hi = 0x20000000;
        msr.lo =  0xfff00;
        wrmsr(MSR_GLIU1 + 0x20, msr);
-
 }
 
 static void mb_gpio_init(void)
@@ -61,7 +60,6 @@ static void mb_gpio_init(void)
 
 void cache_as_ram_main(void)
 {
-       extern void RestartCAR();
        post_code(0x01);
 
        static const struct mem_controller memctrl [] = {

diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c
index 9f52466b6aae06ab0d25215e2de50a91ded98677..6aa3f0e404952874de5e7d2343e02a69c8e6bc17 100644 (file)
--- a/src/mainboard/hp/dl145_g3/mptable.c
+++ b/src/mainboard/hp/dl145_g3/mptable.c
@@ -50,8 +50,6 @@ static void *smp_write_config_table(void *v)
        static const char productid[12] = "TREX        ";
        struct mp_config_table *mc;
 
-       unsigned char bus_num;
-       int i;
        struct mb_sysconf_t *m;
 
        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -78,11 +76,13 @@ static void *smp_write_config_table(void *v)
 
        /*Bus:         Bus ID  Type*/
        /* define bus and isa numbers */
-/*     for(bus_num = 0; bus_num < m->bus_isa; bus_num++) {
+#if 0
+       unsigned char bus_num;
+       for(bus_num = 0; bus_num < m->bus_isa; bus_num++) {
                smp_write_bus(mc, bus_num, "PCI   ");
                printk(BIOS_DEBUG, "writing bus %d as PCI...\n",bus_num);
        }
-       */
+#endif
        smp_write_bus(mc, 0, "PCI   ");
        smp_write_bus(mc, 1, "PCI   ");
        smp_write_bus(mc, 7, "PCI   ");

diff --git a/src/mainboard/kontron/kt690/mainboard.c b/src/mainboard/kontron/kt690/mainboard.c
index 5de74a6cffd254014a9703b47c124ccf8361160e..8f428e918f6c6fb627b7533de16b5323dc9d5924 100644 (file)
--- a/src/mainboard/kontron/kt690/mainboard.c
+++ b/src/mainboard/kontron/kt690/mainboard.c
@@ -57,7 +57,7 @@ uint64_t uma_memory_base, uma_memory_size;
 * RRG4.2.3.1 GPM pins as Input
 * RRG4.2.3.2 GPM pins as Output
 ********************************************************/
-static void enable_onboard_nic()
+static void enable_onboard_nic(void)
 {
        u8 byte;
 
@@ -94,7 +94,7 @@ static void enable_onboard_nic()
 * IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
 * get the cable type, 40 pin or 80 pin?
 ********************************************************/
-static void get_ide_dma66()
+static void get_ide_dma66(void)
 {
        u8 byte;
        struct device *sm_dev;
@@ -120,7 +120,7 @@ static void get_ide_dma66()
 /*
  * set thermal config
  */
-static void set_thermal_config()
+static void set_thermal_config(void)
 {
        u8 byte;
        u16 word;

diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c
index 1ba44403246d19f4ddf2e80527d134b235a8eecc..c4a9cc98e53f810613e78d3582bf3d970e2d07cb 100644 (file)
--- a/src/mainboard/pcengines/alix1c/romstage.c
+++ b/src/mainboard/pcengines/alix1c/romstage.c
@@ -145,8 +145,6 @@ void cache_as_ram_main(void)
                {.channel0 = {0x50}},
        };
 
-       extern void RestartCAR();
-
        post_code(0x01);
 
        SystemPreInit();

diff --git a/src/mainboard/technexion/tim8690/mainboard.c b/src/mainboard/technexion/tim8690/mainboard.c
index 977196beb5d21fd17a856b3185ddcea07c794ce6..11deef2ad4a82e4829268aacb67e688bd527c5a0 100644 (file)
--- a/src/mainboard/technexion/tim8690/mainboard.c
+++ b/src/mainboard/technexion/tim8690/mainboard.c
@@ -54,7 +54,7 @@ uint64_t uma_memory_base, uma_memory_size;
 * Both of their pin PERSTn pins are connected to GPIO 5 of the
 * SB600 southbridge.
 ****************************************************/
-static void enable_onboard_nic()
+static void enable_onboard_nic(void)
 {
 
        u8 byte;
@@ -80,7 +80,7 @@ static void enable_onboard_nic()
 
 /* set thermal config
  */
-static void set_thermal_config()
+static void set_thermal_config(void)
 {
        u8 byte;
        u16 word;

diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c
index bb37481d10a655b6e7b0357aad42a19f950f2433..be02ab3d3b7847d67a6013b09e98c6e6e3cd2649 100644 (file)
--- a/src/northbridge/amd/amdht/h3finit.c
+++ b/src/northbridge/amd/amdht/h3finit.c
@@ -1692,7 +1692,7 @@ void tuning(sMainData *pDat)
  *     @param[out] result BOOL  = true if check is ok, false if it failed
  * ---------------------------------------------------------------------------------------
  */
-BOOL isSanityCheckOk()
+BOOL isSanityCheckOk(void)
 {
        uint64 qValue;
 

diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c
index 3f9e89d63c43fd45d9b07ddae2df34f6412332f0..190529ce046fbe0676c4302aef4c4f1b0eb555c8 100644 (file)
--- a/src/northbridge/amd/gx2/northbridge.c
+++ b/src/northbridge/amd/gx2/northbridge.c
@@ -123,9 +123,9 @@ struct msr_defaults {
 };
 
 /* note that dev is NOT used -- yet */
-static void irq_init_steering(struct device *dev, uint16_t irq_map) {
+static void irq_init_steering(struct device *dev, u16 irq_map) {
        /* Set up IRQ steering */
-       uint32_t pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
+       u32 pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
 
        printk(BIOS_DEBUG, "%s(%p [%08X], %04X)\n", __func__, dev, pciAddr, irq_map);
 
@@ -298,17 +298,17 @@ static void northbridge_init(device_t dev)
 /* this is a test -- we are not sure it will work -- but it ought to */
 static void set_resources(struct device *dev)
 {
+#if 0
         struct resource *resource, *last;
-        unsigned link;
-        uint8_t line;
 
-#if 0
         last = &dev->resource[dev->resources];
 
         for(resource = &dev->resource[0]; resource < last; resource++) {
                 pci_set_resource(dev, resource);
         }
 #endif
+        unsigned link;
+
         for(link = 0; link < dev->links; link++) {
                 struct bus *bus;
                 bus = &dev->link[link];
@@ -327,7 +327,7 @@ static void set_resources(struct device *dev)
         }
 
         /* zero the irq settings */
-        line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
+        u8 line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
         if (line) {
                 pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
         }
@@ -383,10 +383,10 @@ static void tolm_test(void *gp, struct device *dev, struct resource *new)
 }
 
 #if 0
-static uint32_t find_pci_tolm(struct bus *bus)
+static u32 find_pci_tolm(struct bus *bus)
 {
        struct resource *min;
-       uint32_t tolm;
+       u32 tolm;
        min = 0;
        search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
        tolm = 0xffffffffUL;
@@ -402,7 +402,7 @@ static void pci_domain_set_resources(device_t dev)
 {
 #if 0
        device_t mc_dev;
-        uint32_t pci_tolm;
+        u32 pci_tolm;
 
         pci_tolm = find_pci_tolm(&dev->link[0]);
        mc_dev = dev->link[0].children;

diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c
index 7d33e4423655b08e58677dc9c43a17bad5152fc2..5023edb546963a869fe6456ab9d132443bff0d21 100644 (file)
--- a/src/northbridge/via/vt8623/northbridge.c
+++ b/src/northbridge/via/vt8623/northbridge.c
@@ -60,7 +60,10 @@ static void northbridge_init(device_t dev)
        }
 }
 
-static void nullfunc(){}
+static void nullfunc(void)
+{
+       /* Nothing to do */
+}
 
 static struct device_operations northbridge_operations = {
        .read_resources   = nullfunc,
@@ -104,7 +107,7 @@ static const struct pci_driver agp_driver __pci_driver = {
 
 static void vga_init(device_t dev)
 {
-//     unsigned long fb;
+       //unsigned long fb;
        //msr_t clocks1,clocks2,instructions,setup;
 
        printk(BIOS_DEBUG, "VGA random fixup ...\n");

diff --git a/src/northbridge/via/vx800/dev_init.c b/src/northbridge/via/vx800/dev_init.c
index 7ec3c86aef9a9e7deac07d20620d2bf22b518682..3a29d29aca9495f17b78b89dbd6a4658ee1c4f05 100644 (file)
--- a/src/northbridge/via/vx800/dev_init.c
+++ b/src/northbridge/via/vx800/dev_init.c
@@ -26,7 +26,7 @@ void InitDDR2CHA(DRAM_SYS_ATTR *DramAttr);
 void InitDDR2CHB(DRAM_SYS_ATTR *DramAttr);
 void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr);
 
-CB_STATUS VerifyChc();
+CB_STATUS VerifyChc(void);
 
 /*===================================================================
 Function   : DRAMRegInitValue()

diff --git a/src/northbridge/via/vx800/dram_init.c b/src/northbridge/via/vx800/dram_init.c
index d059b519ef9687aec81f4c13f78cecf8ad8fa930..b6c8cf2ab09ac190d463ba1d70bee1c8ba6c3945 100644 (file)
--- a/src/northbridge/via/vx800/dram_init.c
+++ b/src/northbridge/via/vx800/dram_init.c
@@ -17,12 +17,10 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-CB_STATUS DDR2_DRAM_INIT()
+CB_STATUS DDR2_DRAM_INIT(void)
 {
-       CB_STATUS Status;
        u8 i;
        u32 RamSize;
-       BOOLEAN bTest;
        DRAM_SYS_ATTR DramAttr;
 
        PRINT_DEBUG_MEM("DRAM_INIT \r");
@@ -76,7 +74,7 @@ CB_STATUS DDR2_DRAM_INIT()
        PRINT_DEBUG_MEM_HEX32(RamSize);
        PRINT_DEBUG_MEM("\r");
        DumpRegisters(0, 3);
-       //bTest = DramBaseTest( M1, RamSize - M1 * 2,SPARE, FALSE);
+       //BOOLEAN bTest = DramBaseTest( M1, RamSize - M1 * 2,SPARE, FALSE);
        /* the memory can not correct work, this is because the user set the incorrect memory
           parameter from setup interface.so we must set the boot mode to recovery mode, let
           the system to reset and use the spd value to initialize the memory */

diff --git a/src/northbridge/via/vx800/dram_init.h b/src/northbridge/via/vx800/dram_init.h
index 51b98934e5edd389099da1671b46f8044736c2f3..27f73f0f4d0964a2776f605a810febdab4feb920 100644 (file)
--- a/src/northbridge/via/vx800/dram_init.h
+++ b/src/northbridge/via/vx800/dram_init.h
@@ -253,9 +253,9 @@ void DRAMRefreshCounter(DRAM_SYS_ATTR * DramAttr);
 void DRAMRegFinalValue(DRAM_SYS_ATTR * DramAttr);
 
 /*set UMA*/
-void SetUMARam();
+void SetUMARam(void);
 
 CB_STATUS InstallMemory(DRAM_SYS_ATTR * DramAttr, u32 RamSize);
-CB_STATUS DDR2_DRAM_INIT();
+CB_STATUS DDR2_DRAM_INIT(void);
 
 #endif

diff --git a/src/northbridge/via/vx800/drdy_bl.c b/src/northbridge/via/vx800/drdy_bl.c
index 627fb28552db7ad75e1edb71e1840c314ea2e177..da8aae13c8c3ef5f1d086cc50e6c789bbe80a616 100644 (file)
--- a/src/northbridge/via/vx800/drdy_bl.c
+++ b/src/northbridge/via/vx800/drdy_bl.c
@@ -407,9 +407,6 @@ void DRAMDRDYSetting(DRAM_SYS_ATTR * DramAttr)
        u8 Data, CL, RDRPH;
        u8 CpuFreq, DramFreq;
        u8 ProgData[PT894_RDRDY_TBL_Width];
-       u8 DelayMode;
-       u8 DrdyMode;
-       u8 Index;
 
        /*
           this function has 3 switchs, correspond to 3 level of Drdy setting.
@@ -483,16 +480,19 @@ void DRAMDRDYSetting(DRAM_SYS_ATTR * DramAttr)
        Data = pci_read_config8(MEMCTRL, 0x90);
        DramFreq = Data & 0x07;
 
+       u8 DelayMode;
        DelayMode = CL + RDRPH; // RDELAYMD = bit0 of (CAS Latency + RDRPH)
        DelayMode &= 0x01;
 
        //In 364, there is no 128 bit
        if (DelayMode == 1) {   // DelayMode 1
+               u8 Index;
                for (Index = 0; Index < PT894_RDRDY_TBL_Width; Index++)
                        ProgData[Index] =
                            PT894_64bit_DELAYMD1_RCONV0[CpuFreq][DramFreq]
                            [Index];
        } else {                // DelayMode 0
+               u8 Index;
                for (Index = 0; Index < PT894_RDRDY_TBL_Width; Index++)
                        ProgData[Index] =
                            PT894_64bit_DELAYMD0_RCONV0[CpuFreq][DramFreq]

diff --git a/src/northbridge/via/vx800/freq_setting.c b/src/northbridge/via/vx800/freq_setting.c
index b81b90de79d08ce212b30d178d0bf5697d9e61f4..47a99c3cc11a7ee36083880ba2fb9382b442501e 100644 (file)
--- a/src/northbridge/via/vx800/freq_setting.c
+++ b/src/northbridge/via/vx800/freq_setting.c
@@ -120,7 +120,7 @@ static const u8 CL_DDR2[7] = { 0, 0, 20, 30, 40, 50, 60 };
 void CalcCLAndFreq(DRAM_SYS_ATTR * DramAttr)
 {
        u8 AllDimmSupportedCL, Tmp;
-       u8 CLMask, tmpMask, IndexDelta;
+       u8 CLMask, tmpMask;
        u8 SckId, BitId, TmpId;
        u16 CycTime, TmpCycTime;
 

diff --git a/src/northbridge/via/vx800/raminit.c b/src/northbridge/via/vx800/raminit.c
index 4daf2b785da9859c3234cbd0800e1dfd7e0c6409..ce9b7d4fab9ba58b1e036eea133a55b2dc693e8a 100644 (file)
--- a/src/northbridge/via/vx800/raminit.c
+++ b/src/northbridge/via/vx800/raminit.c
@@ -55,9 +55,8 @@
  * Support one dimm with up to 2 ranks
  */
 
-static void ddr2_ram_setup()
+static void ddr2_ram_setup(void)
 {
-       u8 Data;
        CB_STATUS Status;
        PRINT_DEBUG_MEM("In ddr2_ram_setup\r");
 

diff --git a/src/northbridge/via/vx800/rank_map.c b/src/northbridge/via/vx800/rank_map.c
index 00e1e47fa30e6cd65508163653247acefb5a8a7c..df39ce589985e306de75f1af0cfceda4a66d5baa 100644 (file)
--- a/src/northbridge/via/vx800/rank_map.c
+++ b/src/northbridge/via/vx800/rank_map.c
@@ -138,7 +138,6 @@ void DRAMSizingEachRank(DRAM_SYS_ATTR * DramAttr)
        u32 Size;
        BOOLEAN HasThreeBitBA;
        u8 Data;
-       u32 Address;
 
        HasThreeBitBA = FALSE;
        for (Slot = 0; Slot < 2; Slot++) {

diff --git a/src/northbridge/via/vx800/uma_ram_setting.c b/src/northbridge/via/vx800/uma_ram_setting.c
index 6988ffe4b02d008cbc26d006faf53a8a1cfc5ded..71379e7ec378992b6ed335fbc502f778844247ee 100644 (file)
--- a/src/northbridge/via/vx800/uma_ram_setting.c
+++ b/src/northbridge/via/vx800/uma_ram_setting.c
@@ -333,6 +333,7 @@ void SetUMARam(void)
        ByteVal = (ByteVal & 0xE5) | 0x1A;
        outb(ByteVal, 0x03d5);
 
+#if 0
        u8 table3c43c5[0x70] = {
                0x03, 0x01, 0x0F, 0x00, 0x06, 0x00, 0x00, 0x00,
                0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -395,9 +396,9 @@ void SetUMARam(void)
                0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
                0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
        };
-#if 0
-//for(i=0;i<0xc0;i++)
-       for (i = 0; i < 0x40; i++)      //
+
+       //for(i=0;i<0xc0;i++)
+       for (i = 0; i < 0x40; i++)
        {
                outb(table3c0space[i], 0x03c0 + i);
        }
@@ -410,6 +411,7 @@ void SetUMARam(void)
                outb(i, 0x03d4);
                outb(table3d43d5[i], 0x03d5);
        }
+
        outb(0x92, 0x03d4);
        outb(0x80, 0x03d5);
 
@@ -419,12 +421,12 @@ void SetUMARam(void)
        outb(0xe8, 0x03d4);
        outb(0x40, 0x03d5);
 #endif
-//3d4 3d freq
-//IO Port / Index: 3X5.3D
-//Scratch Pad Register 4
 
-//    outb(0x39,0x03c4);//
-       //outb(1 << SLD0F3Val ,0x03c5);
+// 3d4 3d freq
+// IO Port / Index: 3X5.3D
+// Scratch Pad Register 4
+//     outb(0x39,0x03c4);
+//     outb(1 << SLD0F3Val ,0x03c5);
 //
 #endif
 

diff --git a/src/northbridge/via/vx800/vgabios.c b/src/northbridge/via/vx800/vgabios.c
index f8029ae157be489faa56167f9d8ac2fab64c4cfc..9690170d1e653d47eafe52ed9c58fa9a344cbb89 100644 (file)
--- a/src/northbridge/via/vx800/vgabios.c
+++ b/src/northbridge/via/vx800/vgabios.c
@@ -299,8 +299,6 @@ void do_vgabios(void)
        unsigned char *buf;
        unsigned int size = 64 * 1024;
        int i;
-       u16 tmp;
-       u8 tmp8;
 
        printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
 
@@ -646,15 +644,7 @@ pcibios(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp,
        unsigned long *pesp, unsigned long *pebx, unsigned long *pedx,
        unsigned long *pecx, unsigned long *peax, unsigned long *pflags)
 {
-       unsigned long edi = *pedi;
-       unsigned long esi = *pesi;
-       unsigned long ebp = *pebp;
-       unsigned long esp = *pesp;
-       unsigned long ebx = *pebx;
-       unsigned long edx = *pedx;
-       unsigned long ecx = *pecx;
        unsigned long eax = *peax;
-       unsigned long flags = *pflags;
        unsigned short func = (unsigned short)eax;
        int retval = 0;
        unsigned short devid, vendorid, devfn;

diff --git a/src/southbridge/amd/cs5535/cs5535_early_setup.c b/src/southbridge/amd/cs5535/cs5535_early_setup.c
index 583602c3dda27d74f51560b82935173de47509a2..fbb3647578c15891eb273f1f4d5f964d9e9a3953 100644 (file)
--- a/src/southbridge/amd/cs5535/cs5535_early_setup.c
+++ b/src/southbridge/amd/cs5535/cs5535_early_setup.c
@@ -23,11 +23,11 @@ static void cs5535_setup_extmsr(void)
 
        /* forward MSR access to CS5535_GLINK_PORT_NUM to CS5535_DEV_NUM */
        msr.hi = msr.lo = 0x00000000;
-       if (CS5535_GLINK_PORT_NUM <= 4) {
-               msr.lo = CS5535_DEV_NUM << ((CS5535_GLINK_PORT_NUM - 1) * 8);
-       } else {
-               msr.hi = CS5535_DEV_NUM << ((CS5535_GLINK_PORT_NUM - 5) * 8);
-       }
+#if CS5535_GLINK_PORT_NUM <= 4
+       msr.lo = CS5535_DEV_NUM << ((CS5535_GLINK_PORT_NUM - 1) * 8);
+#else
+       msr.hi = CS5535_DEV_NUM << ((CS5535_GLINK_PORT_NUM - 5) * 8);
+#endif
        wrmsr(0x5000201e, msr);
 }
 

diff --git a/src/southbridge/amd/cs5536/cs5536_smbus2.h b/src/southbridge/amd/cs5536/cs5536_smbus2.h
index a470b3714c51114f2908f5301d967733e1170f8c..6e50a8cc84a041eb5d6299ec094ac53a78fae080 100644 (file)
--- a/src/southbridge/amd/cs5536/cs5536_smbus2.h
+++ b/src/southbridge/amd/cs5536/cs5536_smbus2.h
@@ -239,9 +239,9 @@ static void _doread(unsigned smbus_io_base, unsigned char device,
                *data++ = val;
 
                if (count > 1) {
-                       int ret = smbus_wait(smbus_io_base);
+                       ret = smbus_wait(smbus_io_base);
                        if (ret)
-                               return ret;
+                               return;
                }
 
                count--;

diff --git a/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c b/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c
index 0ad5c74ee0c849d7aeb2e21a1de13464c6730fbd..3b24d62c255cb11f5865a779b62c6d3ed96adf4d 100644 (file)
--- a/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c
+++ b/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c
@@ -66,8 +66,6 @@ static void smbus_write_byte(unsigned device, unsigned address, unsigned char va
 static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, 
                 unsigned data1, unsigned data2)
 {
-       unsigned char global_control_register;
-       unsigned char global_status_register;
        unsigned char byte;
        unsigned char stat;
        int i;

diff --git a/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c b/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
index 6d776d38bd612335ad5b7ba946e3b6f8c478f3f9..06d9f273c4eb05298f0b898eb264fdd5b2d265b1 100644 (file)
--- a/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
@@ -388,7 +388,7 @@ static int mcp55_early_setup_x(void)
        int mcp55_num = 0;
        unsigned busnx;
        unsigned devnx;
-       int ht_c_index,j;
+       int ht_c_index;
 
        /* FIXME: multi pci segment handling */
 

diff --git a/src/southbridge/nvidia/mcp55/mcp55_fadt.c b/src/southbridge/nvidia/mcp55/mcp55_fadt.c
index 7c7ad6954cb17250c706a84616df1d49724e33bc..8d8040971969d5d2a4f114788b3df37e061631c2 100644 (file)
--- a/src/southbridge/nvidia/mcp55/mcp55_fadt.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_fadt.c
@@ -51,8 +51,8 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
 
        printk(BIOS_INFO, "ACPI: pm_base: %u...\n", pm_base);
 
-       fadt->firmware_ctrl = facs;
-       fadt->dsdt = dsdt;
+       fadt->firmware_ctrl = (u32)facs;
+       fadt->dsdt = (u32)dsdt;
        fadt->preferred_pm_profile = 1; //check
        fadt->sci_int = 9;
        /* disable system management mode by setting to 0 */
@@ -108,9 +108,9 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
        fadt->reset_reg.addrh = 0x0;
 
        fadt->reset_value = 0;
-       fadt->x_firmware_ctl_l = facs;
+       fadt->x_firmware_ctl_l = (u32)facs;
        fadt->x_firmware_ctl_h = 0;
-       fadt->x_dsdt_l = dsdt;
+       fadt->x_dsdt_l = (u32)dsdt;
        fadt->x_dsdt_h = 0;
 
        fadt->x_pm1a_evt_blk.space_id = 1;

diff --git a/src/southbridge/via/vt8235/vt8235.c b/src/southbridge/via/vt8235/vt8235.c
index 2687972afa070bdaf03b2e8af303e80d2834bfd2..92bd9d83916a5a4410970fa860a12f0d4e4088cc 100644 (file)
--- a/src/southbridge/via/vt8235/vt8235.c
+++ b/src/southbridge/via/vt8235/vt8235.c
@@ -41,7 +41,7 @@ void dump_south(device_t dev0)
        }
 }
 
-void set_led()
+void set_led(void)
 {
        // set power led to steady now that lxbios has virtually done its job
        device_t dev;